1 /* 2 * Copyright (c) 2006 Luc Verhaegen (quirks list) 3 * Copyright (c) 2007-2008 Intel Corporation 4 * Jesse Barnes <jesse.barnes@intel.com> 5 * Copyright 2010 Red Hat, Inc. 6 * 7 * DDC probing routines (drm_ddc_read & drm_do_probe_ddc_edid) originally from 8 * FB layer. 9 * Copyright (C) 2006 Dennis Munsie <dmunsie@cecropia.com> 10 * 11 * Permission is hereby granted, free of charge, to any person obtaining a 12 * copy of this software and associated documentation files (the "Software"), 13 * to deal in the Software without restriction, including without limitation 14 * the rights to use, copy, modify, merge, publish, distribute, sub license, 15 * and/or sell copies of the Software, and to permit persons to whom the 16 * Software is furnished to do so, subject to the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 27 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 28 * DEALINGS IN THE SOFTWARE. 29 */ 30 31 #include <linux/bitfield.h> 32 #include <linux/byteorder/generic.h> 33 #include <linux/cec.h> 34 #include <linux/hdmi.h> 35 #include <linux/i2c.h> 36 #include <linux/kernel.h> 37 #include <linux/module.h> 38 #include <linux/pci.h> 39 #include <linux/seq_buf.h> 40 #include <linux/slab.h> 41 #include <linux/vga_switcheroo.h> 42 43 #include <drm/drm_drv.h> 44 #include <drm/drm_edid.h> 45 #include <drm/drm_eld.h> 46 #include <drm/drm_encoder.h> 47 #include <drm/drm_print.h> 48 49 #include "drm_crtc_internal.h" 50 #include "drm_displayid_internal.h" 51 #include "drm_internal.h" 52 53 static int oui(u8 first, u8 second, u8 third) 54 { 55 return (first << 16) | (second << 8) | third; 56 } 57 58 #define EDID_EST_TIMINGS 16 59 #define EDID_STD_TIMINGS 8 60 #define EDID_DETAILED_TIMINGS 4 61 62 /* 63 * EDID blocks out in the wild have a variety of bugs, try to collect 64 * them here (note that userspace may work around broken monitors first, 65 * but fixes should make their way here so that the kernel "just works" 66 * on as many displays as possible). 67 */ 68 69 /* First detailed mode wrong, use largest 60Hz mode */ 70 #define EDID_QUIRK_PREFER_LARGE_60 (1 << 0) 71 /* Reported 135MHz pixel clock is too high, needs adjustment */ 72 #define EDID_QUIRK_135_CLOCK_TOO_HIGH (1 << 1) 73 /* Prefer the largest mode at 75 Hz */ 74 #define EDID_QUIRK_PREFER_LARGE_75 (1 << 2) 75 /* Detail timing is in cm not mm */ 76 #define EDID_QUIRK_DETAILED_IN_CM (1 << 3) 77 /* Detailed timing descriptors have bogus size values, so just take the 78 * maximum size and use that. 79 */ 80 #define EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE (1 << 4) 81 /* use +hsync +vsync for detailed mode */ 82 #define EDID_QUIRK_DETAILED_SYNC_PP (1 << 6) 83 /* Force reduced-blanking timings for detailed modes */ 84 #define EDID_QUIRK_FORCE_REDUCED_BLANKING (1 << 7) 85 /* Force 8bpc */ 86 #define EDID_QUIRK_FORCE_8BPC (1 << 8) 87 /* Force 12bpc */ 88 #define EDID_QUIRK_FORCE_12BPC (1 << 9) 89 /* Force 6bpc */ 90 #define EDID_QUIRK_FORCE_6BPC (1 << 10) 91 /* Force 10bpc */ 92 #define EDID_QUIRK_FORCE_10BPC (1 << 11) 93 /* Non desktop display (i.e. HMD) */ 94 #define EDID_QUIRK_NON_DESKTOP (1 << 12) 95 /* Cap the DSC target bitrate to 15bpp */ 96 #define EDID_QUIRK_CAP_DSC_15BPP (1 << 13) 97 98 #define MICROSOFT_IEEE_OUI 0xca125c 99 100 struct detailed_mode_closure { 101 struct drm_connector *connector; 102 const struct drm_edid *drm_edid; 103 bool preferred; 104 int modes; 105 }; 106 107 struct drm_edid_match_closure { 108 const struct drm_edid_ident *ident; 109 bool matched; 110 }; 111 112 #define LEVEL_DMT 0 113 #define LEVEL_GTF 1 114 #define LEVEL_GTF2 2 115 #define LEVEL_CVT 3 116 117 #define EDID_QUIRK(vend_chr_0, vend_chr_1, vend_chr_2, product_id, _quirks) \ 118 { \ 119 .ident = { \ 120 .panel_id = drm_edid_encode_panel_id(vend_chr_0, vend_chr_1, \ 121 vend_chr_2, product_id), \ 122 }, \ 123 .quirks = _quirks \ 124 } 125 126 static const struct edid_quirk { 127 const struct drm_edid_ident ident; 128 u32 quirks; 129 } edid_quirk_list[] = { 130 /* Acer AL1706 */ 131 EDID_QUIRK('A', 'C', 'R', 44358, EDID_QUIRK_PREFER_LARGE_60), 132 /* Acer F51 */ 133 EDID_QUIRK('A', 'P', 'I', 0x7602, EDID_QUIRK_PREFER_LARGE_60), 134 135 /* AEO model 0 reports 8 bpc, but is a 6 bpc panel */ 136 EDID_QUIRK('A', 'E', 'O', 0, EDID_QUIRK_FORCE_6BPC), 137 138 /* BenQ GW2765 */ 139 EDID_QUIRK('B', 'N', 'Q', 0x78d6, EDID_QUIRK_FORCE_8BPC), 140 141 /* BOE model on HP Pavilion 15-n233sl reports 8 bpc, but is a 6 bpc panel */ 142 EDID_QUIRK('B', 'O', 'E', 0x78b, EDID_QUIRK_FORCE_6BPC), 143 144 /* CPT panel of Asus UX303LA reports 8 bpc, but is a 6 bpc panel */ 145 EDID_QUIRK('C', 'P', 'T', 0x17df, EDID_QUIRK_FORCE_6BPC), 146 147 /* SDC panel of Lenovo B50-80 reports 8 bpc, but is a 6 bpc panel */ 148 EDID_QUIRK('S', 'D', 'C', 0x3652, EDID_QUIRK_FORCE_6BPC), 149 150 /* BOE model 0x0771 reports 8 bpc, but is a 6 bpc panel */ 151 EDID_QUIRK('B', 'O', 'E', 0x0771, EDID_QUIRK_FORCE_6BPC), 152 153 /* Belinea 10 15 55 */ 154 EDID_QUIRK('M', 'A', 'X', 1516, EDID_QUIRK_PREFER_LARGE_60), 155 EDID_QUIRK('M', 'A', 'X', 0x77e, EDID_QUIRK_PREFER_LARGE_60), 156 157 /* Envision Peripherals, Inc. EN-7100e */ 158 EDID_QUIRK('E', 'P', 'I', 59264, EDID_QUIRK_135_CLOCK_TOO_HIGH), 159 /* Envision EN2028 */ 160 EDID_QUIRK('E', 'P', 'I', 8232, EDID_QUIRK_PREFER_LARGE_60), 161 162 /* Funai Electronics PM36B */ 163 EDID_QUIRK('F', 'C', 'M', 13600, EDID_QUIRK_PREFER_LARGE_75 | 164 EDID_QUIRK_DETAILED_IN_CM), 165 166 /* LG 27GP950 */ 167 EDID_QUIRK('G', 'S', 'M', 0x5bbf, EDID_QUIRK_CAP_DSC_15BPP), 168 169 /* LG 27GN950 */ 170 EDID_QUIRK('G', 'S', 'M', 0x5b9a, EDID_QUIRK_CAP_DSC_15BPP), 171 172 /* LGD panel of HP zBook 17 G2, eDP 10 bpc, but reports unknown bpc */ 173 EDID_QUIRK('L', 'G', 'D', 764, EDID_QUIRK_FORCE_10BPC), 174 175 /* LG Philips LCD LP154W01-A5 */ 176 EDID_QUIRK('L', 'P', 'L', 0, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 177 EDID_QUIRK('L', 'P', 'L', 0x2a00, EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE), 178 179 /* Samsung SyncMaster 205BW. Note: irony */ 180 EDID_QUIRK('S', 'A', 'M', 541, EDID_QUIRK_DETAILED_SYNC_PP), 181 /* Samsung SyncMaster 22[5-6]BW */ 182 EDID_QUIRK('S', 'A', 'M', 596, EDID_QUIRK_PREFER_LARGE_60), 183 EDID_QUIRK('S', 'A', 'M', 638, EDID_QUIRK_PREFER_LARGE_60), 184 185 /* Sony PVM-2541A does up to 12 bpc, but only reports max 8 bpc */ 186 EDID_QUIRK('S', 'N', 'Y', 0x2541, EDID_QUIRK_FORCE_12BPC), 187 188 /* ViewSonic VA2026w */ 189 EDID_QUIRK('V', 'S', 'C', 5020, EDID_QUIRK_FORCE_REDUCED_BLANKING), 190 191 /* Medion MD 30217 PG */ 192 EDID_QUIRK('M', 'E', 'D', 0x7b8, EDID_QUIRK_PREFER_LARGE_75), 193 194 /* Lenovo G50 */ 195 EDID_QUIRK('S', 'D', 'C', 18514, EDID_QUIRK_FORCE_6BPC), 196 197 /* Panel in Samsung NP700G7A-S01PL notebook reports 6bpc */ 198 EDID_QUIRK('S', 'E', 'C', 0xd033, EDID_QUIRK_FORCE_8BPC), 199 200 /* Rotel RSX-1058 forwards sink's EDID but only does HDMI 1.1*/ 201 EDID_QUIRK('E', 'T', 'R', 13896, EDID_QUIRK_FORCE_8BPC), 202 203 /* Valve Index Headset */ 204 EDID_QUIRK('V', 'L', 'V', 0x91a8, EDID_QUIRK_NON_DESKTOP), 205 EDID_QUIRK('V', 'L', 'V', 0x91b0, EDID_QUIRK_NON_DESKTOP), 206 EDID_QUIRK('V', 'L', 'V', 0x91b1, EDID_QUIRK_NON_DESKTOP), 207 EDID_QUIRK('V', 'L', 'V', 0x91b2, EDID_QUIRK_NON_DESKTOP), 208 EDID_QUIRK('V', 'L', 'V', 0x91b3, EDID_QUIRK_NON_DESKTOP), 209 EDID_QUIRK('V', 'L', 'V', 0x91b4, EDID_QUIRK_NON_DESKTOP), 210 EDID_QUIRK('V', 'L', 'V', 0x91b5, EDID_QUIRK_NON_DESKTOP), 211 EDID_QUIRK('V', 'L', 'V', 0x91b6, EDID_QUIRK_NON_DESKTOP), 212 EDID_QUIRK('V', 'L', 'V', 0x91b7, EDID_QUIRK_NON_DESKTOP), 213 EDID_QUIRK('V', 'L', 'V', 0x91b8, EDID_QUIRK_NON_DESKTOP), 214 EDID_QUIRK('V', 'L', 'V', 0x91b9, EDID_QUIRK_NON_DESKTOP), 215 EDID_QUIRK('V', 'L', 'V', 0x91ba, EDID_QUIRK_NON_DESKTOP), 216 EDID_QUIRK('V', 'L', 'V', 0x91bb, EDID_QUIRK_NON_DESKTOP), 217 EDID_QUIRK('V', 'L', 'V', 0x91bc, EDID_QUIRK_NON_DESKTOP), 218 EDID_QUIRK('V', 'L', 'V', 0x91bd, EDID_QUIRK_NON_DESKTOP), 219 EDID_QUIRK('V', 'L', 'V', 0x91be, EDID_QUIRK_NON_DESKTOP), 220 EDID_QUIRK('V', 'L', 'V', 0x91bf, EDID_QUIRK_NON_DESKTOP), 221 222 /* HTC Vive and Vive Pro VR Headsets */ 223 EDID_QUIRK('H', 'V', 'R', 0xaa01, EDID_QUIRK_NON_DESKTOP), 224 EDID_QUIRK('H', 'V', 'R', 0xaa02, EDID_QUIRK_NON_DESKTOP), 225 226 /* Oculus Rift DK1, DK2, CV1 and Rift S VR Headsets */ 227 EDID_QUIRK('O', 'V', 'R', 0x0001, EDID_QUIRK_NON_DESKTOP), 228 EDID_QUIRK('O', 'V', 'R', 0x0003, EDID_QUIRK_NON_DESKTOP), 229 EDID_QUIRK('O', 'V', 'R', 0x0004, EDID_QUIRK_NON_DESKTOP), 230 EDID_QUIRK('O', 'V', 'R', 0x0012, EDID_QUIRK_NON_DESKTOP), 231 232 /* Windows Mixed Reality Headsets */ 233 EDID_QUIRK('A', 'C', 'R', 0x7fce, EDID_QUIRK_NON_DESKTOP), 234 EDID_QUIRK('L', 'E', 'N', 0x0408, EDID_QUIRK_NON_DESKTOP), 235 EDID_QUIRK('F', 'U', 'J', 0x1970, EDID_QUIRK_NON_DESKTOP), 236 EDID_QUIRK('D', 'E', 'L', 0x7fce, EDID_QUIRK_NON_DESKTOP), 237 EDID_QUIRK('S', 'E', 'C', 0x144a, EDID_QUIRK_NON_DESKTOP), 238 EDID_QUIRK('A', 'U', 'S', 0xc102, EDID_QUIRK_NON_DESKTOP), 239 240 /* Sony PlayStation VR Headset */ 241 EDID_QUIRK('S', 'N', 'Y', 0x0704, EDID_QUIRK_NON_DESKTOP), 242 243 /* Sensics VR Headsets */ 244 EDID_QUIRK('S', 'E', 'N', 0x1019, EDID_QUIRK_NON_DESKTOP), 245 246 /* OSVR HDK and HDK2 VR Headsets */ 247 EDID_QUIRK('S', 'V', 'R', 0x1019, EDID_QUIRK_NON_DESKTOP), 248 EDID_QUIRK('A', 'U', 'O', 0x1111, EDID_QUIRK_NON_DESKTOP), 249 }; 250 251 /* 252 * Autogenerated from the DMT spec. 253 * This table is copied from xfree86/modes/xf86EdidModes.c. 254 */ 255 static const struct drm_display_mode drm_dmt_modes[] = { 256 /* 0x01 - 640x350@85Hz */ 257 { DRM_MODE("640x350", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 258 736, 832, 0, 350, 382, 385, 445, 0, 259 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 260 /* 0x02 - 640x400@85Hz */ 261 { DRM_MODE("640x400", DRM_MODE_TYPE_DRIVER, 31500, 640, 672, 262 736, 832, 0, 400, 401, 404, 445, 0, 263 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 264 /* 0x03 - 720x400@85Hz */ 265 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 756, 266 828, 936, 0, 400, 401, 404, 446, 0, 267 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 268 /* 0x04 - 640x480@60Hz */ 269 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 270 752, 800, 0, 480, 490, 492, 525, 0, 271 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 272 /* 0x05 - 640x480@72Hz */ 273 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 274 704, 832, 0, 480, 489, 492, 520, 0, 275 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 276 /* 0x06 - 640x480@75Hz */ 277 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 278 720, 840, 0, 480, 481, 484, 500, 0, 279 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 280 /* 0x07 - 640x480@85Hz */ 281 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 36000, 640, 696, 282 752, 832, 0, 480, 481, 484, 509, 0, 283 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 284 /* 0x08 - 800x600@56Hz */ 285 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 286 896, 1024, 0, 600, 601, 603, 625, 0, 287 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 288 /* 0x09 - 800x600@60Hz */ 289 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 290 968, 1056, 0, 600, 601, 605, 628, 0, 291 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 292 /* 0x0a - 800x600@72Hz */ 293 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 294 976, 1040, 0, 600, 637, 643, 666, 0, 295 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 296 /* 0x0b - 800x600@75Hz */ 297 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 298 896, 1056, 0, 600, 601, 604, 625, 0, 299 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 300 /* 0x0c - 800x600@85Hz */ 301 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 56250, 800, 832, 302 896, 1048, 0, 600, 601, 604, 631, 0, 303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 304 /* 0x0d - 800x600@120Hz RB */ 305 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 73250, 800, 848, 306 880, 960, 0, 600, 603, 607, 636, 0, 307 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 308 /* 0x0e - 848x480@60Hz */ 309 { DRM_MODE("848x480", DRM_MODE_TYPE_DRIVER, 33750, 848, 864, 310 976, 1088, 0, 480, 486, 494, 517, 0, 311 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 312 /* 0x0f - 1024x768@43Hz, interlace */ 313 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER, 44900, 1024, 1032, 314 1208, 1264, 0, 768, 768, 776, 817, 0, 315 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 316 DRM_MODE_FLAG_INTERLACE) }, 317 /* 0x10 - 1024x768@60Hz */ 318 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 319 1184, 1344, 0, 768, 771, 777, 806, 0, 320 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 321 /* 0x11 - 1024x768@70Hz */ 322 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 323 1184, 1328, 0, 768, 771, 777, 806, 0, 324 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 325 /* 0x12 - 1024x768@75Hz */ 326 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 327 1136, 1312, 0, 768, 769, 772, 800, 0, 328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 329 /* 0x13 - 1024x768@85Hz */ 330 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 94500, 1024, 1072, 331 1168, 1376, 0, 768, 769, 772, 808, 0, 332 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 333 /* 0x14 - 1024x768@120Hz RB */ 334 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 115500, 1024, 1072, 335 1104, 1184, 0, 768, 771, 775, 813, 0, 336 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 337 /* 0x15 - 1152x864@75Hz */ 338 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 339 1344, 1600, 0, 864, 865, 868, 900, 0, 340 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 341 /* 0x55 - 1280x720@60Hz */ 342 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 343 1430, 1650, 0, 720, 725, 730, 750, 0, 344 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 345 /* 0x16 - 1280x768@60Hz RB */ 346 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 68250, 1280, 1328, 347 1360, 1440, 0, 768, 771, 778, 790, 0, 348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 349 /* 0x17 - 1280x768@60Hz */ 350 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 79500, 1280, 1344, 351 1472, 1664, 0, 768, 771, 778, 798, 0, 352 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 353 /* 0x18 - 1280x768@75Hz */ 354 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 102250, 1280, 1360, 355 1488, 1696, 0, 768, 771, 778, 805, 0, 356 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 357 /* 0x19 - 1280x768@85Hz */ 358 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 117500, 1280, 1360, 359 1496, 1712, 0, 768, 771, 778, 809, 0, 360 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 361 /* 0x1a - 1280x768@120Hz RB */ 362 { DRM_MODE("1280x768", DRM_MODE_TYPE_DRIVER, 140250, 1280, 1328, 363 1360, 1440, 0, 768, 771, 778, 813, 0, 364 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 365 /* 0x1b - 1280x800@60Hz RB */ 366 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 71000, 1280, 1328, 367 1360, 1440, 0, 800, 803, 809, 823, 0, 368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 369 /* 0x1c - 1280x800@60Hz */ 370 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 83500, 1280, 1352, 371 1480, 1680, 0, 800, 803, 809, 831, 0, 372 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 373 /* 0x1d - 1280x800@75Hz */ 374 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 106500, 1280, 1360, 375 1488, 1696, 0, 800, 803, 809, 838, 0, 376 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 377 /* 0x1e - 1280x800@85Hz */ 378 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 122500, 1280, 1360, 379 1496, 1712, 0, 800, 803, 809, 843, 0, 380 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 381 /* 0x1f - 1280x800@120Hz RB */ 382 { DRM_MODE("1280x800", DRM_MODE_TYPE_DRIVER, 146250, 1280, 1328, 383 1360, 1440, 0, 800, 803, 809, 847, 0, 384 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 385 /* 0x20 - 1280x960@60Hz */ 386 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1376, 387 1488, 1800, 0, 960, 961, 964, 1000, 0, 388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 389 /* 0x21 - 1280x960@85Hz */ 390 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1344, 391 1504, 1728, 0, 960, 961, 964, 1011, 0, 392 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 393 /* 0x22 - 1280x960@120Hz RB */ 394 { DRM_MODE("1280x960", DRM_MODE_TYPE_DRIVER, 175500, 1280, 1328, 395 1360, 1440, 0, 960, 963, 967, 1017, 0, 396 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 397 /* 0x23 - 1280x1024@60Hz */ 398 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 108000, 1280, 1328, 399 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 400 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 401 /* 0x24 - 1280x1024@75Hz */ 402 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 403 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 404 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 405 /* 0x25 - 1280x1024@85Hz */ 406 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 157500, 1280, 1344, 407 1504, 1728, 0, 1024, 1025, 1028, 1072, 0, 408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 409 /* 0x26 - 1280x1024@120Hz RB */ 410 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 187250, 1280, 1328, 411 1360, 1440, 0, 1024, 1027, 1034, 1084, 0, 412 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 413 /* 0x27 - 1360x768@60Hz */ 414 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 85500, 1360, 1424, 415 1536, 1792, 0, 768, 771, 777, 795, 0, 416 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 417 /* 0x28 - 1360x768@120Hz RB */ 418 { DRM_MODE("1360x768", DRM_MODE_TYPE_DRIVER, 148250, 1360, 1408, 419 1440, 1520, 0, 768, 771, 776, 813, 0, 420 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 421 /* 0x51 - 1366x768@60Hz */ 422 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 85500, 1366, 1436, 423 1579, 1792, 0, 768, 771, 774, 798, 0, 424 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 425 /* 0x56 - 1366x768@60Hz */ 426 { DRM_MODE("1366x768", DRM_MODE_TYPE_DRIVER, 72000, 1366, 1380, 427 1436, 1500, 0, 768, 769, 772, 800, 0, 428 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 429 /* 0x29 - 1400x1050@60Hz RB */ 430 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 101000, 1400, 1448, 431 1480, 1560, 0, 1050, 1053, 1057, 1080, 0, 432 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 433 /* 0x2a - 1400x1050@60Hz */ 434 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 121750, 1400, 1488, 435 1632, 1864, 0, 1050, 1053, 1057, 1089, 0, 436 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 437 /* 0x2b - 1400x1050@75Hz */ 438 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 156000, 1400, 1504, 439 1648, 1896, 0, 1050, 1053, 1057, 1099, 0, 440 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 441 /* 0x2c - 1400x1050@85Hz */ 442 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 179500, 1400, 1504, 443 1656, 1912, 0, 1050, 1053, 1057, 1105, 0, 444 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 445 /* 0x2d - 1400x1050@120Hz RB */ 446 { DRM_MODE("1400x1050", DRM_MODE_TYPE_DRIVER, 208000, 1400, 1448, 447 1480, 1560, 0, 1050, 1053, 1057, 1112, 0, 448 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 449 /* 0x2e - 1440x900@60Hz RB */ 450 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 88750, 1440, 1488, 451 1520, 1600, 0, 900, 903, 909, 926, 0, 452 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 453 /* 0x2f - 1440x900@60Hz */ 454 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 106500, 1440, 1520, 455 1672, 1904, 0, 900, 903, 909, 934, 0, 456 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 457 /* 0x30 - 1440x900@75Hz */ 458 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 136750, 1440, 1536, 459 1688, 1936, 0, 900, 903, 909, 942, 0, 460 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 461 /* 0x31 - 1440x900@85Hz */ 462 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 157000, 1440, 1544, 463 1696, 1952, 0, 900, 903, 909, 948, 0, 464 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 465 /* 0x32 - 1440x900@120Hz RB */ 466 { DRM_MODE("1440x900", DRM_MODE_TYPE_DRIVER, 182750, 1440, 1488, 467 1520, 1600, 0, 900, 903, 909, 953, 0, 468 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 469 /* 0x53 - 1600x900@60Hz */ 470 { DRM_MODE("1600x900", DRM_MODE_TYPE_DRIVER, 108000, 1600, 1624, 471 1704, 1800, 0, 900, 901, 904, 1000, 0, 472 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 473 /* 0x33 - 1600x1200@60Hz */ 474 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 162000, 1600, 1664, 475 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 477 /* 0x34 - 1600x1200@65Hz */ 478 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 175500, 1600, 1664, 479 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 480 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 481 /* 0x35 - 1600x1200@70Hz */ 482 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 189000, 1600, 1664, 483 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 484 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 485 /* 0x36 - 1600x1200@75Hz */ 486 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 202500, 1600, 1664, 487 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 488 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 489 /* 0x37 - 1600x1200@85Hz */ 490 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 229500, 1600, 1664, 491 1856, 2160, 0, 1200, 1201, 1204, 1250, 0, 492 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 493 /* 0x38 - 1600x1200@120Hz RB */ 494 { DRM_MODE("1600x1200", DRM_MODE_TYPE_DRIVER, 268250, 1600, 1648, 495 1680, 1760, 0, 1200, 1203, 1207, 1271, 0, 496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 497 /* 0x39 - 1680x1050@60Hz RB */ 498 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 119000, 1680, 1728, 499 1760, 1840, 0, 1050, 1053, 1059, 1080, 0, 500 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 501 /* 0x3a - 1680x1050@60Hz */ 502 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 146250, 1680, 1784, 503 1960, 2240, 0, 1050, 1053, 1059, 1089, 0, 504 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 505 /* 0x3b - 1680x1050@75Hz */ 506 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 187000, 1680, 1800, 507 1976, 2272, 0, 1050, 1053, 1059, 1099, 0, 508 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 509 /* 0x3c - 1680x1050@85Hz */ 510 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 214750, 1680, 1808, 511 1984, 2288, 0, 1050, 1053, 1059, 1105, 0, 512 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 513 /* 0x3d - 1680x1050@120Hz RB */ 514 { DRM_MODE("1680x1050", DRM_MODE_TYPE_DRIVER, 245500, 1680, 1728, 515 1760, 1840, 0, 1050, 1053, 1059, 1112, 0, 516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 517 /* 0x3e - 1792x1344@60Hz */ 518 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 204750, 1792, 1920, 519 2120, 2448, 0, 1344, 1345, 1348, 1394, 0, 520 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 521 /* 0x3f - 1792x1344@75Hz */ 522 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 261000, 1792, 1888, 523 2104, 2456, 0, 1344, 1345, 1348, 1417, 0, 524 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 525 /* 0x40 - 1792x1344@120Hz RB */ 526 { DRM_MODE("1792x1344", DRM_MODE_TYPE_DRIVER, 333250, 1792, 1840, 527 1872, 1952, 0, 1344, 1347, 1351, 1423, 0, 528 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 529 /* 0x41 - 1856x1392@60Hz */ 530 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 218250, 1856, 1952, 531 2176, 2528, 0, 1392, 1393, 1396, 1439, 0, 532 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 533 /* 0x42 - 1856x1392@75Hz */ 534 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 288000, 1856, 1984, 535 2208, 2560, 0, 1392, 1393, 1396, 1500, 0, 536 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 537 /* 0x43 - 1856x1392@120Hz RB */ 538 { DRM_MODE("1856x1392", DRM_MODE_TYPE_DRIVER, 356500, 1856, 1904, 539 1936, 2016, 0, 1392, 1395, 1399, 1474, 0, 540 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 541 /* 0x52 - 1920x1080@60Hz */ 542 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 543 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 544 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, 545 /* 0x44 - 1920x1200@60Hz RB */ 546 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 154000, 1920, 1968, 547 2000, 2080, 0, 1200, 1203, 1209, 1235, 0, 548 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 549 /* 0x45 - 1920x1200@60Hz */ 550 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 193250, 1920, 2056, 551 2256, 2592, 0, 1200, 1203, 1209, 1245, 0, 552 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 553 /* 0x46 - 1920x1200@75Hz */ 554 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 245250, 1920, 2056, 555 2264, 2608, 0, 1200, 1203, 1209, 1255, 0, 556 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 557 /* 0x47 - 1920x1200@85Hz */ 558 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 281250, 1920, 2064, 559 2272, 2624, 0, 1200, 1203, 1209, 1262, 0, 560 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 561 /* 0x48 - 1920x1200@120Hz RB */ 562 { DRM_MODE("1920x1200", DRM_MODE_TYPE_DRIVER, 317000, 1920, 1968, 563 2000, 2080, 0, 1200, 1203, 1209, 1271, 0, 564 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 565 /* 0x49 - 1920x1440@60Hz */ 566 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 234000, 1920, 2048, 567 2256, 2600, 0, 1440, 1441, 1444, 1500, 0, 568 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 569 /* 0x4a - 1920x1440@75Hz */ 570 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2064, 571 2288, 2640, 0, 1440, 1441, 1444, 1500, 0, 572 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 573 /* 0x4b - 1920x1440@120Hz RB */ 574 { DRM_MODE("1920x1440", DRM_MODE_TYPE_DRIVER, 380500, 1920, 1968, 575 2000, 2080, 0, 1440, 1443, 1447, 1525, 0, 576 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 577 /* 0x54 - 2048x1152@60Hz */ 578 { DRM_MODE("2048x1152", DRM_MODE_TYPE_DRIVER, 162000, 2048, 2074, 579 2154, 2250, 0, 1152, 1153, 1156, 1200, 0, 580 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, 581 /* 0x4c - 2560x1600@60Hz RB */ 582 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 268500, 2560, 2608, 583 2640, 2720, 0, 1600, 1603, 1609, 1646, 0, 584 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 585 /* 0x4d - 2560x1600@60Hz */ 586 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 348500, 2560, 2752, 587 3032, 3504, 0, 1600, 1603, 1609, 1658, 0, 588 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 589 /* 0x4e - 2560x1600@75Hz */ 590 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 443250, 2560, 2768, 591 3048, 3536, 0, 1600, 1603, 1609, 1672, 0, 592 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 593 /* 0x4f - 2560x1600@85Hz */ 594 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 505250, 2560, 2768, 595 3048, 3536, 0, 1600, 1603, 1609, 1682, 0, 596 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, 597 /* 0x50 - 2560x1600@120Hz RB */ 598 { DRM_MODE("2560x1600", DRM_MODE_TYPE_DRIVER, 552750, 2560, 2608, 599 2640, 2720, 0, 1600, 1603, 1609, 1694, 0, 600 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 601 /* 0x57 - 4096x2160@60Hz RB */ 602 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556744, 4096, 4104, 603 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 604 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 605 /* 0x58 - 4096x2160@59.94Hz RB */ 606 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 556188, 4096, 4104, 607 4136, 4176, 0, 2160, 2208, 2216, 2222, 0, 608 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC) }, 609 }; 610 611 /* 612 * These more or less come from the DMT spec. The 720x400 modes are 613 * inferred from historical 80x25 practice. The 640x480@67 and 832x624@75 614 * modes are old-school Mac modes. The EDID spec says the 1152x864@75 mode 615 * should be 1152x870, again for the Mac, but instead we use the x864 DMT 616 * mode. 617 * 618 * The DMT modes have been fact-checked; the rest are mild guesses. 619 */ 620 static const struct drm_display_mode edid_est_modes[] = { 621 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 40000, 800, 840, 622 968, 1056, 0, 600, 601, 605, 628, 0, 623 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@60Hz */ 624 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 36000, 800, 824, 625 896, 1024, 0, 600, 601, 603, 625, 0, 626 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@56Hz */ 627 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 656, 628 720, 840, 0, 480, 481, 484, 500, 0, 629 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@75Hz */ 630 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 31500, 640, 664, 631 704, 832, 0, 480, 489, 492, 520, 0, 632 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@72Hz */ 633 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 30240, 640, 704, 634 768, 864, 0, 480, 483, 486, 525, 0, 635 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@67Hz */ 636 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 637 752, 800, 0, 480, 490, 492, 525, 0, 638 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 640x480@60Hz */ 639 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 35500, 720, 738, 640 846, 900, 0, 400, 421, 423, 449, 0, 641 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 720x400@88Hz */ 642 { DRM_MODE("720x400", DRM_MODE_TYPE_DRIVER, 28320, 720, 738, 643 846, 900, 0, 400, 412, 414, 449, 0, 644 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 720x400@70Hz */ 645 { DRM_MODE("1280x1024", DRM_MODE_TYPE_DRIVER, 135000, 1280, 1296, 646 1440, 1688, 0, 1024, 1025, 1028, 1066, 0, 647 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1280x1024@75Hz */ 648 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 78750, 1024, 1040, 649 1136, 1312, 0, 768, 769, 772, 800, 0, 650 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1024x768@75Hz */ 651 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 75000, 1024, 1048, 652 1184, 1328, 0, 768, 771, 777, 806, 0, 653 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@70Hz */ 654 { DRM_MODE("1024x768", DRM_MODE_TYPE_DRIVER, 65000, 1024, 1048, 655 1184, 1344, 0, 768, 771, 777, 806, 0, 656 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 1024x768@60Hz */ 657 { DRM_MODE("1024x768i", DRM_MODE_TYPE_DRIVER,44900, 1024, 1032, 658 1208, 1264, 0, 768, 768, 776, 817, 0, 659 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_INTERLACE) }, /* 1024x768@43Hz */ 660 { DRM_MODE("832x624", DRM_MODE_TYPE_DRIVER, 57284, 832, 864, 661 928, 1152, 0, 624, 625, 628, 667, 0, 662 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC) }, /* 832x624@75Hz */ 663 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 49500, 800, 816, 664 896, 1056, 0, 600, 601, 604, 625, 0, 665 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@75Hz */ 666 { DRM_MODE("800x600", DRM_MODE_TYPE_DRIVER, 50000, 800, 856, 667 976, 1040, 0, 600, 637, 643, 666, 0, 668 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 800x600@72Hz */ 669 { DRM_MODE("1152x864", DRM_MODE_TYPE_DRIVER, 108000, 1152, 1216, 670 1344, 1600, 0, 864, 865, 868, 900, 0, 671 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC) }, /* 1152x864@75Hz */ 672 }; 673 674 struct minimode { 675 short w; 676 short h; 677 short r; 678 short rb; 679 }; 680 681 static const struct minimode est3_modes[] = { 682 /* byte 6 */ 683 { 640, 350, 85, 0 }, 684 { 640, 400, 85, 0 }, 685 { 720, 400, 85, 0 }, 686 { 640, 480, 85, 0 }, 687 { 848, 480, 60, 0 }, 688 { 800, 600, 85, 0 }, 689 { 1024, 768, 85, 0 }, 690 { 1152, 864, 75, 0 }, 691 /* byte 7 */ 692 { 1280, 768, 60, 1 }, 693 { 1280, 768, 60, 0 }, 694 { 1280, 768, 75, 0 }, 695 { 1280, 768, 85, 0 }, 696 { 1280, 960, 60, 0 }, 697 { 1280, 960, 85, 0 }, 698 { 1280, 1024, 60, 0 }, 699 { 1280, 1024, 85, 0 }, 700 /* byte 8 */ 701 { 1360, 768, 60, 0 }, 702 { 1440, 900, 60, 1 }, 703 { 1440, 900, 60, 0 }, 704 { 1440, 900, 75, 0 }, 705 { 1440, 900, 85, 0 }, 706 { 1400, 1050, 60, 1 }, 707 { 1400, 1050, 60, 0 }, 708 { 1400, 1050, 75, 0 }, 709 /* byte 9 */ 710 { 1400, 1050, 85, 0 }, 711 { 1680, 1050, 60, 1 }, 712 { 1680, 1050, 60, 0 }, 713 { 1680, 1050, 75, 0 }, 714 { 1680, 1050, 85, 0 }, 715 { 1600, 1200, 60, 0 }, 716 { 1600, 1200, 65, 0 }, 717 { 1600, 1200, 70, 0 }, 718 /* byte 10 */ 719 { 1600, 1200, 75, 0 }, 720 { 1600, 1200, 85, 0 }, 721 { 1792, 1344, 60, 0 }, 722 { 1792, 1344, 75, 0 }, 723 { 1856, 1392, 60, 0 }, 724 { 1856, 1392, 75, 0 }, 725 { 1920, 1200, 60, 1 }, 726 { 1920, 1200, 60, 0 }, 727 /* byte 11 */ 728 { 1920, 1200, 75, 0 }, 729 { 1920, 1200, 85, 0 }, 730 { 1920, 1440, 60, 0 }, 731 { 1920, 1440, 75, 0 }, 732 }; 733 734 static const struct minimode extra_modes[] = { 735 { 1024, 576, 60, 0 }, 736 { 1366, 768, 60, 0 }, 737 { 1600, 900, 60, 0 }, 738 { 1680, 945, 60, 0 }, 739 { 1920, 1080, 60, 0 }, 740 { 2048, 1152, 60, 0 }, 741 { 2048, 1536, 60, 0 }, 742 }; 743 744 /* 745 * From CEA/CTA-861 spec. 746 * 747 * Do not access directly, instead always use cea_mode_for_vic(). 748 */ 749 static const struct drm_display_mode edid_cea_modes_1[] = { 750 /* 1 - 640x480@60Hz 4:3 */ 751 { DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656, 752 752, 800, 0, 480, 490, 492, 525, 0, 753 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 754 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 755 /* 2 - 720x480@60Hz 4:3 */ 756 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 757 798, 858, 0, 480, 489, 495, 525, 0, 758 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 759 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 760 /* 3 - 720x480@60Hz 16:9 */ 761 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 27000, 720, 736, 762 798, 858, 0, 480, 489, 495, 525, 0, 763 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 764 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 765 /* 4 - 1280x720@60Hz 16:9 */ 766 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 767 1430, 1650, 0, 720, 725, 730, 750, 0, 768 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 769 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 770 /* 5 - 1920x1080i@60Hz 16:9 */ 771 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 772 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 773 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 774 DRM_MODE_FLAG_INTERLACE), 775 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 776 /* 6 - 720(1440)x480i@60Hz 4:3 */ 777 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 778 801, 858, 0, 480, 488, 494, 525, 0, 779 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 780 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 781 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 782 /* 7 - 720(1440)x480i@60Hz 16:9 */ 783 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 784 801, 858, 0, 480, 488, 494, 525, 0, 785 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 786 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 787 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 788 /* 8 - 720(1440)x240@60Hz 4:3 */ 789 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 790 801, 858, 0, 240, 244, 247, 262, 0, 791 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 792 DRM_MODE_FLAG_DBLCLK), 793 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 794 /* 9 - 720(1440)x240@60Hz 16:9 */ 795 { DRM_MODE("720x240", DRM_MODE_TYPE_DRIVER, 13500, 720, 739, 796 801, 858, 0, 240, 244, 247, 262, 0, 797 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 798 DRM_MODE_FLAG_DBLCLK), 799 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 800 /* 10 - 2880x480i@60Hz 4:3 */ 801 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 802 3204, 3432, 0, 480, 488, 494, 525, 0, 803 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 804 DRM_MODE_FLAG_INTERLACE), 805 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 806 /* 11 - 2880x480i@60Hz 16:9 */ 807 { DRM_MODE("2880x480i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 808 3204, 3432, 0, 480, 488, 494, 525, 0, 809 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 810 DRM_MODE_FLAG_INTERLACE), 811 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 812 /* 12 - 2880x240@60Hz 4:3 */ 813 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 814 3204, 3432, 0, 240, 244, 247, 262, 0, 815 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 816 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 817 /* 13 - 2880x240@60Hz 16:9 */ 818 { DRM_MODE("2880x240", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2956, 819 3204, 3432, 0, 240, 244, 247, 262, 0, 820 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 821 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 822 /* 14 - 1440x480@60Hz 4:3 */ 823 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 824 1596, 1716, 0, 480, 489, 495, 525, 0, 825 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 826 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 827 /* 15 - 1440x480@60Hz 16:9 */ 828 { DRM_MODE("1440x480", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1472, 829 1596, 1716, 0, 480, 489, 495, 525, 0, 830 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 831 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 832 /* 16 - 1920x1080@60Hz 16:9 */ 833 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 834 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 835 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 836 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 837 /* 17 - 720x576@50Hz 4:3 */ 838 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 839 796, 864, 0, 576, 581, 586, 625, 0, 840 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 841 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 842 /* 18 - 720x576@50Hz 16:9 */ 843 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 844 796, 864, 0, 576, 581, 586, 625, 0, 845 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 846 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 847 /* 19 - 1280x720@50Hz 16:9 */ 848 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 849 1760, 1980, 0, 720, 725, 730, 750, 0, 850 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 851 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 852 /* 20 - 1920x1080i@50Hz 16:9 */ 853 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 854 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 855 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 856 DRM_MODE_FLAG_INTERLACE), 857 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 858 /* 21 - 720(1440)x576i@50Hz 4:3 */ 859 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 860 795, 864, 0, 576, 580, 586, 625, 0, 861 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 862 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 863 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 864 /* 22 - 720(1440)x576i@50Hz 16:9 */ 865 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 866 795, 864, 0, 576, 580, 586, 625, 0, 867 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 868 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 869 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 870 /* 23 - 720(1440)x288@50Hz 4:3 */ 871 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 872 795, 864, 0, 288, 290, 293, 312, 0, 873 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 874 DRM_MODE_FLAG_DBLCLK), 875 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 876 /* 24 - 720(1440)x288@50Hz 16:9 */ 877 { DRM_MODE("720x288", DRM_MODE_TYPE_DRIVER, 13500, 720, 732, 878 795, 864, 0, 288, 290, 293, 312, 0, 879 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 880 DRM_MODE_FLAG_DBLCLK), 881 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 882 /* 25 - 2880x576i@50Hz 4:3 */ 883 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 884 3180, 3456, 0, 576, 580, 586, 625, 0, 885 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 886 DRM_MODE_FLAG_INTERLACE), 887 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 888 /* 26 - 2880x576i@50Hz 16:9 */ 889 { DRM_MODE("2880x576i", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 890 3180, 3456, 0, 576, 580, 586, 625, 0, 891 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 892 DRM_MODE_FLAG_INTERLACE), 893 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 894 /* 27 - 2880x288@50Hz 4:3 */ 895 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 896 3180, 3456, 0, 288, 290, 293, 312, 0, 897 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 898 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 899 /* 28 - 2880x288@50Hz 16:9 */ 900 { DRM_MODE("2880x288", DRM_MODE_TYPE_DRIVER, 54000, 2880, 2928, 901 3180, 3456, 0, 288, 290, 293, 312, 0, 902 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 903 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 904 /* 29 - 1440x576@50Hz 4:3 */ 905 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 906 1592, 1728, 0, 576, 581, 586, 625, 0, 907 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 908 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 909 /* 30 - 1440x576@50Hz 16:9 */ 910 { DRM_MODE("1440x576", DRM_MODE_TYPE_DRIVER, 54000, 1440, 1464, 911 1592, 1728, 0, 576, 581, 586, 625, 0, 912 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 913 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 914 /* 31 - 1920x1080@50Hz 16:9 */ 915 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 916 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 917 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 918 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 919 /* 32 - 1920x1080@24Hz 16:9 */ 920 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 921 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 922 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 923 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 924 /* 33 - 1920x1080@25Hz 16:9 */ 925 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 926 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 927 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 928 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 929 /* 34 - 1920x1080@30Hz 16:9 */ 930 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 931 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 932 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 933 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 934 /* 35 - 2880x480@60Hz 4:3 */ 935 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 936 3192, 3432, 0, 480, 489, 495, 525, 0, 937 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 938 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 939 /* 36 - 2880x480@60Hz 16:9 */ 940 { DRM_MODE("2880x480", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2944, 941 3192, 3432, 0, 480, 489, 495, 525, 0, 942 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 943 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 944 /* 37 - 2880x576@50Hz 4:3 */ 945 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 946 3184, 3456, 0, 576, 581, 586, 625, 0, 947 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 948 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 949 /* 38 - 2880x576@50Hz 16:9 */ 950 { DRM_MODE("2880x576", DRM_MODE_TYPE_DRIVER, 108000, 2880, 2928, 951 3184, 3456, 0, 576, 581, 586, 625, 0, 952 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 953 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 954 /* 39 - 1920x1080i@50Hz 16:9 */ 955 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 72000, 1920, 1952, 956 2120, 2304, 0, 1080, 1126, 1136, 1250, 0, 957 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NVSYNC | 958 DRM_MODE_FLAG_INTERLACE), 959 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 960 /* 40 - 1920x1080i@100Hz 16:9 */ 961 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 962 2492, 2640, 0, 1080, 1084, 1094, 1125, 0, 963 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 964 DRM_MODE_FLAG_INTERLACE), 965 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 966 /* 41 - 1280x720@100Hz 16:9 */ 967 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 968 1760, 1980, 0, 720, 725, 730, 750, 0, 969 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 970 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 971 /* 42 - 720x576@100Hz 4:3 */ 972 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 973 796, 864, 0, 576, 581, 586, 625, 0, 974 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 975 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 976 /* 43 - 720x576@100Hz 16:9 */ 977 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 978 796, 864, 0, 576, 581, 586, 625, 0, 979 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 980 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 981 /* 44 - 720(1440)x576i@100Hz 4:3 */ 982 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 983 795, 864, 0, 576, 580, 586, 625, 0, 984 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 985 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 986 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 987 /* 45 - 720(1440)x576i@100Hz 16:9 */ 988 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 27000, 720, 732, 989 795, 864, 0, 576, 580, 586, 625, 0, 990 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 991 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 992 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 993 /* 46 - 1920x1080i@120Hz 16:9 */ 994 { DRM_MODE("1920x1080i", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 995 2052, 2200, 0, 1080, 1084, 1094, 1125, 0, 996 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC | 997 DRM_MODE_FLAG_INTERLACE), 998 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 999 /* 47 - 1280x720@120Hz 16:9 */ 1000 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1001 1430, 1650, 0, 720, 725, 730, 750, 0, 1002 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1003 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1004 /* 48 - 720x480@120Hz 4:3 */ 1005 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 1006 798, 858, 0, 480, 489, 495, 525, 0, 1007 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1008 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1009 /* 49 - 720x480@120Hz 16:9 */ 1010 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 54000, 720, 736, 1011 798, 858, 0, 480, 489, 495, 525, 0, 1012 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1013 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1014 /* 50 - 720(1440)x480i@120Hz 4:3 */ 1015 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1016 801, 858, 0, 480, 488, 494, 525, 0, 1017 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1018 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1019 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1020 /* 51 - 720(1440)x480i@120Hz 16:9 */ 1021 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 27000, 720, 739, 1022 801, 858, 0, 480, 488, 494, 525, 0, 1023 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1024 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1025 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1026 /* 52 - 720x576@200Hz 4:3 */ 1027 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1028 796, 864, 0, 576, 581, 586, 625, 0, 1029 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1030 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1031 /* 53 - 720x576@200Hz 16:9 */ 1032 { DRM_MODE("720x576", DRM_MODE_TYPE_DRIVER, 108000, 720, 732, 1033 796, 864, 0, 576, 581, 586, 625, 0, 1034 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1035 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1036 /* 54 - 720(1440)x576i@200Hz 4:3 */ 1037 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1038 795, 864, 0, 576, 580, 586, 625, 0, 1039 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1040 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1041 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1042 /* 55 - 720(1440)x576i@200Hz 16:9 */ 1043 { DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 54000, 720, 732, 1044 795, 864, 0, 576, 580, 586, 625, 0, 1045 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1046 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1047 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1048 /* 56 - 720x480@240Hz 4:3 */ 1049 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1050 798, 858, 0, 480, 489, 495, 525, 0, 1051 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1052 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1053 /* 57 - 720x480@240Hz 16:9 */ 1054 { DRM_MODE("720x480", DRM_MODE_TYPE_DRIVER, 108000, 720, 736, 1055 798, 858, 0, 480, 489, 495, 525, 0, 1056 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC), 1057 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1058 /* 58 - 720(1440)x480i@240Hz 4:3 */ 1059 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1060 801, 858, 0, 480, 488, 494, 525, 0, 1061 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1062 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1063 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_4_3, }, 1064 /* 59 - 720(1440)x480i@240Hz 16:9 */ 1065 { DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 54000, 720, 739, 1066 801, 858, 0, 480, 488, 494, 525, 0, 1067 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC | 1068 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK), 1069 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1070 /* 60 - 1280x720@24Hz 16:9 */ 1071 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1072 3080, 3300, 0, 720, 725, 730, 750, 0, 1073 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1074 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1075 /* 61 - 1280x720@25Hz 16:9 */ 1076 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1077 3740, 3960, 0, 720, 725, 730, 750, 0, 1078 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1079 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1080 /* 62 - 1280x720@30Hz 16:9 */ 1081 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1082 3080, 3300, 0, 720, 725, 730, 750, 0, 1083 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1084 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1085 /* 63 - 1920x1080@120Hz 16:9 */ 1086 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1087 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1088 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1089 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1090 /* 64 - 1920x1080@100Hz 16:9 */ 1091 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1092 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1093 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1094 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1095 /* 65 - 1280x720@24Hz 64:27 */ 1096 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 59400, 1280, 3040, 1097 3080, 3300, 0, 720, 725, 730, 750, 0, 1098 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1099 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1100 /* 66 - 1280x720@25Hz 64:27 */ 1101 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3700, 1102 3740, 3960, 0, 720, 725, 730, 750, 0, 1103 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1104 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1105 /* 67 - 1280x720@30Hz 64:27 */ 1106 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 3040, 1107 3080, 3300, 0, 720, 725, 730, 750, 0, 1108 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1109 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1110 /* 68 - 1280x720@50Hz 64:27 */ 1111 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720, 1112 1760, 1980, 0, 720, 725, 730, 750, 0, 1113 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1114 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1115 /* 69 - 1280x720@60Hz 64:27 */ 1116 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390, 1117 1430, 1650, 0, 720, 725, 730, 750, 0, 1118 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1119 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1120 /* 70 - 1280x720@100Hz 64:27 */ 1121 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1720, 1122 1760, 1980, 0, 720, 725, 730, 750, 0, 1123 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1124 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1125 /* 71 - 1280x720@120Hz 64:27 */ 1126 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 148500, 1280, 1390, 1127 1430, 1650, 0, 720, 725, 730, 750, 0, 1128 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1129 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1130 /* 72 - 1920x1080@24Hz 64:27 */ 1131 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2558, 1132 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1133 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1134 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1135 /* 73 - 1920x1080@25Hz 64:27 */ 1136 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2448, 1137 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1138 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1139 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1140 /* 74 - 1920x1080@30Hz 64:27 */ 1141 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 74250, 1920, 2008, 1142 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1143 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1144 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1145 /* 75 - 1920x1080@50Hz 64:27 */ 1146 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2448, 1147 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1148 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1149 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1150 /* 76 - 1920x1080@60Hz 64:27 */ 1151 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2008, 1152 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1153 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1154 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1155 /* 77 - 1920x1080@100Hz 64:27 */ 1156 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2448, 1157 2492, 2640, 0, 1080, 1084, 1089, 1125, 0, 1158 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1159 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1160 /* 78 - 1920x1080@120Hz 64:27 */ 1161 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 297000, 1920, 2008, 1162 2052, 2200, 0, 1080, 1084, 1089, 1125, 0, 1163 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1164 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1165 /* 79 - 1680x720@24Hz 64:27 */ 1166 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 3040, 1167 3080, 3300, 0, 720, 725, 730, 750, 0, 1168 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1169 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1170 /* 80 - 1680x720@25Hz 64:27 */ 1171 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2908, 1172 2948, 3168, 0, 720, 725, 730, 750, 0, 1173 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1174 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1175 /* 81 - 1680x720@30Hz 64:27 */ 1176 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 59400, 1680, 2380, 1177 2420, 2640, 0, 720, 725, 730, 750, 0, 1178 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1179 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1180 /* 82 - 1680x720@50Hz 64:27 */ 1181 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 82500, 1680, 1940, 1182 1980, 2200, 0, 720, 725, 730, 750, 0, 1183 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1184 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1185 /* 83 - 1680x720@60Hz 64:27 */ 1186 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 1940, 1187 1980, 2200, 0, 720, 725, 730, 750, 0, 1188 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1189 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1190 /* 84 - 1680x720@100Hz 64:27 */ 1191 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 165000, 1680, 1740, 1192 1780, 2000, 0, 720, 725, 730, 825, 0, 1193 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1194 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1195 /* 85 - 1680x720@120Hz 64:27 */ 1196 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 198000, 1680, 1740, 1197 1780, 2000, 0, 720, 725, 730, 825, 0, 1198 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1199 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1200 /* 86 - 2560x1080@24Hz 64:27 */ 1201 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 99000, 2560, 3558, 1202 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1203 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1204 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1205 /* 87 - 2560x1080@25Hz 64:27 */ 1206 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 90000, 2560, 3008, 1207 3052, 3200, 0, 1080, 1084, 1089, 1125, 0, 1208 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1209 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1210 /* 88 - 2560x1080@30Hz 64:27 */ 1211 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 118800, 2560, 3328, 1212 3372, 3520, 0, 1080, 1084, 1089, 1125, 0, 1213 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1214 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1215 /* 89 - 2560x1080@50Hz 64:27 */ 1216 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 185625, 2560, 3108, 1217 3152, 3300, 0, 1080, 1084, 1089, 1125, 0, 1218 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1219 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1220 /* 90 - 2560x1080@60Hz 64:27 */ 1221 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 2808, 1222 2852, 3000, 0, 1080, 1084, 1089, 1100, 0, 1223 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1224 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1225 /* 91 - 2560x1080@100Hz 64:27 */ 1226 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 371250, 2560, 2778, 1227 2822, 2970, 0, 1080, 1084, 1089, 1250, 0, 1228 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1229 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1230 /* 92 - 2560x1080@120Hz 64:27 */ 1231 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 495000, 2560, 3108, 1232 3152, 3300, 0, 1080, 1084, 1089, 1250, 0, 1233 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1234 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1235 /* 93 - 3840x2160@24Hz 16:9 */ 1236 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1237 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1238 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1239 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1240 /* 94 - 3840x2160@25Hz 16:9 */ 1241 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1242 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1243 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1244 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1245 /* 95 - 3840x2160@30Hz 16:9 */ 1246 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1247 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1248 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1249 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1250 /* 96 - 3840x2160@50Hz 16:9 */ 1251 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1252 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1253 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1254 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1255 /* 97 - 3840x2160@60Hz 16:9 */ 1256 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1257 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1258 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1259 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1260 /* 98 - 4096x2160@24Hz 256:135 */ 1261 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5116, 1262 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1263 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1264 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1265 /* 99 - 4096x2160@25Hz 256:135 */ 1266 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 5064, 1267 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1268 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1269 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1270 /* 100 - 4096x2160@30Hz 256:135 */ 1271 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 4096, 4184, 1272 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1273 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1274 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1275 /* 101 - 4096x2160@50Hz 256:135 */ 1276 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5064, 1277 5152, 5280, 0, 2160, 2168, 2178, 2250, 0, 1278 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1279 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1280 /* 102 - 4096x2160@60Hz 256:135 */ 1281 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 4184, 1282 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1283 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1284 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1285 /* 103 - 3840x2160@24Hz 64:27 */ 1286 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 5116, 1287 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1288 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1289 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1290 /* 104 - 3840x2160@25Hz 64:27 */ 1291 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4896, 1292 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1293 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1294 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1295 /* 105 - 3840x2160@30Hz 64:27 */ 1296 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 3840, 4016, 1297 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1298 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1299 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1300 /* 106 - 3840x2160@50Hz 64:27 */ 1301 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4896, 1302 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1303 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1304 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1305 /* 107 - 3840x2160@60Hz 64:27 */ 1306 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 4016, 1307 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1308 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1309 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1310 /* 108 - 1280x720@48Hz 16:9 */ 1311 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1312 2280, 2500, 0, 720, 725, 730, 750, 0, 1313 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1314 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1315 /* 109 - 1280x720@48Hz 64:27 */ 1316 { DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 90000, 1280, 2240, 1317 2280, 2500, 0, 720, 725, 730, 750, 0, 1318 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1319 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1320 /* 110 - 1680x720@48Hz 64:27 */ 1321 { DRM_MODE("1680x720", DRM_MODE_TYPE_DRIVER, 99000, 1680, 2490, 1322 2530, 2750, 0, 720, 725, 730, 750, 0, 1323 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1324 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1325 /* 111 - 1920x1080@48Hz 16:9 */ 1326 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1327 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1328 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1329 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1330 /* 112 - 1920x1080@48Hz 64:27 */ 1331 { DRM_MODE("1920x1080", DRM_MODE_TYPE_DRIVER, 148500, 1920, 2558, 1332 2602, 2750, 0, 1080, 1084, 1089, 1125, 0, 1333 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1334 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1335 /* 113 - 2560x1080@48Hz 64:27 */ 1336 { DRM_MODE("2560x1080", DRM_MODE_TYPE_DRIVER, 198000, 2560, 3558, 1337 3602, 3750, 0, 1080, 1084, 1089, 1100, 0, 1338 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1339 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1340 /* 114 - 3840x2160@48Hz 16:9 */ 1341 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1342 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1343 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1344 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1345 /* 115 - 4096x2160@48Hz 256:135 */ 1346 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 594000, 4096, 5116, 1347 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1348 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1349 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1350 /* 116 - 3840x2160@48Hz 64:27 */ 1351 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 594000, 3840, 5116, 1352 5204, 5500, 0, 2160, 2168, 2178, 2250, 0, 1353 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1354 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1355 /* 117 - 3840x2160@100Hz 16:9 */ 1356 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1357 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1358 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1359 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1360 /* 118 - 3840x2160@120Hz 16:9 */ 1361 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1362 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1363 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1364 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1365 /* 119 - 3840x2160@100Hz 64:27 */ 1366 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4896, 1367 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1368 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1369 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1370 /* 120 - 3840x2160@120Hz 64:27 */ 1371 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 1188000, 3840, 4016, 1372 4104, 4400, 0, 2160, 2168, 2178, 2250, 0, 1373 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1374 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1375 /* 121 - 5120x2160@24Hz 64:27 */ 1376 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 7116, 1377 7204, 7500, 0, 2160, 2168, 2178, 2200, 0, 1378 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1379 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1380 /* 122 - 5120x2160@25Hz 64:27 */ 1381 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 6816, 1382 6904, 7200, 0, 2160, 2168, 2178, 2200, 0, 1383 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1384 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1385 /* 123 - 5120x2160@30Hz 64:27 */ 1386 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 396000, 5120, 5784, 1387 5872, 6000, 0, 2160, 2168, 2178, 2200, 0, 1388 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1389 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1390 /* 124 - 5120x2160@48Hz 64:27 */ 1391 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5866, 1392 5954, 6250, 0, 2160, 2168, 2178, 2475, 0, 1393 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1394 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1395 /* 125 - 5120x2160@50Hz 64:27 */ 1396 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 6216, 1397 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1398 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1399 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1400 /* 126 - 5120x2160@60Hz 64:27 */ 1401 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 742500, 5120, 5284, 1402 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1403 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1404 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1405 /* 127 - 5120x2160@100Hz 64:27 */ 1406 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 6216, 1407 6304, 6600, 0, 2160, 2168, 2178, 2250, 0, 1408 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1409 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1410 }; 1411 1412 /* 1413 * From CEA/CTA-861 spec. 1414 * 1415 * Do not access directly, instead always use cea_mode_for_vic(). 1416 */ 1417 static const struct drm_display_mode edid_cea_modes_193[] = { 1418 /* 193 - 5120x2160@120Hz 64:27 */ 1419 { DRM_MODE("5120x2160", DRM_MODE_TYPE_DRIVER, 1485000, 5120, 5284, 1420 5372, 5500, 0, 2160, 2168, 2178, 2250, 0, 1421 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1422 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1423 /* 194 - 7680x4320@24Hz 16:9 */ 1424 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1425 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1426 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1427 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1428 /* 195 - 7680x4320@25Hz 16:9 */ 1429 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1430 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1431 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1432 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1433 /* 196 - 7680x4320@30Hz 16:9 */ 1434 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1435 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1436 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1437 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1438 /* 197 - 7680x4320@48Hz 16:9 */ 1439 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1440 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1441 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1442 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1443 /* 198 - 7680x4320@50Hz 16:9 */ 1444 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1445 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1446 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1447 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1448 /* 199 - 7680x4320@60Hz 16:9 */ 1449 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1450 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1451 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1452 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1453 /* 200 - 7680x4320@100Hz 16:9 */ 1454 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1455 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1456 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1457 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1458 /* 201 - 7680x4320@120Hz 16:9 */ 1459 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1460 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1461 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1462 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1463 /* 202 - 7680x4320@24Hz 64:27 */ 1464 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10232, 1465 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1466 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1467 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1468 /* 203 - 7680x4320@25Hz 64:27 */ 1469 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 10032, 1470 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1471 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1472 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1473 /* 204 - 7680x4320@30Hz 64:27 */ 1474 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 1188000, 7680, 8232, 1475 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1476 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1477 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1478 /* 205 - 7680x4320@48Hz 64:27 */ 1479 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10232, 1480 10408, 11000, 0, 4320, 4336, 4356, 4500, 0, 1481 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1482 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1483 /* 206 - 7680x4320@50Hz 64:27 */ 1484 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 10032, 1485 10208, 10800, 0, 4320, 4336, 4356, 4400, 0, 1486 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1487 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1488 /* 207 - 7680x4320@60Hz 64:27 */ 1489 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 2376000, 7680, 8232, 1490 8408, 9000, 0, 4320, 4336, 4356, 4400, 0, 1491 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1492 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1493 /* 208 - 7680x4320@100Hz 64:27 */ 1494 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 9792, 1495 9968, 10560, 0, 4320, 4336, 4356, 4500, 0, 1496 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1497 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1498 /* 209 - 7680x4320@120Hz 64:27 */ 1499 { DRM_MODE("7680x4320", DRM_MODE_TYPE_DRIVER, 4752000, 7680, 8032, 1500 8208, 8800, 0, 4320, 4336, 4356, 4500, 0, 1501 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1502 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1503 /* 210 - 10240x4320@24Hz 64:27 */ 1504 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 11732, 1505 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1506 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1507 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1508 /* 211 - 10240x4320@25Hz 64:27 */ 1509 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 12732, 1510 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1511 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1512 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1513 /* 212 - 10240x4320@30Hz 64:27 */ 1514 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 1485000, 10240, 10528, 1515 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1516 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1517 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1518 /* 213 - 10240x4320@48Hz 64:27 */ 1519 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 11732, 1520 11908, 12500, 0, 4320, 4336, 4356, 4950, 0, 1521 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1522 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1523 /* 214 - 10240x4320@50Hz 64:27 */ 1524 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 12732, 1525 12908, 13500, 0, 4320, 4336, 4356, 4400, 0, 1526 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1527 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1528 /* 215 - 10240x4320@60Hz 64:27 */ 1529 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 2970000, 10240, 10528, 1530 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1531 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1532 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1533 /* 216 - 10240x4320@100Hz 64:27 */ 1534 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 12432, 1535 12608, 13200, 0, 4320, 4336, 4356, 4500, 0, 1536 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1537 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1538 /* 217 - 10240x4320@120Hz 64:27 */ 1539 { DRM_MODE("10240x4320", DRM_MODE_TYPE_DRIVER, 5940000, 10240, 10528, 1540 10704, 11000, 0, 4320, 4336, 4356, 4500, 0, 1541 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1542 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_64_27, }, 1543 /* 218 - 4096x2160@100Hz 256:135 */ 1544 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4896, 1545 4984, 5280, 0, 2160, 2168, 2178, 2250, 0, 1546 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1547 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1548 /* 219 - 4096x2160@120Hz 256:135 */ 1549 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 1188000, 4096, 4184, 1550 4272, 4400, 0, 2160, 2168, 2178, 2250, 0, 1551 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1552 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1553 }; 1554 1555 /* 1556 * HDMI 1.4 4k modes. Index using the VIC. 1557 */ 1558 static const struct drm_display_mode edid_4k_modes[] = { 1559 /* 0 - dummy, VICs start at 1 */ 1560 { }, 1561 /* 1 - 3840x2160@30Hz */ 1562 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1563 3840, 4016, 4104, 4400, 0, 1564 2160, 2168, 2178, 2250, 0, 1565 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1566 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1567 /* 2 - 3840x2160@25Hz */ 1568 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1569 3840, 4896, 4984, 5280, 0, 1570 2160, 2168, 2178, 2250, 0, 1571 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1572 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1573 /* 3 - 3840x2160@24Hz */ 1574 { DRM_MODE("3840x2160", DRM_MODE_TYPE_DRIVER, 297000, 1575 3840, 5116, 5204, 5500, 0, 1576 2160, 2168, 2178, 2250, 0, 1577 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1578 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_16_9, }, 1579 /* 4 - 4096x2160@24Hz (SMPTE) */ 1580 { DRM_MODE("4096x2160", DRM_MODE_TYPE_DRIVER, 297000, 1581 4096, 5116, 5204, 5500, 0, 1582 2160, 2168, 2178, 2250, 0, 1583 DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC), 1584 .picture_aspect_ratio = HDMI_PICTURE_ASPECT_256_135, }, 1585 }; 1586 1587 /*** DDC fetch and block validation ***/ 1588 1589 /* 1590 * The opaque EDID type, internal to drm_edid.c. 1591 */ 1592 struct drm_edid { 1593 /* Size allocated for edid */ 1594 size_t size; 1595 const struct edid *edid; 1596 }; 1597 1598 static int edid_hfeeodb_extension_block_count(const struct edid *edid); 1599 1600 static int edid_hfeeodb_block_count(const struct edid *edid) 1601 { 1602 int eeodb = edid_hfeeodb_extension_block_count(edid); 1603 1604 return eeodb ? eeodb + 1 : 0; 1605 } 1606 1607 static int edid_extension_block_count(const struct edid *edid) 1608 { 1609 return edid->extensions; 1610 } 1611 1612 static int edid_block_count(const struct edid *edid) 1613 { 1614 return edid_extension_block_count(edid) + 1; 1615 } 1616 1617 static int edid_size_by_blocks(int num_blocks) 1618 { 1619 return num_blocks * EDID_LENGTH; 1620 } 1621 1622 static int edid_size(const struct edid *edid) 1623 { 1624 return edid_size_by_blocks(edid_block_count(edid)); 1625 } 1626 1627 static const void *edid_block_data(const struct edid *edid, int index) 1628 { 1629 BUILD_BUG_ON(sizeof(*edid) != EDID_LENGTH); 1630 1631 return edid + index; 1632 } 1633 1634 static const void *edid_extension_block_data(const struct edid *edid, int index) 1635 { 1636 return edid_block_data(edid, index + 1); 1637 } 1638 1639 /* EDID block count indicated in EDID, may exceed allocated size */ 1640 static int __drm_edid_block_count(const struct drm_edid *drm_edid) 1641 { 1642 int num_blocks; 1643 1644 /* Starting point */ 1645 num_blocks = edid_block_count(drm_edid->edid); 1646 1647 /* HF-EEODB override */ 1648 if (drm_edid->size >= edid_size_by_blocks(2)) { 1649 int eeodb; 1650 1651 /* 1652 * Note: HF-EEODB may specify a smaller extension count than the 1653 * regular one. Unlike in buffer allocation, here we can use it. 1654 */ 1655 eeodb = edid_hfeeodb_block_count(drm_edid->edid); 1656 if (eeodb) 1657 num_blocks = eeodb; 1658 } 1659 1660 return num_blocks; 1661 } 1662 1663 /* EDID block count, limited by allocated size */ 1664 static int drm_edid_block_count(const struct drm_edid *drm_edid) 1665 { 1666 /* Limit by allocated size */ 1667 return min(__drm_edid_block_count(drm_edid), 1668 (int)drm_edid->size / EDID_LENGTH); 1669 } 1670 1671 /* EDID extension block count, limited by allocated size */ 1672 static int drm_edid_extension_block_count(const struct drm_edid *drm_edid) 1673 { 1674 return drm_edid_block_count(drm_edid) - 1; 1675 } 1676 1677 static const void *drm_edid_block_data(const struct drm_edid *drm_edid, int index) 1678 { 1679 return edid_block_data(drm_edid->edid, index); 1680 } 1681 1682 static const void *drm_edid_extension_block_data(const struct drm_edid *drm_edid, 1683 int index) 1684 { 1685 return edid_extension_block_data(drm_edid->edid, index); 1686 } 1687 1688 /* 1689 * Initializer helper for legacy interfaces, where we have no choice but to 1690 * trust edid size. Not for general purpose use. 1691 */ 1692 static const struct drm_edid *drm_edid_legacy_init(struct drm_edid *drm_edid, 1693 const struct edid *edid) 1694 { 1695 if (!edid) 1696 return NULL; 1697 1698 memset(drm_edid, 0, sizeof(*drm_edid)); 1699 1700 drm_edid->edid = edid; 1701 drm_edid->size = edid_size(edid); 1702 1703 return drm_edid; 1704 } 1705 1706 /* 1707 * EDID base and extension block iterator. 1708 * 1709 * struct drm_edid_iter iter; 1710 * const u8 *block; 1711 * 1712 * drm_edid_iter_begin(drm_edid, &iter); 1713 * drm_edid_iter_for_each(block, &iter) { 1714 * // do stuff with block 1715 * } 1716 * drm_edid_iter_end(&iter); 1717 */ 1718 struct drm_edid_iter { 1719 const struct drm_edid *drm_edid; 1720 1721 /* Current block index. */ 1722 int index; 1723 }; 1724 1725 static void drm_edid_iter_begin(const struct drm_edid *drm_edid, 1726 struct drm_edid_iter *iter) 1727 { 1728 memset(iter, 0, sizeof(*iter)); 1729 1730 iter->drm_edid = drm_edid; 1731 } 1732 1733 static const void *__drm_edid_iter_next(struct drm_edid_iter *iter) 1734 { 1735 const void *block = NULL; 1736 1737 if (!iter->drm_edid) 1738 return NULL; 1739 1740 if (iter->index < drm_edid_block_count(iter->drm_edid)) 1741 block = drm_edid_block_data(iter->drm_edid, iter->index++); 1742 1743 return block; 1744 } 1745 1746 #define drm_edid_iter_for_each(__block, __iter) \ 1747 while (((__block) = __drm_edid_iter_next(__iter))) 1748 1749 static void drm_edid_iter_end(struct drm_edid_iter *iter) 1750 { 1751 memset(iter, 0, sizeof(*iter)); 1752 } 1753 1754 static const u8 edid_header[] = { 1755 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00 1756 }; 1757 1758 static void edid_header_fix(void *edid) 1759 { 1760 memcpy(edid, edid_header, sizeof(edid_header)); 1761 } 1762 1763 /** 1764 * drm_edid_header_is_valid - sanity check the header of the base EDID block 1765 * @_edid: pointer to raw base EDID block 1766 * 1767 * Sanity check the header of the base EDID block. 1768 * 1769 * Return: 8 if the header is perfect, down to 0 if it's totally wrong. 1770 */ 1771 int drm_edid_header_is_valid(const void *_edid) 1772 { 1773 const struct edid *edid = _edid; 1774 int i, score = 0; 1775 1776 for (i = 0; i < sizeof(edid_header); i++) { 1777 if (edid->header[i] == edid_header[i]) 1778 score++; 1779 } 1780 1781 return score; 1782 } 1783 EXPORT_SYMBOL(drm_edid_header_is_valid); 1784 1785 static int edid_fixup __read_mostly = 6; 1786 module_param_named(edid_fixup, edid_fixup, int, 0400); 1787 MODULE_PARM_DESC(edid_fixup, 1788 "Minimum number of valid EDID header bytes (0-8, default 6)"); 1789 1790 static int edid_block_compute_checksum(const void *_block) 1791 { 1792 const u8 *block = _block; 1793 int i; 1794 u8 csum = 0, crc = 0; 1795 1796 for (i = 0; i < EDID_LENGTH - 1; i++) 1797 csum += block[i]; 1798 1799 crc = 0x100 - csum; 1800 1801 return crc; 1802 } 1803 1804 static int edid_block_get_checksum(const void *_block) 1805 { 1806 const struct edid *block = _block; 1807 1808 return block->checksum; 1809 } 1810 1811 static int edid_block_tag(const void *_block) 1812 { 1813 const u8 *block = _block; 1814 1815 return block[0]; 1816 } 1817 1818 static bool edid_block_is_zero(const void *edid) 1819 { 1820 return !memchr_inv(edid, 0, EDID_LENGTH); 1821 } 1822 1823 static bool drm_edid_eq(const struct drm_edid *drm_edid, 1824 const void *raw_edid, size_t raw_edid_size) 1825 { 1826 bool edid1_present = drm_edid && drm_edid->edid && drm_edid->size; 1827 bool edid2_present = raw_edid && raw_edid_size; 1828 1829 if (edid1_present != edid2_present) 1830 return false; 1831 1832 if (edid1_present) { 1833 if (drm_edid->size != raw_edid_size) 1834 return false; 1835 1836 if (memcmp(drm_edid->edid, raw_edid, drm_edid->size)) 1837 return false; 1838 } 1839 1840 return true; 1841 } 1842 1843 enum edid_block_status { 1844 EDID_BLOCK_OK = 0, 1845 EDID_BLOCK_READ_FAIL, 1846 EDID_BLOCK_NULL, 1847 EDID_BLOCK_ZERO, 1848 EDID_BLOCK_HEADER_CORRUPT, 1849 EDID_BLOCK_HEADER_REPAIR, 1850 EDID_BLOCK_HEADER_FIXED, 1851 EDID_BLOCK_CHECKSUM, 1852 EDID_BLOCK_VERSION, 1853 }; 1854 1855 static enum edid_block_status edid_block_check(const void *_block, 1856 bool is_base_block) 1857 { 1858 const struct edid *block = _block; 1859 1860 if (!block) 1861 return EDID_BLOCK_NULL; 1862 1863 if (is_base_block) { 1864 int score = drm_edid_header_is_valid(block); 1865 1866 if (score < clamp(edid_fixup, 0, 8)) { 1867 if (edid_block_is_zero(block)) 1868 return EDID_BLOCK_ZERO; 1869 else 1870 return EDID_BLOCK_HEADER_CORRUPT; 1871 } 1872 1873 if (score < 8) 1874 return EDID_BLOCK_HEADER_REPAIR; 1875 } 1876 1877 if (edid_block_compute_checksum(block) != edid_block_get_checksum(block)) { 1878 if (edid_block_is_zero(block)) 1879 return EDID_BLOCK_ZERO; 1880 else 1881 return EDID_BLOCK_CHECKSUM; 1882 } 1883 1884 if (is_base_block) { 1885 if (block->version != 1) 1886 return EDID_BLOCK_VERSION; 1887 } 1888 1889 return EDID_BLOCK_OK; 1890 } 1891 1892 static bool edid_block_status_valid(enum edid_block_status status, int tag) 1893 { 1894 return status == EDID_BLOCK_OK || 1895 status == EDID_BLOCK_HEADER_FIXED || 1896 (status == EDID_BLOCK_CHECKSUM && tag == CEA_EXT); 1897 } 1898 1899 static bool edid_block_valid(const void *block, bool base) 1900 { 1901 return edid_block_status_valid(edid_block_check(block, base), 1902 edid_block_tag(block)); 1903 } 1904 1905 static void edid_block_status_print(enum edid_block_status status, 1906 const struct edid *block, 1907 int block_num) 1908 { 1909 switch (status) { 1910 case EDID_BLOCK_OK: 1911 break; 1912 case EDID_BLOCK_READ_FAIL: 1913 pr_debug("EDID block %d read failed\n", block_num); 1914 break; 1915 case EDID_BLOCK_NULL: 1916 pr_debug("EDID block %d pointer is NULL\n", block_num); 1917 break; 1918 case EDID_BLOCK_ZERO: 1919 pr_notice("EDID block %d is all zeroes\n", block_num); 1920 break; 1921 case EDID_BLOCK_HEADER_CORRUPT: 1922 pr_notice("EDID has corrupt header\n"); 1923 break; 1924 case EDID_BLOCK_HEADER_REPAIR: 1925 pr_debug("EDID corrupt header needs repair\n"); 1926 break; 1927 case EDID_BLOCK_HEADER_FIXED: 1928 pr_debug("EDID corrupt header fixed\n"); 1929 break; 1930 case EDID_BLOCK_CHECKSUM: 1931 if (edid_block_status_valid(status, edid_block_tag(block))) { 1932 pr_debug("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d, ignoring\n", 1933 block_num, edid_block_tag(block), 1934 edid_block_compute_checksum(block)); 1935 } else { 1936 pr_notice("EDID block %d (tag 0x%02x) checksum is invalid, remainder is %d\n", 1937 block_num, edid_block_tag(block), 1938 edid_block_compute_checksum(block)); 1939 } 1940 break; 1941 case EDID_BLOCK_VERSION: 1942 pr_notice("EDID has major version %d, instead of 1\n", 1943 block->version); 1944 break; 1945 default: 1946 WARN(1, "EDID block %d unknown edid block status code %d\n", 1947 block_num, status); 1948 break; 1949 } 1950 } 1951 1952 static void edid_block_dump(const char *level, const void *block, int block_num) 1953 { 1954 enum edid_block_status status; 1955 char prefix[20]; 1956 1957 status = edid_block_check(block, block_num == 0); 1958 if (status == EDID_BLOCK_ZERO) 1959 sprintf(prefix, "\t[%02x] ZERO ", block_num); 1960 else if (!edid_block_status_valid(status, edid_block_tag(block))) 1961 sprintf(prefix, "\t[%02x] BAD ", block_num); 1962 else 1963 sprintf(prefix, "\t[%02x] GOOD ", block_num); 1964 1965 print_hex_dump(level, prefix, DUMP_PREFIX_NONE, 16, 1, 1966 block, EDID_LENGTH, false); 1967 } 1968 1969 /** 1970 * drm_edid_block_valid - Sanity check the EDID block (base or extension) 1971 * @_block: pointer to raw EDID block 1972 * @block_num: type of block to validate (0 for base, extension otherwise) 1973 * @print_bad_edid: if true, dump bad EDID blocks to the console 1974 * @edid_corrupt: if true, the header or checksum is invalid 1975 * 1976 * Validate a base or extension EDID block and optionally dump bad blocks to 1977 * the console. 1978 * 1979 * Return: True if the block is valid, false otherwise. 1980 */ 1981 bool drm_edid_block_valid(u8 *_block, int block_num, bool print_bad_edid, 1982 bool *edid_corrupt) 1983 { 1984 struct edid *block = (struct edid *)_block; 1985 enum edid_block_status status; 1986 bool is_base_block = block_num == 0; 1987 bool valid; 1988 1989 if (WARN_ON(!block)) 1990 return false; 1991 1992 status = edid_block_check(block, is_base_block); 1993 if (status == EDID_BLOCK_HEADER_REPAIR) { 1994 DRM_DEBUG_KMS("Fixing EDID header, your hardware may be failing\n"); 1995 edid_header_fix(block); 1996 1997 /* Retry with fixed header, update status if that worked. */ 1998 status = edid_block_check(block, is_base_block); 1999 if (status == EDID_BLOCK_OK) 2000 status = EDID_BLOCK_HEADER_FIXED; 2001 } 2002 2003 if (edid_corrupt) { 2004 /* 2005 * Unknown major version isn't corrupt but we can't use it. Only 2006 * the base block can reset edid_corrupt to false. 2007 */ 2008 if (is_base_block && 2009 (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION)) 2010 *edid_corrupt = false; 2011 else if (status != EDID_BLOCK_OK) 2012 *edid_corrupt = true; 2013 } 2014 2015 edid_block_status_print(status, block, block_num); 2016 2017 /* Determine whether we can use this block with this status. */ 2018 valid = edid_block_status_valid(status, edid_block_tag(block)); 2019 2020 if (!valid && print_bad_edid && status != EDID_BLOCK_ZERO) { 2021 pr_notice("Raw EDID:\n"); 2022 edid_block_dump(KERN_NOTICE, block, block_num); 2023 } 2024 2025 return valid; 2026 } 2027 EXPORT_SYMBOL(drm_edid_block_valid); 2028 2029 /** 2030 * drm_edid_is_valid - sanity check EDID data 2031 * @edid: EDID data 2032 * 2033 * Sanity-check an entire EDID record (including extensions) 2034 * 2035 * Return: True if the EDID data is valid, false otherwise. 2036 */ 2037 bool drm_edid_is_valid(struct edid *edid) 2038 { 2039 int i; 2040 2041 if (!edid) 2042 return false; 2043 2044 for (i = 0; i < edid_block_count(edid); i++) { 2045 void *block = (void *)edid_block_data(edid, i); 2046 2047 if (!drm_edid_block_valid(block, i, true, NULL)) 2048 return false; 2049 } 2050 2051 return true; 2052 } 2053 EXPORT_SYMBOL(drm_edid_is_valid); 2054 2055 /** 2056 * drm_edid_valid - sanity check EDID data 2057 * @drm_edid: EDID data 2058 * 2059 * Sanity check an EDID. Cross check block count against allocated size and 2060 * checksum the blocks. 2061 * 2062 * Return: True if the EDID data is valid, false otherwise. 2063 */ 2064 bool drm_edid_valid(const struct drm_edid *drm_edid) 2065 { 2066 int i; 2067 2068 if (!drm_edid) 2069 return false; 2070 2071 if (edid_size_by_blocks(__drm_edid_block_count(drm_edid)) != drm_edid->size) 2072 return false; 2073 2074 for (i = 0; i < drm_edid_block_count(drm_edid); i++) { 2075 const void *block = drm_edid_block_data(drm_edid, i); 2076 2077 if (!edid_block_valid(block, i == 0)) 2078 return false; 2079 } 2080 2081 return true; 2082 } 2083 EXPORT_SYMBOL(drm_edid_valid); 2084 2085 static struct edid *edid_filter_invalid_blocks(struct edid *edid, 2086 size_t *alloc_size) 2087 { 2088 struct edid *new; 2089 int i, valid_blocks = 0; 2090 2091 /* 2092 * Note: If the EDID uses HF-EEODB, but has invalid blocks, we'll revert 2093 * back to regular extension count here. We don't want to start 2094 * modifying the HF-EEODB extension too. 2095 */ 2096 for (i = 0; i < edid_block_count(edid); i++) { 2097 const void *src_block = edid_block_data(edid, i); 2098 2099 if (edid_block_valid(src_block, i == 0)) { 2100 void *dst_block = (void *)edid_block_data(edid, valid_blocks); 2101 2102 memmove(dst_block, src_block, EDID_LENGTH); 2103 valid_blocks++; 2104 } 2105 } 2106 2107 /* We already trusted the base block to be valid here... */ 2108 if (WARN_ON(!valid_blocks)) { 2109 kfree(edid); 2110 return NULL; 2111 } 2112 2113 edid->extensions = valid_blocks - 1; 2114 edid->checksum = edid_block_compute_checksum(edid); 2115 2116 *alloc_size = edid_size_by_blocks(valid_blocks); 2117 2118 new = krealloc(edid, *alloc_size, GFP_KERNEL); 2119 if (!new) 2120 kfree(edid); 2121 2122 return new; 2123 } 2124 2125 #define DDC_SEGMENT_ADDR 0x30 2126 /** 2127 * drm_do_probe_ddc_edid() - get EDID information via I2C 2128 * @data: I2C device adapter 2129 * @buf: EDID data buffer to be filled 2130 * @block: 128 byte EDID block to start fetching from 2131 * @len: EDID data buffer length to fetch 2132 * 2133 * Try to fetch EDID information by calling I2C driver functions. 2134 * 2135 * Return: 0 on success or -1 on failure. 2136 */ 2137 static int 2138 drm_do_probe_ddc_edid(void *data, u8 *buf, unsigned int block, size_t len) 2139 { 2140 struct i2c_adapter *adapter = data; 2141 unsigned char start = block * EDID_LENGTH; 2142 unsigned char segment = block >> 1; 2143 unsigned char xfers = segment ? 3 : 2; 2144 int ret, retries = 5; 2145 2146 /* 2147 * The core I2C driver will automatically retry the transfer if the 2148 * adapter reports EAGAIN. However, we find that bit-banging transfers 2149 * are susceptible to errors under a heavily loaded machine and 2150 * generate spurious NAKs and timeouts. Retrying the transfer 2151 * of the individual block a few times seems to overcome this. 2152 */ 2153 do { 2154 struct i2c_msg msgs[] = { 2155 { 2156 .addr = DDC_SEGMENT_ADDR, 2157 .flags = 0, 2158 .len = 1, 2159 .buf = &segment, 2160 }, { 2161 .addr = DDC_ADDR, 2162 .flags = 0, 2163 .len = 1, 2164 .buf = &start, 2165 }, { 2166 .addr = DDC_ADDR, 2167 .flags = I2C_M_RD, 2168 .len = len, 2169 .buf = buf, 2170 } 2171 }; 2172 2173 /* 2174 * Avoid sending the segment addr to not upset non-compliant 2175 * DDC monitors. 2176 */ 2177 ret = i2c_transfer(adapter, &msgs[3 - xfers], xfers); 2178 2179 if (ret == -ENXIO) { 2180 DRM_DEBUG_KMS("drm: skipping non-existent adapter %s\n", 2181 adapter->name); 2182 break; 2183 } 2184 } while (ret != xfers && --retries); 2185 2186 return ret == xfers ? 0 : -1; 2187 } 2188 2189 static void connector_bad_edid(struct drm_connector *connector, 2190 const struct edid *edid, int num_blocks) 2191 { 2192 int i; 2193 u8 last_block; 2194 2195 /* 2196 * 0x7e in the EDID is the number of extension blocks. The EDID 2197 * is 1 (base block) + num_ext_blocks big. That means we can think 2198 * of 0x7e in the EDID of the _index_ of the last block in the 2199 * combined chunk of memory. 2200 */ 2201 last_block = edid->extensions; 2202 2203 /* Calculate real checksum for the last edid extension block data */ 2204 if (last_block < num_blocks) 2205 connector->real_edid_checksum = 2206 edid_block_compute_checksum(edid + last_block); 2207 2208 if (connector->bad_edid_counter++ && !drm_debug_enabled(DRM_UT_KMS)) 2209 return; 2210 2211 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID is invalid:\n", 2212 connector->base.id, connector->name); 2213 for (i = 0; i < num_blocks; i++) 2214 edid_block_dump(KERN_DEBUG, edid + i, i); 2215 } 2216 2217 /* Get override or firmware EDID */ 2218 static const struct drm_edid *drm_edid_override_get(struct drm_connector *connector) 2219 { 2220 const struct drm_edid *override = NULL; 2221 2222 mutex_lock(&connector->edid_override_mutex); 2223 2224 if (connector->edid_override) 2225 override = drm_edid_dup(connector->edid_override); 2226 2227 mutex_unlock(&connector->edid_override_mutex); 2228 2229 if (!override) 2230 override = drm_edid_load_firmware(connector); 2231 2232 return IS_ERR(override) ? NULL : override; 2233 } 2234 2235 /* For debugfs edid_override implementation */ 2236 int drm_edid_override_show(struct drm_connector *connector, struct seq_file *m) 2237 { 2238 const struct drm_edid *drm_edid; 2239 2240 mutex_lock(&connector->edid_override_mutex); 2241 2242 drm_edid = connector->edid_override; 2243 if (drm_edid) 2244 seq_write(m, drm_edid->edid, drm_edid->size); 2245 2246 mutex_unlock(&connector->edid_override_mutex); 2247 2248 return 0; 2249 } 2250 2251 /* For debugfs edid_override implementation */ 2252 int drm_edid_override_set(struct drm_connector *connector, const void *edid, 2253 size_t size) 2254 { 2255 const struct drm_edid *drm_edid; 2256 2257 drm_edid = drm_edid_alloc(edid, size); 2258 if (!drm_edid_valid(drm_edid)) { 2259 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override invalid\n", 2260 connector->base.id, connector->name); 2261 drm_edid_free(drm_edid); 2262 return -EINVAL; 2263 } 2264 2265 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override set\n", 2266 connector->base.id, connector->name); 2267 2268 mutex_lock(&connector->edid_override_mutex); 2269 2270 drm_edid_free(connector->edid_override); 2271 connector->edid_override = drm_edid; 2272 2273 mutex_unlock(&connector->edid_override_mutex); 2274 2275 return 0; 2276 } 2277 2278 /* For debugfs edid_override implementation */ 2279 int drm_edid_override_reset(struct drm_connector *connector) 2280 { 2281 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] EDID override reset\n", 2282 connector->base.id, connector->name); 2283 2284 mutex_lock(&connector->edid_override_mutex); 2285 2286 drm_edid_free(connector->edid_override); 2287 connector->edid_override = NULL; 2288 2289 mutex_unlock(&connector->edid_override_mutex); 2290 2291 return 0; 2292 } 2293 2294 /** 2295 * drm_edid_override_connector_update - add modes from override/firmware EDID 2296 * @connector: connector we're probing 2297 * 2298 * Add modes from the override/firmware EDID, if available. Only to be used from 2299 * drm_helper_probe_single_connector_modes() as a fallback for when DDC probe 2300 * failed during drm_get_edid() and caused the override/firmware EDID to be 2301 * skipped. 2302 * 2303 * Return: The number of modes added or 0 if we couldn't find any. 2304 */ 2305 int drm_edid_override_connector_update(struct drm_connector *connector) 2306 { 2307 const struct drm_edid *override; 2308 int num_modes = 0; 2309 2310 override = drm_edid_override_get(connector); 2311 if (override) { 2312 if (drm_edid_connector_update(connector, override) == 0) 2313 num_modes = drm_edid_connector_add_modes(connector); 2314 2315 drm_edid_free(override); 2316 2317 drm_dbg_kms(connector->dev, 2318 "[CONNECTOR:%d:%s] adding %d modes via fallback override/firmware EDID\n", 2319 connector->base.id, connector->name, num_modes); 2320 } 2321 2322 return num_modes; 2323 } 2324 EXPORT_SYMBOL(drm_edid_override_connector_update); 2325 2326 typedef int read_block_fn(void *context, u8 *buf, unsigned int block, size_t len); 2327 2328 static enum edid_block_status edid_block_read(void *block, unsigned int block_num, 2329 read_block_fn read_block, 2330 void *context) 2331 { 2332 enum edid_block_status status; 2333 bool is_base_block = block_num == 0; 2334 int try; 2335 2336 for (try = 0; try < 4; try++) { 2337 if (read_block(context, block, block_num, EDID_LENGTH)) 2338 return EDID_BLOCK_READ_FAIL; 2339 2340 status = edid_block_check(block, is_base_block); 2341 if (status == EDID_BLOCK_HEADER_REPAIR) { 2342 edid_header_fix(block); 2343 2344 /* Retry with fixed header, update status if that worked. */ 2345 status = edid_block_check(block, is_base_block); 2346 if (status == EDID_BLOCK_OK) 2347 status = EDID_BLOCK_HEADER_FIXED; 2348 } 2349 2350 if (edid_block_status_valid(status, edid_block_tag(block))) 2351 break; 2352 2353 /* Fail early for unrepairable base block all zeros. */ 2354 if (try == 0 && is_base_block && status == EDID_BLOCK_ZERO) 2355 break; 2356 } 2357 2358 return status; 2359 } 2360 2361 static struct edid *_drm_do_get_edid(struct drm_connector *connector, 2362 read_block_fn read_block, void *context, 2363 size_t *size) 2364 { 2365 enum edid_block_status status; 2366 int i, num_blocks, invalid_blocks = 0; 2367 const struct drm_edid *override; 2368 struct edid *edid, *new; 2369 size_t alloc_size = EDID_LENGTH; 2370 2371 override = drm_edid_override_get(connector); 2372 if (override) { 2373 alloc_size = override->size; 2374 edid = kmemdup(override->edid, alloc_size, GFP_KERNEL); 2375 drm_edid_free(override); 2376 if (!edid) 2377 return NULL; 2378 goto ok; 2379 } 2380 2381 edid = kmalloc(alloc_size, GFP_KERNEL); 2382 if (!edid) 2383 return NULL; 2384 2385 status = edid_block_read(edid, 0, read_block, context); 2386 2387 edid_block_status_print(status, edid, 0); 2388 2389 if (status == EDID_BLOCK_READ_FAIL) 2390 goto fail; 2391 2392 /* FIXME: Clarify what a corrupt EDID actually means. */ 2393 if (status == EDID_BLOCK_OK || status == EDID_BLOCK_VERSION) 2394 connector->edid_corrupt = false; 2395 else 2396 connector->edid_corrupt = true; 2397 2398 if (!edid_block_status_valid(status, edid_block_tag(edid))) { 2399 if (status == EDID_BLOCK_ZERO) 2400 connector->null_edid_counter++; 2401 2402 connector_bad_edid(connector, edid, 1); 2403 goto fail; 2404 } 2405 2406 if (!edid_extension_block_count(edid)) 2407 goto ok; 2408 2409 alloc_size = edid_size(edid); 2410 new = krealloc(edid, alloc_size, GFP_KERNEL); 2411 if (!new) 2412 goto fail; 2413 edid = new; 2414 2415 num_blocks = edid_block_count(edid); 2416 for (i = 1; i < num_blocks; i++) { 2417 void *block = (void *)edid_block_data(edid, i); 2418 2419 status = edid_block_read(block, i, read_block, context); 2420 2421 edid_block_status_print(status, block, i); 2422 2423 if (!edid_block_status_valid(status, edid_block_tag(block))) { 2424 if (status == EDID_BLOCK_READ_FAIL) 2425 goto fail; 2426 invalid_blocks++; 2427 } else if (i == 1) { 2428 /* 2429 * If the first EDID extension is a CTA extension, and 2430 * the first Data Block is HF-EEODB, override the 2431 * extension block count. 2432 * 2433 * Note: HF-EEODB could specify a smaller extension 2434 * count too, but we can't risk allocating a smaller 2435 * amount. 2436 */ 2437 int eeodb = edid_hfeeodb_block_count(edid); 2438 2439 if (eeodb > num_blocks) { 2440 num_blocks = eeodb; 2441 alloc_size = edid_size_by_blocks(num_blocks); 2442 new = krealloc(edid, alloc_size, GFP_KERNEL); 2443 if (!new) 2444 goto fail; 2445 edid = new; 2446 } 2447 } 2448 } 2449 2450 if (invalid_blocks) { 2451 connector_bad_edid(connector, edid, num_blocks); 2452 2453 edid = edid_filter_invalid_blocks(edid, &alloc_size); 2454 } 2455 2456 ok: 2457 if (size) 2458 *size = alloc_size; 2459 2460 return edid; 2461 2462 fail: 2463 kfree(edid); 2464 return NULL; 2465 } 2466 2467 /** 2468 * drm_do_get_edid - get EDID data using a custom EDID block read function 2469 * @connector: connector we're probing 2470 * @read_block: EDID block read function 2471 * @context: private data passed to the block read function 2472 * 2473 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2474 * exposes a different interface to read EDID blocks this function can be used 2475 * to get EDID data using a custom block read function. 2476 * 2477 * As in the general case the DDC bus is accessible by the kernel at the I2C 2478 * level, drivers must make all reasonable efforts to expose it as an I2C 2479 * adapter and use drm_get_edid() instead of abusing this function. 2480 * 2481 * The EDID may be overridden using debugfs override_edid or firmware EDID 2482 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2483 * order. Having either of them bypasses actual EDID reads. 2484 * 2485 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2486 */ 2487 struct edid *drm_do_get_edid(struct drm_connector *connector, 2488 read_block_fn read_block, 2489 void *context) 2490 { 2491 return _drm_do_get_edid(connector, read_block, context, NULL); 2492 } 2493 EXPORT_SYMBOL_GPL(drm_do_get_edid); 2494 2495 /** 2496 * drm_edid_raw - Get a pointer to the raw EDID data. 2497 * @drm_edid: drm_edid container 2498 * 2499 * Get a pointer to the raw EDID data. 2500 * 2501 * This is for transition only. Avoid using this like the plague. 2502 * 2503 * Return: Pointer to raw EDID data. 2504 */ 2505 const struct edid *drm_edid_raw(const struct drm_edid *drm_edid) 2506 { 2507 if (!drm_edid || !drm_edid->size) 2508 return NULL; 2509 2510 /* 2511 * Do not return pointers where relying on EDID extension count would 2512 * lead to buffer overflow. 2513 */ 2514 if (WARN_ON(edid_size(drm_edid->edid) > drm_edid->size)) 2515 return NULL; 2516 2517 return drm_edid->edid; 2518 } 2519 EXPORT_SYMBOL(drm_edid_raw); 2520 2521 /* Allocate struct drm_edid container *without* duplicating the edid data */ 2522 static const struct drm_edid *_drm_edid_alloc(const void *edid, size_t size) 2523 { 2524 struct drm_edid *drm_edid; 2525 2526 if (!edid || !size || size < EDID_LENGTH) 2527 return NULL; 2528 2529 drm_edid = kzalloc(sizeof(*drm_edid), GFP_KERNEL); 2530 if (drm_edid) { 2531 drm_edid->edid = edid; 2532 drm_edid->size = size; 2533 } 2534 2535 return drm_edid; 2536 } 2537 2538 /** 2539 * drm_edid_alloc - Allocate a new drm_edid container 2540 * @edid: Pointer to raw EDID data 2541 * @size: Size of memory allocated for EDID 2542 * 2543 * Allocate a new drm_edid container. Do not calculate edid size from edid, pass 2544 * the actual size that has been allocated for the data. There is no validation 2545 * of the raw EDID data against the size, but at least the EDID base block must 2546 * fit in the buffer. 2547 * 2548 * The returned pointer must be freed using drm_edid_free(). 2549 * 2550 * Return: drm_edid container, or NULL on errors 2551 */ 2552 const struct drm_edid *drm_edid_alloc(const void *edid, size_t size) 2553 { 2554 const struct drm_edid *drm_edid; 2555 2556 if (!edid || !size || size < EDID_LENGTH) 2557 return NULL; 2558 2559 edid = kmemdup(edid, size, GFP_KERNEL); 2560 if (!edid) 2561 return NULL; 2562 2563 drm_edid = _drm_edid_alloc(edid, size); 2564 if (!drm_edid) 2565 kfree(edid); 2566 2567 return drm_edid; 2568 } 2569 EXPORT_SYMBOL(drm_edid_alloc); 2570 2571 /** 2572 * drm_edid_dup - Duplicate a drm_edid container 2573 * @drm_edid: EDID to duplicate 2574 * 2575 * The returned pointer must be freed using drm_edid_free(). 2576 * 2577 * Returns: drm_edid container copy, or NULL on errors 2578 */ 2579 const struct drm_edid *drm_edid_dup(const struct drm_edid *drm_edid) 2580 { 2581 if (!drm_edid) 2582 return NULL; 2583 2584 return drm_edid_alloc(drm_edid->edid, drm_edid->size); 2585 } 2586 EXPORT_SYMBOL(drm_edid_dup); 2587 2588 /** 2589 * drm_edid_free - Free the drm_edid container 2590 * @drm_edid: EDID to free 2591 */ 2592 void drm_edid_free(const struct drm_edid *drm_edid) 2593 { 2594 if (!drm_edid) 2595 return; 2596 2597 kfree(drm_edid->edid); 2598 kfree(drm_edid); 2599 } 2600 EXPORT_SYMBOL(drm_edid_free); 2601 2602 /** 2603 * drm_probe_ddc() - probe DDC presence 2604 * @adapter: I2C adapter to probe 2605 * 2606 * Return: True on success, false on failure. 2607 */ 2608 bool 2609 drm_probe_ddc(struct i2c_adapter *adapter) 2610 { 2611 unsigned char out; 2612 2613 return (drm_do_probe_ddc_edid(adapter, &out, 0, 1) == 0); 2614 } 2615 EXPORT_SYMBOL(drm_probe_ddc); 2616 2617 /** 2618 * drm_get_edid - get EDID data, if available 2619 * @connector: connector we're probing 2620 * @adapter: I2C adapter to use for DDC 2621 * 2622 * Poke the given I2C channel to grab EDID data if possible. If found, 2623 * attach it to the connector. 2624 * 2625 * Return: Pointer to valid EDID or NULL if we couldn't find any. 2626 */ 2627 struct edid *drm_get_edid(struct drm_connector *connector, 2628 struct i2c_adapter *adapter) 2629 { 2630 struct edid *edid; 2631 2632 if (connector->force == DRM_FORCE_OFF) 2633 return NULL; 2634 2635 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2636 return NULL; 2637 2638 edid = _drm_do_get_edid(connector, drm_do_probe_ddc_edid, adapter, NULL); 2639 drm_connector_update_edid_property(connector, edid); 2640 return edid; 2641 } 2642 EXPORT_SYMBOL(drm_get_edid); 2643 2644 /** 2645 * drm_edid_read_custom - Read EDID data using given EDID block read function 2646 * @connector: Connector to use 2647 * @read_block: EDID block read function 2648 * @context: Private data passed to the block read function 2649 * 2650 * When the I2C adapter connected to the DDC bus is hidden behind a device that 2651 * exposes a different interface to read EDID blocks this function can be used 2652 * to get EDID data using a custom block read function. 2653 * 2654 * As in the general case the DDC bus is accessible by the kernel at the I2C 2655 * level, drivers must make all reasonable efforts to expose it as an I2C 2656 * adapter and use drm_edid_read() or drm_edid_read_ddc() instead of abusing 2657 * this function. 2658 * 2659 * The EDID may be overridden using debugfs override_edid or firmware EDID 2660 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2661 * order. Having either of them bypasses actual EDID reads. 2662 * 2663 * The returned pointer must be freed using drm_edid_free(). 2664 * 2665 * Return: Pointer to EDID, or NULL if probe/read failed. 2666 */ 2667 const struct drm_edid *drm_edid_read_custom(struct drm_connector *connector, 2668 read_block_fn read_block, 2669 void *context) 2670 { 2671 const struct drm_edid *drm_edid; 2672 struct edid *edid; 2673 size_t size = 0; 2674 2675 edid = _drm_do_get_edid(connector, read_block, context, &size); 2676 if (!edid) 2677 return NULL; 2678 2679 /* Sanity check for now */ 2680 drm_WARN_ON(connector->dev, !size); 2681 2682 drm_edid = _drm_edid_alloc(edid, size); 2683 if (!drm_edid) 2684 kfree(edid); 2685 2686 return drm_edid; 2687 } 2688 EXPORT_SYMBOL(drm_edid_read_custom); 2689 2690 /** 2691 * drm_edid_read_ddc - Read EDID data using given I2C adapter 2692 * @connector: Connector to use 2693 * @adapter: I2C adapter to use for DDC 2694 * 2695 * Read EDID using the given I2C adapter. 2696 * 2697 * The EDID may be overridden using debugfs override_edid or firmware EDID 2698 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2699 * order. Having either of them bypasses actual EDID reads. 2700 * 2701 * Prefer initializing connector->ddc with drm_connector_init_with_ddc() and 2702 * using drm_edid_read() instead of this function. 2703 * 2704 * The returned pointer must be freed using drm_edid_free(). 2705 * 2706 * Return: Pointer to EDID, or NULL if probe/read failed. 2707 */ 2708 const struct drm_edid *drm_edid_read_ddc(struct drm_connector *connector, 2709 struct i2c_adapter *adapter) 2710 { 2711 const struct drm_edid *drm_edid; 2712 2713 if (connector->force == DRM_FORCE_OFF) 2714 return NULL; 2715 2716 if (connector->force == DRM_FORCE_UNSPECIFIED && !drm_probe_ddc(adapter)) 2717 return NULL; 2718 2719 drm_edid = drm_edid_read_custom(connector, drm_do_probe_ddc_edid, adapter); 2720 2721 /* Note: Do *not* call connector updates here. */ 2722 2723 return drm_edid; 2724 } 2725 EXPORT_SYMBOL(drm_edid_read_ddc); 2726 2727 /** 2728 * drm_edid_read - Read EDID data using connector's I2C adapter 2729 * @connector: Connector to use 2730 * 2731 * Read EDID using the connector's I2C adapter. 2732 * 2733 * The EDID may be overridden using debugfs override_edid or firmware EDID 2734 * (drm_edid_load_firmware() and drm.edid_firmware parameter), in this priority 2735 * order. Having either of them bypasses actual EDID reads. 2736 * 2737 * The returned pointer must be freed using drm_edid_free(). 2738 * 2739 * Return: Pointer to EDID, or NULL if probe/read failed. 2740 */ 2741 const struct drm_edid *drm_edid_read(struct drm_connector *connector) 2742 { 2743 if (drm_WARN_ON(connector->dev, !connector->ddc)) 2744 return NULL; 2745 2746 return drm_edid_read_ddc(connector, connector->ddc); 2747 } 2748 EXPORT_SYMBOL(drm_edid_read); 2749 2750 /** 2751 * drm_edid_get_product_id - Get the vendor and product identification 2752 * @drm_edid: EDID 2753 * @id: Where to place the product id 2754 */ 2755 void drm_edid_get_product_id(const struct drm_edid *drm_edid, 2756 struct drm_edid_product_id *id) 2757 { 2758 if (drm_edid && drm_edid->edid && drm_edid->size >= EDID_LENGTH) 2759 memcpy(id, &drm_edid->edid->product_id, sizeof(*id)); 2760 else 2761 memset(id, 0, sizeof(*id)); 2762 } 2763 EXPORT_SYMBOL(drm_edid_get_product_id); 2764 2765 static void decode_date(struct seq_buf *s, const struct drm_edid_product_id *id) 2766 { 2767 int week = id->week_of_manufacture; 2768 int year = id->year_of_manufacture + 1990; 2769 2770 if (week == 0xff) 2771 seq_buf_printf(s, "model year: %d", year); 2772 else if (!week) 2773 seq_buf_printf(s, "year of manufacture: %d", year); 2774 else 2775 seq_buf_printf(s, "week/year of manufacture: %d/%d", week, year); 2776 } 2777 2778 /** 2779 * drm_edid_print_product_id - Print decoded product id to printer 2780 * @p: drm printer 2781 * @id: EDID product id 2782 * @raw: If true, also print the raw hex 2783 * 2784 * See VESA E-EDID 1.4 section 3.4. 2785 */ 2786 void drm_edid_print_product_id(struct drm_printer *p, 2787 const struct drm_edid_product_id *id, bool raw) 2788 { 2789 DECLARE_SEQ_BUF(date, 40); 2790 char vend[4]; 2791 2792 drm_edid_decode_mfg_id(be16_to_cpu(id->manufacturer_name), vend); 2793 2794 decode_date(&date, id); 2795 2796 drm_printf(p, "manufacturer name: %s, product code: %u, serial number: %u, %s\n", 2797 vend, le16_to_cpu(id->product_code), 2798 le32_to_cpu(id->serial_number), seq_buf_str(&date)); 2799 2800 if (raw) 2801 drm_printf(p, "raw product id: %*ph\n", (int)sizeof(*id), id); 2802 2803 WARN_ON(seq_buf_has_overflowed(&date)); 2804 } 2805 EXPORT_SYMBOL(drm_edid_print_product_id); 2806 2807 /** 2808 * drm_edid_get_panel_id - Get a panel's ID from EDID 2809 * @drm_edid: EDID that contains panel ID. 2810 * 2811 * This function uses the first block of the EDID of a panel and (assuming 2812 * that the EDID is valid) extracts the ID out of it. The ID is a 32-bit value 2813 * (16 bits of manufacturer ID and 16 bits of per-manufacturer ID) that's 2814 * supposed to be different for each different modem of panel. 2815 * 2816 * Return: A 32-bit ID that should be different for each make/model of panel. 2817 * See the functions drm_edid_encode_panel_id() and 2818 * drm_edid_decode_panel_id() for some details on the structure of this 2819 * ID. Return 0 if the EDID size is less than a base block. 2820 */ 2821 u32 drm_edid_get_panel_id(const struct drm_edid *drm_edid) 2822 { 2823 const struct edid *edid = drm_edid->edid; 2824 2825 if (drm_edid->size < EDID_LENGTH) 2826 return 0; 2827 2828 /* 2829 * We represent the ID as a 32-bit number so it can easily be compared 2830 * with "==". 2831 * 2832 * NOTE that we deal with endianness differently for the top half 2833 * of this ID than for the bottom half. The bottom half (the product 2834 * id) gets decoded as little endian by the EDID_PRODUCT_ID because 2835 * that's how everyone seems to interpret it. The top half (the mfg_id) 2836 * gets stored as big endian because that makes 2837 * drm_edid_encode_panel_id() and drm_edid_decode_panel_id() easier 2838 * to write (it's easier to extract the ASCII). It doesn't really 2839 * matter, though, as long as the number here is unique. 2840 */ 2841 return (u32)edid->mfg_id[0] << 24 | 2842 (u32)edid->mfg_id[1] << 16 | 2843 (u32)EDID_PRODUCT_ID(edid); 2844 } 2845 EXPORT_SYMBOL(drm_edid_get_panel_id); 2846 2847 /** 2848 * drm_edid_read_base_block - Get a panel's EDID base block 2849 * @adapter: I2C adapter to use for DDC 2850 * 2851 * This function returns the drm_edid containing the first block of the EDID of 2852 * a panel. 2853 * 2854 * This function is intended to be used during early probing on devices where 2855 * more than one panel might be present. Because of its intended use it must 2856 * assume that the EDID of the panel is correct, at least as far as the base 2857 * block is concerned (in other words, we don't process any overrides here). 2858 * 2859 * Caller should call drm_edid_free() after use. 2860 * 2861 * NOTE: it's expected that this function and drm_do_get_edid() will both 2862 * be read the EDID, but there is no caching between them. Since we're only 2863 * reading the first block, hopefully this extra overhead won't be too big. 2864 * 2865 * WARNING: Only use this function when the connector is unknown. For example, 2866 * during the early probe of panel. The EDID read from the function is temporary 2867 * and should be replaced by the full EDID returned from other drm_edid_read. 2868 * 2869 * Return: Pointer to allocated EDID base block, or NULL on any failure. 2870 */ 2871 const struct drm_edid *drm_edid_read_base_block(struct i2c_adapter *adapter) 2872 { 2873 enum edid_block_status status; 2874 void *base_block; 2875 2876 base_block = kzalloc(EDID_LENGTH, GFP_KERNEL); 2877 if (!base_block) 2878 return NULL; 2879 2880 status = edid_block_read(base_block, 0, drm_do_probe_ddc_edid, adapter); 2881 2882 edid_block_status_print(status, base_block, 0); 2883 2884 if (!edid_block_status_valid(status, edid_block_tag(base_block))) { 2885 edid_block_dump(KERN_NOTICE, base_block, 0); 2886 kfree(base_block); 2887 return NULL; 2888 } 2889 2890 return _drm_edid_alloc(base_block, EDID_LENGTH); 2891 } 2892 EXPORT_SYMBOL(drm_edid_read_base_block); 2893 2894 /** 2895 * drm_get_edid_switcheroo - get EDID data for a vga_switcheroo output 2896 * @connector: connector we're probing 2897 * @adapter: I2C adapter to use for DDC 2898 * 2899 * Wrapper around drm_get_edid() for laptops with dual GPUs using one set of 2900 * outputs. The wrapper adds the requisite vga_switcheroo calls to temporarily 2901 * switch DDC to the GPU which is retrieving EDID. 2902 * 2903 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2904 */ 2905 struct edid *drm_get_edid_switcheroo(struct drm_connector *connector, 2906 struct i2c_adapter *adapter) 2907 { 2908 struct drm_device *dev = connector->dev; 2909 struct pci_dev *pdev = to_pci_dev(dev->dev); 2910 struct edid *edid; 2911 2912 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2913 return NULL; 2914 2915 vga_switcheroo_lock_ddc(pdev); 2916 edid = drm_get_edid(connector, adapter); 2917 vga_switcheroo_unlock_ddc(pdev); 2918 2919 return edid; 2920 } 2921 EXPORT_SYMBOL(drm_get_edid_switcheroo); 2922 2923 /** 2924 * drm_edid_read_switcheroo - get EDID data for a vga_switcheroo output 2925 * @connector: connector we're probing 2926 * @adapter: I2C adapter to use for DDC 2927 * 2928 * Wrapper around drm_edid_read_ddc() for laptops with dual GPUs using one set 2929 * of outputs. The wrapper adds the requisite vga_switcheroo calls to 2930 * temporarily switch DDC to the GPU which is retrieving EDID. 2931 * 2932 * Return: Pointer to valid EDID or %NULL if we couldn't find any. 2933 */ 2934 const struct drm_edid *drm_edid_read_switcheroo(struct drm_connector *connector, 2935 struct i2c_adapter *adapter) 2936 { 2937 struct drm_device *dev = connector->dev; 2938 struct pci_dev *pdev = to_pci_dev(dev->dev); 2939 const struct drm_edid *drm_edid; 2940 2941 if (drm_WARN_ON_ONCE(dev, !dev_is_pci(dev->dev))) 2942 return NULL; 2943 2944 vga_switcheroo_lock_ddc(pdev); 2945 drm_edid = drm_edid_read_ddc(connector, adapter); 2946 vga_switcheroo_unlock_ddc(pdev); 2947 2948 return drm_edid; 2949 } 2950 EXPORT_SYMBOL(drm_edid_read_switcheroo); 2951 2952 /** 2953 * drm_edid_duplicate - duplicate an EDID and the extensions 2954 * @edid: EDID to duplicate 2955 * 2956 * Return: Pointer to duplicated EDID or NULL on allocation failure. 2957 */ 2958 struct edid *drm_edid_duplicate(const struct edid *edid) 2959 { 2960 if (!edid) 2961 return NULL; 2962 2963 return kmemdup(edid, edid_size(edid), GFP_KERNEL); 2964 } 2965 EXPORT_SYMBOL(drm_edid_duplicate); 2966 2967 /*** EDID parsing ***/ 2968 2969 /** 2970 * edid_get_quirks - return quirk flags for a given EDID 2971 * @drm_edid: EDID to process 2972 * 2973 * This tells subsequent routines what fixes they need to apply. 2974 * 2975 * Return: A u32 represents the quirks to apply. 2976 */ 2977 static u32 edid_get_quirks(const struct drm_edid *drm_edid) 2978 { 2979 const struct edid_quirk *quirk; 2980 int i; 2981 2982 for (i = 0; i < ARRAY_SIZE(edid_quirk_list); i++) { 2983 quirk = &edid_quirk_list[i]; 2984 if (drm_edid_match(drm_edid, &quirk->ident)) 2985 return quirk->quirks; 2986 } 2987 2988 return 0; 2989 } 2990 2991 #define MODE_SIZE(m) ((m)->hdisplay * (m)->vdisplay) 2992 #define MODE_REFRESH_DIFF(c,t) (abs((c) - (t))) 2993 2994 /* 2995 * Walk the mode list for connector, clearing the preferred status on existing 2996 * modes and setting it anew for the right mode ala quirks. 2997 */ 2998 static void edid_fixup_preferred(struct drm_connector *connector) 2999 { 3000 const struct drm_display_info *info = &connector->display_info; 3001 struct drm_display_mode *t, *cur_mode, *preferred_mode; 3002 int target_refresh = 0; 3003 int cur_vrefresh, preferred_vrefresh; 3004 3005 if (list_empty(&connector->probed_modes)) 3006 return; 3007 3008 if (info->quirks & EDID_QUIRK_PREFER_LARGE_60) 3009 target_refresh = 60; 3010 if (info->quirks & EDID_QUIRK_PREFER_LARGE_75) 3011 target_refresh = 75; 3012 3013 preferred_mode = list_first_entry(&connector->probed_modes, 3014 struct drm_display_mode, head); 3015 3016 list_for_each_entry_safe(cur_mode, t, &connector->probed_modes, head) { 3017 cur_mode->type &= ~DRM_MODE_TYPE_PREFERRED; 3018 3019 if (cur_mode == preferred_mode) 3020 continue; 3021 3022 /* Largest mode is preferred */ 3023 if (MODE_SIZE(cur_mode) > MODE_SIZE(preferred_mode)) 3024 preferred_mode = cur_mode; 3025 3026 cur_vrefresh = drm_mode_vrefresh(cur_mode); 3027 preferred_vrefresh = drm_mode_vrefresh(preferred_mode); 3028 /* At a given size, try to get closest to target refresh */ 3029 if ((MODE_SIZE(cur_mode) == MODE_SIZE(preferred_mode)) && 3030 MODE_REFRESH_DIFF(cur_vrefresh, target_refresh) < 3031 MODE_REFRESH_DIFF(preferred_vrefresh, target_refresh)) { 3032 preferred_mode = cur_mode; 3033 } 3034 } 3035 3036 preferred_mode->type |= DRM_MODE_TYPE_PREFERRED; 3037 } 3038 3039 static bool 3040 mode_is_rb(const struct drm_display_mode *mode) 3041 { 3042 return (mode->htotal - mode->hdisplay == 160) && 3043 (mode->hsync_end - mode->hdisplay == 80) && 3044 (mode->hsync_end - mode->hsync_start == 32) && 3045 (mode->vsync_start - mode->vdisplay == 3); 3046 } 3047 3048 /* 3049 * drm_mode_find_dmt - Create a copy of a mode if present in DMT 3050 * @dev: Device to duplicate against 3051 * @hsize: Mode width 3052 * @vsize: Mode height 3053 * @fresh: Mode refresh rate 3054 * @rb: Mode reduced-blanking-ness 3055 * 3056 * Walk the DMT mode list looking for a match for the given parameters. 3057 * 3058 * Return: A newly allocated copy of the mode, or NULL if not found. 3059 */ 3060 struct drm_display_mode *drm_mode_find_dmt(struct drm_device *dev, 3061 int hsize, int vsize, int fresh, 3062 bool rb) 3063 { 3064 int i; 3065 3066 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3067 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 3068 3069 if (hsize != ptr->hdisplay) 3070 continue; 3071 if (vsize != ptr->vdisplay) 3072 continue; 3073 if (fresh != drm_mode_vrefresh(ptr)) 3074 continue; 3075 if (rb != mode_is_rb(ptr)) 3076 continue; 3077 3078 return drm_mode_duplicate(dev, ptr); 3079 } 3080 3081 return NULL; 3082 } 3083 EXPORT_SYMBOL(drm_mode_find_dmt); 3084 3085 static bool is_display_descriptor(const struct detailed_timing *descriptor, u8 type) 3086 { 3087 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3088 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.pad1) != 2); 3089 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.type) != 3); 3090 3091 return descriptor->pixel_clock == 0 && 3092 descriptor->data.other_data.pad1 == 0 && 3093 descriptor->data.other_data.type == type; 3094 } 3095 3096 static bool is_detailed_timing_descriptor(const struct detailed_timing *descriptor) 3097 { 3098 BUILD_BUG_ON(offsetof(typeof(*descriptor), pixel_clock) != 0); 3099 3100 return descriptor->pixel_clock != 0; 3101 } 3102 3103 typedef void detailed_cb(const struct detailed_timing *timing, void *closure); 3104 3105 static void 3106 cea_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3107 { 3108 int i, n; 3109 u8 d = ext[0x02]; 3110 const u8 *det_base = ext + d; 3111 3112 if (d < 4 || d > 127) 3113 return; 3114 3115 n = (127 - d) / 18; 3116 for (i = 0; i < n; i++) 3117 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3118 } 3119 3120 static void 3121 vtb_for_each_detailed_block(const u8 *ext, detailed_cb *cb, void *closure) 3122 { 3123 unsigned int i, n = min((int)ext[0x02], 6); 3124 const u8 *det_base = ext + 5; 3125 3126 if (ext[0x01] != 1) 3127 return; /* unknown version */ 3128 3129 for (i = 0; i < n; i++) 3130 cb((const struct detailed_timing *)(det_base + 18 * i), closure); 3131 } 3132 3133 static void drm_for_each_detailed_block(const struct drm_edid *drm_edid, 3134 detailed_cb *cb, void *closure) 3135 { 3136 struct drm_edid_iter edid_iter; 3137 const u8 *ext; 3138 int i; 3139 3140 if (!drm_edid) 3141 return; 3142 3143 for (i = 0; i < EDID_DETAILED_TIMINGS; i++) 3144 cb(&drm_edid->edid->detailed_timings[i], closure); 3145 3146 drm_edid_iter_begin(drm_edid, &edid_iter); 3147 drm_edid_iter_for_each(ext, &edid_iter) { 3148 switch (*ext) { 3149 case CEA_EXT: 3150 cea_for_each_detailed_block(ext, cb, closure); 3151 break; 3152 case VTB_EXT: 3153 vtb_for_each_detailed_block(ext, cb, closure); 3154 break; 3155 default: 3156 break; 3157 } 3158 } 3159 drm_edid_iter_end(&edid_iter); 3160 } 3161 3162 static void 3163 is_rb(const struct detailed_timing *descriptor, void *data) 3164 { 3165 bool *res = data; 3166 3167 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3168 return; 3169 3170 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3171 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.cvt.flags) != 15); 3172 3173 if (descriptor->data.other_data.data.range.flags == DRM_EDID_CVT_SUPPORT_FLAG && 3174 descriptor->data.other_data.data.range.formula.cvt.flags & DRM_EDID_CVT_FLAGS_REDUCED_BLANKING) 3175 *res = true; 3176 } 3177 3178 /* EDID 1.4 defines this explicitly. For EDID 1.3, we guess, badly. */ 3179 static bool 3180 drm_monitor_supports_rb(const struct drm_edid *drm_edid) 3181 { 3182 if (drm_edid->edid->revision >= 4) { 3183 bool ret = false; 3184 3185 drm_for_each_detailed_block(drm_edid, is_rb, &ret); 3186 return ret; 3187 } 3188 3189 return drm_edid_is_digital(drm_edid); 3190 } 3191 3192 static void 3193 find_gtf2(const struct detailed_timing *descriptor, void *data) 3194 { 3195 const struct detailed_timing **res = data; 3196 3197 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3198 return; 3199 3200 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3201 3202 if (descriptor->data.other_data.data.range.flags == DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG) 3203 *res = descriptor; 3204 } 3205 3206 /* Secondary GTF curve kicks in above some break frequency */ 3207 static int 3208 drm_gtf2_hbreak(const struct drm_edid *drm_edid) 3209 { 3210 const struct detailed_timing *descriptor = NULL; 3211 3212 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3213 3214 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.hfreq_start_khz) != 12); 3215 3216 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.hfreq_start_khz * 2 : 0; 3217 } 3218 3219 static int 3220 drm_gtf2_2c(const struct drm_edid *drm_edid) 3221 { 3222 const struct detailed_timing *descriptor = NULL; 3223 3224 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3225 3226 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.c) != 13); 3227 3228 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.c : 0; 3229 } 3230 3231 static int 3232 drm_gtf2_m(const struct drm_edid *drm_edid) 3233 { 3234 const struct detailed_timing *descriptor = NULL; 3235 3236 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3237 3238 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.m) != 14); 3239 3240 return descriptor ? le16_to_cpu(descriptor->data.other_data.data.range.formula.gtf2.m) : 0; 3241 } 3242 3243 static int 3244 drm_gtf2_k(const struct drm_edid *drm_edid) 3245 { 3246 const struct detailed_timing *descriptor = NULL; 3247 3248 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3249 3250 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.k) != 16); 3251 3252 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.k : 0; 3253 } 3254 3255 static int 3256 drm_gtf2_2j(const struct drm_edid *drm_edid) 3257 { 3258 const struct detailed_timing *descriptor = NULL; 3259 3260 drm_for_each_detailed_block(drm_edid, find_gtf2, &descriptor); 3261 3262 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.formula.gtf2.j) != 17); 3263 3264 return descriptor ? descriptor->data.other_data.data.range.formula.gtf2.j : 0; 3265 } 3266 3267 static void 3268 get_timing_level(const struct detailed_timing *descriptor, void *data) 3269 { 3270 int *res = data; 3271 3272 if (!is_display_descriptor(descriptor, EDID_DETAIL_MONITOR_RANGE)) 3273 return; 3274 3275 BUILD_BUG_ON(offsetof(typeof(*descriptor), data.other_data.data.range.flags) != 10); 3276 3277 switch (descriptor->data.other_data.data.range.flags) { 3278 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3279 *res = LEVEL_GTF; 3280 break; 3281 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3282 *res = LEVEL_GTF2; 3283 break; 3284 case DRM_EDID_CVT_SUPPORT_FLAG: 3285 *res = LEVEL_CVT; 3286 break; 3287 default: 3288 break; 3289 } 3290 } 3291 3292 /* Get standard timing level (CVT/GTF/DMT). */ 3293 static int standard_timing_level(const struct drm_edid *drm_edid) 3294 { 3295 const struct edid *edid = drm_edid->edid; 3296 3297 if (edid->revision >= 4) { 3298 /* 3299 * If the range descriptor doesn't 3300 * indicate otherwise default to CVT 3301 */ 3302 int ret = LEVEL_CVT; 3303 3304 drm_for_each_detailed_block(drm_edid, get_timing_level, &ret); 3305 3306 return ret; 3307 } else if (edid->revision >= 3 && drm_gtf2_hbreak(drm_edid)) { 3308 return LEVEL_GTF2; 3309 } else if (edid->revision >= 2) { 3310 return LEVEL_GTF; 3311 } else { 3312 return LEVEL_DMT; 3313 } 3314 } 3315 3316 /* 3317 * 0 is reserved. The spec says 0x01 fill for unused timings. Some old 3318 * monitors fill with ascii space (0x20) instead. 3319 */ 3320 static int 3321 bad_std_timing(u8 a, u8 b) 3322 { 3323 return (a == 0x00 && b == 0x00) || 3324 (a == 0x01 && b == 0x01) || 3325 (a == 0x20 && b == 0x20); 3326 } 3327 3328 static int drm_mode_hsync(const struct drm_display_mode *mode) 3329 { 3330 if (mode->htotal <= 0) 3331 return 0; 3332 3333 return DIV_ROUND_CLOSEST(mode->clock, mode->htotal); 3334 } 3335 3336 static struct drm_display_mode * 3337 drm_gtf2_mode(struct drm_device *dev, 3338 const struct drm_edid *drm_edid, 3339 int hsize, int vsize, int vrefresh_rate) 3340 { 3341 struct drm_display_mode *mode; 3342 3343 /* 3344 * This is potentially wrong if there's ever a monitor with 3345 * more than one ranges section, each claiming a different 3346 * secondary GTF curve. Please don't do that. 3347 */ 3348 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3349 if (!mode) 3350 return NULL; 3351 3352 if (drm_mode_hsync(mode) > drm_gtf2_hbreak(drm_edid)) { 3353 drm_mode_destroy(dev, mode); 3354 mode = drm_gtf_mode_complex(dev, hsize, vsize, 3355 vrefresh_rate, 0, 0, 3356 drm_gtf2_m(drm_edid), 3357 drm_gtf2_2c(drm_edid), 3358 drm_gtf2_k(drm_edid), 3359 drm_gtf2_2j(drm_edid)); 3360 } 3361 3362 return mode; 3363 } 3364 3365 /* 3366 * Take the standard timing params (in this case width, aspect, and refresh) 3367 * and convert them into a real mode using CVT/GTF/DMT. 3368 */ 3369 static struct drm_display_mode *drm_mode_std(struct drm_connector *connector, 3370 const struct drm_edid *drm_edid, 3371 const struct std_timing *t) 3372 { 3373 struct drm_device *dev = connector->dev; 3374 struct drm_display_mode *m, *mode = NULL; 3375 int hsize, vsize; 3376 int vrefresh_rate; 3377 unsigned aspect_ratio = (t->vfreq_aspect & EDID_TIMING_ASPECT_MASK) 3378 >> EDID_TIMING_ASPECT_SHIFT; 3379 unsigned vfreq = (t->vfreq_aspect & EDID_TIMING_VFREQ_MASK) 3380 >> EDID_TIMING_VFREQ_SHIFT; 3381 int timing_level = standard_timing_level(drm_edid); 3382 3383 if (bad_std_timing(t->hsize, t->vfreq_aspect)) 3384 return NULL; 3385 3386 /* According to the EDID spec, the hdisplay = hsize * 8 + 248 */ 3387 hsize = t->hsize * 8 + 248; 3388 /* vrefresh_rate = vfreq + 60 */ 3389 vrefresh_rate = vfreq + 60; 3390 /* the vdisplay is calculated based on the aspect ratio */ 3391 if (aspect_ratio == 0) { 3392 if (drm_edid->edid->revision < 3) 3393 vsize = hsize; 3394 else 3395 vsize = (hsize * 10) / 16; 3396 } else if (aspect_ratio == 1) 3397 vsize = (hsize * 3) / 4; 3398 else if (aspect_ratio == 2) 3399 vsize = (hsize * 4) / 5; 3400 else 3401 vsize = (hsize * 9) / 16; 3402 3403 /* HDTV hack, part 1 */ 3404 if (vrefresh_rate == 60 && 3405 ((hsize == 1360 && vsize == 765) || 3406 (hsize == 1368 && vsize == 769))) { 3407 hsize = 1366; 3408 vsize = 768; 3409 } 3410 3411 /* 3412 * If this connector already has a mode for this size and refresh 3413 * rate (because it came from detailed or CVT info), use that 3414 * instead. This way we don't have to guess at interlace or 3415 * reduced blanking. 3416 */ 3417 list_for_each_entry(m, &connector->probed_modes, head) 3418 if (m->hdisplay == hsize && m->vdisplay == vsize && 3419 drm_mode_vrefresh(m) == vrefresh_rate) 3420 return NULL; 3421 3422 /* HDTV hack, part 2 */ 3423 if (hsize == 1366 && vsize == 768 && vrefresh_rate == 60) { 3424 mode = drm_cvt_mode(dev, 1366, 768, vrefresh_rate, 0, 0, 3425 false); 3426 if (!mode) 3427 return NULL; 3428 mode->hdisplay = 1366; 3429 mode->hsync_start = mode->hsync_start - 1; 3430 mode->hsync_end = mode->hsync_end - 1; 3431 return mode; 3432 } 3433 3434 /* check whether it can be found in default mode table */ 3435 if (drm_monitor_supports_rb(drm_edid)) { 3436 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, 3437 true); 3438 if (mode) 3439 return mode; 3440 } 3441 mode = drm_mode_find_dmt(dev, hsize, vsize, vrefresh_rate, false); 3442 if (mode) 3443 return mode; 3444 3445 /* okay, generate it */ 3446 switch (timing_level) { 3447 case LEVEL_DMT: 3448 break; 3449 case LEVEL_GTF: 3450 mode = drm_gtf_mode(dev, hsize, vsize, vrefresh_rate, 0, 0); 3451 break; 3452 case LEVEL_GTF2: 3453 mode = drm_gtf2_mode(dev, drm_edid, hsize, vsize, vrefresh_rate); 3454 break; 3455 case LEVEL_CVT: 3456 mode = drm_cvt_mode(dev, hsize, vsize, vrefresh_rate, 0, 0, 3457 false); 3458 break; 3459 } 3460 return mode; 3461 } 3462 3463 /* 3464 * EDID is delightfully ambiguous about how interlaced modes are to be 3465 * encoded. Our internal representation is of frame height, but some 3466 * HDTV detailed timings are encoded as field height. 3467 * 3468 * The format list here is from CEA, in frame size. Technically we 3469 * should be checking refresh rate too. Whatever. 3470 */ 3471 static void 3472 drm_mode_do_interlace_quirk(struct drm_display_mode *mode, 3473 const struct detailed_pixel_timing *pt) 3474 { 3475 int i; 3476 static const struct { 3477 int w, h; 3478 } cea_interlaced[] = { 3479 { 1920, 1080 }, 3480 { 720, 480 }, 3481 { 1440, 480 }, 3482 { 2880, 480 }, 3483 { 720, 576 }, 3484 { 1440, 576 }, 3485 { 2880, 576 }, 3486 }; 3487 3488 if (!(pt->misc & DRM_EDID_PT_INTERLACED)) 3489 return; 3490 3491 for (i = 0; i < ARRAY_SIZE(cea_interlaced); i++) { 3492 if ((mode->hdisplay == cea_interlaced[i].w) && 3493 (mode->vdisplay == cea_interlaced[i].h / 2)) { 3494 mode->vdisplay *= 2; 3495 mode->vsync_start *= 2; 3496 mode->vsync_end *= 2; 3497 mode->vtotal *= 2; 3498 mode->vtotal |= 1; 3499 } 3500 } 3501 3502 mode->flags |= DRM_MODE_FLAG_INTERLACE; 3503 } 3504 3505 /* 3506 * Create a new mode from an EDID detailed timing section. An EDID detailed 3507 * timing block contains enough info for us to create and return a new struct 3508 * drm_display_mode. 3509 */ 3510 static struct drm_display_mode *drm_mode_detailed(struct drm_connector *connector, 3511 const struct drm_edid *drm_edid, 3512 const struct detailed_timing *timing) 3513 { 3514 const struct drm_display_info *info = &connector->display_info; 3515 struct drm_device *dev = connector->dev; 3516 struct drm_display_mode *mode; 3517 const struct detailed_pixel_timing *pt = &timing->data.pixel_data; 3518 unsigned hactive = (pt->hactive_hblank_hi & 0xf0) << 4 | pt->hactive_lo; 3519 unsigned vactive = (pt->vactive_vblank_hi & 0xf0) << 4 | pt->vactive_lo; 3520 unsigned hblank = (pt->hactive_hblank_hi & 0xf) << 8 | pt->hblank_lo; 3521 unsigned vblank = (pt->vactive_vblank_hi & 0xf) << 8 | pt->vblank_lo; 3522 unsigned hsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc0) << 2 | pt->hsync_offset_lo; 3523 unsigned hsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x30) << 4 | pt->hsync_pulse_width_lo; 3524 unsigned vsync_offset = (pt->hsync_vsync_offset_pulse_width_hi & 0xc) << 2 | pt->vsync_offset_pulse_width_lo >> 4; 3525 unsigned vsync_pulse_width = (pt->hsync_vsync_offset_pulse_width_hi & 0x3) << 4 | (pt->vsync_offset_pulse_width_lo & 0xf); 3526 3527 /* ignore tiny modes */ 3528 if (hactive < 64 || vactive < 64) 3529 return NULL; 3530 3531 if (pt->misc & DRM_EDID_PT_STEREO) { 3532 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Stereo mode not supported\n", 3533 connector->base.id, connector->name); 3534 return NULL; 3535 } 3536 if (!(pt->misc & DRM_EDID_PT_SEPARATE_SYNC)) { 3537 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Composite sync not supported\n", 3538 connector->base.id, connector->name); 3539 } 3540 3541 /* it is incorrect if hsync/vsync width is zero */ 3542 if (!hsync_pulse_width || !vsync_pulse_width) { 3543 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Incorrect Detailed timing. Wrong Hsync/Vsync pulse width\n", 3544 connector->base.id, connector->name); 3545 return NULL; 3546 } 3547 3548 if (info->quirks & EDID_QUIRK_FORCE_REDUCED_BLANKING) { 3549 mode = drm_cvt_mode(dev, hactive, vactive, 60, true, false, false); 3550 if (!mode) 3551 return NULL; 3552 3553 goto set_size; 3554 } 3555 3556 mode = drm_mode_create(dev); 3557 if (!mode) 3558 return NULL; 3559 3560 if (info->quirks & EDID_QUIRK_135_CLOCK_TOO_HIGH) 3561 mode->clock = 1088 * 10; 3562 else 3563 mode->clock = le16_to_cpu(timing->pixel_clock) * 10; 3564 3565 mode->hdisplay = hactive; 3566 mode->hsync_start = mode->hdisplay + hsync_offset; 3567 mode->hsync_end = mode->hsync_start + hsync_pulse_width; 3568 mode->htotal = mode->hdisplay + hblank; 3569 3570 mode->vdisplay = vactive; 3571 mode->vsync_start = mode->vdisplay + vsync_offset; 3572 mode->vsync_end = mode->vsync_start + vsync_pulse_width; 3573 mode->vtotal = mode->vdisplay + vblank; 3574 3575 /* Some EDIDs have bogus h/vsync_end values */ 3576 if (mode->hsync_end > mode->htotal) { 3577 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing hsync_end %d->%d\n", 3578 connector->base.id, connector->name, 3579 mode->hsync_end, mode->htotal); 3580 mode->hsync_end = mode->htotal; 3581 } 3582 if (mode->vsync_end > mode->vtotal) { 3583 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] reducing vsync_end %d->%d\n", 3584 connector->base.id, connector->name, 3585 mode->vsync_end, mode->vtotal); 3586 mode->vsync_end = mode->vtotal; 3587 } 3588 3589 drm_mode_do_interlace_quirk(mode, pt); 3590 3591 if (info->quirks & EDID_QUIRK_DETAILED_SYNC_PP) { 3592 mode->flags |= DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC; 3593 } else { 3594 mode->flags |= (pt->misc & DRM_EDID_PT_HSYNC_POSITIVE) ? 3595 DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 3596 mode->flags |= (pt->misc & DRM_EDID_PT_VSYNC_POSITIVE) ? 3597 DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 3598 } 3599 3600 set_size: 3601 mode->width_mm = pt->width_mm_lo | (pt->width_height_mm_hi & 0xf0) << 4; 3602 mode->height_mm = pt->height_mm_lo | (pt->width_height_mm_hi & 0xf) << 8; 3603 3604 if (info->quirks & EDID_QUIRK_DETAILED_IN_CM) { 3605 mode->width_mm *= 10; 3606 mode->height_mm *= 10; 3607 } 3608 3609 if (info->quirks & EDID_QUIRK_DETAILED_USE_MAXIMUM_SIZE) { 3610 mode->width_mm = drm_edid->edid->width_cm * 10; 3611 mode->height_mm = drm_edid->edid->height_cm * 10; 3612 } 3613 3614 mode->type = DRM_MODE_TYPE_DRIVER; 3615 drm_mode_set_name(mode); 3616 3617 return mode; 3618 } 3619 3620 static bool 3621 mode_in_hsync_range(const struct drm_display_mode *mode, 3622 const struct edid *edid, const u8 *t) 3623 { 3624 int hsync, hmin, hmax; 3625 3626 hmin = t[7]; 3627 if (edid->revision >= 4) 3628 hmin += ((t[4] & 0x04) ? 255 : 0); 3629 hmax = t[8]; 3630 if (edid->revision >= 4) 3631 hmax += ((t[4] & 0x08) ? 255 : 0); 3632 hsync = drm_mode_hsync(mode); 3633 3634 return (hsync <= hmax && hsync >= hmin); 3635 } 3636 3637 static bool 3638 mode_in_vsync_range(const struct drm_display_mode *mode, 3639 const struct edid *edid, const u8 *t) 3640 { 3641 int vsync, vmin, vmax; 3642 3643 vmin = t[5]; 3644 if (edid->revision >= 4) 3645 vmin += ((t[4] & 0x01) ? 255 : 0); 3646 vmax = t[6]; 3647 if (edid->revision >= 4) 3648 vmax += ((t[4] & 0x02) ? 255 : 0); 3649 vsync = drm_mode_vrefresh(mode); 3650 3651 return (vsync <= vmax && vsync >= vmin); 3652 } 3653 3654 static u32 3655 range_pixel_clock(const struct edid *edid, const u8 *t) 3656 { 3657 /* unspecified */ 3658 if (t[9] == 0 || t[9] == 255) 3659 return 0; 3660 3661 /* 1.4 with CVT support gives us real precision, yay */ 3662 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3663 return (t[9] * 10000) - ((t[12] >> 2) * 250); 3664 3665 /* 1.3 is pathetic, so fuzz up a bit */ 3666 return t[9] * 10000 + 5001; 3667 } 3668 3669 static bool mode_in_range(const struct drm_display_mode *mode, 3670 const struct drm_edid *drm_edid, 3671 const struct detailed_timing *timing) 3672 { 3673 const struct edid *edid = drm_edid->edid; 3674 u32 max_clock; 3675 const u8 *t = (const u8 *)timing; 3676 3677 if (!mode_in_hsync_range(mode, edid, t)) 3678 return false; 3679 3680 if (!mode_in_vsync_range(mode, edid, t)) 3681 return false; 3682 3683 max_clock = range_pixel_clock(edid, t); 3684 if (max_clock) 3685 if (mode->clock > max_clock) 3686 return false; 3687 3688 /* 1.4 max horizontal check */ 3689 if (edid->revision >= 4 && t[10] == DRM_EDID_CVT_SUPPORT_FLAG) 3690 if (t[13] && mode->hdisplay > 8 * (t[13] + (256 * (t[12]&0x3)))) 3691 return false; 3692 3693 if (mode_is_rb(mode) && !drm_monitor_supports_rb(drm_edid)) 3694 return false; 3695 3696 return true; 3697 } 3698 3699 static bool valid_inferred_mode(const struct drm_connector *connector, 3700 const struct drm_display_mode *mode) 3701 { 3702 const struct drm_display_mode *m; 3703 bool ok = false; 3704 3705 list_for_each_entry(m, &connector->probed_modes, head) { 3706 if (mode->hdisplay == m->hdisplay && 3707 mode->vdisplay == m->vdisplay && 3708 drm_mode_vrefresh(mode) == drm_mode_vrefresh(m)) 3709 return false; /* duplicated */ 3710 if (mode->hdisplay <= m->hdisplay && 3711 mode->vdisplay <= m->vdisplay) 3712 ok = true; 3713 } 3714 return ok; 3715 } 3716 3717 static int drm_dmt_modes_for_range(struct drm_connector *connector, 3718 const struct drm_edid *drm_edid, 3719 const struct detailed_timing *timing) 3720 { 3721 int i, modes = 0; 3722 struct drm_display_mode *newmode; 3723 struct drm_device *dev = connector->dev; 3724 3725 for (i = 0; i < ARRAY_SIZE(drm_dmt_modes); i++) { 3726 if (mode_in_range(drm_dmt_modes + i, drm_edid, timing) && 3727 valid_inferred_mode(connector, drm_dmt_modes + i)) { 3728 newmode = drm_mode_duplicate(dev, &drm_dmt_modes[i]); 3729 if (newmode) { 3730 drm_mode_probed_add(connector, newmode); 3731 modes++; 3732 } 3733 } 3734 } 3735 3736 return modes; 3737 } 3738 3739 /* fix up 1366x768 mode from 1368x768; 3740 * GFT/CVT can't express 1366 width which isn't dividable by 8 3741 */ 3742 void drm_mode_fixup_1366x768(struct drm_display_mode *mode) 3743 { 3744 if (mode->hdisplay == 1368 && mode->vdisplay == 768) { 3745 mode->hdisplay = 1366; 3746 mode->hsync_start--; 3747 mode->hsync_end--; 3748 drm_mode_set_name(mode); 3749 } 3750 } 3751 3752 static int drm_gtf_modes_for_range(struct drm_connector *connector, 3753 const struct drm_edid *drm_edid, 3754 const struct detailed_timing *timing) 3755 { 3756 int i, modes = 0; 3757 struct drm_display_mode *newmode; 3758 struct drm_device *dev = connector->dev; 3759 3760 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3761 const struct minimode *m = &extra_modes[i]; 3762 3763 newmode = drm_gtf_mode(dev, m->w, m->h, m->r, 0, 0); 3764 if (!newmode) 3765 return modes; 3766 3767 drm_mode_fixup_1366x768(newmode); 3768 if (!mode_in_range(newmode, drm_edid, timing) || 3769 !valid_inferred_mode(connector, newmode)) { 3770 drm_mode_destroy(dev, newmode); 3771 continue; 3772 } 3773 3774 drm_mode_probed_add(connector, newmode); 3775 modes++; 3776 } 3777 3778 return modes; 3779 } 3780 3781 static int drm_gtf2_modes_for_range(struct drm_connector *connector, 3782 const struct drm_edid *drm_edid, 3783 const struct detailed_timing *timing) 3784 { 3785 int i, modes = 0; 3786 struct drm_display_mode *newmode; 3787 struct drm_device *dev = connector->dev; 3788 3789 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3790 const struct minimode *m = &extra_modes[i]; 3791 3792 newmode = drm_gtf2_mode(dev, drm_edid, m->w, m->h, m->r); 3793 if (!newmode) 3794 return modes; 3795 3796 drm_mode_fixup_1366x768(newmode); 3797 if (!mode_in_range(newmode, drm_edid, timing) || 3798 !valid_inferred_mode(connector, newmode)) { 3799 drm_mode_destroy(dev, newmode); 3800 continue; 3801 } 3802 3803 drm_mode_probed_add(connector, newmode); 3804 modes++; 3805 } 3806 3807 return modes; 3808 } 3809 3810 static int drm_cvt_modes_for_range(struct drm_connector *connector, 3811 const struct drm_edid *drm_edid, 3812 const struct detailed_timing *timing) 3813 { 3814 int i, modes = 0; 3815 struct drm_display_mode *newmode; 3816 struct drm_device *dev = connector->dev; 3817 bool rb = drm_monitor_supports_rb(drm_edid); 3818 3819 for (i = 0; i < ARRAY_SIZE(extra_modes); i++) { 3820 const struct minimode *m = &extra_modes[i]; 3821 3822 newmode = drm_cvt_mode(dev, m->w, m->h, m->r, rb, 0, 0); 3823 if (!newmode) 3824 return modes; 3825 3826 drm_mode_fixup_1366x768(newmode); 3827 if (!mode_in_range(newmode, drm_edid, timing) || 3828 !valid_inferred_mode(connector, newmode)) { 3829 drm_mode_destroy(dev, newmode); 3830 continue; 3831 } 3832 3833 drm_mode_probed_add(connector, newmode); 3834 modes++; 3835 } 3836 3837 return modes; 3838 } 3839 3840 static void 3841 do_inferred_modes(const struct detailed_timing *timing, void *c) 3842 { 3843 struct detailed_mode_closure *closure = c; 3844 const struct detailed_non_pixel *data = &timing->data.other_data; 3845 const struct detailed_data_monitor_range *range = &data->data.range; 3846 3847 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 3848 return; 3849 3850 closure->modes += drm_dmt_modes_for_range(closure->connector, 3851 closure->drm_edid, 3852 timing); 3853 3854 if (closure->drm_edid->edid->revision < 2) 3855 return; /* GTF not defined yet */ 3856 3857 switch (range->flags) { 3858 case DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG: 3859 closure->modes += drm_gtf2_modes_for_range(closure->connector, 3860 closure->drm_edid, 3861 timing); 3862 break; 3863 case DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG: 3864 closure->modes += drm_gtf_modes_for_range(closure->connector, 3865 closure->drm_edid, 3866 timing); 3867 break; 3868 case DRM_EDID_CVT_SUPPORT_FLAG: 3869 if (closure->drm_edid->edid->revision < 4) 3870 break; 3871 3872 closure->modes += drm_cvt_modes_for_range(closure->connector, 3873 closure->drm_edid, 3874 timing); 3875 break; 3876 case DRM_EDID_RANGE_LIMITS_ONLY_FLAG: 3877 default: 3878 break; 3879 } 3880 } 3881 3882 static int add_inferred_modes(struct drm_connector *connector, 3883 const struct drm_edid *drm_edid) 3884 { 3885 struct detailed_mode_closure closure = { 3886 .connector = connector, 3887 .drm_edid = drm_edid, 3888 }; 3889 3890 if (drm_edid->edid->revision >= 1) 3891 drm_for_each_detailed_block(drm_edid, do_inferred_modes, &closure); 3892 3893 return closure.modes; 3894 } 3895 3896 static int 3897 drm_est3_modes(struct drm_connector *connector, const struct detailed_timing *timing) 3898 { 3899 int i, j, m, modes = 0; 3900 struct drm_display_mode *mode; 3901 const u8 *est = ((const u8 *)timing) + 6; 3902 3903 for (i = 0; i < 6; i++) { 3904 for (j = 7; j >= 0; j--) { 3905 m = (i * 8) + (7 - j); 3906 if (m >= ARRAY_SIZE(est3_modes)) 3907 break; 3908 if (est[i] & (1 << j)) { 3909 mode = drm_mode_find_dmt(connector->dev, 3910 est3_modes[m].w, 3911 est3_modes[m].h, 3912 est3_modes[m].r, 3913 est3_modes[m].rb); 3914 if (mode) { 3915 drm_mode_probed_add(connector, mode); 3916 modes++; 3917 } 3918 } 3919 } 3920 } 3921 3922 return modes; 3923 } 3924 3925 static void 3926 do_established_modes(const struct detailed_timing *timing, void *c) 3927 { 3928 struct detailed_mode_closure *closure = c; 3929 3930 if (!is_display_descriptor(timing, EDID_DETAIL_EST_TIMINGS)) 3931 return; 3932 3933 closure->modes += drm_est3_modes(closure->connector, timing); 3934 } 3935 3936 /* 3937 * Get established modes from EDID and add them. Each EDID block contains a 3938 * bitmap of the supported "established modes" list (defined above). Tease them 3939 * out and add them to the global modes list. 3940 */ 3941 static int add_established_modes(struct drm_connector *connector, 3942 const struct drm_edid *drm_edid) 3943 { 3944 struct drm_device *dev = connector->dev; 3945 const struct edid *edid = drm_edid->edid; 3946 unsigned long est_bits = edid->established_timings.t1 | 3947 (edid->established_timings.t2 << 8) | 3948 ((edid->established_timings.mfg_rsvd & 0x80) << 9); 3949 int i, modes = 0; 3950 struct detailed_mode_closure closure = { 3951 .connector = connector, 3952 .drm_edid = drm_edid, 3953 }; 3954 3955 for (i = 0; i <= EDID_EST_TIMINGS; i++) { 3956 if (est_bits & (1<<i)) { 3957 struct drm_display_mode *newmode; 3958 3959 newmode = drm_mode_duplicate(dev, &edid_est_modes[i]); 3960 if (newmode) { 3961 drm_mode_probed_add(connector, newmode); 3962 modes++; 3963 } 3964 } 3965 } 3966 3967 if (edid->revision >= 1) 3968 drm_for_each_detailed_block(drm_edid, do_established_modes, 3969 &closure); 3970 3971 return modes + closure.modes; 3972 } 3973 3974 static void 3975 do_standard_modes(const struct detailed_timing *timing, void *c) 3976 { 3977 struct detailed_mode_closure *closure = c; 3978 const struct detailed_non_pixel *data = &timing->data.other_data; 3979 struct drm_connector *connector = closure->connector; 3980 int i; 3981 3982 if (!is_display_descriptor(timing, EDID_DETAIL_STD_MODES)) 3983 return; 3984 3985 for (i = 0; i < 6; i++) { 3986 const struct std_timing *std = &data->data.timings[i]; 3987 struct drm_display_mode *newmode; 3988 3989 newmode = drm_mode_std(connector, closure->drm_edid, std); 3990 if (newmode) { 3991 drm_mode_probed_add(connector, newmode); 3992 closure->modes++; 3993 } 3994 } 3995 } 3996 3997 /* 3998 * Get standard modes from EDID and add them. Standard modes can be calculated 3999 * using the appropriate standard (DMT, GTF, or CVT). Grab them from EDID and 4000 * add them to the list. 4001 */ 4002 static int add_standard_modes(struct drm_connector *connector, 4003 const struct drm_edid *drm_edid) 4004 { 4005 int i, modes = 0; 4006 struct detailed_mode_closure closure = { 4007 .connector = connector, 4008 .drm_edid = drm_edid, 4009 }; 4010 4011 for (i = 0; i < EDID_STD_TIMINGS; i++) { 4012 struct drm_display_mode *newmode; 4013 4014 newmode = drm_mode_std(connector, drm_edid, 4015 &drm_edid->edid->standard_timings[i]); 4016 if (newmode) { 4017 drm_mode_probed_add(connector, newmode); 4018 modes++; 4019 } 4020 } 4021 4022 if (drm_edid->edid->revision >= 1) 4023 drm_for_each_detailed_block(drm_edid, do_standard_modes, 4024 &closure); 4025 4026 /* XXX should also look for standard codes in VTB blocks */ 4027 4028 return modes + closure.modes; 4029 } 4030 4031 static int drm_cvt_modes(struct drm_connector *connector, 4032 const struct detailed_timing *timing) 4033 { 4034 int i, j, modes = 0; 4035 struct drm_display_mode *newmode; 4036 struct drm_device *dev = connector->dev; 4037 const struct cvt_timing *cvt; 4038 static const int rates[] = { 60, 85, 75, 60, 50 }; 4039 const u8 empty[3] = { 0, 0, 0 }; 4040 4041 for (i = 0; i < 4; i++) { 4042 int width, height; 4043 4044 cvt = &(timing->data.other_data.data.cvt[i]); 4045 4046 if (!memcmp(cvt->code, empty, 3)) 4047 continue; 4048 4049 height = (cvt->code[0] + ((cvt->code[1] & 0xf0) << 4) + 1) * 2; 4050 switch (cvt->code[1] & 0x0c) { 4051 /* default - because compiler doesn't see that we've enumerated all cases */ 4052 default: 4053 case 0x00: 4054 width = height * 4 / 3; 4055 break; 4056 case 0x04: 4057 width = height * 16 / 9; 4058 break; 4059 case 0x08: 4060 width = height * 16 / 10; 4061 break; 4062 case 0x0c: 4063 width = height * 15 / 9; 4064 break; 4065 } 4066 4067 for (j = 1; j < 5; j++) { 4068 if (cvt->code[2] & (1 << j)) { 4069 newmode = drm_cvt_mode(dev, width, height, 4070 rates[j], j == 0, 4071 false, false); 4072 if (newmode) { 4073 drm_mode_probed_add(connector, newmode); 4074 modes++; 4075 } 4076 } 4077 } 4078 } 4079 4080 return modes; 4081 } 4082 4083 static void 4084 do_cvt_mode(const struct detailed_timing *timing, void *c) 4085 { 4086 struct detailed_mode_closure *closure = c; 4087 4088 if (!is_display_descriptor(timing, EDID_DETAIL_CVT_3BYTE)) 4089 return; 4090 4091 closure->modes += drm_cvt_modes(closure->connector, timing); 4092 } 4093 4094 static int 4095 add_cvt_modes(struct drm_connector *connector, const struct drm_edid *drm_edid) 4096 { 4097 struct detailed_mode_closure closure = { 4098 .connector = connector, 4099 .drm_edid = drm_edid, 4100 }; 4101 4102 if (drm_edid->edid->revision >= 3) 4103 drm_for_each_detailed_block(drm_edid, do_cvt_mode, &closure); 4104 4105 /* XXX should also look for CVT codes in VTB blocks */ 4106 4107 return closure.modes; 4108 } 4109 4110 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 4111 struct drm_display_mode *mode); 4112 4113 static void 4114 do_detailed_mode(const struct detailed_timing *timing, void *c) 4115 { 4116 struct detailed_mode_closure *closure = c; 4117 struct drm_display_mode *newmode; 4118 4119 if (!is_detailed_timing_descriptor(timing)) 4120 return; 4121 4122 newmode = drm_mode_detailed(closure->connector, 4123 closure->drm_edid, timing); 4124 if (!newmode) 4125 return; 4126 4127 if (closure->preferred) 4128 newmode->type |= DRM_MODE_TYPE_PREFERRED; 4129 4130 /* 4131 * Detailed modes are limited to 10kHz pixel clock resolution, 4132 * so fix up anything that looks like CEA/HDMI mode, but the clock 4133 * is just slightly off. 4134 */ 4135 fixup_detailed_cea_mode_clock(closure->connector, newmode); 4136 4137 drm_mode_probed_add(closure->connector, newmode); 4138 closure->modes++; 4139 closure->preferred = false; 4140 } 4141 4142 /* 4143 * add_detailed_modes - Add modes from detailed timings 4144 * @connector: attached connector 4145 * @drm_edid: EDID block to scan 4146 */ 4147 static int add_detailed_modes(struct drm_connector *connector, 4148 const struct drm_edid *drm_edid) 4149 { 4150 struct detailed_mode_closure closure = { 4151 .connector = connector, 4152 .drm_edid = drm_edid, 4153 }; 4154 4155 if (drm_edid->edid->revision >= 4) 4156 closure.preferred = true; /* first detailed timing is always preferred */ 4157 else 4158 closure.preferred = 4159 drm_edid->edid->features & DRM_EDID_FEATURE_PREFERRED_TIMING; 4160 4161 drm_for_each_detailed_block(drm_edid, do_detailed_mode, &closure); 4162 4163 return closure.modes; 4164 } 4165 4166 /* CTA-861-H Table 60 - CTA Tag Codes */ 4167 #define CTA_DB_AUDIO 1 4168 #define CTA_DB_VIDEO 2 4169 #define CTA_DB_VENDOR 3 4170 #define CTA_DB_SPEAKER 4 4171 #define CTA_DB_EXTENDED_TAG 7 4172 4173 /* CTA-861-H Table 62 - CTA Extended Tag Codes */ 4174 #define CTA_EXT_DB_VIDEO_CAP 0 4175 #define CTA_EXT_DB_VENDOR 1 4176 #define CTA_EXT_DB_HDR_STATIC_METADATA 6 4177 #define CTA_EXT_DB_420_VIDEO_DATA 14 4178 #define CTA_EXT_DB_420_VIDEO_CAP_MAP 15 4179 #define CTA_EXT_DB_HF_EEODB 0x78 4180 #define CTA_EXT_DB_HF_SCDB 0x79 4181 4182 #define EDID_BASIC_AUDIO (1 << 6) 4183 #define EDID_CEA_YCRCB444 (1 << 5) 4184 #define EDID_CEA_YCRCB422 (1 << 4) 4185 #define EDID_CEA_VCDB_QS (1 << 6) 4186 4187 /* 4188 * Search EDID for CEA extension block. 4189 * 4190 * FIXME: Prefer not returning pointers to raw EDID data. 4191 */ 4192 const u8 *drm_edid_find_extension(const struct drm_edid *drm_edid, 4193 int ext_id, int *ext_index) 4194 { 4195 const u8 *edid_ext = NULL; 4196 int i; 4197 4198 /* No EDID or EDID extensions */ 4199 if (!drm_edid || !drm_edid_extension_block_count(drm_edid)) 4200 return NULL; 4201 4202 /* Find CEA extension */ 4203 for (i = *ext_index; i < drm_edid_extension_block_count(drm_edid); i++) { 4204 edid_ext = drm_edid_extension_block_data(drm_edid, i); 4205 if (edid_block_tag(edid_ext) == ext_id) 4206 break; 4207 } 4208 4209 if (i >= drm_edid_extension_block_count(drm_edid)) 4210 return NULL; 4211 4212 *ext_index = i + 1; 4213 4214 return edid_ext; 4215 } 4216 4217 /* Return true if the EDID has a CTA extension or a DisplayID CTA data block */ 4218 static bool drm_edid_has_cta_extension(const struct drm_edid *drm_edid) 4219 { 4220 const struct displayid_block *block; 4221 struct displayid_iter iter; 4222 struct drm_edid_iter edid_iter; 4223 const u8 *ext; 4224 bool found = false; 4225 4226 /* Look for a top level CEA extension block */ 4227 drm_edid_iter_begin(drm_edid, &edid_iter); 4228 drm_edid_iter_for_each(ext, &edid_iter) { 4229 if (ext[0] == CEA_EXT) { 4230 found = true; 4231 break; 4232 } 4233 } 4234 drm_edid_iter_end(&edid_iter); 4235 4236 if (found) 4237 return true; 4238 4239 /* CEA blocks can also be found embedded in a DisplayID block */ 4240 displayid_iter_edid_begin(drm_edid, &iter); 4241 displayid_iter_for_each(block, &iter) { 4242 if (block->tag == DATA_BLOCK_CTA) { 4243 found = true; 4244 break; 4245 } 4246 } 4247 displayid_iter_end(&iter); 4248 4249 return found; 4250 } 4251 4252 static __always_inline const struct drm_display_mode *cea_mode_for_vic(u8 vic) 4253 { 4254 BUILD_BUG_ON(1 + ARRAY_SIZE(edid_cea_modes_1) - 1 != 127); 4255 BUILD_BUG_ON(193 + ARRAY_SIZE(edid_cea_modes_193) - 1 != 219); 4256 4257 if (vic >= 1 && vic < 1 + ARRAY_SIZE(edid_cea_modes_1)) 4258 return &edid_cea_modes_1[vic - 1]; 4259 if (vic >= 193 && vic < 193 + ARRAY_SIZE(edid_cea_modes_193)) 4260 return &edid_cea_modes_193[vic - 193]; 4261 return NULL; 4262 } 4263 4264 static u8 cea_num_vics(void) 4265 { 4266 return 193 + ARRAY_SIZE(edid_cea_modes_193); 4267 } 4268 4269 static u8 cea_next_vic(u8 vic) 4270 { 4271 if (++vic == 1 + ARRAY_SIZE(edid_cea_modes_1)) 4272 vic = 193; 4273 return vic; 4274 } 4275 4276 /* 4277 * Calculate the alternate clock for the CEA mode 4278 * (60Hz vs. 59.94Hz etc.) 4279 */ 4280 static unsigned int 4281 cea_mode_alternate_clock(const struct drm_display_mode *cea_mode) 4282 { 4283 unsigned int clock = cea_mode->clock; 4284 4285 if (drm_mode_vrefresh(cea_mode) % 6 != 0) 4286 return clock; 4287 4288 /* 4289 * edid_cea_modes contains the 59.94Hz 4290 * variant for 240 and 480 line modes, 4291 * and the 60Hz variant otherwise. 4292 */ 4293 if (cea_mode->vdisplay == 240 || cea_mode->vdisplay == 480) 4294 clock = DIV_ROUND_CLOSEST(clock * 1001, 1000); 4295 else 4296 clock = DIV_ROUND_CLOSEST(clock * 1000, 1001); 4297 4298 return clock; 4299 } 4300 4301 static bool 4302 cea_mode_alternate_timings(u8 vic, struct drm_display_mode *mode) 4303 { 4304 /* 4305 * For certain VICs the spec allows the vertical 4306 * front porch to vary by one or two lines. 4307 * 4308 * cea_modes[] stores the variant with the shortest 4309 * vertical front porch. We can adjust the mode to 4310 * get the other variants by simply increasing the 4311 * vertical front porch length. 4312 */ 4313 BUILD_BUG_ON(cea_mode_for_vic(8)->vtotal != 262 || 4314 cea_mode_for_vic(9)->vtotal != 262 || 4315 cea_mode_for_vic(12)->vtotal != 262 || 4316 cea_mode_for_vic(13)->vtotal != 262 || 4317 cea_mode_for_vic(23)->vtotal != 312 || 4318 cea_mode_for_vic(24)->vtotal != 312 || 4319 cea_mode_for_vic(27)->vtotal != 312 || 4320 cea_mode_for_vic(28)->vtotal != 312); 4321 4322 if (((vic == 8 || vic == 9 || 4323 vic == 12 || vic == 13) && mode->vtotal < 263) || 4324 ((vic == 23 || vic == 24 || 4325 vic == 27 || vic == 28) && mode->vtotal < 314)) { 4326 mode->vsync_start++; 4327 mode->vsync_end++; 4328 mode->vtotal++; 4329 4330 return true; 4331 } 4332 4333 return false; 4334 } 4335 4336 static u8 drm_match_cea_mode_clock_tolerance(const struct drm_display_mode *to_match, 4337 unsigned int clock_tolerance) 4338 { 4339 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4340 u8 vic; 4341 4342 if (!to_match->clock) 4343 return 0; 4344 4345 if (to_match->picture_aspect_ratio) 4346 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4347 4348 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4349 struct drm_display_mode cea_mode; 4350 unsigned int clock1, clock2; 4351 4352 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4353 4354 /* Check both 60Hz and 59.94Hz */ 4355 clock1 = cea_mode.clock; 4356 clock2 = cea_mode_alternate_clock(&cea_mode); 4357 4358 if (abs(to_match->clock - clock1) > clock_tolerance && 4359 abs(to_match->clock - clock2) > clock_tolerance) 4360 continue; 4361 4362 do { 4363 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4364 return vic; 4365 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4366 } 4367 4368 return 0; 4369 } 4370 4371 /** 4372 * drm_match_cea_mode - look for a CEA mode matching given mode 4373 * @to_match: display mode 4374 * 4375 * Return: The CEA Video ID (VIC) of the mode or 0 if it isn't a CEA-861 4376 * mode. 4377 */ 4378 u8 drm_match_cea_mode(const struct drm_display_mode *to_match) 4379 { 4380 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4381 u8 vic; 4382 4383 if (!to_match->clock) 4384 return 0; 4385 4386 if (to_match->picture_aspect_ratio) 4387 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4388 4389 for (vic = 1; vic < cea_num_vics(); vic = cea_next_vic(vic)) { 4390 struct drm_display_mode cea_mode; 4391 unsigned int clock1, clock2; 4392 4393 drm_mode_init(&cea_mode, cea_mode_for_vic(vic)); 4394 4395 /* Check both 60Hz and 59.94Hz */ 4396 clock1 = cea_mode.clock; 4397 clock2 = cea_mode_alternate_clock(&cea_mode); 4398 4399 if (KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock1) && 4400 KHZ2PICOS(to_match->clock) != KHZ2PICOS(clock2)) 4401 continue; 4402 4403 do { 4404 if (drm_mode_match(to_match, &cea_mode, match_flags)) 4405 return vic; 4406 } while (cea_mode_alternate_timings(vic, &cea_mode)); 4407 } 4408 4409 return 0; 4410 } 4411 EXPORT_SYMBOL(drm_match_cea_mode); 4412 4413 static bool drm_valid_cea_vic(u8 vic) 4414 { 4415 return cea_mode_for_vic(vic) != NULL; 4416 } 4417 4418 static enum hdmi_picture_aspect drm_get_cea_aspect_ratio(const u8 video_code) 4419 { 4420 const struct drm_display_mode *mode = cea_mode_for_vic(video_code); 4421 4422 if (mode) 4423 return mode->picture_aspect_ratio; 4424 4425 return HDMI_PICTURE_ASPECT_NONE; 4426 } 4427 4428 static enum hdmi_picture_aspect drm_get_hdmi_aspect_ratio(const u8 video_code) 4429 { 4430 return edid_4k_modes[video_code].picture_aspect_ratio; 4431 } 4432 4433 /* 4434 * Calculate the alternate clock for HDMI modes (those from the HDMI vendor 4435 * specific block). 4436 */ 4437 static unsigned int 4438 hdmi_mode_alternate_clock(const struct drm_display_mode *hdmi_mode) 4439 { 4440 return cea_mode_alternate_clock(hdmi_mode); 4441 } 4442 4443 static u8 drm_match_hdmi_mode_clock_tolerance(const struct drm_display_mode *to_match, 4444 unsigned int clock_tolerance) 4445 { 4446 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4447 u8 vic; 4448 4449 if (!to_match->clock) 4450 return 0; 4451 4452 if (to_match->picture_aspect_ratio) 4453 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4454 4455 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4456 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4457 unsigned int clock1, clock2; 4458 4459 /* Make sure to also match alternate clocks */ 4460 clock1 = hdmi_mode->clock; 4461 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4462 4463 if (abs(to_match->clock - clock1) > clock_tolerance && 4464 abs(to_match->clock - clock2) > clock_tolerance) 4465 continue; 4466 4467 if (drm_mode_match(to_match, hdmi_mode, match_flags)) 4468 return vic; 4469 } 4470 4471 return 0; 4472 } 4473 4474 /* 4475 * drm_match_hdmi_mode - look for a HDMI mode matching given mode 4476 * @to_match: display mode 4477 * 4478 * An HDMI mode is one defined in the HDMI vendor specific block. 4479 * 4480 * Returns the HDMI Video ID (VIC) of the mode or 0 if it isn't one. 4481 */ 4482 static u8 drm_match_hdmi_mode(const struct drm_display_mode *to_match) 4483 { 4484 unsigned int match_flags = DRM_MODE_MATCH_TIMINGS | DRM_MODE_MATCH_FLAGS; 4485 u8 vic; 4486 4487 if (!to_match->clock) 4488 return 0; 4489 4490 if (to_match->picture_aspect_ratio) 4491 match_flags |= DRM_MODE_MATCH_ASPECT_RATIO; 4492 4493 for (vic = 1; vic < ARRAY_SIZE(edid_4k_modes); vic++) { 4494 const struct drm_display_mode *hdmi_mode = &edid_4k_modes[vic]; 4495 unsigned int clock1, clock2; 4496 4497 /* Make sure to also match alternate clocks */ 4498 clock1 = hdmi_mode->clock; 4499 clock2 = hdmi_mode_alternate_clock(hdmi_mode); 4500 4501 if ((KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock1) || 4502 KHZ2PICOS(to_match->clock) == KHZ2PICOS(clock2)) && 4503 drm_mode_match(to_match, hdmi_mode, match_flags)) 4504 return vic; 4505 } 4506 return 0; 4507 } 4508 4509 static bool drm_valid_hdmi_vic(u8 vic) 4510 { 4511 return vic > 0 && vic < ARRAY_SIZE(edid_4k_modes); 4512 } 4513 4514 static int add_alternate_cea_modes(struct drm_connector *connector, 4515 const struct drm_edid *drm_edid) 4516 { 4517 struct drm_device *dev = connector->dev; 4518 struct drm_display_mode *mode, *tmp; 4519 LIST_HEAD(list); 4520 int modes = 0; 4521 4522 /* Don't add CTA modes if the CTA extension block is missing */ 4523 if (!drm_edid_has_cta_extension(drm_edid)) 4524 return 0; 4525 4526 /* 4527 * Go through all probed modes and create a new mode 4528 * with the alternate clock for certain CEA modes. 4529 */ 4530 list_for_each_entry(mode, &connector->probed_modes, head) { 4531 const struct drm_display_mode *cea_mode = NULL; 4532 struct drm_display_mode *newmode; 4533 u8 vic = drm_match_cea_mode(mode); 4534 unsigned int clock1, clock2; 4535 4536 if (drm_valid_cea_vic(vic)) { 4537 cea_mode = cea_mode_for_vic(vic); 4538 clock2 = cea_mode_alternate_clock(cea_mode); 4539 } else { 4540 vic = drm_match_hdmi_mode(mode); 4541 if (drm_valid_hdmi_vic(vic)) { 4542 cea_mode = &edid_4k_modes[vic]; 4543 clock2 = hdmi_mode_alternate_clock(cea_mode); 4544 } 4545 } 4546 4547 if (!cea_mode) 4548 continue; 4549 4550 clock1 = cea_mode->clock; 4551 4552 if (clock1 == clock2) 4553 continue; 4554 4555 if (mode->clock != clock1 && mode->clock != clock2) 4556 continue; 4557 4558 newmode = drm_mode_duplicate(dev, cea_mode); 4559 if (!newmode) 4560 continue; 4561 4562 /* Carry over the stereo flags */ 4563 newmode->flags |= mode->flags & DRM_MODE_FLAG_3D_MASK; 4564 4565 /* 4566 * The current mode could be either variant. Make 4567 * sure to pick the "other" clock for the new mode. 4568 */ 4569 if (mode->clock != clock1) 4570 newmode->clock = clock1; 4571 else 4572 newmode->clock = clock2; 4573 4574 list_add_tail(&newmode->head, &list); 4575 } 4576 4577 list_for_each_entry_safe(mode, tmp, &list, head) { 4578 list_del(&mode->head); 4579 drm_mode_probed_add(connector, mode); 4580 modes++; 4581 } 4582 4583 return modes; 4584 } 4585 4586 static u8 svd_to_vic(u8 svd) 4587 { 4588 /* 0-6 bit vic, 7th bit native mode indicator */ 4589 if ((svd >= 1 && svd <= 64) || (svd >= 129 && svd <= 192)) 4590 return svd & 127; 4591 4592 return svd; 4593 } 4594 4595 /* 4596 * Return a display mode for the 0-based vic_index'th VIC across all CTA VDBs in 4597 * the EDID, or NULL on errors. 4598 */ 4599 static struct drm_display_mode * 4600 drm_display_mode_from_vic_index(struct drm_connector *connector, int vic_index) 4601 { 4602 const struct drm_display_info *info = &connector->display_info; 4603 struct drm_device *dev = connector->dev; 4604 4605 if (!info->vics || vic_index >= info->vics_len || !info->vics[vic_index]) 4606 return NULL; 4607 4608 return drm_display_mode_from_cea_vic(dev, info->vics[vic_index]); 4609 } 4610 4611 /* 4612 * do_y420vdb_modes - Parse YCBCR 420 only modes 4613 * @connector: connector corresponding to the HDMI sink 4614 * @svds: start of the data block of CEA YCBCR 420 VDB 4615 * @len: length of the CEA YCBCR 420 VDB 4616 * 4617 * Parse the CEA-861-F YCBCR 420 Video Data Block (Y420VDB) 4618 * which contains modes which can be supported in YCBCR 420 4619 * output format only. 4620 */ 4621 static int do_y420vdb_modes(struct drm_connector *connector, 4622 const u8 *svds, u8 svds_len) 4623 { 4624 struct drm_device *dev = connector->dev; 4625 int modes = 0, i; 4626 4627 for (i = 0; i < svds_len; i++) { 4628 u8 vic = svd_to_vic(svds[i]); 4629 struct drm_display_mode *newmode; 4630 4631 if (!drm_valid_cea_vic(vic)) 4632 continue; 4633 4634 newmode = drm_mode_duplicate(dev, cea_mode_for_vic(vic)); 4635 if (!newmode) 4636 break; 4637 drm_mode_probed_add(connector, newmode); 4638 modes++; 4639 } 4640 4641 return modes; 4642 } 4643 4644 /** 4645 * drm_display_mode_from_cea_vic() - return a mode for CEA VIC 4646 * @dev: DRM device 4647 * @video_code: CEA VIC of the mode 4648 * 4649 * Creates a new mode matching the specified CEA VIC. 4650 * 4651 * Returns: A new drm_display_mode on success or NULL on failure 4652 */ 4653 struct drm_display_mode * 4654 drm_display_mode_from_cea_vic(struct drm_device *dev, 4655 u8 video_code) 4656 { 4657 const struct drm_display_mode *cea_mode; 4658 struct drm_display_mode *newmode; 4659 4660 cea_mode = cea_mode_for_vic(video_code); 4661 if (!cea_mode) 4662 return NULL; 4663 4664 newmode = drm_mode_duplicate(dev, cea_mode); 4665 if (!newmode) 4666 return NULL; 4667 4668 return newmode; 4669 } 4670 EXPORT_SYMBOL(drm_display_mode_from_cea_vic); 4671 4672 /* Add modes based on VICs parsed in parse_cta_vdb() */ 4673 static int add_cta_vdb_modes(struct drm_connector *connector) 4674 { 4675 const struct drm_display_info *info = &connector->display_info; 4676 int i, modes = 0; 4677 4678 if (!info->vics) 4679 return 0; 4680 4681 for (i = 0; i < info->vics_len; i++) { 4682 struct drm_display_mode *mode; 4683 4684 mode = drm_display_mode_from_vic_index(connector, i); 4685 if (mode) { 4686 drm_mode_probed_add(connector, mode); 4687 modes++; 4688 } 4689 } 4690 4691 return modes; 4692 } 4693 4694 struct stereo_mandatory_mode { 4695 int width, height, vrefresh; 4696 unsigned int flags; 4697 }; 4698 4699 static const struct stereo_mandatory_mode stereo_mandatory_modes[] = { 4700 { 1920, 1080, 24, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4701 { 1920, 1080, 24, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4702 { 1920, 1080, 50, 4703 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4704 { 1920, 1080, 60, 4705 DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF }, 4706 { 1280, 720, 50, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4707 { 1280, 720, 50, DRM_MODE_FLAG_3D_FRAME_PACKING }, 4708 { 1280, 720, 60, DRM_MODE_FLAG_3D_TOP_AND_BOTTOM }, 4709 { 1280, 720, 60, DRM_MODE_FLAG_3D_FRAME_PACKING } 4710 }; 4711 4712 static bool 4713 stereo_match_mandatory(const struct drm_display_mode *mode, 4714 const struct stereo_mandatory_mode *stereo_mode) 4715 { 4716 unsigned int interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE; 4717 4718 return mode->hdisplay == stereo_mode->width && 4719 mode->vdisplay == stereo_mode->height && 4720 interlaced == (stereo_mode->flags & DRM_MODE_FLAG_INTERLACE) && 4721 drm_mode_vrefresh(mode) == stereo_mode->vrefresh; 4722 } 4723 4724 static int add_hdmi_mandatory_stereo_modes(struct drm_connector *connector) 4725 { 4726 struct drm_device *dev = connector->dev; 4727 const struct drm_display_mode *mode; 4728 struct list_head stereo_modes; 4729 int modes = 0, i; 4730 4731 INIT_LIST_HEAD(&stereo_modes); 4732 4733 list_for_each_entry(mode, &connector->probed_modes, head) { 4734 for (i = 0; i < ARRAY_SIZE(stereo_mandatory_modes); i++) { 4735 const struct stereo_mandatory_mode *mandatory; 4736 struct drm_display_mode *new_mode; 4737 4738 if (!stereo_match_mandatory(mode, 4739 &stereo_mandatory_modes[i])) 4740 continue; 4741 4742 mandatory = &stereo_mandatory_modes[i]; 4743 new_mode = drm_mode_duplicate(dev, mode); 4744 if (!new_mode) 4745 continue; 4746 4747 new_mode->flags |= mandatory->flags; 4748 list_add_tail(&new_mode->head, &stereo_modes); 4749 modes++; 4750 } 4751 } 4752 4753 list_splice_tail(&stereo_modes, &connector->probed_modes); 4754 4755 return modes; 4756 } 4757 4758 static int add_hdmi_mode(struct drm_connector *connector, u8 vic) 4759 { 4760 struct drm_device *dev = connector->dev; 4761 struct drm_display_mode *newmode; 4762 4763 if (!drm_valid_hdmi_vic(vic)) { 4764 drm_err(connector->dev, "[CONNECTOR:%d:%s] Unknown HDMI VIC: %d\n", 4765 connector->base.id, connector->name, vic); 4766 return 0; 4767 } 4768 4769 newmode = drm_mode_duplicate(dev, &edid_4k_modes[vic]); 4770 if (!newmode) 4771 return 0; 4772 4773 drm_mode_probed_add(connector, newmode); 4774 4775 return 1; 4776 } 4777 4778 static int add_3d_struct_modes(struct drm_connector *connector, u16 structure, 4779 int vic_index) 4780 { 4781 struct drm_display_mode *newmode; 4782 int modes = 0; 4783 4784 if (structure & (1 << 0)) { 4785 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4786 if (newmode) { 4787 newmode->flags |= DRM_MODE_FLAG_3D_FRAME_PACKING; 4788 drm_mode_probed_add(connector, newmode); 4789 modes++; 4790 } 4791 } 4792 if (structure & (1 << 6)) { 4793 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4794 if (newmode) { 4795 newmode->flags |= DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4796 drm_mode_probed_add(connector, newmode); 4797 modes++; 4798 } 4799 } 4800 if (structure & (1 << 8)) { 4801 newmode = drm_display_mode_from_vic_index(connector, vic_index); 4802 if (newmode) { 4803 newmode->flags |= DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4804 drm_mode_probed_add(connector, newmode); 4805 modes++; 4806 } 4807 } 4808 4809 return modes; 4810 } 4811 4812 static bool hdmi_vsdb_latency_present(const u8 *db) 4813 { 4814 return db[8] & BIT(7); 4815 } 4816 4817 static bool hdmi_vsdb_i_latency_present(const u8 *db) 4818 { 4819 return hdmi_vsdb_latency_present(db) && db[8] & BIT(6); 4820 } 4821 4822 static int hdmi_vsdb_latency_length(const u8 *db) 4823 { 4824 if (hdmi_vsdb_i_latency_present(db)) 4825 return 4; 4826 else if (hdmi_vsdb_latency_present(db)) 4827 return 2; 4828 else 4829 return 0; 4830 } 4831 4832 /* 4833 * do_hdmi_vsdb_modes - Parse the HDMI Vendor Specific data block 4834 * @connector: connector corresponding to the HDMI sink 4835 * @db: start of the CEA vendor specific block 4836 * @len: length of the CEA block payload, ie. one can access up to db[len] 4837 * 4838 * Parses the HDMI VSDB looking for modes to add to @connector. This function 4839 * also adds the stereo 3d modes when applicable. 4840 */ 4841 static int 4842 do_hdmi_vsdb_modes(struct drm_connector *connector, const u8 *db, u8 len) 4843 { 4844 int modes = 0, offset = 0, i, multi_present = 0, multi_len; 4845 u8 vic_len, hdmi_3d_len = 0; 4846 u16 mask; 4847 u16 structure_all; 4848 4849 if (len < 8) 4850 goto out; 4851 4852 /* no HDMI_Video_Present */ 4853 if (!(db[8] & (1 << 5))) 4854 goto out; 4855 4856 offset += hdmi_vsdb_latency_length(db); 4857 4858 /* the declared length is not long enough for the 2 first bytes 4859 * of additional video format capabilities */ 4860 if (len < (8 + offset + 2)) 4861 goto out; 4862 4863 /* 3D_Present */ 4864 offset++; 4865 if (db[8 + offset] & (1 << 7)) { 4866 modes += add_hdmi_mandatory_stereo_modes(connector); 4867 4868 /* 3D_Multi_present */ 4869 multi_present = (db[8 + offset] & 0x60) >> 5; 4870 } 4871 4872 offset++; 4873 vic_len = db[8 + offset] >> 5; 4874 hdmi_3d_len = db[8 + offset] & 0x1f; 4875 4876 for (i = 0; i < vic_len && len >= (9 + offset + i); i++) { 4877 u8 vic; 4878 4879 vic = db[9 + offset + i]; 4880 modes += add_hdmi_mode(connector, vic); 4881 } 4882 offset += 1 + vic_len; 4883 4884 if (multi_present == 1) 4885 multi_len = 2; 4886 else if (multi_present == 2) 4887 multi_len = 4; 4888 else 4889 multi_len = 0; 4890 4891 if (len < (8 + offset + hdmi_3d_len - 1)) 4892 goto out; 4893 4894 if (hdmi_3d_len < multi_len) 4895 goto out; 4896 4897 if (multi_present == 1 || multi_present == 2) { 4898 /* 3D_Structure_ALL */ 4899 structure_all = (db[8 + offset] << 8) | db[9 + offset]; 4900 4901 /* check if 3D_MASK is present */ 4902 if (multi_present == 2) 4903 mask = (db[10 + offset] << 8) | db[11 + offset]; 4904 else 4905 mask = 0xffff; 4906 4907 for (i = 0; i < 16; i++) { 4908 if (mask & (1 << i)) 4909 modes += add_3d_struct_modes(connector, 4910 structure_all, i); 4911 } 4912 } 4913 4914 offset += multi_len; 4915 4916 for (i = 0; i < (hdmi_3d_len - multi_len); i++) { 4917 int vic_index; 4918 struct drm_display_mode *newmode = NULL; 4919 unsigned int newflag = 0; 4920 bool detail_present; 4921 4922 detail_present = ((db[8 + offset + i] & 0x0f) > 7); 4923 4924 if (detail_present && (i + 1 == hdmi_3d_len - multi_len)) 4925 break; 4926 4927 /* 2D_VIC_order_X */ 4928 vic_index = db[8 + offset + i] >> 4; 4929 4930 /* 3D_Structure_X */ 4931 switch (db[8 + offset + i] & 0x0f) { 4932 case 0: 4933 newflag = DRM_MODE_FLAG_3D_FRAME_PACKING; 4934 break; 4935 case 6: 4936 newflag = DRM_MODE_FLAG_3D_TOP_AND_BOTTOM; 4937 break; 4938 case 8: 4939 /* 3D_Detail_X */ 4940 if ((db[9 + offset + i] >> 4) == 1) 4941 newflag = DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF; 4942 break; 4943 } 4944 4945 if (newflag != 0) { 4946 newmode = drm_display_mode_from_vic_index(connector, 4947 vic_index); 4948 4949 if (newmode) { 4950 newmode->flags |= newflag; 4951 drm_mode_probed_add(connector, newmode); 4952 modes++; 4953 } 4954 } 4955 4956 if (detail_present) 4957 i++; 4958 } 4959 4960 out: 4961 return modes; 4962 } 4963 4964 static int 4965 cea_revision(const u8 *cea) 4966 { 4967 /* 4968 * FIXME is this correct for the DispID variant? 4969 * The DispID spec doesn't really specify whether 4970 * this is the revision of the CEA extension or 4971 * the DispID CEA data block. And the only value 4972 * given as an example is 0. 4973 */ 4974 return cea[1]; 4975 } 4976 4977 /* 4978 * CTA Data Block iterator. 4979 * 4980 * Iterate through all CTA Data Blocks in both EDID CTA Extensions and DisplayID 4981 * CTA Data Blocks. 4982 * 4983 * struct cea_db *db: 4984 * struct cea_db_iter iter; 4985 * 4986 * cea_db_iter_edid_begin(edid, &iter); 4987 * cea_db_iter_for_each(db, &iter) { 4988 * // do stuff with db 4989 * } 4990 * cea_db_iter_end(&iter); 4991 */ 4992 struct cea_db_iter { 4993 struct drm_edid_iter edid_iter; 4994 struct displayid_iter displayid_iter; 4995 4996 /* Current Data Block Collection. */ 4997 const u8 *collection; 4998 4999 /* Current Data Block index in current collection. */ 5000 int index; 5001 5002 /* End index in current collection. */ 5003 int end; 5004 }; 5005 5006 /* CTA-861-H section 7.4 CTA Data BLock Collection */ 5007 struct cea_db { 5008 u8 tag_length; 5009 u8 data[]; 5010 } __packed; 5011 5012 static int cea_db_tag(const struct cea_db *db) 5013 { 5014 return db->tag_length >> 5; 5015 } 5016 5017 static int cea_db_payload_len(const void *_db) 5018 { 5019 /* FIXME: Transition to passing struct cea_db * everywhere. */ 5020 const struct cea_db *db = _db; 5021 5022 return db->tag_length & 0x1f; 5023 } 5024 5025 static const void *cea_db_data(const struct cea_db *db) 5026 { 5027 return db->data; 5028 } 5029 5030 static bool cea_db_is_extended_tag(const struct cea_db *db, int tag) 5031 { 5032 return cea_db_tag(db) == CTA_DB_EXTENDED_TAG && 5033 cea_db_payload_len(db) >= 1 && 5034 db->data[0] == tag; 5035 } 5036 5037 static bool cea_db_is_vendor(const struct cea_db *db, int vendor_oui) 5038 { 5039 const u8 *data = cea_db_data(db); 5040 5041 return cea_db_tag(db) == CTA_DB_VENDOR && 5042 cea_db_payload_len(db) >= 3 && 5043 oui(data[2], data[1], data[0]) == vendor_oui; 5044 } 5045 5046 static void cea_db_iter_edid_begin(const struct drm_edid *drm_edid, 5047 struct cea_db_iter *iter) 5048 { 5049 memset(iter, 0, sizeof(*iter)); 5050 5051 drm_edid_iter_begin(drm_edid, &iter->edid_iter); 5052 displayid_iter_edid_begin(drm_edid, &iter->displayid_iter); 5053 } 5054 5055 static const struct cea_db * 5056 __cea_db_iter_current_block(const struct cea_db_iter *iter) 5057 { 5058 const struct cea_db *db; 5059 5060 if (!iter->collection) 5061 return NULL; 5062 5063 db = (const struct cea_db *)&iter->collection[iter->index]; 5064 5065 if (iter->index + sizeof(*db) <= iter->end && 5066 iter->index + sizeof(*db) + cea_db_payload_len(db) <= iter->end) 5067 return db; 5068 5069 return NULL; 5070 } 5071 5072 /* 5073 * References: 5074 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5075 */ 5076 static int cea_db_collection_size(const u8 *cta) 5077 { 5078 u8 d = cta[2]; 5079 5080 if (d < 4 || d > 127) 5081 return 0; 5082 5083 return d - 4; 5084 } 5085 5086 /* 5087 * References: 5088 * - VESA E-EDID v1.4 5089 * - CTA-861-H section 7.3.3 CTA Extension Version 3 5090 */ 5091 static const void *__cea_db_iter_edid_next(struct cea_db_iter *iter) 5092 { 5093 const u8 *ext; 5094 5095 drm_edid_iter_for_each(ext, &iter->edid_iter) { 5096 int size; 5097 5098 /* Only support CTA Extension revision 3+ */ 5099 if (ext[0] != CEA_EXT || cea_revision(ext) < 3) 5100 continue; 5101 5102 size = cea_db_collection_size(ext); 5103 if (!size) 5104 continue; 5105 5106 iter->index = 4; 5107 iter->end = iter->index + size; 5108 5109 return ext; 5110 } 5111 5112 return NULL; 5113 } 5114 5115 /* 5116 * References: 5117 * - DisplayID v1.3 Appendix C: CEA Data Block within a DisplayID Data Block 5118 * - DisplayID v2.0 section 4.10 CTA DisplayID Data Block 5119 * 5120 * Note that the above do not specify any connection between DisplayID Data 5121 * Block revision and CTA Extension versions. 5122 */ 5123 static const void *__cea_db_iter_displayid_next(struct cea_db_iter *iter) 5124 { 5125 const struct displayid_block *block; 5126 5127 displayid_iter_for_each(block, &iter->displayid_iter) { 5128 if (block->tag != DATA_BLOCK_CTA) 5129 continue; 5130 5131 /* 5132 * The displayid iterator has already verified the block bounds 5133 * in displayid_iter_block(). 5134 */ 5135 iter->index = sizeof(*block); 5136 iter->end = iter->index + block->num_bytes; 5137 5138 return block; 5139 } 5140 5141 return NULL; 5142 } 5143 5144 static const struct cea_db *__cea_db_iter_next(struct cea_db_iter *iter) 5145 { 5146 const struct cea_db *db; 5147 5148 if (iter->collection) { 5149 /* Current collection should always be valid. */ 5150 db = __cea_db_iter_current_block(iter); 5151 if (WARN_ON(!db)) { 5152 iter->collection = NULL; 5153 return NULL; 5154 } 5155 5156 /* Next block in CTA Data Block Collection */ 5157 iter->index += sizeof(*db) + cea_db_payload_len(db); 5158 5159 db = __cea_db_iter_current_block(iter); 5160 if (db) 5161 return db; 5162 } 5163 5164 for (;;) { 5165 /* 5166 * Find the next CTA Data Block Collection. First iterate all 5167 * the EDID CTA Extensions, then all the DisplayID CTA blocks. 5168 * 5169 * Per DisplayID v1.3 Appendix B: DisplayID as an EDID 5170 * Extension, it's recommended that DisplayID extensions are 5171 * exposed after all of the CTA Extensions. 5172 */ 5173 iter->collection = __cea_db_iter_edid_next(iter); 5174 if (!iter->collection) 5175 iter->collection = __cea_db_iter_displayid_next(iter); 5176 5177 if (!iter->collection) 5178 return NULL; 5179 5180 db = __cea_db_iter_current_block(iter); 5181 if (db) 5182 return db; 5183 } 5184 } 5185 5186 #define cea_db_iter_for_each(__db, __iter) \ 5187 while (((__db) = __cea_db_iter_next(__iter))) 5188 5189 static void cea_db_iter_end(struct cea_db_iter *iter) 5190 { 5191 displayid_iter_end(&iter->displayid_iter); 5192 drm_edid_iter_end(&iter->edid_iter); 5193 5194 memset(iter, 0, sizeof(*iter)); 5195 } 5196 5197 static bool cea_db_is_hdmi_vsdb(const struct cea_db *db) 5198 { 5199 return cea_db_is_vendor(db, HDMI_IEEE_OUI) && 5200 cea_db_payload_len(db) >= 5; 5201 } 5202 5203 static bool cea_db_is_hdmi_forum_vsdb(const struct cea_db *db) 5204 { 5205 return cea_db_is_vendor(db, HDMI_FORUM_IEEE_OUI) && 5206 cea_db_payload_len(db) >= 7; 5207 } 5208 5209 static bool cea_db_is_hdmi_forum_eeodb(const void *db) 5210 { 5211 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_EEODB) && 5212 cea_db_payload_len(db) >= 2; 5213 } 5214 5215 static bool cea_db_is_microsoft_vsdb(const struct cea_db *db) 5216 { 5217 return cea_db_is_vendor(db, MICROSOFT_IEEE_OUI) && 5218 cea_db_payload_len(db) == 21; 5219 } 5220 5221 static bool cea_db_is_vcdb(const struct cea_db *db) 5222 { 5223 return cea_db_is_extended_tag(db, CTA_EXT_DB_VIDEO_CAP) && 5224 cea_db_payload_len(db) == 2; 5225 } 5226 5227 static bool cea_db_is_hdmi_forum_scdb(const struct cea_db *db) 5228 { 5229 return cea_db_is_extended_tag(db, CTA_EXT_DB_HF_SCDB) && 5230 cea_db_payload_len(db) >= 7; 5231 } 5232 5233 static bool cea_db_is_y420cmdb(const struct cea_db *db) 5234 { 5235 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_CAP_MAP); 5236 } 5237 5238 static bool cea_db_is_y420vdb(const struct cea_db *db) 5239 { 5240 return cea_db_is_extended_tag(db, CTA_EXT_DB_420_VIDEO_DATA); 5241 } 5242 5243 static bool cea_db_is_hdmi_hdr_metadata_block(const struct cea_db *db) 5244 { 5245 return cea_db_is_extended_tag(db, CTA_EXT_DB_HDR_STATIC_METADATA) && 5246 cea_db_payload_len(db) >= 3; 5247 } 5248 5249 /* 5250 * Get the HF-EEODB override extension block count from EDID. 5251 * 5252 * The passed in EDID may be partially read, as long as it has at least two 5253 * blocks (base block and one extension block) if EDID extension count is > 0. 5254 * 5255 * Note that this is *not* how you should parse CTA Data Blocks in general; this 5256 * is only to handle partially read EDIDs. Normally, use the CTA Data Block 5257 * iterators instead. 5258 * 5259 * References: 5260 * - HDMI 2.1 section 10.3.6 HDMI Forum EDID Extension Override Data Block 5261 */ 5262 static int edid_hfeeodb_extension_block_count(const struct edid *edid) 5263 { 5264 const u8 *cta; 5265 5266 /* No extensions according to base block, no HF-EEODB. */ 5267 if (!edid_extension_block_count(edid)) 5268 return 0; 5269 5270 /* HF-EEODB is always in the first EDID extension block only */ 5271 cta = edid_extension_block_data(edid, 0); 5272 if (edid_block_tag(cta) != CEA_EXT || cea_revision(cta) < 3) 5273 return 0; 5274 5275 /* Need to have the data block collection, and at least 3 bytes. */ 5276 if (cea_db_collection_size(cta) < 3) 5277 return 0; 5278 5279 /* 5280 * Sinks that include the HF-EEODB in their E-EDID shall include one and 5281 * only one instance of the HF-EEODB in the E-EDID, occupying bytes 4 5282 * through 6 of Block 1 of the E-EDID. 5283 */ 5284 if (!cea_db_is_hdmi_forum_eeodb(&cta[4])) 5285 return 0; 5286 5287 return cta[4 + 2]; 5288 } 5289 5290 /* 5291 * CTA-861 YCbCr 4:2:0 Capability Map Data Block (CTA Y420CMDB) 5292 * 5293 * Y420CMDB contains a bitmap which gives the index of CTA modes from CTA VDB, 5294 * which can support YCBCR 420 sampling output also (apart from RGB/YCBCR444 5295 * etc). For example, if the bit 0 in bitmap is set, first mode in VDB can 5296 * support YCBCR420 output too. 5297 */ 5298 static void parse_cta_y420cmdb(struct drm_connector *connector, 5299 const struct cea_db *db, u64 *y420cmdb_map) 5300 { 5301 struct drm_display_info *info = &connector->display_info; 5302 int i, map_len = cea_db_payload_len(db) - 1; 5303 const u8 *data = cea_db_data(db) + 1; 5304 u64 map = 0; 5305 5306 if (map_len == 0) { 5307 /* All CEA modes support ycbcr420 sampling also.*/ 5308 map = U64_MAX; 5309 goto out; 5310 } 5311 5312 /* 5313 * This map indicates which of the existing CEA block modes 5314 * from VDB can support YCBCR420 output too. So if bit=0 is 5315 * set, first mode from VDB can support YCBCR420 output too. 5316 * We will parse and keep this map, before parsing VDB itself 5317 * to avoid going through the same block again and again. 5318 * 5319 * Spec is not clear about max possible size of this block. 5320 * Clamping max bitmap block size at 8 bytes. Every byte can 5321 * address 8 CEA modes, in this way this map can address 5322 * 8*8 = first 64 SVDs. 5323 */ 5324 if (WARN_ON_ONCE(map_len > 8)) 5325 map_len = 8; 5326 5327 for (i = 0; i < map_len; i++) 5328 map |= (u64)data[i] << (8 * i); 5329 5330 out: 5331 if (map) 5332 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 5333 5334 *y420cmdb_map = map; 5335 } 5336 5337 static int add_cea_modes(struct drm_connector *connector, 5338 const struct drm_edid *drm_edid) 5339 { 5340 const struct cea_db *db; 5341 struct cea_db_iter iter; 5342 int modes; 5343 5344 /* CTA VDB block VICs parsed earlier */ 5345 modes = add_cta_vdb_modes(connector); 5346 5347 cea_db_iter_edid_begin(drm_edid, &iter); 5348 cea_db_iter_for_each(db, &iter) { 5349 if (cea_db_is_hdmi_vsdb(db)) { 5350 modes += do_hdmi_vsdb_modes(connector, (const u8 *)db, 5351 cea_db_payload_len(db)); 5352 } else if (cea_db_is_y420vdb(db)) { 5353 const u8 *vdb420 = cea_db_data(db) + 1; 5354 5355 /* Add 4:2:0(only) modes present in EDID */ 5356 modes += do_y420vdb_modes(connector, vdb420, 5357 cea_db_payload_len(db) - 1); 5358 } 5359 } 5360 cea_db_iter_end(&iter); 5361 5362 return modes; 5363 } 5364 5365 static void fixup_detailed_cea_mode_clock(struct drm_connector *connector, 5366 struct drm_display_mode *mode) 5367 { 5368 const struct drm_display_mode *cea_mode; 5369 int clock1, clock2, clock; 5370 u8 vic; 5371 const char *type; 5372 5373 /* 5374 * allow 5kHz clock difference either way to account for 5375 * the 10kHz clock resolution limit of detailed timings. 5376 */ 5377 vic = drm_match_cea_mode_clock_tolerance(mode, 5); 5378 if (drm_valid_cea_vic(vic)) { 5379 type = "CEA"; 5380 cea_mode = cea_mode_for_vic(vic); 5381 clock1 = cea_mode->clock; 5382 clock2 = cea_mode_alternate_clock(cea_mode); 5383 } else { 5384 vic = drm_match_hdmi_mode_clock_tolerance(mode, 5); 5385 if (drm_valid_hdmi_vic(vic)) { 5386 type = "HDMI"; 5387 cea_mode = &edid_4k_modes[vic]; 5388 clock1 = cea_mode->clock; 5389 clock2 = hdmi_mode_alternate_clock(cea_mode); 5390 } else { 5391 return; 5392 } 5393 } 5394 5395 /* pick whichever is closest */ 5396 if (abs(mode->clock - clock1) < abs(mode->clock - clock2)) 5397 clock = clock1; 5398 else 5399 clock = clock2; 5400 5401 if (mode->clock == clock) 5402 return; 5403 5404 drm_dbg_kms(connector->dev, 5405 "[CONNECTOR:%d:%s] detailed mode matches %s VIC %d, adjusting clock %d -> %d\n", 5406 connector->base.id, connector->name, 5407 type, vic, mode->clock, clock); 5408 mode->clock = clock; 5409 } 5410 5411 static void drm_calculate_luminance_range(struct drm_connector *connector) 5412 { 5413 struct hdr_static_metadata *hdr_metadata = &connector->hdr_sink_metadata.hdmi_type1; 5414 struct drm_luminance_range_info *luminance_range = 5415 &connector->display_info.luminance_range; 5416 static const u8 pre_computed_values[] = { 5417 50, 51, 52, 53, 55, 56, 57, 58, 59, 61, 62, 63, 65, 66, 68, 69, 5418 71, 72, 74, 75, 77, 79, 81, 82, 84, 86, 88, 90, 92, 94, 96, 98 5419 }; 5420 u32 max_avg, min_cll, max, min, q, r; 5421 5422 if (!(hdr_metadata->metadata_type & BIT(HDMI_STATIC_METADATA_TYPE1))) 5423 return; 5424 5425 max_avg = hdr_metadata->max_fall; 5426 min_cll = hdr_metadata->min_cll; 5427 5428 /* 5429 * From the specification (CTA-861-G), for calculating the maximum 5430 * luminance we need to use: 5431 * Luminance = 50*2**(CV/32) 5432 * Where CV is a one-byte value. 5433 * For calculating this expression we may need float point precision; 5434 * to avoid this complexity level, we take advantage that CV is divided 5435 * by a constant. From the Euclids division algorithm, we know that CV 5436 * can be written as: CV = 32*q + r. Next, we replace CV in the 5437 * Luminance expression and get 50*(2**q)*(2**(r/32)), hence we just 5438 * need to pre-compute the value of r/32. For pre-computing the values 5439 * We just used the following Ruby line: 5440 * (0...32).each {|cv| puts (50*2**(cv/32.0)).round} 5441 * The results of the above expressions can be verified at 5442 * pre_computed_values. 5443 */ 5444 q = max_avg >> 5; 5445 r = max_avg % 32; 5446 max = (1 << q) * pre_computed_values[r]; 5447 5448 /* min luminance: maxLum * (CV/255)^2 / 100 */ 5449 q = DIV_ROUND_CLOSEST(min_cll, 255); 5450 min = max * DIV_ROUND_CLOSEST((q * q), 100); 5451 5452 luminance_range->min_luminance = min; 5453 luminance_range->max_luminance = max; 5454 } 5455 5456 static uint8_t eotf_supported(const u8 *edid_ext) 5457 { 5458 return edid_ext[2] & 5459 (BIT(HDMI_EOTF_TRADITIONAL_GAMMA_SDR) | 5460 BIT(HDMI_EOTF_TRADITIONAL_GAMMA_HDR) | 5461 BIT(HDMI_EOTF_SMPTE_ST2084) | 5462 BIT(HDMI_EOTF_BT_2100_HLG)); 5463 } 5464 5465 static uint8_t hdr_metadata_type(const u8 *edid_ext) 5466 { 5467 return edid_ext[3] & 5468 BIT(HDMI_STATIC_METADATA_TYPE1); 5469 } 5470 5471 static void 5472 drm_parse_hdr_metadata_block(struct drm_connector *connector, const u8 *db) 5473 { 5474 u16 len; 5475 5476 len = cea_db_payload_len(db); 5477 5478 connector->hdr_sink_metadata.hdmi_type1.eotf = 5479 eotf_supported(db); 5480 connector->hdr_sink_metadata.hdmi_type1.metadata_type = 5481 hdr_metadata_type(db); 5482 5483 if (len >= 4) 5484 connector->hdr_sink_metadata.hdmi_type1.max_cll = db[4]; 5485 if (len >= 5) 5486 connector->hdr_sink_metadata.hdmi_type1.max_fall = db[5]; 5487 if (len >= 6) { 5488 connector->hdr_sink_metadata.hdmi_type1.min_cll = db[6]; 5489 5490 /* Calculate only when all values are available */ 5491 drm_calculate_luminance_range(connector); 5492 } 5493 } 5494 5495 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 5496 static void 5497 drm_parse_hdmi_vsdb_audio(struct drm_connector *connector, const u8 *db) 5498 { 5499 u8 len = cea_db_payload_len(db); 5500 5501 if (len >= 6 && (db[6] & (1 << 7))) 5502 connector->eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_SUPPORTS_AI; 5503 5504 if (len >= 10 && hdmi_vsdb_latency_present(db)) { 5505 connector->latency_present[0] = true; 5506 connector->video_latency[0] = db[9]; 5507 connector->audio_latency[0] = db[10]; 5508 } 5509 5510 if (len >= 12 && hdmi_vsdb_i_latency_present(db)) { 5511 connector->latency_present[1] = true; 5512 connector->video_latency[1] = db[11]; 5513 connector->audio_latency[1] = db[12]; 5514 } 5515 5516 drm_dbg_kms(connector->dev, 5517 "[CONNECTOR:%d:%s] HDMI: latency present %d %d, video latency %d %d, audio latency %d %d\n", 5518 connector->base.id, connector->name, 5519 connector->latency_present[0], connector->latency_present[1], 5520 connector->video_latency[0], connector->video_latency[1], 5521 connector->audio_latency[0], connector->audio_latency[1]); 5522 } 5523 5524 static void 5525 match_identity(const struct detailed_timing *timing, void *data) 5526 { 5527 struct drm_edid_match_closure *closure = data; 5528 unsigned int i; 5529 const char *name = closure->ident->name; 5530 unsigned int name_len = strlen(name); 5531 const char *desc = timing->data.other_data.data.str.str; 5532 unsigned int desc_len = ARRAY_SIZE(timing->data.other_data.data.str.str); 5533 5534 if (name_len > desc_len || 5535 !(is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME) || 5536 is_display_descriptor(timing, EDID_DETAIL_MONITOR_STRING))) 5537 return; 5538 5539 if (strncmp(name, desc, name_len)) 5540 return; 5541 5542 for (i = name_len; i < desc_len; i++) { 5543 if (desc[i] == '\n') 5544 break; 5545 /* Allow white space before EDID string terminator. */ 5546 if (!isspace(desc[i])) 5547 return; 5548 } 5549 5550 closure->matched = true; 5551 } 5552 5553 /** 5554 * drm_edid_match - match drm_edid with given identity 5555 * @drm_edid: EDID 5556 * @ident: the EDID identity to match with 5557 * 5558 * Check if the EDID matches with the given identity. 5559 * 5560 * Return: True if the given identity matched with EDID, false otherwise. 5561 */ 5562 bool drm_edid_match(const struct drm_edid *drm_edid, 5563 const struct drm_edid_ident *ident) 5564 { 5565 if (!drm_edid || drm_edid_get_panel_id(drm_edid) != ident->panel_id) 5566 return false; 5567 5568 /* Match with name only if it's not NULL. */ 5569 if (ident->name) { 5570 struct drm_edid_match_closure closure = { 5571 .ident = ident, 5572 .matched = false, 5573 }; 5574 5575 drm_for_each_detailed_block(drm_edid, match_identity, &closure); 5576 5577 return closure.matched; 5578 } 5579 5580 return true; 5581 } 5582 EXPORT_SYMBOL(drm_edid_match); 5583 5584 static void 5585 monitor_name(const struct detailed_timing *timing, void *data) 5586 { 5587 const char **res = data; 5588 5589 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_NAME)) 5590 return; 5591 5592 *res = timing->data.other_data.data.str.str; 5593 } 5594 5595 static int get_monitor_name(const struct drm_edid *drm_edid, char name[13]) 5596 { 5597 const char *edid_name = NULL; 5598 int mnl; 5599 5600 if (!drm_edid || !name) 5601 return 0; 5602 5603 drm_for_each_detailed_block(drm_edid, monitor_name, &edid_name); 5604 for (mnl = 0; edid_name && mnl < 13; mnl++) { 5605 if (edid_name[mnl] == 0x0a) 5606 break; 5607 5608 name[mnl] = edid_name[mnl]; 5609 } 5610 5611 return mnl; 5612 } 5613 5614 /** 5615 * drm_edid_get_monitor_name - fetch the monitor name from the edid 5616 * @edid: monitor EDID information 5617 * @name: pointer to a character array to hold the name of the monitor 5618 * @bufsize: The size of the name buffer (should be at least 14 chars.) 5619 * 5620 */ 5621 void drm_edid_get_monitor_name(const struct edid *edid, char *name, int bufsize) 5622 { 5623 int name_length = 0; 5624 5625 if (bufsize <= 0) 5626 return; 5627 5628 if (edid) { 5629 char buf[13]; 5630 struct drm_edid drm_edid = { 5631 .edid = edid, 5632 .size = edid_size(edid), 5633 }; 5634 5635 name_length = min(get_monitor_name(&drm_edid, buf), bufsize - 1); 5636 memcpy(name, buf, name_length); 5637 } 5638 5639 name[name_length] = '\0'; 5640 } 5641 EXPORT_SYMBOL(drm_edid_get_monitor_name); 5642 5643 static void clear_eld(struct drm_connector *connector) 5644 { 5645 memset(connector->eld, 0, sizeof(connector->eld)); 5646 5647 connector->latency_present[0] = false; 5648 connector->latency_present[1] = false; 5649 connector->video_latency[0] = 0; 5650 connector->audio_latency[0] = 0; 5651 connector->video_latency[1] = 0; 5652 connector->audio_latency[1] = 0; 5653 } 5654 5655 /* 5656 * Get 3-byte SAD buffer from struct cea_sad. 5657 */ 5658 void drm_edid_cta_sad_get(const struct cea_sad *cta_sad, u8 *sad) 5659 { 5660 sad[0] = cta_sad->format << 3 | cta_sad->channels; 5661 sad[1] = cta_sad->freq; 5662 sad[2] = cta_sad->byte2; 5663 } 5664 5665 /* 5666 * Set struct cea_sad from 3-byte SAD buffer. 5667 */ 5668 void drm_edid_cta_sad_set(struct cea_sad *cta_sad, const u8 *sad) 5669 { 5670 cta_sad->format = (sad[0] & 0x78) >> 3; 5671 cta_sad->channels = sad[0] & 0x07; 5672 cta_sad->freq = sad[1] & 0x7f; 5673 cta_sad->byte2 = sad[2]; 5674 } 5675 5676 /* 5677 * drm_edid_to_eld - build ELD from EDID 5678 * @connector: connector corresponding to the HDMI/DP sink 5679 * @drm_edid: EDID to parse 5680 * 5681 * Fill the ELD (EDID-Like Data) buffer for passing to the audio driver. The 5682 * HDCP and Port_ID ELD fields are left for the graphics driver to fill in. 5683 */ 5684 static void drm_edid_to_eld(struct drm_connector *connector, 5685 const struct drm_edid *drm_edid) 5686 { 5687 const struct drm_display_info *info = &connector->display_info; 5688 const struct cea_db *db; 5689 struct cea_db_iter iter; 5690 uint8_t *eld = connector->eld; 5691 int total_sad_count = 0; 5692 int mnl; 5693 5694 if (!drm_edid) 5695 return; 5696 5697 mnl = get_monitor_name(drm_edid, &eld[DRM_ELD_MONITOR_NAME_STRING]); 5698 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD monitor %s\n", 5699 connector->base.id, connector->name, 5700 &eld[DRM_ELD_MONITOR_NAME_STRING]); 5701 5702 eld[DRM_ELD_CEA_EDID_VER_MNL] = info->cea_rev << DRM_ELD_CEA_EDID_VER_SHIFT; 5703 eld[DRM_ELD_CEA_EDID_VER_MNL] |= mnl; 5704 5705 eld[DRM_ELD_VER] = DRM_ELD_VER_CEA861D; 5706 5707 eld[DRM_ELD_MANUFACTURER_NAME0] = drm_edid->edid->mfg_id[0]; 5708 eld[DRM_ELD_MANUFACTURER_NAME1] = drm_edid->edid->mfg_id[1]; 5709 eld[DRM_ELD_PRODUCT_CODE0] = drm_edid->edid->prod_code[0]; 5710 eld[DRM_ELD_PRODUCT_CODE1] = drm_edid->edid->prod_code[1]; 5711 5712 cea_db_iter_edid_begin(drm_edid, &iter); 5713 cea_db_iter_for_each(db, &iter) { 5714 const u8 *data = cea_db_data(db); 5715 int len = cea_db_payload_len(db); 5716 int sad_count; 5717 5718 switch (cea_db_tag(db)) { 5719 case CTA_DB_AUDIO: 5720 /* Audio Data Block, contains SADs */ 5721 sad_count = min(len / 3, 15 - total_sad_count); 5722 if (sad_count >= 1) 5723 memcpy(&eld[DRM_ELD_CEA_SAD(mnl, total_sad_count)], 5724 data, sad_count * 3); 5725 total_sad_count += sad_count; 5726 break; 5727 case CTA_DB_SPEAKER: 5728 /* Speaker Allocation Data Block */ 5729 if (len >= 1) 5730 eld[DRM_ELD_SPEAKER] = data[0]; 5731 break; 5732 case CTA_DB_VENDOR: 5733 /* HDMI Vendor-Specific Data Block */ 5734 if (cea_db_is_hdmi_vsdb(db)) 5735 drm_parse_hdmi_vsdb_audio(connector, (const u8 *)db); 5736 break; 5737 default: 5738 break; 5739 } 5740 } 5741 cea_db_iter_end(&iter); 5742 5743 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= total_sad_count << DRM_ELD_SAD_COUNT_SHIFT; 5744 5745 if (connector->connector_type == DRM_MODE_CONNECTOR_DisplayPort || 5746 connector->connector_type == DRM_MODE_CONNECTOR_eDP) 5747 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_DP; 5748 else 5749 eld[DRM_ELD_SAD_COUNT_CONN_TYPE] |= DRM_ELD_CONN_TYPE_HDMI; 5750 5751 eld[DRM_ELD_BASELINE_ELD_LEN] = 5752 DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4); 5753 5754 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] ELD size %d, SAD count %d\n", 5755 connector->base.id, connector->name, 5756 drm_eld_size(eld), total_sad_count); 5757 } 5758 5759 static int _drm_edid_to_sad(const struct drm_edid *drm_edid, 5760 struct cea_sad **psads) 5761 { 5762 const struct cea_db *db; 5763 struct cea_db_iter iter; 5764 int count = 0; 5765 5766 cea_db_iter_edid_begin(drm_edid, &iter); 5767 cea_db_iter_for_each(db, &iter) { 5768 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5769 struct cea_sad *sads; 5770 int i; 5771 5772 count = cea_db_payload_len(db) / 3; /* SAD is 3B */ 5773 sads = kcalloc(count, sizeof(*sads), GFP_KERNEL); 5774 *psads = sads; 5775 if (!sads) 5776 return -ENOMEM; 5777 for (i = 0; i < count; i++) 5778 drm_edid_cta_sad_set(&sads[i], &db->data[i * 3]); 5779 break; 5780 } 5781 } 5782 cea_db_iter_end(&iter); 5783 5784 DRM_DEBUG_KMS("Found %d Short Audio Descriptors\n", count); 5785 5786 return count; 5787 } 5788 5789 /** 5790 * drm_edid_to_sad - extracts SADs from EDID 5791 * @edid: EDID to parse 5792 * @sads: pointer that will be set to the extracted SADs 5793 * 5794 * Looks for CEA EDID block and extracts SADs (Short Audio Descriptors) from it. 5795 * 5796 * Note: The returned pointer needs to be freed using kfree(). 5797 * 5798 * Return: The number of found SADs or negative number on error. 5799 */ 5800 int drm_edid_to_sad(const struct edid *edid, struct cea_sad **sads) 5801 { 5802 struct drm_edid drm_edid; 5803 5804 return _drm_edid_to_sad(drm_edid_legacy_init(&drm_edid, edid), sads); 5805 } 5806 EXPORT_SYMBOL(drm_edid_to_sad); 5807 5808 static int _drm_edid_to_speaker_allocation(const struct drm_edid *drm_edid, 5809 u8 **sadb) 5810 { 5811 const struct cea_db *db; 5812 struct cea_db_iter iter; 5813 int count = 0; 5814 5815 cea_db_iter_edid_begin(drm_edid, &iter); 5816 cea_db_iter_for_each(db, &iter) { 5817 if (cea_db_tag(db) == CTA_DB_SPEAKER && 5818 cea_db_payload_len(db) == 3) { 5819 *sadb = kmemdup(db->data, cea_db_payload_len(db), 5820 GFP_KERNEL); 5821 if (!*sadb) 5822 return -ENOMEM; 5823 count = cea_db_payload_len(db); 5824 break; 5825 } 5826 } 5827 cea_db_iter_end(&iter); 5828 5829 DRM_DEBUG_KMS("Found %d Speaker Allocation Data Blocks\n", count); 5830 5831 return count; 5832 } 5833 5834 /** 5835 * drm_edid_to_speaker_allocation - extracts Speaker Allocation Data Blocks from EDID 5836 * @edid: EDID to parse 5837 * @sadb: pointer to the speaker block 5838 * 5839 * Looks for CEA EDID block and extracts the Speaker Allocation Data Block from it. 5840 * 5841 * Note: The returned pointer needs to be freed using kfree(). 5842 * 5843 * Return: The number of found Speaker Allocation Blocks or negative number on 5844 * error. 5845 */ 5846 int drm_edid_to_speaker_allocation(const struct edid *edid, u8 **sadb) 5847 { 5848 struct drm_edid drm_edid; 5849 5850 return _drm_edid_to_speaker_allocation(drm_edid_legacy_init(&drm_edid, edid), 5851 sadb); 5852 } 5853 EXPORT_SYMBOL(drm_edid_to_speaker_allocation); 5854 5855 /** 5856 * drm_av_sync_delay - compute the HDMI/DP sink audio-video sync delay 5857 * @connector: connector associated with the HDMI/DP sink 5858 * @mode: the display mode 5859 * 5860 * Return: The HDMI/DP sink's audio-video sync delay in milliseconds or 0 if 5861 * the sink doesn't support audio or video. 5862 */ 5863 int drm_av_sync_delay(struct drm_connector *connector, 5864 const struct drm_display_mode *mode) 5865 { 5866 int i = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 5867 int a, v; 5868 5869 if (!connector->latency_present[0]) 5870 return 0; 5871 if (!connector->latency_present[1]) 5872 i = 0; 5873 5874 a = connector->audio_latency[i]; 5875 v = connector->video_latency[i]; 5876 5877 /* 5878 * HDMI/DP sink doesn't support audio or video? 5879 */ 5880 if (a == 255 || v == 255) 5881 return 0; 5882 5883 /* 5884 * Convert raw EDID values to millisecond. 5885 * Treat unknown latency as 0ms. 5886 */ 5887 if (a) 5888 a = min(2 * (a - 1), 500); 5889 if (v) 5890 v = min(2 * (v - 1), 500); 5891 5892 return max(v - a, 0); 5893 } 5894 EXPORT_SYMBOL(drm_av_sync_delay); 5895 5896 static bool _drm_detect_hdmi_monitor(const struct drm_edid *drm_edid) 5897 { 5898 const struct cea_db *db; 5899 struct cea_db_iter iter; 5900 bool hdmi = false; 5901 5902 /* 5903 * Because HDMI identifier is in Vendor Specific Block, 5904 * search it from all data blocks of CEA extension. 5905 */ 5906 cea_db_iter_edid_begin(drm_edid, &iter); 5907 cea_db_iter_for_each(db, &iter) { 5908 if (cea_db_is_hdmi_vsdb(db)) { 5909 hdmi = true; 5910 break; 5911 } 5912 } 5913 cea_db_iter_end(&iter); 5914 5915 return hdmi; 5916 } 5917 5918 /** 5919 * drm_detect_hdmi_monitor - detect whether monitor is HDMI 5920 * @edid: monitor EDID information 5921 * 5922 * Parse the CEA extension according to CEA-861-B. 5923 * 5924 * Drivers that have added the modes parsed from EDID to drm_display_info 5925 * should use &drm_display_info.is_hdmi instead of calling this function. 5926 * 5927 * Return: True if the monitor is HDMI, false if not or unknown. 5928 */ 5929 bool drm_detect_hdmi_monitor(const struct edid *edid) 5930 { 5931 struct drm_edid drm_edid; 5932 5933 return _drm_detect_hdmi_monitor(drm_edid_legacy_init(&drm_edid, edid)); 5934 } 5935 EXPORT_SYMBOL(drm_detect_hdmi_monitor); 5936 5937 static bool _drm_detect_monitor_audio(const struct drm_edid *drm_edid) 5938 { 5939 struct drm_edid_iter edid_iter; 5940 const struct cea_db *db; 5941 struct cea_db_iter iter; 5942 const u8 *edid_ext; 5943 bool has_audio = false; 5944 5945 drm_edid_iter_begin(drm_edid, &edid_iter); 5946 drm_edid_iter_for_each(edid_ext, &edid_iter) { 5947 if (edid_ext[0] == CEA_EXT) { 5948 has_audio = edid_ext[3] & EDID_BASIC_AUDIO; 5949 if (has_audio) 5950 break; 5951 } 5952 } 5953 drm_edid_iter_end(&edid_iter); 5954 5955 if (has_audio) { 5956 DRM_DEBUG_KMS("Monitor has basic audio support\n"); 5957 goto end; 5958 } 5959 5960 cea_db_iter_edid_begin(drm_edid, &iter); 5961 cea_db_iter_for_each(db, &iter) { 5962 if (cea_db_tag(db) == CTA_DB_AUDIO) { 5963 const u8 *data = cea_db_data(db); 5964 int i; 5965 5966 for (i = 0; i < cea_db_payload_len(db); i += 3) 5967 DRM_DEBUG_KMS("CEA audio format %d\n", 5968 (data[i] >> 3) & 0xf); 5969 has_audio = true; 5970 break; 5971 } 5972 } 5973 cea_db_iter_end(&iter); 5974 5975 end: 5976 return has_audio; 5977 } 5978 5979 /** 5980 * drm_detect_monitor_audio - check monitor audio capability 5981 * @edid: EDID block to scan 5982 * 5983 * Monitor should have CEA extension block. 5984 * If monitor has 'basic audio', but no CEA audio blocks, it's 'basic 5985 * audio' only. If there is any audio extension block and supported 5986 * audio format, assume at least 'basic audio' support, even if 'basic 5987 * audio' is not defined in EDID. 5988 * 5989 * Return: True if the monitor supports audio, false otherwise. 5990 */ 5991 bool drm_detect_monitor_audio(const struct edid *edid) 5992 { 5993 struct drm_edid drm_edid; 5994 5995 return _drm_detect_monitor_audio(drm_edid_legacy_init(&drm_edid, edid)); 5996 } 5997 EXPORT_SYMBOL(drm_detect_monitor_audio); 5998 5999 6000 /** 6001 * drm_default_rgb_quant_range - default RGB quantization range 6002 * @mode: display mode 6003 * 6004 * Determine the default RGB quantization range for the mode, 6005 * as specified in CEA-861. 6006 * 6007 * Return: The default RGB quantization range for the mode 6008 */ 6009 enum hdmi_quantization_range 6010 drm_default_rgb_quant_range(const struct drm_display_mode *mode) 6011 { 6012 /* All CEA modes other than VIC 1 use limited quantization range. */ 6013 return drm_match_cea_mode(mode) > 1 ? 6014 HDMI_QUANTIZATION_RANGE_LIMITED : 6015 HDMI_QUANTIZATION_RANGE_FULL; 6016 } 6017 EXPORT_SYMBOL(drm_default_rgb_quant_range); 6018 6019 /* CTA-861 Video Data Block (CTA VDB) */ 6020 static void parse_cta_vdb(struct drm_connector *connector, const struct cea_db *db) 6021 { 6022 struct drm_display_info *info = &connector->display_info; 6023 int i, vic_index, len = cea_db_payload_len(db); 6024 const u8 *svds = cea_db_data(db); 6025 u8 *vics; 6026 6027 if (!len) 6028 return; 6029 6030 /* Gracefully handle multiple VDBs, however unlikely that is */ 6031 vics = krealloc(info->vics, info->vics_len + len, GFP_KERNEL); 6032 if (!vics) 6033 return; 6034 6035 vic_index = info->vics_len; 6036 info->vics_len += len; 6037 info->vics = vics; 6038 6039 for (i = 0; i < len; i++) { 6040 u8 vic = svd_to_vic(svds[i]); 6041 6042 if (!drm_valid_cea_vic(vic)) 6043 vic = 0; 6044 6045 info->vics[vic_index++] = vic; 6046 } 6047 } 6048 6049 /* 6050 * Update y420_cmdb_modes based on previously parsed CTA VDB and Y420CMDB. 6051 * 6052 * Translate the y420cmdb_map based on VIC indexes to y420_cmdb_modes indexed 6053 * using the VICs themselves. 6054 */ 6055 static void update_cta_y420cmdb(struct drm_connector *connector, u64 y420cmdb_map) 6056 { 6057 struct drm_display_info *info = &connector->display_info; 6058 struct drm_hdmi_info *hdmi = &info->hdmi; 6059 int i, len = min_t(int, info->vics_len, BITS_PER_TYPE(y420cmdb_map)); 6060 6061 for (i = 0; i < len; i++) { 6062 u8 vic = info->vics[i]; 6063 6064 if (vic && y420cmdb_map & BIT_ULL(i)) 6065 bitmap_set(hdmi->y420_cmdb_modes, vic, 1); 6066 } 6067 } 6068 6069 static bool cta_vdb_has_vic(const struct drm_connector *connector, u8 vic) 6070 { 6071 const struct drm_display_info *info = &connector->display_info; 6072 int i; 6073 6074 if (!vic || !info->vics) 6075 return false; 6076 6077 for (i = 0; i < info->vics_len; i++) { 6078 if (info->vics[i] == vic) 6079 return true; 6080 } 6081 6082 return false; 6083 } 6084 6085 /* CTA-861-H YCbCr 4:2:0 Video Data Block (CTA Y420VDB) */ 6086 static void parse_cta_y420vdb(struct drm_connector *connector, 6087 const struct cea_db *db) 6088 { 6089 struct drm_display_info *info = &connector->display_info; 6090 struct drm_hdmi_info *hdmi = &info->hdmi; 6091 const u8 *svds = cea_db_data(db) + 1; 6092 int i; 6093 6094 for (i = 0; i < cea_db_payload_len(db) - 1; i++) { 6095 u8 vic = svd_to_vic(svds[i]); 6096 6097 if (!drm_valid_cea_vic(vic)) 6098 continue; 6099 6100 bitmap_set(hdmi->y420_vdb_modes, vic, 1); 6101 info->color_formats |= DRM_COLOR_FORMAT_YCBCR420; 6102 } 6103 } 6104 6105 static void drm_parse_vcdb(struct drm_connector *connector, const u8 *db) 6106 { 6107 struct drm_display_info *info = &connector->display_info; 6108 6109 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] CEA VCDB 0x%02x\n", 6110 connector->base.id, connector->name, db[2]); 6111 6112 if (db[2] & EDID_CEA_VCDB_QS) 6113 info->rgb_quant_range_selectable = true; 6114 } 6115 6116 static 6117 void drm_get_max_frl_rate(int max_frl_rate, u8 *max_lanes, u8 *max_rate_per_lane) 6118 { 6119 switch (max_frl_rate) { 6120 case 1: 6121 *max_lanes = 3; 6122 *max_rate_per_lane = 3; 6123 break; 6124 case 2: 6125 *max_lanes = 3; 6126 *max_rate_per_lane = 6; 6127 break; 6128 case 3: 6129 *max_lanes = 4; 6130 *max_rate_per_lane = 6; 6131 break; 6132 case 4: 6133 *max_lanes = 4; 6134 *max_rate_per_lane = 8; 6135 break; 6136 case 5: 6137 *max_lanes = 4; 6138 *max_rate_per_lane = 10; 6139 break; 6140 case 6: 6141 *max_lanes = 4; 6142 *max_rate_per_lane = 12; 6143 break; 6144 case 0: 6145 default: 6146 *max_lanes = 0; 6147 *max_rate_per_lane = 0; 6148 } 6149 } 6150 6151 static void drm_parse_ycbcr420_deep_color_info(struct drm_connector *connector, 6152 const u8 *db) 6153 { 6154 u8 dc_mask; 6155 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 6156 6157 dc_mask = db[7] & DRM_EDID_YCBCR420_DC_MASK; 6158 hdmi->y420_dc_modes = dc_mask; 6159 } 6160 6161 static void drm_parse_dsc_info(struct drm_hdmi_dsc_cap *hdmi_dsc, 6162 const u8 *hf_scds) 6163 { 6164 hdmi_dsc->v_1p2 = hf_scds[11] & DRM_EDID_DSC_1P2; 6165 6166 if (!hdmi_dsc->v_1p2) 6167 return; 6168 6169 hdmi_dsc->native_420 = hf_scds[11] & DRM_EDID_DSC_NATIVE_420; 6170 hdmi_dsc->all_bpp = hf_scds[11] & DRM_EDID_DSC_ALL_BPP; 6171 6172 if (hf_scds[11] & DRM_EDID_DSC_16BPC) 6173 hdmi_dsc->bpc_supported = 16; 6174 else if (hf_scds[11] & DRM_EDID_DSC_12BPC) 6175 hdmi_dsc->bpc_supported = 12; 6176 else if (hf_scds[11] & DRM_EDID_DSC_10BPC) 6177 hdmi_dsc->bpc_supported = 10; 6178 else 6179 /* Supports min 8 BPC if DSC 1.2 is supported*/ 6180 hdmi_dsc->bpc_supported = 8; 6181 6182 if (cea_db_payload_len(hf_scds) >= 12 && hf_scds[12]) { 6183 u8 dsc_max_slices; 6184 u8 dsc_max_frl_rate; 6185 6186 dsc_max_frl_rate = (hf_scds[12] & DRM_EDID_DSC_MAX_FRL_RATE_MASK) >> 4; 6187 drm_get_max_frl_rate(dsc_max_frl_rate, &hdmi_dsc->max_lanes, 6188 &hdmi_dsc->max_frl_rate_per_lane); 6189 6190 dsc_max_slices = hf_scds[12] & DRM_EDID_DSC_MAX_SLICES; 6191 6192 switch (dsc_max_slices) { 6193 case 1: 6194 hdmi_dsc->max_slices = 1; 6195 hdmi_dsc->clk_per_slice = 340; 6196 break; 6197 case 2: 6198 hdmi_dsc->max_slices = 2; 6199 hdmi_dsc->clk_per_slice = 340; 6200 break; 6201 case 3: 6202 hdmi_dsc->max_slices = 4; 6203 hdmi_dsc->clk_per_slice = 340; 6204 break; 6205 case 4: 6206 hdmi_dsc->max_slices = 8; 6207 hdmi_dsc->clk_per_slice = 340; 6208 break; 6209 case 5: 6210 hdmi_dsc->max_slices = 8; 6211 hdmi_dsc->clk_per_slice = 400; 6212 break; 6213 case 6: 6214 hdmi_dsc->max_slices = 12; 6215 hdmi_dsc->clk_per_slice = 400; 6216 break; 6217 case 7: 6218 hdmi_dsc->max_slices = 16; 6219 hdmi_dsc->clk_per_slice = 400; 6220 break; 6221 case 0: 6222 default: 6223 hdmi_dsc->max_slices = 0; 6224 hdmi_dsc->clk_per_slice = 0; 6225 } 6226 } 6227 6228 if (cea_db_payload_len(hf_scds) >= 13 && hf_scds[13]) 6229 hdmi_dsc->total_chunk_kbytes = hf_scds[13] & DRM_EDID_DSC_TOTAL_CHUNK_KBYTES; 6230 } 6231 6232 /* Sink Capability Data Structure */ 6233 static void drm_parse_hdmi_forum_scds(struct drm_connector *connector, 6234 const u8 *hf_scds) 6235 { 6236 struct drm_display_info *info = &connector->display_info; 6237 struct drm_hdmi_info *hdmi = &info->hdmi; 6238 struct drm_hdmi_dsc_cap *hdmi_dsc = &hdmi->dsc_cap; 6239 int max_tmds_clock = 0; 6240 u8 max_frl_rate = 0; 6241 bool dsc_support = false; 6242 6243 info->has_hdmi_infoframe = true; 6244 6245 if (hf_scds[6] & 0x80) { 6246 hdmi->scdc.supported = true; 6247 if (hf_scds[6] & 0x40) 6248 hdmi->scdc.read_request = true; 6249 } 6250 6251 /* 6252 * All HDMI 2.0 monitors must support scrambling at rates > 340 MHz. 6253 * And as per the spec, three factors confirm this: 6254 * * Availability of a HF-VSDB block in EDID (check) 6255 * * Non zero Max_TMDS_Char_Rate filed in HF-VSDB (let's check) 6256 * * SCDC support available (let's check) 6257 * Lets check it out. 6258 */ 6259 6260 if (hf_scds[5]) { 6261 struct drm_scdc *scdc = &hdmi->scdc; 6262 6263 /* max clock is 5000 KHz times block value */ 6264 max_tmds_clock = hf_scds[5] * 5000; 6265 6266 if (max_tmds_clock > 340000) { 6267 info->max_tmds_clock = max_tmds_clock; 6268 } 6269 6270 if (scdc->supported) { 6271 scdc->scrambling.supported = true; 6272 6273 /* Few sinks support scrambling for clocks < 340M */ 6274 if ((hf_scds[6] & 0x8)) 6275 scdc->scrambling.low_rates = true; 6276 } 6277 } 6278 6279 if (hf_scds[7]) { 6280 max_frl_rate = (hf_scds[7] & DRM_EDID_MAX_FRL_RATE_MASK) >> 4; 6281 drm_get_max_frl_rate(max_frl_rate, &hdmi->max_lanes, 6282 &hdmi->max_frl_rate_per_lane); 6283 } 6284 6285 drm_parse_ycbcr420_deep_color_info(connector, hf_scds); 6286 6287 if (cea_db_payload_len(hf_scds) >= 11 && hf_scds[11]) { 6288 drm_parse_dsc_info(hdmi_dsc, hf_scds); 6289 dsc_support = true; 6290 } 6291 6292 drm_dbg_kms(connector->dev, 6293 "[CONNECTOR:%d:%s] HF-VSDB: max TMDS clock: %d KHz, HDMI 2.1 support: %s, DSC 1.2 support: %s\n", 6294 connector->base.id, connector->name, 6295 max_tmds_clock, str_yes_no(max_frl_rate), str_yes_no(dsc_support)); 6296 } 6297 6298 static void drm_parse_hdmi_deep_color_info(struct drm_connector *connector, 6299 const u8 *hdmi) 6300 { 6301 struct drm_display_info *info = &connector->display_info; 6302 unsigned int dc_bpc = 0; 6303 6304 /* HDMI supports at least 8 bpc */ 6305 info->bpc = 8; 6306 6307 if (cea_db_payload_len(hdmi) < 6) 6308 return; 6309 6310 if (hdmi[6] & DRM_EDID_HDMI_DC_30) { 6311 dc_bpc = 10; 6312 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_30; 6313 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 30.\n", 6314 connector->base.id, connector->name); 6315 } 6316 6317 if (hdmi[6] & DRM_EDID_HDMI_DC_36) { 6318 dc_bpc = 12; 6319 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_36; 6320 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 36.\n", 6321 connector->base.id, connector->name); 6322 } 6323 6324 if (hdmi[6] & DRM_EDID_HDMI_DC_48) { 6325 dc_bpc = 16; 6326 info->edid_hdmi_rgb444_dc_modes |= DRM_EDID_HDMI_DC_48; 6327 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does deep color 48.\n", 6328 connector->base.id, connector->name); 6329 } 6330 6331 if (dc_bpc == 0) { 6332 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] No deep color support on this HDMI sink.\n", 6333 connector->base.id, connector->name); 6334 return; 6335 } 6336 6337 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Assigning HDMI sink color depth as %d bpc.\n", 6338 connector->base.id, connector->name, dc_bpc); 6339 info->bpc = dc_bpc; 6340 6341 /* YCRCB444 is optional according to spec. */ 6342 if (hdmi[6] & DRM_EDID_HDMI_DC_Y444) { 6343 info->edid_hdmi_ycbcr444_dc_modes = info->edid_hdmi_rgb444_dc_modes; 6344 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink does YCRCB444 in deep color.\n", 6345 connector->base.id, connector->name); 6346 } 6347 6348 /* 6349 * Spec says that if any deep color mode is supported at all, 6350 * then deep color 36 bit must be supported. 6351 */ 6352 if (!(hdmi[6] & DRM_EDID_HDMI_DC_36)) { 6353 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI sink should do DC_36, but does not!\n", 6354 connector->base.id, connector->name); 6355 } 6356 } 6357 6358 /* HDMI Vendor-Specific Data Block (HDMI VSDB, H14b-VSDB) */ 6359 static void 6360 drm_parse_hdmi_vsdb_video(struct drm_connector *connector, const u8 *db) 6361 { 6362 struct drm_display_info *info = &connector->display_info; 6363 u8 len = cea_db_payload_len(db); 6364 6365 info->is_hdmi = true; 6366 6367 info->source_physical_address = (db[4] << 8) | db[5]; 6368 6369 if (len >= 6) 6370 info->dvi_dual = db[6] & 1; 6371 if (len >= 7) 6372 info->max_tmds_clock = db[7] * 5000; 6373 6374 /* 6375 * Try to infer whether the sink supports HDMI infoframes. 6376 * 6377 * HDMI infoframe support was first added in HDMI 1.4. Assume the sink 6378 * supports infoframes if HDMI_Video_present is set. 6379 */ 6380 if (len >= 8 && db[8] & BIT(5)) 6381 info->has_hdmi_infoframe = true; 6382 6383 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] HDMI: DVI dual %d, max TMDS clock %d kHz\n", 6384 connector->base.id, connector->name, 6385 info->dvi_dual, info->max_tmds_clock); 6386 6387 drm_parse_hdmi_deep_color_info(connector, db); 6388 } 6389 6390 /* 6391 * See EDID extension for head-mounted and specialized monitors, specified at: 6392 * https://docs.microsoft.com/en-us/windows-hardware/drivers/display/specialized-monitors-edid-extension 6393 */ 6394 static void drm_parse_microsoft_vsdb(struct drm_connector *connector, 6395 const u8 *db) 6396 { 6397 struct drm_display_info *info = &connector->display_info; 6398 u8 version = db[4]; 6399 bool desktop_usage = db[5] & BIT(6); 6400 6401 /* Version 1 and 2 for HMDs, version 3 flags desktop usage explicitly */ 6402 if (version == 1 || version == 2 || (version == 3 && !desktop_usage)) 6403 info->non_desktop = true; 6404 6405 drm_dbg_kms(connector->dev, 6406 "[CONNECTOR:%d:%s] HMD or specialized display VSDB version %u: 0x%02x\n", 6407 connector->base.id, connector->name, version, db[5]); 6408 } 6409 6410 static void drm_parse_cea_ext(struct drm_connector *connector, 6411 const struct drm_edid *drm_edid) 6412 { 6413 struct drm_display_info *info = &connector->display_info; 6414 struct drm_edid_iter edid_iter; 6415 const struct cea_db *db; 6416 struct cea_db_iter iter; 6417 const u8 *edid_ext; 6418 u64 y420cmdb_map = 0; 6419 6420 drm_edid_iter_begin(drm_edid, &edid_iter); 6421 drm_edid_iter_for_each(edid_ext, &edid_iter) { 6422 if (edid_ext[0] != CEA_EXT) 6423 continue; 6424 6425 if (!info->cea_rev) 6426 info->cea_rev = edid_ext[1]; 6427 6428 if (info->cea_rev != edid_ext[1]) 6429 drm_dbg_kms(connector->dev, 6430 "[CONNECTOR:%d:%s] CEA extension version mismatch %u != %u\n", 6431 connector->base.id, connector->name, 6432 info->cea_rev, edid_ext[1]); 6433 6434 /* The existence of a CTA extension should imply RGB support */ 6435 info->color_formats = DRM_COLOR_FORMAT_RGB444; 6436 if (edid_ext[3] & EDID_CEA_YCRCB444) 6437 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6438 if (edid_ext[3] & EDID_CEA_YCRCB422) 6439 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6440 if (edid_ext[3] & EDID_BASIC_AUDIO) 6441 info->has_audio = true; 6442 6443 } 6444 drm_edid_iter_end(&edid_iter); 6445 6446 cea_db_iter_edid_begin(drm_edid, &iter); 6447 cea_db_iter_for_each(db, &iter) { 6448 /* FIXME: convert parsers to use struct cea_db */ 6449 const u8 *data = (const u8 *)db; 6450 6451 if (cea_db_is_hdmi_vsdb(db)) 6452 drm_parse_hdmi_vsdb_video(connector, data); 6453 else if (cea_db_is_hdmi_forum_vsdb(db) || 6454 cea_db_is_hdmi_forum_scdb(db)) 6455 drm_parse_hdmi_forum_scds(connector, data); 6456 else if (cea_db_is_microsoft_vsdb(db)) 6457 drm_parse_microsoft_vsdb(connector, data); 6458 else if (cea_db_is_y420cmdb(db)) 6459 parse_cta_y420cmdb(connector, db, &y420cmdb_map); 6460 else if (cea_db_is_y420vdb(db)) 6461 parse_cta_y420vdb(connector, db); 6462 else if (cea_db_is_vcdb(db)) 6463 drm_parse_vcdb(connector, data); 6464 else if (cea_db_is_hdmi_hdr_metadata_block(db)) 6465 drm_parse_hdr_metadata_block(connector, data); 6466 else if (cea_db_tag(db) == CTA_DB_VIDEO) 6467 parse_cta_vdb(connector, db); 6468 else if (cea_db_tag(db) == CTA_DB_AUDIO) 6469 info->has_audio = true; 6470 } 6471 cea_db_iter_end(&iter); 6472 6473 if (y420cmdb_map) 6474 update_cta_y420cmdb(connector, y420cmdb_map); 6475 } 6476 6477 static 6478 void get_monitor_range(const struct detailed_timing *timing, void *c) 6479 { 6480 struct detailed_mode_closure *closure = c; 6481 struct drm_display_info *info = &closure->connector->display_info; 6482 struct drm_monitor_range_info *monitor_range = &info->monitor_range; 6483 const struct detailed_non_pixel *data = &timing->data.other_data; 6484 const struct detailed_data_monitor_range *range = &data->data.range; 6485 const struct edid *edid = closure->drm_edid->edid; 6486 6487 if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE)) 6488 return; 6489 6490 /* 6491 * These limits are used to determine the VRR refresh 6492 * rate range. Only the "range limits only" variant 6493 * of the range descriptor seems to guarantee that 6494 * any and all timings are accepted by the sink, as 6495 * opposed to just timings conforming to the indicated 6496 * formula (GTF/GTF2/CVT). Thus other variants of the 6497 * range descriptor are not accepted here. 6498 */ 6499 if (range->flags != DRM_EDID_RANGE_LIMITS_ONLY_FLAG) 6500 return; 6501 6502 monitor_range->min_vfreq = range->min_vfreq; 6503 monitor_range->max_vfreq = range->max_vfreq; 6504 6505 if (edid->revision >= 4) { 6506 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ) 6507 monitor_range->min_vfreq += 255; 6508 if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ) 6509 monitor_range->max_vfreq += 255; 6510 } 6511 } 6512 6513 static void drm_get_monitor_range(struct drm_connector *connector, 6514 const struct drm_edid *drm_edid) 6515 { 6516 const struct drm_display_info *info = &connector->display_info; 6517 struct detailed_mode_closure closure = { 6518 .connector = connector, 6519 .drm_edid = drm_edid, 6520 }; 6521 6522 if (drm_edid->edid->revision < 4) 6523 return; 6524 6525 if (!(drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ)) 6526 return; 6527 6528 drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure); 6529 6530 drm_dbg_kms(connector->dev, 6531 "[CONNECTOR:%d:%s] Supported Monitor Refresh rate range is %d Hz - %d Hz\n", 6532 connector->base.id, connector->name, 6533 info->monitor_range.min_vfreq, info->monitor_range.max_vfreq); 6534 } 6535 6536 static void drm_parse_vesa_mso_data(struct drm_connector *connector, 6537 const struct displayid_block *block) 6538 { 6539 struct displayid_vesa_vendor_specific_block *vesa = 6540 (struct displayid_vesa_vendor_specific_block *)block; 6541 struct drm_display_info *info = &connector->display_info; 6542 6543 if (block->num_bytes < 3) { 6544 drm_dbg_kms(connector->dev, 6545 "[CONNECTOR:%d:%s] Unexpected vendor block size %u\n", 6546 connector->base.id, connector->name, block->num_bytes); 6547 return; 6548 } 6549 6550 if (oui(vesa->oui[0], vesa->oui[1], vesa->oui[2]) != VESA_IEEE_OUI) 6551 return; 6552 6553 if (sizeof(*vesa) != sizeof(*block) + block->num_bytes) { 6554 drm_dbg_kms(connector->dev, 6555 "[CONNECTOR:%d:%s] Unexpected VESA vendor block size\n", 6556 connector->base.id, connector->name); 6557 return; 6558 } 6559 6560 switch (FIELD_GET(DISPLAYID_VESA_MSO_MODE, vesa->mso)) { 6561 default: 6562 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Reserved MSO mode value\n", 6563 connector->base.id, connector->name); 6564 fallthrough; 6565 case 0: 6566 info->mso_stream_count = 0; 6567 break; 6568 case 1: 6569 info->mso_stream_count = 2; /* 2 or 4 links */ 6570 break; 6571 case 2: 6572 info->mso_stream_count = 4; /* 4 links */ 6573 break; 6574 } 6575 6576 if (!info->mso_stream_count) { 6577 info->mso_pixel_overlap = 0; 6578 return; 6579 } 6580 6581 info->mso_pixel_overlap = FIELD_GET(DISPLAYID_VESA_MSO_OVERLAP, vesa->mso); 6582 if (info->mso_pixel_overlap > 8) { 6583 drm_dbg_kms(connector->dev, 6584 "[CONNECTOR:%d:%s] Reserved MSO pixel overlap value %u\n", 6585 connector->base.id, connector->name, 6586 info->mso_pixel_overlap); 6587 info->mso_pixel_overlap = 8; 6588 } 6589 6590 drm_dbg_kms(connector->dev, 6591 "[CONNECTOR:%d:%s] MSO stream count %u, pixel overlap %u\n", 6592 connector->base.id, connector->name, 6593 info->mso_stream_count, info->mso_pixel_overlap); 6594 } 6595 6596 static void drm_update_mso(struct drm_connector *connector, 6597 const struct drm_edid *drm_edid) 6598 { 6599 const struct displayid_block *block; 6600 struct displayid_iter iter; 6601 6602 displayid_iter_edid_begin(drm_edid, &iter); 6603 displayid_iter_for_each(block, &iter) { 6604 if (block->tag == DATA_BLOCK_2_VENDOR_SPECIFIC) 6605 drm_parse_vesa_mso_data(connector, block); 6606 } 6607 displayid_iter_end(&iter); 6608 } 6609 6610 /* A connector has no EDID information, so we've got no EDID to compute quirks from. Reset 6611 * all of the values which would have been set from EDID 6612 */ 6613 static void drm_reset_display_info(struct drm_connector *connector) 6614 { 6615 struct drm_display_info *info = &connector->display_info; 6616 6617 info->width_mm = 0; 6618 info->height_mm = 0; 6619 6620 info->bpc = 0; 6621 info->color_formats = 0; 6622 info->cea_rev = 0; 6623 info->max_tmds_clock = 0; 6624 info->dvi_dual = false; 6625 info->is_hdmi = false; 6626 info->has_audio = false; 6627 info->has_hdmi_infoframe = false; 6628 info->rgb_quant_range_selectable = false; 6629 memset(&info->hdmi, 0, sizeof(info->hdmi)); 6630 6631 info->edid_hdmi_rgb444_dc_modes = 0; 6632 info->edid_hdmi_ycbcr444_dc_modes = 0; 6633 6634 info->non_desktop = 0; 6635 memset(&info->monitor_range, 0, sizeof(info->monitor_range)); 6636 memset(&info->luminance_range, 0, sizeof(info->luminance_range)); 6637 6638 info->mso_stream_count = 0; 6639 info->mso_pixel_overlap = 0; 6640 info->max_dsc_bpp = 0; 6641 6642 kfree(info->vics); 6643 info->vics = NULL; 6644 info->vics_len = 0; 6645 6646 info->quirks = 0; 6647 6648 info->source_physical_address = CEC_PHYS_ADDR_INVALID; 6649 } 6650 6651 static void update_displayid_info(struct drm_connector *connector, 6652 const struct drm_edid *drm_edid) 6653 { 6654 struct drm_display_info *info = &connector->display_info; 6655 const struct displayid_block *block; 6656 struct displayid_iter iter; 6657 6658 displayid_iter_edid_begin(drm_edid, &iter); 6659 displayid_iter_for_each(block, &iter) { 6660 if (displayid_version(&iter) == DISPLAY_ID_STRUCTURE_VER_20 && 6661 (displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_VR || 6662 displayid_primary_use(&iter) == PRIMARY_USE_HEAD_MOUNTED_AR)) 6663 info->non_desktop = true; 6664 6665 /* 6666 * We're only interested in the base section here, no need to 6667 * iterate further. 6668 */ 6669 break; 6670 } 6671 displayid_iter_end(&iter); 6672 } 6673 6674 static void update_display_info(struct drm_connector *connector, 6675 const struct drm_edid *drm_edid) 6676 { 6677 struct drm_display_info *info = &connector->display_info; 6678 const struct edid *edid; 6679 6680 drm_reset_display_info(connector); 6681 clear_eld(connector); 6682 6683 if (!drm_edid) 6684 return; 6685 6686 edid = drm_edid->edid; 6687 6688 info->quirks = edid_get_quirks(drm_edid); 6689 6690 info->width_mm = edid->width_cm * 10; 6691 info->height_mm = edid->height_cm * 10; 6692 6693 drm_get_monitor_range(connector, drm_edid); 6694 6695 if (edid->revision < 3) 6696 goto out; 6697 6698 if (!drm_edid_is_digital(drm_edid)) 6699 goto out; 6700 6701 info->color_formats |= DRM_COLOR_FORMAT_RGB444; 6702 drm_parse_cea_ext(connector, drm_edid); 6703 6704 update_displayid_info(connector, drm_edid); 6705 6706 /* 6707 * Digital sink with "DFP 1.x compliant TMDS" according to EDID 1.3? 6708 * 6709 * For such displays, the DFP spec 1.0, section 3.10 "EDID support" 6710 * tells us to assume 8 bpc color depth if the EDID doesn't have 6711 * extensions which tell otherwise. 6712 */ 6713 if (info->bpc == 0 && edid->revision == 3 && 6714 edid->input & DRM_EDID_DIGITAL_DFP_1_X) { 6715 info->bpc = 8; 6716 drm_dbg_kms(connector->dev, 6717 "[CONNECTOR:%d:%s] Assigning DFP sink color depth as %d bpc.\n", 6718 connector->base.id, connector->name, info->bpc); 6719 } 6720 6721 /* Only defined for 1.4 with digital displays */ 6722 if (edid->revision < 4) 6723 goto out; 6724 6725 switch (edid->input & DRM_EDID_DIGITAL_DEPTH_MASK) { 6726 case DRM_EDID_DIGITAL_DEPTH_6: 6727 info->bpc = 6; 6728 break; 6729 case DRM_EDID_DIGITAL_DEPTH_8: 6730 info->bpc = 8; 6731 break; 6732 case DRM_EDID_DIGITAL_DEPTH_10: 6733 info->bpc = 10; 6734 break; 6735 case DRM_EDID_DIGITAL_DEPTH_12: 6736 info->bpc = 12; 6737 break; 6738 case DRM_EDID_DIGITAL_DEPTH_14: 6739 info->bpc = 14; 6740 break; 6741 case DRM_EDID_DIGITAL_DEPTH_16: 6742 info->bpc = 16; 6743 break; 6744 case DRM_EDID_DIGITAL_DEPTH_UNDEF: 6745 default: 6746 info->bpc = 0; 6747 break; 6748 } 6749 6750 drm_dbg_kms(connector->dev, 6751 "[CONNECTOR:%d:%s] Assigning EDID-1.4 digital sink color depth as %d bpc.\n", 6752 connector->base.id, connector->name, info->bpc); 6753 6754 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB444) 6755 info->color_formats |= DRM_COLOR_FORMAT_YCBCR444; 6756 if (edid->features & DRM_EDID_FEATURE_RGB_YCRCB422) 6757 info->color_formats |= DRM_COLOR_FORMAT_YCBCR422; 6758 6759 drm_update_mso(connector, drm_edid); 6760 6761 out: 6762 if (info->quirks & EDID_QUIRK_NON_DESKTOP) { 6763 drm_dbg_kms(connector->dev, "[CONNECTOR:%d:%s] Non-desktop display%s\n", 6764 connector->base.id, connector->name, 6765 info->non_desktop ? " (redundant quirk)" : ""); 6766 info->non_desktop = true; 6767 } 6768 6769 if (info->quirks & EDID_QUIRK_CAP_DSC_15BPP) 6770 info->max_dsc_bpp = 15; 6771 6772 if (info->quirks & EDID_QUIRK_FORCE_6BPC) 6773 info->bpc = 6; 6774 6775 if (info->quirks & EDID_QUIRK_FORCE_8BPC) 6776 info->bpc = 8; 6777 6778 if (info->quirks & EDID_QUIRK_FORCE_10BPC) 6779 info->bpc = 10; 6780 6781 if (info->quirks & EDID_QUIRK_FORCE_12BPC) 6782 info->bpc = 12; 6783 6784 /* Depends on info->cea_rev set by drm_parse_cea_ext() above */ 6785 drm_edid_to_eld(connector, drm_edid); 6786 } 6787 6788 static struct drm_display_mode *drm_mode_displayid_detailed(struct drm_device *dev, 6789 struct displayid_detailed_timings_1 *timings, 6790 bool type_7) 6791 { 6792 struct drm_display_mode *mode; 6793 unsigned pixel_clock = (timings->pixel_clock[0] | 6794 (timings->pixel_clock[1] << 8) | 6795 (timings->pixel_clock[2] << 16)) + 1; 6796 unsigned hactive = (timings->hactive[0] | timings->hactive[1] << 8) + 1; 6797 unsigned hblank = (timings->hblank[0] | timings->hblank[1] << 8) + 1; 6798 unsigned hsync = (timings->hsync[0] | (timings->hsync[1] & 0x7f) << 8) + 1; 6799 unsigned hsync_width = (timings->hsw[0] | timings->hsw[1] << 8) + 1; 6800 unsigned vactive = (timings->vactive[0] | timings->vactive[1] << 8) + 1; 6801 unsigned vblank = (timings->vblank[0] | timings->vblank[1] << 8) + 1; 6802 unsigned vsync = (timings->vsync[0] | (timings->vsync[1] & 0x7f) << 8) + 1; 6803 unsigned vsync_width = (timings->vsw[0] | timings->vsw[1] << 8) + 1; 6804 bool hsync_positive = (timings->hsync[1] >> 7) & 0x1; 6805 bool vsync_positive = (timings->vsync[1] >> 7) & 0x1; 6806 6807 mode = drm_mode_create(dev); 6808 if (!mode) 6809 return NULL; 6810 6811 /* resolution is kHz for type VII, and 10 kHz for type I */ 6812 mode->clock = type_7 ? pixel_clock : pixel_clock * 10; 6813 mode->hdisplay = hactive; 6814 mode->hsync_start = mode->hdisplay + hsync; 6815 mode->hsync_end = mode->hsync_start + hsync_width; 6816 mode->htotal = mode->hdisplay + hblank; 6817 6818 mode->vdisplay = vactive; 6819 mode->vsync_start = mode->vdisplay + vsync; 6820 mode->vsync_end = mode->vsync_start + vsync_width; 6821 mode->vtotal = mode->vdisplay + vblank; 6822 6823 mode->flags = 0; 6824 mode->flags |= hsync_positive ? DRM_MODE_FLAG_PHSYNC : DRM_MODE_FLAG_NHSYNC; 6825 mode->flags |= vsync_positive ? DRM_MODE_FLAG_PVSYNC : DRM_MODE_FLAG_NVSYNC; 6826 mode->type = DRM_MODE_TYPE_DRIVER; 6827 6828 if (timings->flags & 0x80) 6829 mode->type |= DRM_MODE_TYPE_PREFERRED; 6830 drm_mode_set_name(mode); 6831 6832 return mode; 6833 } 6834 6835 static int add_displayid_detailed_1_modes(struct drm_connector *connector, 6836 const struct displayid_block *block) 6837 { 6838 struct displayid_detailed_timing_block *det = (struct displayid_detailed_timing_block *)block; 6839 int i; 6840 int num_timings; 6841 struct drm_display_mode *newmode; 6842 int num_modes = 0; 6843 bool type_7 = block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING; 6844 /* blocks must be multiple of 20 bytes length */ 6845 if (block->num_bytes % 20) 6846 return 0; 6847 6848 num_timings = block->num_bytes / 20; 6849 for (i = 0; i < num_timings; i++) { 6850 struct displayid_detailed_timings_1 *timings = &det->timings[i]; 6851 6852 newmode = drm_mode_displayid_detailed(connector->dev, timings, type_7); 6853 if (!newmode) 6854 continue; 6855 6856 drm_mode_probed_add(connector, newmode); 6857 num_modes++; 6858 } 6859 return num_modes; 6860 } 6861 6862 static int add_displayid_detailed_modes(struct drm_connector *connector, 6863 const struct drm_edid *drm_edid) 6864 { 6865 const struct displayid_block *block; 6866 struct displayid_iter iter; 6867 int num_modes = 0; 6868 6869 displayid_iter_edid_begin(drm_edid, &iter); 6870 displayid_iter_for_each(block, &iter) { 6871 if (block->tag == DATA_BLOCK_TYPE_1_DETAILED_TIMING || 6872 block->tag == DATA_BLOCK_2_TYPE_7_DETAILED_TIMING) 6873 num_modes += add_displayid_detailed_1_modes(connector, block); 6874 } 6875 displayid_iter_end(&iter); 6876 6877 return num_modes; 6878 } 6879 6880 static int _drm_edid_connector_add_modes(struct drm_connector *connector, 6881 const struct drm_edid *drm_edid) 6882 { 6883 const struct drm_display_info *info = &connector->display_info; 6884 int num_modes = 0; 6885 6886 if (!drm_edid) 6887 return 0; 6888 6889 /* 6890 * EDID spec says modes should be preferred in this order: 6891 * - preferred detailed mode 6892 * - other detailed modes from base block 6893 * - detailed modes from extension blocks 6894 * - CVT 3-byte code modes 6895 * - standard timing codes 6896 * - established timing codes 6897 * - modes inferred from GTF or CVT range information 6898 * 6899 * We get this pretty much right. 6900 * 6901 * XXX order for additional mode types in extension blocks? 6902 */ 6903 num_modes += add_detailed_modes(connector, drm_edid); 6904 num_modes += add_cvt_modes(connector, drm_edid); 6905 num_modes += add_standard_modes(connector, drm_edid); 6906 num_modes += add_established_modes(connector, drm_edid); 6907 num_modes += add_cea_modes(connector, drm_edid); 6908 num_modes += add_alternate_cea_modes(connector, drm_edid); 6909 num_modes += add_displayid_detailed_modes(connector, drm_edid); 6910 if (drm_edid->edid->features & DRM_EDID_FEATURE_CONTINUOUS_FREQ) 6911 num_modes += add_inferred_modes(connector, drm_edid); 6912 6913 if (info->quirks & (EDID_QUIRK_PREFER_LARGE_60 | EDID_QUIRK_PREFER_LARGE_75)) 6914 edid_fixup_preferred(connector); 6915 6916 return num_modes; 6917 } 6918 6919 static void _drm_update_tile_info(struct drm_connector *connector, 6920 const struct drm_edid *drm_edid); 6921 6922 static int _drm_edid_connector_property_update(struct drm_connector *connector, 6923 const struct drm_edid *drm_edid) 6924 { 6925 struct drm_device *dev = connector->dev; 6926 int ret; 6927 6928 if (connector->edid_blob_ptr) { 6929 const void *old_edid = connector->edid_blob_ptr->data; 6930 size_t old_edid_size = connector->edid_blob_ptr->length; 6931 6932 if (old_edid && !drm_edid_eq(drm_edid, old_edid, old_edid_size)) { 6933 connector->epoch_counter++; 6934 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID changed, epoch counter %llu\n", 6935 connector->base.id, connector->name, 6936 connector->epoch_counter); 6937 } 6938 } 6939 6940 ret = drm_property_replace_global_blob(dev, 6941 &connector->edid_blob_ptr, 6942 drm_edid ? drm_edid->size : 0, 6943 drm_edid ? drm_edid->edid : NULL, 6944 &connector->base, 6945 dev->mode_config.edid_property); 6946 if (ret) { 6947 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] EDID property update failed (%d)\n", 6948 connector->base.id, connector->name, ret); 6949 goto out; 6950 } 6951 6952 ret = drm_object_property_set_value(&connector->base, 6953 dev->mode_config.non_desktop_property, 6954 connector->display_info.non_desktop); 6955 if (ret) { 6956 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Non-desktop property update failed (%d)\n", 6957 connector->base.id, connector->name, ret); 6958 goto out; 6959 } 6960 6961 ret = drm_connector_set_tile_property(connector); 6962 if (ret) { 6963 drm_dbg_kms(dev, "[CONNECTOR:%d:%s] Tile property update failed (%d)\n", 6964 connector->base.id, connector->name, ret); 6965 goto out; 6966 } 6967 6968 out: 6969 return ret; 6970 } 6971 6972 /** 6973 * drm_edid_connector_update - Update connector information from EDID 6974 * @connector: Connector 6975 * @drm_edid: EDID 6976 * 6977 * Update the connector display info, ELD, HDR metadata, relevant properties, 6978 * etc. from the passed in EDID. 6979 * 6980 * If EDID is NULL, reset the information. 6981 * 6982 * Must be called before calling drm_edid_connector_add_modes(). 6983 * 6984 * Return: 0 on success, negative error on errors. 6985 */ 6986 int drm_edid_connector_update(struct drm_connector *connector, 6987 const struct drm_edid *drm_edid) 6988 { 6989 update_display_info(connector, drm_edid); 6990 6991 _drm_update_tile_info(connector, drm_edid); 6992 6993 return _drm_edid_connector_property_update(connector, drm_edid); 6994 } 6995 EXPORT_SYMBOL(drm_edid_connector_update); 6996 6997 /** 6998 * drm_edid_connector_add_modes - Update probed modes from the EDID property 6999 * @connector: Connector 7000 * 7001 * Add the modes from the previously updated EDID property to the connector 7002 * probed modes list. 7003 * 7004 * drm_edid_connector_update() must have been called before this to update the 7005 * EDID property. 7006 * 7007 * Return: The number of modes added, or 0 if we couldn't find any. 7008 */ 7009 int drm_edid_connector_add_modes(struct drm_connector *connector) 7010 { 7011 const struct drm_edid *drm_edid = NULL; 7012 int count; 7013 7014 if (connector->edid_blob_ptr) 7015 drm_edid = drm_edid_alloc(connector->edid_blob_ptr->data, 7016 connector->edid_blob_ptr->length); 7017 7018 count = _drm_edid_connector_add_modes(connector, drm_edid); 7019 7020 drm_edid_free(drm_edid); 7021 7022 return count; 7023 } 7024 EXPORT_SYMBOL(drm_edid_connector_add_modes); 7025 7026 /** 7027 * drm_connector_update_edid_property - update the edid property of a connector 7028 * @connector: drm connector 7029 * @edid: new value of the edid property 7030 * 7031 * This function creates a new blob modeset object and assigns its id to the 7032 * connector's edid property. 7033 * Since we also parse tile information from EDID's displayID block, we also 7034 * set the connector's tile property here. See drm_connector_set_tile_property() 7035 * for more details. 7036 * 7037 * This function is deprecated. Use drm_edid_connector_update() instead. 7038 * 7039 * Returns: 7040 * Zero on success, negative errno on failure. 7041 */ 7042 int drm_connector_update_edid_property(struct drm_connector *connector, 7043 const struct edid *edid) 7044 { 7045 struct drm_edid drm_edid; 7046 7047 return drm_edid_connector_update(connector, drm_edid_legacy_init(&drm_edid, edid)); 7048 } 7049 EXPORT_SYMBOL(drm_connector_update_edid_property); 7050 7051 /** 7052 * drm_add_edid_modes - add modes from EDID data, if available 7053 * @connector: connector we're probing 7054 * @edid: EDID data 7055 * 7056 * Add the specified modes to the connector's mode list. Also fills out the 7057 * &drm_display_info structure and ELD in @connector with any information which 7058 * can be derived from the edid. 7059 * 7060 * This function is deprecated. Use drm_edid_connector_add_modes() instead. 7061 * 7062 * Return: The number of modes added or 0 if we couldn't find any. 7063 */ 7064 int drm_add_edid_modes(struct drm_connector *connector, struct edid *edid) 7065 { 7066 struct drm_edid _drm_edid; 7067 const struct drm_edid *drm_edid; 7068 7069 if (edid && !drm_edid_is_valid(edid)) { 7070 drm_warn(connector->dev, "[CONNECTOR:%d:%s] EDID invalid.\n", 7071 connector->base.id, connector->name); 7072 edid = NULL; 7073 } 7074 7075 drm_edid = drm_edid_legacy_init(&_drm_edid, edid); 7076 7077 update_display_info(connector, drm_edid); 7078 7079 return _drm_edid_connector_add_modes(connector, drm_edid); 7080 } 7081 EXPORT_SYMBOL(drm_add_edid_modes); 7082 7083 /** 7084 * drm_add_modes_noedid - add modes for the connectors without EDID 7085 * @connector: connector we're probing 7086 * @hdisplay: the horizontal display limit 7087 * @vdisplay: the vertical display limit 7088 * 7089 * Add the specified modes to the connector's mode list. Only when the 7090 * hdisplay/vdisplay is not beyond the given limit, it will be added. 7091 * 7092 * Return: The number of modes added or 0 if we couldn't find any. 7093 */ 7094 int drm_add_modes_noedid(struct drm_connector *connector, 7095 int hdisplay, int vdisplay) 7096 { 7097 int i, count, num_modes = 0; 7098 struct drm_display_mode *mode; 7099 struct drm_device *dev = connector->dev; 7100 7101 count = ARRAY_SIZE(drm_dmt_modes); 7102 if (hdisplay < 0) 7103 hdisplay = 0; 7104 if (vdisplay < 0) 7105 vdisplay = 0; 7106 7107 for (i = 0; i < count; i++) { 7108 const struct drm_display_mode *ptr = &drm_dmt_modes[i]; 7109 7110 if (hdisplay && vdisplay) { 7111 /* 7112 * Only when two are valid, they will be used to check 7113 * whether the mode should be added to the mode list of 7114 * the connector. 7115 */ 7116 if (ptr->hdisplay > hdisplay || 7117 ptr->vdisplay > vdisplay) 7118 continue; 7119 } 7120 if (drm_mode_vrefresh(ptr) > 61) 7121 continue; 7122 mode = drm_mode_duplicate(dev, ptr); 7123 if (mode) { 7124 drm_mode_probed_add(connector, mode); 7125 num_modes++; 7126 } 7127 } 7128 return num_modes; 7129 } 7130 EXPORT_SYMBOL(drm_add_modes_noedid); 7131 7132 static bool is_hdmi2_sink(const struct drm_connector *connector) 7133 { 7134 /* 7135 * FIXME: sil-sii8620 doesn't have a connector around when 7136 * we need one, so we have to be prepared for a NULL connector. 7137 */ 7138 if (!connector) 7139 return true; 7140 7141 return connector->display_info.hdmi.scdc.supported || 7142 connector->display_info.color_formats & DRM_COLOR_FORMAT_YCBCR420; 7143 } 7144 7145 static u8 drm_mode_hdmi_vic(const struct drm_connector *connector, 7146 const struct drm_display_mode *mode) 7147 { 7148 bool has_hdmi_infoframe = connector ? 7149 connector->display_info.has_hdmi_infoframe : false; 7150 7151 if (!has_hdmi_infoframe) 7152 return 0; 7153 7154 /* No HDMI VIC when signalling 3D video format */ 7155 if (mode->flags & DRM_MODE_FLAG_3D_MASK) 7156 return 0; 7157 7158 return drm_match_hdmi_mode(mode); 7159 } 7160 7161 static u8 drm_mode_cea_vic(const struct drm_connector *connector, 7162 const struct drm_display_mode *mode) 7163 { 7164 /* 7165 * HDMI spec says if a mode is found in HDMI 1.4b 4K modes 7166 * we should send its VIC in vendor infoframes, else send the 7167 * VIC in AVI infoframes. Lets check if this mode is present in 7168 * HDMI 1.4b 4K modes 7169 */ 7170 if (drm_mode_hdmi_vic(connector, mode)) 7171 return 0; 7172 7173 return drm_match_cea_mode(mode); 7174 } 7175 7176 /* 7177 * Avoid sending VICs defined in HDMI 2.0 in AVI infoframes to sinks that 7178 * conform to HDMI 1.4. 7179 * 7180 * HDMI 1.4 (CTA-861-D) VIC range: [1..64] 7181 * HDMI 2.0 (CTA-861-F) VIC range: [1..107] 7182 * 7183 * If the sink lists the VIC in CTA VDB, assume it's fine, regardless of HDMI 7184 * version. 7185 */ 7186 static u8 vic_for_avi_infoframe(const struct drm_connector *connector, u8 vic) 7187 { 7188 if (!is_hdmi2_sink(connector) && vic > 64 && 7189 !cta_vdb_has_vic(connector, vic)) 7190 return 0; 7191 7192 return vic; 7193 } 7194 7195 /** 7196 * drm_hdmi_avi_infoframe_from_display_mode() - fill an HDMI AVI infoframe with 7197 * data from a DRM display mode 7198 * @frame: HDMI AVI infoframe 7199 * @connector: the connector 7200 * @mode: DRM display mode 7201 * 7202 * Return: 0 on success or a negative error code on failure. 7203 */ 7204 int 7205 drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, 7206 const struct drm_connector *connector, 7207 const struct drm_display_mode *mode) 7208 { 7209 enum hdmi_picture_aspect picture_aspect; 7210 u8 vic, hdmi_vic; 7211 7212 if (!frame || !mode) 7213 return -EINVAL; 7214 7215 hdmi_avi_infoframe_init(frame); 7216 7217 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 7218 frame->pixel_repeat = 1; 7219 7220 vic = drm_mode_cea_vic(connector, mode); 7221 hdmi_vic = drm_mode_hdmi_vic(connector, mode); 7222 7223 frame->picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7224 7225 /* 7226 * As some drivers don't support atomic, we can't use connector state. 7227 * So just initialize the frame with default values, just the same way 7228 * as it's done with other properties here. 7229 */ 7230 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 7231 frame->itc = 0; 7232 7233 /* 7234 * Populate picture aspect ratio from either 7235 * user input (if specified) or from the CEA/HDMI mode lists. 7236 */ 7237 picture_aspect = mode->picture_aspect_ratio; 7238 if (picture_aspect == HDMI_PICTURE_ASPECT_NONE) { 7239 if (vic) 7240 picture_aspect = drm_get_cea_aspect_ratio(vic); 7241 else if (hdmi_vic) 7242 picture_aspect = drm_get_hdmi_aspect_ratio(hdmi_vic); 7243 } 7244 7245 /* 7246 * The infoframe can't convey anything but none, 4:3 7247 * and 16:9, so if the user has asked for anything else 7248 * we can only satisfy it by specifying the right VIC. 7249 */ 7250 if (picture_aspect > HDMI_PICTURE_ASPECT_16_9) { 7251 if (vic) { 7252 if (picture_aspect != drm_get_cea_aspect_ratio(vic)) 7253 return -EINVAL; 7254 } else if (hdmi_vic) { 7255 if (picture_aspect != drm_get_hdmi_aspect_ratio(hdmi_vic)) 7256 return -EINVAL; 7257 } else { 7258 return -EINVAL; 7259 } 7260 7261 picture_aspect = HDMI_PICTURE_ASPECT_NONE; 7262 } 7263 7264 frame->video_code = vic_for_avi_infoframe(connector, vic); 7265 frame->picture_aspect = picture_aspect; 7266 frame->active_aspect = HDMI_ACTIVE_ASPECT_PICTURE; 7267 frame->scan_mode = HDMI_SCAN_MODE_UNDERSCAN; 7268 7269 return 0; 7270 } 7271 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_from_display_mode); 7272 7273 /** 7274 * drm_hdmi_avi_infoframe_quant_range() - fill the HDMI AVI infoframe 7275 * quantization range information 7276 * @frame: HDMI AVI infoframe 7277 * @connector: the connector 7278 * @mode: DRM display mode 7279 * @rgb_quant_range: RGB quantization range (Q) 7280 */ 7281 void 7282 drm_hdmi_avi_infoframe_quant_range(struct hdmi_avi_infoframe *frame, 7283 const struct drm_connector *connector, 7284 const struct drm_display_mode *mode, 7285 enum hdmi_quantization_range rgb_quant_range) 7286 { 7287 const struct drm_display_info *info = &connector->display_info; 7288 7289 /* 7290 * CEA-861: 7291 * "A Source shall not send a non-zero Q value that does not correspond 7292 * to the default RGB Quantization Range for the transmitted Picture 7293 * unless the Sink indicates support for the Q bit in a Video 7294 * Capabilities Data Block." 7295 * 7296 * HDMI 2.0 recommends sending non-zero Q when it does match the 7297 * default RGB quantization range for the mode, even when QS=0. 7298 */ 7299 if (info->rgb_quant_range_selectable || 7300 rgb_quant_range == drm_default_rgb_quant_range(mode)) 7301 frame->quantization_range = rgb_quant_range; 7302 else 7303 frame->quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 7304 7305 /* 7306 * CEA-861-F: 7307 * "When transmitting any RGB colorimetry, the Source should set the 7308 * YQ-field to match the RGB Quantization Range being transmitted 7309 * (e.g., when Limited Range RGB, set YQ=0 or when Full Range RGB, 7310 * set YQ=1) and the Sink shall ignore the YQ-field." 7311 * 7312 * Unfortunate certain sinks (eg. VIZ Model 67/E261VA) get confused 7313 * by non-zero YQ when receiving RGB. There doesn't seem to be any 7314 * good way to tell which version of CEA-861 the sink supports, so 7315 * we limit non-zero YQ to HDMI 2.0 sinks only as HDMI 2.0 is based 7316 * on CEA-861-F. 7317 */ 7318 if (!is_hdmi2_sink(connector) || 7319 rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) 7320 frame->ycc_quantization_range = 7321 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 7322 else 7323 frame->ycc_quantization_range = 7324 HDMI_YCC_QUANTIZATION_RANGE_FULL; 7325 } 7326 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_quant_range); 7327 7328 static enum hdmi_3d_structure 7329 s3d_structure_from_display_mode(const struct drm_display_mode *mode) 7330 { 7331 u32 layout = mode->flags & DRM_MODE_FLAG_3D_MASK; 7332 7333 switch (layout) { 7334 case DRM_MODE_FLAG_3D_FRAME_PACKING: 7335 return HDMI_3D_STRUCTURE_FRAME_PACKING; 7336 case DRM_MODE_FLAG_3D_FIELD_ALTERNATIVE: 7337 return HDMI_3D_STRUCTURE_FIELD_ALTERNATIVE; 7338 case DRM_MODE_FLAG_3D_LINE_ALTERNATIVE: 7339 return HDMI_3D_STRUCTURE_LINE_ALTERNATIVE; 7340 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_FULL: 7341 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_FULL; 7342 case DRM_MODE_FLAG_3D_L_DEPTH: 7343 return HDMI_3D_STRUCTURE_L_DEPTH; 7344 case DRM_MODE_FLAG_3D_L_DEPTH_GFX_GFX_DEPTH: 7345 return HDMI_3D_STRUCTURE_L_DEPTH_GFX_GFX_DEPTH; 7346 case DRM_MODE_FLAG_3D_TOP_AND_BOTTOM: 7347 return HDMI_3D_STRUCTURE_TOP_AND_BOTTOM; 7348 case DRM_MODE_FLAG_3D_SIDE_BY_SIDE_HALF: 7349 return HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF; 7350 default: 7351 return HDMI_3D_STRUCTURE_INVALID; 7352 } 7353 } 7354 7355 /** 7356 * drm_hdmi_vendor_infoframe_from_display_mode() - fill an HDMI infoframe with 7357 * data from a DRM display mode 7358 * @frame: HDMI vendor infoframe 7359 * @connector: the connector 7360 * @mode: DRM display mode 7361 * 7362 * Note that there's is a need to send HDMI vendor infoframes only when using a 7363 * 4k or stereoscopic 3D mode. So when giving any other mode as input this 7364 * function will return -EINVAL, error that can be safely ignored. 7365 * 7366 * Return: 0 on success or a negative error code on failure. 7367 */ 7368 int 7369 drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, 7370 const struct drm_connector *connector, 7371 const struct drm_display_mode *mode) 7372 { 7373 /* 7374 * FIXME: sil-sii8620 doesn't have a connector around when 7375 * we need one, so we have to be prepared for a NULL connector. 7376 */ 7377 bool has_hdmi_infoframe = connector ? 7378 connector->display_info.has_hdmi_infoframe : false; 7379 int err; 7380 7381 if (!frame || !mode) 7382 return -EINVAL; 7383 7384 if (!has_hdmi_infoframe) 7385 return -EINVAL; 7386 7387 err = hdmi_vendor_infoframe_init(frame); 7388 if (err < 0) 7389 return err; 7390 7391 /* 7392 * Even if it's not absolutely necessary to send the infoframe 7393 * (ie.vic==0 and s3d_struct==0) we will still send it if we 7394 * know that the sink can handle it. This is based on a 7395 * suggestion in HDMI 2.0 Appendix F. Apparently some sinks 7396 * have trouble realizing that they should switch from 3D to 2D 7397 * mode if the source simply stops sending the infoframe when 7398 * it wants to switch from 3D to 2D. 7399 */ 7400 frame->vic = drm_mode_hdmi_vic(connector, mode); 7401 frame->s3d_struct = s3d_structure_from_display_mode(mode); 7402 7403 return 0; 7404 } 7405 EXPORT_SYMBOL(drm_hdmi_vendor_infoframe_from_display_mode); 7406 7407 static void drm_parse_tiled_block(struct drm_connector *connector, 7408 const struct displayid_block *block) 7409 { 7410 const struct displayid_tiled_block *tile = (struct displayid_tiled_block *)block; 7411 u16 w, h; 7412 u8 tile_v_loc, tile_h_loc; 7413 u8 num_v_tile, num_h_tile; 7414 struct drm_tile_group *tg; 7415 7416 w = tile->tile_size[0] | tile->tile_size[1] << 8; 7417 h = tile->tile_size[2] | tile->tile_size[3] << 8; 7418 7419 num_v_tile = (tile->topo[0] & 0xf) | (tile->topo[2] & 0x30); 7420 num_h_tile = (tile->topo[0] >> 4) | ((tile->topo[2] >> 2) & 0x30); 7421 tile_v_loc = (tile->topo[1] & 0xf) | ((tile->topo[2] & 0x3) << 4); 7422 tile_h_loc = (tile->topo[1] >> 4) | (((tile->topo[2] >> 2) & 0x3) << 4); 7423 7424 connector->has_tile = true; 7425 if (tile->tile_cap & 0x80) 7426 connector->tile_is_single_monitor = true; 7427 7428 connector->num_h_tile = num_h_tile + 1; 7429 connector->num_v_tile = num_v_tile + 1; 7430 connector->tile_h_loc = tile_h_loc; 7431 connector->tile_v_loc = tile_v_loc; 7432 connector->tile_h_size = w + 1; 7433 connector->tile_v_size = h + 1; 7434 7435 drm_dbg_kms(connector->dev, 7436 "[CONNECTOR:%d:%s] tile cap 0x%x, size %dx%d, num tiles %dx%d, location %dx%d, vend %c%c%c", 7437 connector->base.id, connector->name, 7438 tile->tile_cap, 7439 connector->tile_h_size, connector->tile_v_size, 7440 connector->num_h_tile, connector->num_v_tile, 7441 connector->tile_h_loc, connector->tile_v_loc, 7442 tile->topology_id[0], tile->topology_id[1], tile->topology_id[2]); 7443 7444 tg = drm_mode_get_tile_group(connector->dev, tile->topology_id); 7445 if (!tg) 7446 tg = drm_mode_create_tile_group(connector->dev, tile->topology_id); 7447 if (!tg) 7448 return; 7449 7450 if (connector->tile_group != tg) { 7451 /* if we haven't got a pointer, 7452 take the reference, drop ref to old tile group */ 7453 if (connector->tile_group) 7454 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7455 connector->tile_group = tg; 7456 } else { 7457 /* if same tile group, then release the ref we just took. */ 7458 drm_mode_put_tile_group(connector->dev, tg); 7459 } 7460 } 7461 7462 static bool displayid_is_tiled_block(const struct displayid_iter *iter, 7463 const struct displayid_block *block) 7464 { 7465 return (displayid_version(iter) < DISPLAY_ID_STRUCTURE_VER_20 && 7466 block->tag == DATA_BLOCK_TILED_DISPLAY) || 7467 (displayid_version(iter) == DISPLAY_ID_STRUCTURE_VER_20 && 7468 block->tag == DATA_BLOCK_2_TILED_DISPLAY_TOPOLOGY); 7469 } 7470 7471 static void _drm_update_tile_info(struct drm_connector *connector, 7472 const struct drm_edid *drm_edid) 7473 { 7474 const struct displayid_block *block; 7475 struct displayid_iter iter; 7476 7477 connector->has_tile = false; 7478 7479 displayid_iter_edid_begin(drm_edid, &iter); 7480 displayid_iter_for_each(block, &iter) { 7481 if (displayid_is_tiled_block(&iter, block)) 7482 drm_parse_tiled_block(connector, block); 7483 } 7484 displayid_iter_end(&iter); 7485 7486 if (!connector->has_tile && connector->tile_group) { 7487 drm_mode_put_tile_group(connector->dev, connector->tile_group); 7488 connector->tile_group = NULL; 7489 } 7490 } 7491 7492 /** 7493 * drm_edid_is_digital - is digital? 7494 * @drm_edid: The EDID 7495 * 7496 * Return true if input is digital. 7497 */ 7498 bool drm_edid_is_digital(const struct drm_edid *drm_edid) 7499 { 7500 return drm_edid && drm_edid->edid && 7501 drm_edid->edid->input & DRM_EDID_INPUT_DIGITAL; 7502 } 7503 EXPORT_SYMBOL(drm_edid_is_digital); 7504