1 // SPDX-License-Identifier: MIT 2 3 #include <linux/module.h> 4 5 #include <drm/display/drm_hdmi_helper.h> 6 #include <drm/drm_connector.h> 7 #include <drm/drm_edid.h> 8 #include <drm/drm_modes.h> 9 #include <drm/drm_print.h> 10 #include <drm/drm_property.h> 11 12 static inline bool is_eotf_supported(u8 output_eotf, u8 sink_eotf) 13 { 14 return sink_eotf & BIT(output_eotf); 15 } 16 17 /** 18 * drm_hdmi_infoframe_set_hdr_metadata() - fill an HDMI DRM infoframe with 19 * HDR metadata from userspace 20 * @frame: HDMI DRM infoframe 21 * @conn_state: Connector state containing HDR metadata 22 * 23 * Return: 0 on success or a negative error code on failure. 24 */ 25 int drm_hdmi_infoframe_set_hdr_metadata(struct hdmi_drm_infoframe *frame, 26 const struct drm_connector_state *conn_state) 27 { 28 struct drm_connector *connector; 29 struct hdr_output_metadata *hdr_metadata; 30 int err; 31 32 if (!frame || !conn_state) 33 return -EINVAL; 34 35 connector = conn_state->connector; 36 37 if (!conn_state->hdr_output_metadata) 38 return -EINVAL; 39 40 hdr_metadata = conn_state->hdr_output_metadata->data; 41 42 if (!hdr_metadata || !connector) 43 return -EINVAL; 44 45 /* Sink EOTF is Bit map while infoframe is absolute values */ 46 if (!is_eotf_supported(hdr_metadata->hdmi_metadata_type1.eotf, 47 connector->hdr_sink_metadata.hdmi_type1.eotf)) 48 DRM_DEBUG_KMS("Unknown EOTF %d\n", hdr_metadata->hdmi_metadata_type1.eotf); 49 50 err = hdmi_drm_infoframe_init(frame); 51 if (err < 0) 52 return err; 53 54 frame->eotf = hdr_metadata->hdmi_metadata_type1.eotf; 55 frame->metadata_type = hdr_metadata->hdmi_metadata_type1.metadata_type; 56 57 BUILD_BUG_ON(sizeof(frame->display_primaries) != 58 sizeof(hdr_metadata->hdmi_metadata_type1.display_primaries)); 59 BUILD_BUG_ON(sizeof(frame->white_point) != 60 sizeof(hdr_metadata->hdmi_metadata_type1.white_point)); 61 62 memcpy(&frame->display_primaries, 63 &hdr_metadata->hdmi_metadata_type1.display_primaries, 64 sizeof(frame->display_primaries)); 65 66 memcpy(&frame->white_point, 67 &hdr_metadata->hdmi_metadata_type1.white_point, 68 sizeof(frame->white_point)); 69 70 frame->max_display_mastering_luminance = 71 hdr_metadata->hdmi_metadata_type1.max_display_mastering_luminance; 72 frame->min_display_mastering_luminance = 73 hdr_metadata->hdmi_metadata_type1.min_display_mastering_luminance; 74 frame->max_fall = hdr_metadata->hdmi_metadata_type1.max_fall; 75 frame->max_cll = hdr_metadata->hdmi_metadata_type1.max_cll; 76 77 return 0; 78 } 79 EXPORT_SYMBOL(drm_hdmi_infoframe_set_hdr_metadata); 80 81 /* HDMI Colorspace Spec Definitions */ 82 #define FULL_COLORIMETRY_MASK 0x1FF 83 #define NORMAL_COLORIMETRY_MASK 0x3 84 #define EXTENDED_COLORIMETRY_MASK 0x7 85 #define EXTENDED_ACE_COLORIMETRY_MASK 0xF 86 87 #define C(x) ((x) << 0) 88 #define EC(x) ((x) << 2) 89 #define ACE(x) ((x) << 5) 90 91 #define HDMI_COLORIMETRY_NO_DATA 0x0 92 #define HDMI_COLORIMETRY_SMPTE_170M_YCC (C(1) | EC(0) | ACE(0)) 93 #define HDMI_COLORIMETRY_BT709_YCC (C(2) | EC(0) | ACE(0)) 94 #define HDMI_COLORIMETRY_XVYCC_601 (C(3) | EC(0) | ACE(0)) 95 #define HDMI_COLORIMETRY_XVYCC_709 (C(3) | EC(1) | ACE(0)) 96 #define HDMI_COLORIMETRY_SYCC_601 (C(3) | EC(2) | ACE(0)) 97 #define HDMI_COLORIMETRY_OPYCC_601 (C(3) | EC(3) | ACE(0)) 98 #define HDMI_COLORIMETRY_OPRGB (C(3) | EC(4) | ACE(0)) 99 #define HDMI_COLORIMETRY_BT2020_CYCC (C(3) | EC(5) | ACE(0)) 100 #define HDMI_COLORIMETRY_BT2020_RGB (C(3) | EC(6) | ACE(0)) 101 #define HDMI_COLORIMETRY_BT2020_YCC (C(3) | EC(6) | ACE(0)) 102 #define HDMI_COLORIMETRY_DCI_P3_RGB_D65 (C(3) | EC(7) | ACE(0)) 103 #define HDMI_COLORIMETRY_DCI_P3_RGB_THEATER (C(3) | EC(7) | ACE(1)) 104 105 static const u32 hdmi_colorimetry_val[] = { 106 [DRM_MODE_COLORIMETRY_NO_DATA] = HDMI_COLORIMETRY_NO_DATA, 107 [DRM_MODE_COLORIMETRY_SMPTE_170M_YCC] = HDMI_COLORIMETRY_SMPTE_170M_YCC, 108 [DRM_MODE_COLORIMETRY_BT709_YCC] = HDMI_COLORIMETRY_BT709_YCC, 109 [DRM_MODE_COLORIMETRY_XVYCC_601] = HDMI_COLORIMETRY_XVYCC_601, 110 [DRM_MODE_COLORIMETRY_XVYCC_709] = HDMI_COLORIMETRY_XVYCC_709, 111 [DRM_MODE_COLORIMETRY_SYCC_601] = HDMI_COLORIMETRY_SYCC_601, 112 [DRM_MODE_COLORIMETRY_OPYCC_601] = HDMI_COLORIMETRY_OPYCC_601, 113 [DRM_MODE_COLORIMETRY_OPRGB] = HDMI_COLORIMETRY_OPRGB, 114 [DRM_MODE_COLORIMETRY_BT2020_CYCC] = HDMI_COLORIMETRY_BT2020_CYCC, 115 [DRM_MODE_COLORIMETRY_BT2020_RGB] = HDMI_COLORIMETRY_BT2020_RGB, 116 [DRM_MODE_COLORIMETRY_BT2020_YCC] = HDMI_COLORIMETRY_BT2020_YCC, 117 }; 118 119 #undef C 120 #undef EC 121 #undef ACE 122 123 /** 124 * drm_hdmi_avi_infoframe_colorimetry() - fill the HDMI AVI infoframe 125 * colorimetry information 126 * @frame: HDMI AVI infoframe 127 * @conn_state: connector state 128 */ 129 void drm_hdmi_avi_infoframe_colorimetry(struct hdmi_avi_infoframe *frame, 130 const struct drm_connector_state *conn_state) 131 { 132 u32 colorimetry_val; 133 u32 colorimetry_index = conn_state->colorspace & FULL_COLORIMETRY_MASK; 134 135 if (colorimetry_index >= ARRAY_SIZE(hdmi_colorimetry_val)) 136 colorimetry_val = HDMI_COLORIMETRY_NO_DATA; 137 else 138 colorimetry_val = hdmi_colorimetry_val[colorimetry_index]; 139 140 frame->colorimetry = colorimetry_val & NORMAL_COLORIMETRY_MASK; 141 /* 142 * ToDo: Extend it for ACE formats as well. Modify the infoframe 143 * structure and extend it in drivers/video/hdmi 144 */ 145 frame->extended_colorimetry = (colorimetry_val >> 2) & 146 EXTENDED_COLORIMETRY_MASK; 147 } 148 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_colorimetry); 149 150 /** 151 * drm_hdmi_avi_infoframe_bars() - fill the HDMI AVI infoframe 152 * bar information 153 * @frame: HDMI AVI infoframe 154 * @conn_state: connector state 155 */ 156 void drm_hdmi_avi_infoframe_bars(struct hdmi_avi_infoframe *frame, 157 const struct drm_connector_state *conn_state) 158 { 159 frame->right_bar = conn_state->tv.margins.right; 160 frame->left_bar = conn_state->tv.margins.left; 161 frame->top_bar = conn_state->tv.margins.top; 162 frame->bottom_bar = conn_state->tv.margins.bottom; 163 } 164 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_bars); 165 166 /** 167 * drm_hdmi_avi_infoframe_content_type() - fill the HDMI AVI infoframe 168 * content type information, based 169 * on correspondent DRM property. 170 * @frame: HDMI AVI infoframe 171 * @conn_state: DRM display connector state 172 * 173 */ 174 void drm_hdmi_avi_infoframe_content_type(struct hdmi_avi_infoframe *frame, 175 const struct drm_connector_state *conn_state) 176 { 177 switch (conn_state->content_type) { 178 case DRM_MODE_CONTENT_TYPE_GRAPHICS: 179 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 180 break; 181 case DRM_MODE_CONTENT_TYPE_CINEMA: 182 frame->content_type = HDMI_CONTENT_TYPE_CINEMA; 183 break; 184 case DRM_MODE_CONTENT_TYPE_GAME: 185 frame->content_type = HDMI_CONTENT_TYPE_GAME; 186 break; 187 case DRM_MODE_CONTENT_TYPE_PHOTO: 188 frame->content_type = HDMI_CONTENT_TYPE_PHOTO; 189 break; 190 default: 191 /* Graphics is the default(0) */ 192 frame->content_type = HDMI_CONTENT_TYPE_GRAPHICS; 193 } 194 195 frame->itc = conn_state->content_type != DRM_MODE_CONTENT_TYPE_NO_DATA; 196 } 197 EXPORT_SYMBOL(drm_hdmi_avi_infoframe_content_type); 198 199 /** 200 * drm_hdmi_compute_mode_clock() - Computes the TMDS Character Rate 201 * @mode: Display mode to compute the clock for 202 * @bpc: Bits per character 203 * @fmt: Output Pixel Format used 204 * 205 * Returns the TMDS Character Rate for a given mode, bpc count and output format. 206 * 207 * RETURNS: 208 * The TMDS Character Rate, in Hertz, or 0 on error. 209 */ 210 unsigned long long 211 drm_hdmi_compute_mode_clock(const struct drm_display_mode *mode, 212 unsigned int bpc, enum hdmi_colorspace fmt) 213 { 214 unsigned long long clock = mode->clock * 1000ULL; 215 unsigned int vic = drm_match_cea_mode(mode); 216 217 /* 218 * CTA-861-G Spec, section 5.4 - Color Coding and Quantization 219 * mandates that VIC 1 always uses 8 bpc. 220 */ 221 if (vic == 1 && bpc != 8) 222 return 0; 223 224 if (fmt == HDMI_COLORSPACE_YUV422) { 225 /* 226 * HDMI 1.0 Spec, section 6.5 - Pixel Encoding states that 227 * YUV422 sends 24 bits over three channels, with Cb and Cr 228 * components being sent on odd and even pixels, respectively. 229 * 230 * If fewer than 12 bpc are sent, data are left justified. 231 */ 232 if (bpc > 12) 233 return 0; 234 235 /* 236 * HDMI 1.0 Spec, section 6.5 - Pixel Encoding 237 * specifies that YUV422 sends two 12-bits components over 238 * three TMDS channels per pixel clock, which is equivalent to 239 * three 8-bits components over three channels used by RGB as 240 * far as the clock rate goes. 241 */ 242 bpc = 8; 243 } 244 245 /* 246 * HDMI 2.0 Spec, Section 7.1 - YCbCr 4:2:0 Pixel Encoding 247 * specifies that YUV420 encoding is carried at a TMDS Character Rate 248 * equal to half the pixel clock rate. 249 */ 250 if (fmt == HDMI_COLORSPACE_YUV420) 251 clock = clock / 2; 252 253 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 254 clock = clock * 2; 255 256 return DIV_ROUND_CLOSEST_ULL(clock * bpc, 8); 257 } 258 EXPORT_SYMBOL(drm_hdmi_compute_mode_clock); 259 260 struct drm_hdmi_acr_n_cts_entry { 261 unsigned int n; 262 unsigned int cts; 263 }; 264 265 struct drm_hdmi_acr_data { 266 unsigned long tmds_clock_khz; 267 struct drm_hdmi_acr_n_cts_entry n_cts_32k, 268 n_cts_44k1, 269 n_cts_48k; 270 }; 271 272 static const struct drm_hdmi_acr_data hdmi_acr_n_cts[] = { 273 { 274 /* "Other" entry */ 275 .n_cts_32k = { .n = 4096, }, 276 .n_cts_44k1 = { .n = 6272, }, 277 .n_cts_48k = { .n = 6144, }, 278 }, { 279 .tmds_clock_khz = 25175, 280 .n_cts_32k = { .n = 4576, .cts = 28125, }, 281 .n_cts_44k1 = { .n = 7007, .cts = 31250, }, 282 .n_cts_48k = { .n = 6864, .cts = 28125, }, 283 }, { 284 .tmds_clock_khz = 25200, 285 .n_cts_32k = { .n = 4096, .cts = 25200, }, 286 .n_cts_44k1 = { .n = 6272, .cts = 28000, }, 287 .n_cts_48k = { .n = 6144, .cts = 25200, }, 288 }, { 289 .tmds_clock_khz = 27000, 290 .n_cts_32k = { .n = 4096, .cts = 27000, }, 291 .n_cts_44k1 = { .n = 6272, .cts = 30000, }, 292 .n_cts_48k = { .n = 6144, .cts = 27000, }, 293 }, { 294 .tmds_clock_khz = 27027, 295 .n_cts_32k = { .n = 4096, .cts = 27027, }, 296 .n_cts_44k1 = { .n = 6272, .cts = 30030, }, 297 .n_cts_48k = { .n = 6144, .cts = 27027, }, 298 }, { 299 .tmds_clock_khz = 54000, 300 .n_cts_32k = { .n = 4096, .cts = 54000, }, 301 .n_cts_44k1 = { .n = 6272, .cts = 60000, }, 302 .n_cts_48k = { .n = 6144, .cts = 54000, }, 303 }, { 304 .tmds_clock_khz = 54054, 305 .n_cts_32k = { .n = 4096, .cts = 54054, }, 306 .n_cts_44k1 = { .n = 6272, .cts = 60060, }, 307 .n_cts_48k = { .n = 6144, .cts = 54054, }, 308 }, { 309 .tmds_clock_khz = 74176, 310 .n_cts_32k = { .n = 11648, .cts = 210937, }, /* and 210938 */ 311 .n_cts_44k1 = { .n = 17836, .cts = 234375, }, 312 .n_cts_48k = { .n = 11648, .cts = 140625, }, 313 }, { 314 .tmds_clock_khz = 74250, 315 .n_cts_32k = { .n = 4096, .cts = 74250, }, 316 .n_cts_44k1 = { .n = 6272, .cts = 82500, }, 317 .n_cts_48k = { .n = 6144, .cts = 74250, }, 318 }, { 319 .tmds_clock_khz = 148352, 320 .n_cts_32k = { .n = 11648, .cts = 421875, }, 321 .n_cts_44k1 = { .n = 8918, .cts = 234375, }, 322 .n_cts_48k = { .n = 5824, .cts = 140625, }, 323 }, { 324 .tmds_clock_khz = 148500, 325 .n_cts_32k = { .n = 4096, .cts = 148500, }, 326 .n_cts_44k1 = { .n = 6272, .cts = 165000, }, 327 .n_cts_48k = { .n = 6144, .cts = 148500, }, 328 }, { 329 .tmds_clock_khz = 296703, 330 .n_cts_32k = { .n = 5824, .cts = 421875, }, 331 .n_cts_44k1 = { .n = 4459, .cts = 234375, }, 332 .n_cts_48k = { .n = 5824, .cts = 281250, }, 333 }, { 334 .tmds_clock_khz = 297000, 335 .n_cts_32k = { .n = 3072, .cts = 222750, }, 336 .n_cts_44k1 = { .n = 4704, .cts = 247500, }, 337 .n_cts_48k = { .n = 5120, .cts = 247500, }, 338 }, { 339 .tmds_clock_khz = 593407, 340 .n_cts_32k = { .n = 5824, .cts = 843750, }, 341 .n_cts_44k1 = { .n = 8918, .cts = 937500, }, 342 .n_cts_48k = { .n = 5824, .cts = 562500, }, 343 }, { 344 .tmds_clock_khz = 594000, 345 .n_cts_32k = { .n = 3072, .cts = 445500, }, 346 .n_cts_44k1 = { .n = 9408, .cts = 990000, }, 347 .n_cts_48k = { .n = 6144, .cts = 594000, }, 348 }, 349 }; 350 351 static int drm_hdmi_acr_find_tmds_entry(unsigned long tmds_clock_khz) 352 { 353 int i; 354 355 /* skip the "other" entry */ 356 for (i = 1; i < ARRAY_SIZE(hdmi_acr_n_cts); i++) { 357 if (hdmi_acr_n_cts[i].tmds_clock_khz == tmds_clock_khz) 358 return i; 359 } 360 361 return 0; 362 } 363 364 /** 365 * drm_hdmi_acr_get_n_cts() - get N and CTS values for Audio Clock Regeneration 366 * 367 * @tmds_char_rate: TMDS clock (char rate) as used by the HDMI connector 368 * @sample_rate: audio sample rate 369 * @out_n: a pointer to write the N value 370 * @out_cts: a pointer to write the CTS value 371 * 372 * Get the N and CTS values (either by calculating them or by returning data 373 * from the tables. This follows the HDMI 1.4b Section 7.2 "Audio Sample Clock 374 * Capture and Regeneration". 375 * 376 * Note, @sample_rate corresponds to the Fs value, see sections 7.2.4 - 7.2.6 377 * on how to select Fs for non-L-PCM formats. 378 */ 379 void 380 drm_hdmi_acr_get_n_cts(unsigned long long tmds_char_rate, 381 unsigned int sample_rate, 382 unsigned int *out_n, 383 unsigned int *out_cts) 384 { 385 /* be a bit more tolerant, especially for the 1.001 entries */ 386 unsigned long tmds_clock_khz = DIV_ROUND_CLOSEST_ULL(tmds_char_rate, 1000); 387 const struct drm_hdmi_acr_n_cts_entry *entry; 388 unsigned int n, cts, mult; 389 int tmds_idx; 390 391 tmds_idx = drm_hdmi_acr_find_tmds_entry(tmds_clock_khz); 392 393 /* 394 * Don't change the order, 192 kHz is divisible by 48k and 32k, but it 395 * should use 48k entry. 396 */ 397 if (sample_rate % 48000 == 0) { 398 entry = &hdmi_acr_n_cts[tmds_idx].n_cts_48k; 399 mult = sample_rate / 48000; 400 } else if (sample_rate % 44100 == 0) { 401 entry = &hdmi_acr_n_cts[tmds_idx].n_cts_44k1; 402 mult = sample_rate / 44100; 403 } else if (sample_rate % 32000 == 0) { 404 entry = &hdmi_acr_n_cts[tmds_idx].n_cts_32k; 405 mult = sample_rate / 32000; 406 } else { 407 entry = NULL; 408 } 409 410 if (entry) { 411 n = entry->n * mult; 412 cts = entry->cts; 413 } else { 414 /* Recommended optimal value, HDMI 1.4b, Section 7.2.1 */ 415 n = 128 * sample_rate / 1000; 416 cts = 0; 417 } 418 419 if (!cts) 420 cts = DIV_ROUND_CLOSEST_ULL(tmds_char_rate * n, 421 128 * sample_rate); 422 423 *out_n = n; 424 *out_cts = cts; 425 } 426 EXPORT_SYMBOL(drm_hdmi_acr_get_n_cts); 427