1 /* 2 * Copyright © 2009 Keith Packard 3 * 4 * Permission to use, copy, modify, distribute, and sell this software and its 5 * documentation for any purpose is hereby granted without fee, provided that 6 * the above copyright notice appear in all copies and that both that copyright 7 * notice and this permission notice appear in supporting documentation, and 8 * that the name of the copyright holders not be used in advertising or 9 * publicity pertaining to distribution of the software without specific, 10 * written prior permission. The copyright holders make no representations 11 * about the suitability of this software for any purpose. It is provided "as 12 * is" without express or implied warranty. 13 * 14 * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE, 15 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO 16 * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR 17 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, 18 * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER 19 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE 20 * OF THIS SOFTWARE. 21 */ 22 23 #include <linux/backlight.h> 24 #include <linux/delay.h> 25 #include <linux/dynamic_debug.h> 26 #include <linux/errno.h> 27 #include <linux/i2c.h> 28 #include <linux/init.h> 29 #include <linux/iopoll.h> 30 #include <linux/kernel.h> 31 #include <linux/module.h> 32 #include <linux/sched.h> 33 #include <linux/seq_file.h> 34 #include <linux/string_helpers.h> 35 36 #include <drm/display/drm_dp_helper.h> 37 #include <drm/display/drm_dp_mst_helper.h> 38 #include <drm/drm_edid.h> 39 #include <drm/drm_fixed.h> 40 #include <drm/drm_print.h> 41 #include <drm/drm_vblank.h> 42 #include <drm/drm_panel.h> 43 44 #include "drm_dp_helper_internal.h" 45 46 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0, 47 "DRM_UT_CORE", 48 "DRM_UT_DRIVER", 49 "DRM_UT_KMS", 50 "DRM_UT_PRIME", 51 "DRM_UT_ATOMIC", 52 "DRM_UT_VBL", 53 "DRM_UT_STATE", 54 "DRM_UT_LEASE", 55 "DRM_UT_DP", 56 "DRM_UT_DRMRES"); 57 58 struct dp_aux_backlight { 59 struct backlight_device *base; 60 struct drm_dp_aux *aux; 61 struct drm_edp_backlight_info info; 62 bool enabled; 63 }; 64 65 /** 66 * DOC: dp helpers 67 * 68 * These functions contain some common logic and helpers at various abstraction 69 * levels to deal with Display Port sink devices and related things like DP aux 70 * channel transfers, EDID reading over DP aux channels, decoding certain DPCD 71 * blocks, ... 72 */ 73 74 /* Helpers for DP link training */ 75 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r) 76 { 77 return link_status[r - DP_LANE0_1_STATUS]; 78 } 79 80 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE], 81 int lane) 82 { 83 int i = DP_LANE0_1_STATUS + (lane >> 1); 84 int s = (lane & 1) * 4; 85 u8 l = dp_link_status(link_status, i); 86 87 return (l >> s) & 0xf; 88 } 89 90 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 91 int lane_count) 92 { 93 u8 lane_align; 94 u8 lane_status; 95 int lane; 96 97 lane_align = dp_link_status(link_status, 98 DP_LANE_ALIGN_STATUS_UPDATED); 99 if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0) 100 return false; 101 for (lane = 0; lane < lane_count; lane++) { 102 lane_status = dp_get_lane_status(link_status, lane); 103 if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS) 104 return false; 105 } 106 return true; 107 } 108 EXPORT_SYMBOL(drm_dp_channel_eq_ok); 109 110 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE], 111 int lane_count) 112 { 113 int lane; 114 u8 lane_status; 115 116 for (lane = 0; lane < lane_count; lane++) { 117 lane_status = dp_get_lane_status(link_status, lane); 118 if ((lane_status & DP_LANE_CR_DONE) == 0) 119 return false; 120 } 121 return true; 122 } 123 EXPORT_SYMBOL(drm_dp_clock_recovery_ok); 124 125 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE], 126 int lane) 127 { 128 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 129 int s = ((lane & 1) ? 130 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT : 131 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); 132 u8 l = dp_link_status(link_status, i); 133 134 return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT; 135 } 136 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage); 137 138 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE], 139 int lane) 140 { 141 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 142 int s = ((lane & 1) ? 143 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT : 144 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); 145 u8 l = dp_link_status(link_status, i); 146 147 return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; 148 } 149 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis); 150 151 /* DP 2.0 128b/132b */ 152 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE], 153 int lane) 154 { 155 int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1); 156 int s = ((lane & 1) ? 157 DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT : 158 DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT); 159 u8 l = dp_link_status(link_status, i); 160 161 return (l >> s) & 0xf; 162 } 163 EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset); 164 165 /* DP 2.0 errata for 128b/132b */ 166 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE], 167 int lane_count) 168 { 169 u8 lane_align, lane_status; 170 int lane; 171 172 lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 173 if (!(lane_align & DP_INTERLANE_ALIGN_DONE)) 174 return false; 175 176 for (lane = 0; lane < lane_count; lane++) { 177 lane_status = dp_get_lane_status(link_status, lane); 178 if (!(lane_status & DP_LANE_CHANNEL_EQ_DONE)) 179 return false; 180 } 181 return true; 182 } 183 EXPORT_SYMBOL(drm_dp_128b132b_lane_channel_eq_done); 184 185 /* DP 2.0 errata for 128b/132b */ 186 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE], 187 int lane_count) 188 { 189 u8 lane_status; 190 int lane; 191 192 for (lane = 0; lane < lane_count; lane++) { 193 lane_status = dp_get_lane_status(link_status, lane); 194 if (!(lane_status & DP_LANE_SYMBOL_LOCKED)) 195 return false; 196 } 197 return true; 198 } 199 EXPORT_SYMBOL(drm_dp_128b132b_lane_symbol_locked); 200 201 /* DP 2.0 errata for 128b/132b */ 202 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]) 203 { 204 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 205 206 return status & DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE; 207 } 208 EXPORT_SYMBOL(drm_dp_128b132b_eq_interlane_align_done); 209 210 /* DP 2.0 errata for 128b/132b */ 211 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE]) 212 { 213 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 214 215 return status & DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE; 216 } 217 EXPORT_SYMBOL(drm_dp_128b132b_cds_interlane_align_done); 218 219 /* DP 2.0 errata for 128b/132b */ 220 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE]) 221 { 222 u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED); 223 224 return status & DP_128B132B_LT_FAILED; 225 } 226 EXPORT_SYMBOL(drm_dp_128b132b_link_training_failed); 227 228 static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 229 { 230 if (rd_interval > 4) 231 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", 232 aux->name, rd_interval); 233 234 if (rd_interval == 0) 235 return 100; 236 237 return rd_interval * 4 * USEC_PER_MSEC; 238 } 239 240 static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 241 { 242 if (rd_interval > 4) 243 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n", 244 aux->name, rd_interval); 245 246 if (rd_interval == 0) 247 return 400; 248 249 return rd_interval * 4 * USEC_PER_MSEC; 250 } 251 252 static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval) 253 { 254 switch (rd_interval) { 255 default: 256 drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n", 257 aux->name, rd_interval); 258 fallthrough; 259 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US: 260 return 400; 261 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS: 262 return 4000; 263 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS: 264 return 8000; 265 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS: 266 return 12000; 267 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS: 268 return 16000; 269 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS: 270 return 32000; 271 case DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS: 272 return 64000; 273 } 274 } 275 276 /* 277 * The link training delays are different for: 278 * 279 * - Clock recovery vs. channel equalization 280 * - DPRX vs. LTTPR 281 * - 128b/132b vs. 8b/10b 282 * - DPCD rev 1.3 vs. later 283 * 284 * Get the correct delay in us, reading DPCD if necessary. 285 */ 286 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 287 enum drm_dp_phy dp_phy, bool uhbr, bool cr) 288 { 289 int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval); 290 unsigned int offset; 291 u8 rd_interval, mask; 292 293 if (dp_phy == DP_PHY_DPRX) { 294 if (uhbr) { 295 if (cr) 296 return 100; 297 298 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL; 299 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 300 parse = __128b132b_channel_eq_delay_us; 301 } else { 302 if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 303 return 100; 304 305 offset = DP_TRAINING_AUX_RD_INTERVAL; 306 mask = DP_TRAINING_AUX_RD_MASK; 307 if (cr) 308 parse = __8b10b_clock_recovery_delay_us; 309 else 310 parse = __8b10b_channel_eq_delay_us; 311 } 312 } else { 313 if (uhbr) { 314 offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); 315 mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 316 parse = __128b132b_channel_eq_delay_us; 317 } else { 318 if (cr) 319 return 100; 320 321 offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy); 322 mask = DP_TRAINING_AUX_RD_MASK; 323 parse = __8b10b_channel_eq_delay_us; 324 } 325 } 326 327 if (offset < DP_RECEIVER_CAP_SIZE) { 328 rd_interval = dpcd[offset]; 329 } else { 330 if (drm_dp_dpcd_readb(aux, offset, &rd_interval) != 1) { 331 drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n", 332 aux->name); 333 /* arbitrary default delay */ 334 return 400; 335 } 336 } 337 338 return parse(aux, rd_interval & mask); 339 } 340 341 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 342 enum drm_dp_phy dp_phy, bool uhbr) 343 { 344 return __read_delay(aux, dpcd, dp_phy, uhbr, true); 345 } 346 EXPORT_SYMBOL(drm_dp_read_clock_recovery_delay); 347 348 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE], 349 enum drm_dp_phy dp_phy, bool uhbr) 350 { 351 return __read_delay(aux, dpcd, dp_phy, uhbr, false); 352 } 353 EXPORT_SYMBOL(drm_dp_read_channel_eq_delay); 354 355 /* Per DP 2.0 Errata */ 356 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux) 357 { 358 int unit; 359 u8 val; 360 361 if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) != 1) { 362 drm_err(aux->drm_dev, "%s: failed rd interval read\n", 363 aux->name); 364 /* default to max */ 365 val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 366 } 367 368 unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2; 369 val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK; 370 371 return (val + 1) * unit * 1000; 372 } 373 EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval); 374 375 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux, 376 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 377 { 378 u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 379 DP_TRAINING_AUX_RD_MASK; 380 int delay_us; 381 382 if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 383 delay_us = 100; 384 else 385 delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval); 386 387 usleep_range(delay_us, delay_us * 2); 388 } 389 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay); 390 391 static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 392 u8 rd_interval) 393 { 394 int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval); 395 396 usleep_range(delay_us, delay_us * 2); 397 } 398 399 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 400 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 401 { 402 __drm_dp_link_train_channel_eq_delay(aux, 403 dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 404 DP_TRAINING_AUX_RD_MASK); 405 } 406 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay); 407 408 /** 409 * drm_dp_phy_name() - Get the name of the given DP PHY 410 * @dp_phy: The DP PHY identifier 411 * 412 * Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or 413 * "LTTPR <N>", or "<INVALID DP PHY>" on errors. The returned string is always 414 * non-NULL and valid. 415 * 416 * Returns: Name of the DP PHY. 417 */ 418 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy) 419 { 420 static const char * const phy_names[] = { 421 [DP_PHY_DPRX] = "DPRX", 422 [DP_PHY_LTTPR1] = "LTTPR 1", 423 [DP_PHY_LTTPR2] = "LTTPR 2", 424 [DP_PHY_LTTPR3] = "LTTPR 3", 425 [DP_PHY_LTTPR4] = "LTTPR 4", 426 [DP_PHY_LTTPR5] = "LTTPR 5", 427 [DP_PHY_LTTPR6] = "LTTPR 6", 428 [DP_PHY_LTTPR7] = "LTTPR 7", 429 [DP_PHY_LTTPR8] = "LTTPR 8", 430 }; 431 432 if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names) || 433 WARN_ON(!phy_names[dp_phy])) 434 return "<INVALID DP PHY>"; 435 436 return phy_names[dp_phy]; 437 } 438 EXPORT_SYMBOL(drm_dp_phy_name); 439 440 void drm_dp_lttpr_link_train_clock_recovery_delay(void) 441 { 442 usleep_range(100, 200); 443 } 444 EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay); 445 446 static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r) 447 { 448 return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1]; 449 } 450 451 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux, 452 const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE]) 453 { 454 u8 interval = dp_lttpr_phy_cap(phy_cap, 455 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) & 456 DP_TRAINING_AUX_RD_MASK; 457 458 __drm_dp_link_train_channel_eq_delay(aux, interval); 459 } 460 EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay); 461 462 u8 drm_dp_link_rate_to_bw_code(int link_rate) 463 { 464 switch (link_rate) { 465 case 1000000: 466 return DP_LINK_BW_10; 467 case 1350000: 468 return DP_LINK_BW_13_5; 469 case 2000000: 470 return DP_LINK_BW_20; 471 default: 472 /* Spec says link_bw = link_rate / 0.27Gbps */ 473 return link_rate / 27000; 474 } 475 } 476 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code); 477 478 int drm_dp_bw_code_to_link_rate(u8 link_bw) 479 { 480 switch (link_bw) { 481 case DP_LINK_BW_10: 482 return 1000000; 483 case DP_LINK_BW_13_5: 484 return 1350000; 485 case DP_LINK_BW_20: 486 return 2000000; 487 default: 488 /* Spec says link_rate = link_bw * 0.27Gbps */ 489 return link_bw * 27000; 490 } 491 } 492 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate); 493 494 #define AUX_RETRY_INTERVAL 500 /* us */ 495 496 static inline void 497 drm_dp_dump_access(const struct drm_dp_aux *aux, 498 u8 request, uint offset, void *buffer, int ret) 499 { 500 const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-"; 501 502 if (ret > 0) 503 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n", 504 aux->name, offset, arrow, ret, min(ret, 20), buffer); 505 else 506 drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n", 507 aux->name, offset, arrow, ret); 508 } 509 510 /** 511 * DOC: dp helpers 512 * 513 * The DisplayPort AUX channel is an abstraction to allow generic, driver- 514 * independent access to AUX functionality. Drivers can take advantage of 515 * this by filling in the fields of the drm_dp_aux structure. 516 * 517 * Transactions are described using a hardware-independent drm_dp_aux_msg 518 * structure, which is passed into a driver's .transfer() implementation. 519 * Both native and I2C-over-AUX transactions are supported. 520 */ 521 522 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request, 523 unsigned int offset, void *buffer, size_t size) 524 { 525 struct drm_dp_aux_msg msg; 526 unsigned int retry, native_reply; 527 int err = 0, ret = 0; 528 529 memset(&msg, 0, sizeof(msg)); 530 msg.address = offset; 531 msg.request = request; 532 msg.buffer = buffer; 533 msg.size = size; 534 535 mutex_lock(&aux->hw_mutex); 536 537 /* 538 * If the device attached to the aux bus is powered down then there's 539 * no reason to attempt a transfer. Error out immediately. 540 */ 541 if (aux->powered_down) { 542 ret = -EBUSY; 543 goto unlock; 544 } 545 546 /* 547 * The specification doesn't give any recommendation on how often to 548 * retry native transactions. We used to retry 7 times like for 549 * aux i2c transactions but real world devices this wasn't 550 * sufficient, bump to 32 which makes Dell 4k monitors happier. 551 */ 552 for (retry = 0; retry < 32; retry++) { 553 if (ret != 0 && ret != -ETIMEDOUT) { 554 usleep_range(AUX_RETRY_INTERVAL, 555 AUX_RETRY_INTERVAL + 100); 556 } 557 558 ret = aux->transfer(aux, &msg); 559 if (ret >= 0) { 560 native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK; 561 if (native_reply == DP_AUX_NATIVE_REPLY_ACK) { 562 if (ret == size) 563 goto unlock; 564 565 ret = -EPROTO; 566 } else 567 ret = -EIO; 568 } 569 570 /* 571 * We want the error we return to be the error we received on 572 * the first transaction, since we may get a different error the 573 * next time we retry 574 */ 575 if (!err) 576 err = ret; 577 } 578 579 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n", 580 aux->name, err); 581 ret = err; 582 583 unlock: 584 mutex_unlock(&aux->hw_mutex); 585 return ret; 586 } 587 588 /** 589 * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access 590 * @aux: DisplayPort AUX channel (SST) 591 * @offset: address of the register to probe 592 * 593 * Probe the provided DPCD address by reading 1 byte from it. The function can 594 * be used to trigger some side-effect the read access has, like waking up the 595 * sink, without the need for the read-out value. 596 * 597 * Returns 0 if the read access suceeded, or a negative error code on failure. 598 */ 599 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset) 600 { 601 u8 buffer; 602 int ret; 603 604 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, 1); 605 WARN_ON(ret == 0); 606 607 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, ret); 608 609 return ret < 0 ? ret : 0; 610 } 611 EXPORT_SYMBOL(drm_dp_dpcd_probe); 612 613 /** 614 * drm_dp_dpcd_set_powered() - Set whether the DP device is powered 615 * @aux: DisplayPort AUX channel; for convenience it's OK to pass NULL here 616 * and the function will be a no-op. 617 * @powered: true if powered; false if not 618 * 619 * If the endpoint device on the DP AUX bus is known to be powered down 620 * then this function can be called to make future transfers fail immediately 621 * instead of needing to time out. 622 * 623 * If this function is never called then a device defaults to being powered. 624 */ 625 void drm_dp_dpcd_set_powered(struct drm_dp_aux *aux, bool powered) 626 { 627 if (!aux) 628 return; 629 630 mutex_lock(&aux->hw_mutex); 631 aux->powered_down = !powered; 632 mutex_unlock(&aux->hw_mutex); 633 } 634 EXPORT_SYMBOL(drm_dp_dpcd_set_powered); 635 636 /** 637 * drm_dp_dpcd_read() - read a series of bytes from the DPCD 638 * @aux: DisplayPort AUX channel (SST or MST) 639 * @offset: address of the (first) register to read 640 * @buffer: buffer to store the register values 641 * @size: number of bytes in @buffer 642 * 643 * Returns the number of bytes transferred on success, or a negative error 644 * code on failure. -EIO is returned if the request was NAKed by the sink or 645 * if the retry count was exceeded. If not all bytes were transferred, this 646 * function returns -EPROTO. Errors from the underlying AUX channel transfer 647 * function, with the exception of -EBUSY (which causes the transaction to 648 * be retried), are propagated to the caller. 649 */ 650 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset, 651 void *buffer, size_t size) 652 { 653 int ret; 654 655 /* 656 * HP ZR24w corrupts the first DPCD access after entering power save 657 * mode. Eg. on a read, the entire buffer will be filled with the same 658 * byte. Do a throw away read to avoid corrupting anything we care 659 * about. Afterwards things will work correctly until the monitor 660 * gets woken up and subsequently re-enters power save mode. 661 * 662 * The user pressing any button on the monitor is enough to wake it 663 * up, so there is no particularly good place to do the workaround. 664 * We just have to do it before any DPCD access and hope that the 665 * monitor doesn't power down exactly after the throw away read. 666 */ 667 if (!aux->is_remote) { 668 ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV); 669 if (ret < 0) 670 return ret; 671 } 672 673 if (aux->is_remote) 674 ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size); 675 else 676 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, 677 buffer, size); 678 679 drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret); 680 return ret; 681 } 682 EXPORT_SYMBOL(drm_dp_dpcd_read); 683 684 /** 685 * drm_dp_dpcd_write() - write a series of bytes to the DPCD 686 * @aux: DisplayPort AUX channel (SST or MST) 687 * @offset: address of the (first) register to write 688 * @buffer: buffer containing the values to write 689 * @size: number of bytes in @buffer 690 * 691 * Returns the number of bytes transferred on success, or a negative error 692 * code on failure. -EIO is returned if the request was NAKed by the sink or 693 * if the retry count was exceeded. If not all bytes were transferred, this 694 * function returns -EPROTO. Errors from the underlying AUX channel transfer 695 * function, with the exception of -EBUSY (which causes the transaction to 696 * be retried), are propagated to the caller. 697 */ 698 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset, 699 void *buffer, size_t size) 700 { 701 int ret; 702 703 if (aux->is_remote) 704 ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size); 705 else 706 ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset, 707 buffer, size); 708 709 drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret); 710 return ret; 711 } 712 EXPORT_SYMBOL(drm_dp_dpcd_write); 713 714 /** 715 * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207) 716 * @aux: DisplayPort AUX channel 717 * @status: buffer to store the link status in (must be at least 6 bytes) 718 * 719 * Returns the number of bytes transferred on success or a negative error 720 * code on failure. 721 */ 722 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux, 723 u8 status[DP_LINK_STATUS_SIZE]) 724 { 725 return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status, 726 DP_LINK_STATUS_SIZE); 727 } 728 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status); 729 730 /** 731 * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY 732 * @aux: DisplayPort AUX channel 733 * @dp_phy: the DP PHY to get the link status for 734 * @link_status: buffer to return the status in 735 * 736 * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The 737 * layout of the returned @link_status matches the DPCD register layout of the 738 * DPRX PHY link status. 739 * 740 * Returns 0 if the information was read successfully or a negative error code 741 * on failure. 742 */ 743 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux, 744 enum drm_dp_phy dp_phy, 745 u8 link_status[DP_LINK_STATUS_SIZE]) 746 { 747 int ret; 748 749 if (dp_phy == DP_PHY_DPRX) { 750 ret = drm_dp_dpcd_read(aux, 751 DP_LANE0_1_STATUS, 752 link_status, 753 DP_LINK_STATUS_SIZE); 754 755 if (ret < 0) 756 return ret; 757 758 WARN_ON(ret != DP_LINK_STATUS_SIZE); 759 760 return 0; 761 } 762 763 ret = drm_dp_dpcd_read(aux, 764 DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy), 765 link_status, 766 DP_LINK_STATUS_SIZE - 1); 767 768 if (ret < 0) 769 return ret; 770 771 WARN_ON(ret != DP_LINK_STATUS_SIZE - 1); 772 773 /* Convert the LTTPR to the sink PHY link status layout */ 774 memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1], 775 &link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS], 776 DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1); 777 link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0; 778 779 return 0; 780 } 781 EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status); 782 783 static int read_payload_update_status(struct drm_dp_aux *aux) 784 { 785 int ret; 786 u8 status; 787 788 ret = drm_dp_dpcd_readb(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, &status); 789 if (ret < 0) 790 return ret; 791 792 return status; 793 } 794 795 /** 796 * drm_dp_dpcd_write_payload() - Write Virtual Channel information to payload table 797 * @aux: DisplayPort AUX channel 798 * @vcpid: Virtual Channel Payload ID 799 * @start_time_slot: Starting time slot 800 * @time_slot_count: Time slot count 801 * 802 * Write the Virtual Channel payload allocation table, checking the payload 803 * update status and retrying as necessary. 804 * 805 * Returns: 806 * 0 on success, negative error otherwise 807 */ 808 int drm_dp_dpcd_write_payload(struct drm_dp_aux *aux, 809 int vcpid, u8 start_time_slot, u8 time_slot_count) 810 { 811 u8 payload_alloc[3], status; 812 int ret; 813 int retries = 0; 814 815 drm_dp_dpcd_writeb(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, 816 DP_PAYLOAD_TABLE_UPDATED); 817 818 payload_alloc[0] = vcpid; 819 payload_alloc[1] = start_time_slot; 820 payload_alloc[2] = time_slot_count; 821 822 ret = drm_dp_dpcd_write(aux, DP_PAYLOAD_ALLOCATE_SET, payload_alloc, 3); 823 if (ret != 3) { 824 drm_dbg_kms(aux->drm_dev, "failed to write payload allocation %d\n", ret); 825 goto fail; 826 } 827 828 retry: 829 ret = drm_dp_dpcd_readb(aux, DP_PAYLOAD_TABLE_UPDATE_STATUS, &status); 830 if (ret < 0) { 831 drm_dbg_kms(aux->drm_dev, "failed to read payload table status %d\n", ret); 832 goto fail; 833 } 834 835 if (!(status & DP_PAYLOAD_TABLE_UPDATED)) { 836 retries++; 837 if (retries < 20) { 838 usleep_range(10000, 20000); 839 goto retry; 840 } 841 drm_dbg_kms(aux->drm_dev, "status not set after read payload table status %d\n", 842 status); 843 ret = -EINVAL; 844 goto fail; 845 } 846 ret = 0; 847 fail: 848 return ret; 849 } 850 EXPORT_SYMBOL(drm_dp_dpcd_write_payload); 851 852 /** 853 * drm_dp_dpcd_clear_payload() - Clear the entire VC Payload ID table 854 * @aux: DisplayPort AUX channel 855 * 856 * Clear the entire VC Payload ID table. 857 * 858 * Returns: 0 on success, negative error code on errors. 859 */ 860 int drm_dp_dpcd_clear_payload(struct drm_dp_aux *aux) 861 { 862 return drm_dp_dpcd_write_payload(aux, 0, 0, 0x3f); 863 } 864 EXPORT_SYMBOL(drm_dp_dpcd_clear_payload); 865 866 /** 867 * drm_dp_dpcd_poll_act_handled() - Poll for ACT handled status 868 * @aux: DisplayPort AUX channel 869 * @timeout_ms: Timeout in ms 870 * 871 * Try waiting for the sink to finish updating its payload table by polling for 872 * the ACT handled bit of DP_PAYLOAD_TABLE_UPDATE_STATUS for up to @timeout_ms 873 * milliseconds, defaulting to 3000 ms if 0. 874 * 875 * Returns: 876 * 0 if the ACT was handled in time, negative error code on failure. 877 */ 878 int drm_dp_dpcd_poll_act_handled(struct drm_dp_aux *aux, int timeout_ms) 879 { 880 int ret, status; 881 882 /* default to 3 seconds, this is arbitrary */ 883 timeout_ms = timeout_ms ?: 3000; 884 885 ret = readx_poll_timeout(read_payload_update_status, aux, status, 886 status & DP_PAYLOAD_ACT_HANDLED || status < 0, 887 200, timeout_ms * USEC_PER_MSEC); 888 if (ret < 0 && status >= 0) { 889 drm_err(aux->drm_dev, "Failed to get ACT after %d ms, last status: %02x\n", 890 timeout_ms, status); 891 return -EINVAL; 892 } else if (status < 0) { 893 /* 894 * Failure here isn't unexpected - the hub may have 895 * just been unplugged 896 */ 897 drm_dbg_kms(aux->drm_dev, "Failed to read payload table status: %d\n", status); 898 return status; 899 } 900 901 return 0; 902 } 903 EXPORT_SYMBOL(drm_dp_dpcd_poll_act_handled); 904 905 static bool is_edid_digital_input_dp(const struct drm_edid *drm_edid) 906 { 907 /* FIXME: get rid of drm_edid_raw() */ 908 const struct edid *edid = drm_edid_raw(drm_edid); 909 910 return edid && edid->revision >= 4 && 911 edid->input & DRM_EDID_INPUT_DIGITAL && 912 (edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP; 913 } 914 915 /** 916 * drm_dp_downstream_is_type() - is the downstream facing port of certain type? 917 * @dpcd: DisplayPort configuration data 918 * @port_cap: port capabilities 919 * @type: port type to be checked. Can be: 920 * %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI, 921 * %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID, 922 * %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS. 923 * 924 * Caveat: Only works with DPCD 1.1+ port caps. 925 * 926 * Returns: whether the downstream facing port matches the type. 927 */ 928 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 929 const u8 port_cap[4], u8 type) 930 { 931 return drm_dp_is_branch(dpcd) && 932 dpcd[DP_DPCD_REV] >= 0x11 && 933 (port_cap[0] & DP_DS_PORT_TYPE_MASK) == type; 934 } 935 EXPORT_SYMBOL(drm_dp_downstream_is_type); 936 937 /** 938 * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS? 939 * @dpcd: DisplayPort configuration data 940 * @port_cap: port capabilities 941 * @drm_edid: EDID 942 * 943 * Returns: whether the downstream facing port is TMDS (HDMI/DVI). 944 */ 945 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 946 const u8 port_cap[4], 947 const struct drm_edid *drm_edid) 948 { 949 if (dpcd[DP_DPCD_REV] < 0x11) { 950 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 951 case DP_DWN_STRM_PORT_TYPE_TMDS: 952 return true; 953 default: 954 return false; 955 } 956 } 957 958 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 959 case DP_DS_PORT_TYPE_DP_DUALMODE: 960 if (is_edid_digital_input_dp(drm_edid)) 961 return false; 962 fallthrough; 963 case DP_DS_PORT_TYPE_DVI: 964 case DP_DS_PORT_TYPE_HDMI: 965 return true; 966 default: 967 return false; 968 } 969 } 970 EXPORT_SYMBOL(drm_dp_downstream_is_tmds); 971 972 /** 973 * drm_dp_send_real_edid_checksum() - send back real edid checksum value 974 * @aux: DisplayPort AUX channel 975 * @real_edid_checksum: real edid checksum for the last block 976 * 977 * Returns: 978 * True on success 979 */ 980 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux, 981 u8 real_edid_checksum) 982 { 983 u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0; 984 985 if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, 986 &auto_test_req, 1) < 1) { 987 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", 988 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); 989 return false; 990 } 991 auto_test_req &= DP_AUTOMATED_TEST_REQUEST; 992 993 if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) { 994 drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n", 995 aux->name, DP_TEST_REQUEST); 996 return false; 997 } 998 link_edid_read &= DP_TEST_LINK_EDID_READ; 999 1000 if (!auto_test_req || !link_edid_read) { 1001 drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n", 1002 aux->name); 1003 return false; 1004 } 1005 1006 if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR, 1007 &auto_test_req, 1) < 1) { 1008 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 1009 aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR); 1010 return false; 1011 } 1012 1013 /* send back checksum for the last edid extension block data */ 1014 if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM, 1015 &real_edid_checksum, 1) < 1) { 1016 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 1017 aux->name, DP_TEST_EDID_CHECKSUM); 1018 return false; 1019 } 1020 1021 test_resp |= DP_TEST_EDID_CHECKSUM_WRITE; 1022 if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) { 1023 drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n", 1024 aux->name, DP_TEST_RESPONSE); 1025 return false; 1026 } 1027 1028 return true; 1029 } 1030 EXPORT_SYMBOL(drm_dp_send_real_edid_checksum); 1031 1032 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1033 { 1034 u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK; 1035 1036 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4) 1037 port_count = 4; 1038 1039 return port_count; 1040 } 1041 1042 static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux, 1043 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1044 { 1045 u8 dpcd_ext[DP_RECEIVER_CAP_SIZE]; 1046 int ret; 1047 1048 /* 1049 * Prior to DP1.3 the bit represented by 1050 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. 1051 * If it is set DP_DPCD_REV at 0000h could be at a value less than 1052 * the true capability of the panel. The only way to check is to 1053 * then compare 0000h and 2200h. 1054 */ 1055 if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 1056 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) 1057 return 0; 1058 1059 ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext, 1060 sizeof(dpcd_ext)); 1061 if (ret < 0) 1062 return ret; 1063 if (ret != sizeof(dpcd_ext)) 1064 return -EIO; 1065 1066 if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { 1067 drm_dbg_kms(aux->drm_dev, 1068 "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n", 1069 aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]); 1070 return 0; 1071 } 1072 1073 if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext))) 1074 return 0; 1075 1076 drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 1077 1078 memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext)); 1079 1080 return 0; 1081 } 1082 1083 /** 1084 * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if 1085 * available 1086 * @aux: DisplayPort AUX channel 1087 * @dpcd: Buffer to store the resulting DPCD in 1088 * 1089 * Attempts to read the base DPCD caps for @aux. Additionally, this function 1090 * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if 1091 * present. 1092 * 1093 * Returns: %0 if the DPCD was read successfully, negative error code 1094 * otherwise. 1095 */ 1096 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux, 1097 u8 dpcd[DP_RECEIVER_CAP_SIZE]) 1098 { 1099 int ret; 1100 1101 ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE); 1102 if (ret < 0) 1103 return ret; 1104 if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0) 1105 return -EIO; 1106 1107 ret = drm_dp_read_extended_dpcd_caps(aux, dpcd); 1108 if (ret < 0) 1109 return ret; 1110 1111 drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd); 1112 1113 return ret; 1114 } 1115 EXPORT_SYMBOL(drm_dp_read_dpcd_caps); 1116 1117 /** 1118 * drm_dp_read_downstream_info() - read DPCD downstream port info if available 1119 * @aux: DisplayPort AUX channel 1120 * @dpcd: A cached copy of the port's DPCD 1121 * @downstream_ports: buffer to store the downstream port info in 1122 * 1123 * See also: 1124 * drm_dp_downstream_max_clock() 1125 * drm_dp_downstream_max_bpc() 1126 * 1127 * Returns: 0 if either the downstream port info was read successfully or 1128 * there was no downstream info to read, or a negative error code otherwise. 1129 */ 1130 int drm_dp_read_downstream_info(struct drm_dp_aux *aux, 1131 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1132 u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS]) 1133 { 1134 int ret; 1135 u8 len; 1136 1137 memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS); 1138 1139 /* No downstream info to read */ 1140 if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) 1141 return 0; 1142 1143 /* Some branches advertise having 0 downstream ports, despite also advertising they have a 1144 * downstream port present. The DP spec isn't clear on if this is allowed or not, but since 1145 * some branches do it we need to handle it regardless. 1146 */ 1147 len = drm_dp_downstream_port_count(dpcd); 1148 if (!len) 1149 return 0; 1150 1151 if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) 1152 len *= 4; 1153 1154 ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len); 1155 if (ret < 0) 1156 return ret; 1157 if (ret != len) 1158 return -EIO; 1159 1160 drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports); 1161 1162 return 0; 1163 } 1164 EXPORT_SYMBOL(drm_dp_read_downstream_info); 1165 1166 /** 1167 * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock 1168 * @dpcd: DisplayPort configuration data 1169 * @port_cap: port capabilities 1170 * 1171 * Returns: Downstream facing port max dot clock in kHz on success, 1172 * or 0 if max clock not defined 1173 */ 1174 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1175 const u8 port_cap[4]) 1176 { 1177 if (!drm_dp_is_branch(dpcd)) 1178 return 0; 1179 1180 if (dpcd[DP_DPCD_REV] < 0x11) 1181 return 0; 1182 1183 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1184 case DP_DS_PORT_TYPE_VGA: 1185 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1186 return 0; 1187 return port_cap[1] * 8000; 1188 default: 1189 return 0; 1190 } 1191 } 1192 EXPORT_SYMBOL(drm_dp_downstream_max_dotclock); 1193 1194 /** 1195 * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock 1196 * @dpcd: DisplayPort configuration data 1197 * @port_cap: port capabilities 1198 * @drm_edid: EDID 1199 * 1200 * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success, 1201 * or 0 if max TMDS clock not defined 1202 */ 1203 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1204 const u8 port_cap[4], 1205 const struct drm_edid *drm_edid) 1206 { 1207 if (!drm_dp_is_branch(dpcd)) 1208 return 0; 1209 1210 if (dpcd[DP_DPCD_REV] < 0x11) { 1211 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1212 case DP_DWN_STRM_PORT_TYPE_TMDS: 1213 return 165000; 1214 default: 1215 return 0; 1216 } 1217 } 1218 1219 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1220 case DP_DS_PORT_TYPE_DP_DUALMODE: 1221 if (is_edid_digital_input_dp(drm_edid)) 1222 return 0; 1223 /* 1224 * It's left up to the driver to check the 1225 * DP dual mode adapter's max TMDS clock. 1226 * 1227 * Unfortunately it looks like branch devices 1228 * may not fordward that the DP dual mode i2c 1229 * access so we just usually get i2c nak :( 1230 */ 1231 fallthrough; 1232 case DP_DS_PORT_TYPE_HDMI: 1233 /* 1234 * We should perhaps assume 165 MHz when detailed cap 1235 * info is not available. But looks like many typical 1236 * branch devices fall into that category and so we'd 1237 * probably end up with users complaining that they can't 1238 * get high resolution modes with their favorite dongle. 1239 * 1240 * So let's limit to 300 MHz instead since DPCD 1.4 1241 * HDMI 2.0 DFPs are required to have the detailed cap 1242 * info. So it's more likely we're dealing with a HDMI 1.4 1243 * compatible* device here. 1244 */ 1245 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1246 return 300000; 1247 return port_cap[1] * 2500; 1248 case DP_DS_PORT_TYPE_DVI: 1249 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1250 return 165000; 1251 /* FIXME what to do about DVI dual link? */ 1252 return port_cap[1] * 2500; 1253 default: 1254 return 0; 1255 } 1256 } 1257 EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock); 1258 1259 /** 1260 * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock 1261 * @dpcd: DisplayPort configuration data 1262 * @port_cap: port capabilities 1263 * @drm_edid: EDID 1264 * 1265 * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success, 1266 * or 0 if max TMDS clock not defined 1267 */ 1268 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1269 const u8 port_cap[4], 1270 const struct drm_edid *drm_edid) 1271 { 1272 if (!drm_dp_is_branch(dpcd)) 1273 return 0; 1274 1275 if (dpcd[DP_DPCD_REV] < 0x11) { 1276 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1277 case DP_DWN_STRM_PORT_TYPE_TMDS: 1278 return 25000; 1279 default: 1280 return 0; 1281 } 1282 } 1283 1284 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1285 case DP_DS_PORT_TYPE_DP_DUALMODE: 1286 if (is_edid_digital_input_dp(drm_edid)) 1287 return 0; 1288 fallthrough; 1289 case DP_DS_PORT_TYPE_DVI: 1290 case DP_DS_PORT_TYPE_HDMI: 1291 /* 1292 * Unclear whether the protocol converter could 1293 * utilize pixel replication. Assume it won't. 1294 */ 1295 return 25000; 1296 default: 1297 return 0; 1298 } 1299 } 1300 EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock); 1301 1302 /** 1303 * drm_dp_downstream_max_bpc() - extract downstream facing port max 1304 * bits per component 1305 * @dpcd: DisplayPort configuration data 1306 * @port_cap: downstream facing port capabilities 1307 * @drm_edid: EDID 1308 * 1309 * Returns: Max bpc on success or 0 if max bpc not defined 1310 */ 1311 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1312 const u8 port_cap[4], 1313 const struct drm_edid *drm_edid) 1314 { 1315 if (!drm_dp_is_branch(dpcd)) 1316 return 0; 1317 1318 if (dpcd[DP_DPCD_REV] < 0x11) { 1319 switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) { 1320 case DP_DWN_STRM_PORT_TYPE_DP: 1321 return 0; 1322 default: 1323 return 8; 1324 } 1325 } 1326 1327 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1328 case DP_DS_PORT_TYPE_DP: 1329 return 0; 1330 case DP_DS_PORT_TYPE_DP_DUALMODE: 1331 if (is_edid_digital_input_dp(drm_edid)) 1332 return 0; 1333 fallthrough; 1334 case DP_DS_PORT_TYPE_HDMI: 1335 case DP_DS_PORT_TYPE_DVI: 1336 case DP_DS_PORT_TYPE_VGA: 1337 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1338 return 8; 1339 1340 switch (port_cap[2] & DP_DS_MAX_BPC_MASK) { 1341 case DP_DS_8BPC: 1342 return 8; 1343 case DP_DS_10BPC: 1344 return 10; 1345 case DP_DS_12BPC: 1346 return 12; 1347 case DP_DS_16BPC: 1348 return 16; 1349 default: 1350 return 8; 1351 } 1352 break; 1353 default: 1354 return 8; 1355 } 1356 } 1357 EXPORT_SYMBOL(drm_dp_downstream_max_bpc); 1358 1359 /** 1360 * drm_dp_downstream_420_passthrough() - determine downstream facing port 1361 * YCbCr 4:2:0 pass-through capability 1362 * @dpcd: DisplayPort configuration data 1363 * @port_cap: downstream facing port capabilities 1364 * 1365 * Returns: whether the downstream facing port can pass through YCbCr 4:2:0 1366 */ 1367 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1368 const u8 port_cap[4]) 1369 { 1370 if (!drm_dp_is_branch(dpcd)) 1371 return false; 1372 1373 if (dpcd[DP_DPCD_REV] < 0x13) 1374 return false; 1375 1376 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1377 case DP_DS_PORT_TYPE_DP: 1378 return true; 1379 case DP_DS_PORT_TYPE_HDMI: 1380 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1381 return false; 1382 1383 return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH; 1384 default: 1385 return false; 1386 } 1387 } 1388 EXPORT_SYMBOL(drm_dp_downstream_420_passthrough); 1389 1390 /** 1391 * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port 1392 * YCbCr 4:4:4->4:2:0 conversion capability 1393 * @dpcd: DisplayPort configuration data 1394 * @port_cap: downstream facing port capabilities 1395 * 1396 * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0 1397 */ 1398 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1399 const u8 port_cap[4]) 1400 { 1401 if (!drm_dp_is_branch(dpcd)) 1402 return false; 1403 1404 if (dpcd[DP_DPCD_REV] < 0x13) 1405 return false; 1406 1407 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1408 case DP_DS_PORT_TYPE_HDMI: 1409 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1410 return false; 1411 1412 return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV; 1413 default: 1414 return false; 1415 } 1416 } 1417 EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion); 1418 1419 /** 1420 * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port 1421 * RGB->YCbCr conversion capability 1422 * @dpcd: DisplayPort configuration data 1423 * @port_cap: downstream facing port capabilities 1424 * @color_spc: Colorspace for which conversion cap is sought 1425 * 1426 * Returns: whether the downstream facing port can convert RGB->YCbCr for a given 1427 * colorspace. 1428 */ 1429 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1430 const u8 port_cap[4], 1431 u8 color_spc) 1432 { 1433 if (!drm_dp_is_branch(dpcd)) 1434 return false; 1435 1436 if (dpcd[DP_DPCD_REV] < 0x13) 1437 return false; 1438 1439 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1440 case DP_DS_PORT_TYPE_HDMI: 1441 if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0) 1442 return false; 1443 1444 return port_cap[3] & color_spc; 1445 default: 1446 return false; 1447 } 1448 } 1449 EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion); 1450 1451 /** 1452 * drm_dp_downstream_mode() - return a mode for downstream facing port 1453 * @dev: DRM device 1454 * @dpcd: DisplayPort configuration data 1455 * @port_cap: port capabilities 1456 * 1457 * Provides a suitable mode for downstream facing ports without EDID. 1458 * 1459 * Returns: A new drm_display_mode on success or NULL on failure 1460 */ 1461 struct drm_display_mode * 1462 drm_dp_downstream_mode(struct drm_device *dev, 1463 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1464 const u8 port_cap[4]) 1465 1466 { 1467 u8 vic; 1468 1469 if (!drm_dp_is_branch(dpcd)) 1470 return NULL; 1471 1472 if (dpcd[DP_DPCD_REV] < 0x11) 1473 return NULL; 1474 1475 switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) { 1476 case DP_DS_PORT_TYPE_NON_EDID: 1477 switch (port_cap[0] & DP_DS_NON_EDID_MASK) { 1478 case DP_DS_NON_EDID_720x480i_60: 1479 vic = 6; 1480 break; 1481 case DP_DS_NON_EDID_720x480i_50: 1482 vic = 21; 1483 break; 1484 case DP_DS_NON_EDID_1920x1080i_60: 1485 vic = 5; 1486 break; 1487 case DP_DS_NON_EDID_1920x1080i_50: 1488 vic = 20; 1489 break; 1490 case DP_DS_NON_EDID_1280x720_60: 1491 vic = 4; 1492 break; 1493 case DP_DS_NON_EDID_1280x720_50: 1494 vic = 19; 1495 break; 1496 default: 1497 return NULL; 1498 } 1499 return drm_display_mode_from_cea_vic(dev, vic); 1500 default: 1501 return NULL; 1502 } 1503 } 1504 EXPORT_SYMBOL(drm_dp_downstream_mode); 1505 1506 /** 1507 * drm_dp_downstream_id() - identify branch device 1508 * @aux: DisplayPort AUX channel 1509 * @id: DisplayPort branch device id 1510 * 1511 * Returns branch device id on success or NULL on failure 1512 */ 1513 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6]) 1514 { 1515 return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6); 1516 } 1517 EXPORT_SYMBOL(drm_dp_downstream_id); 1518 1519 /** 1520 * drm_dp_downstream_debug() - debug DP branch devices 1521 * @m: pointer for debugfs file 1522 * @dpcd: DisplayPort configuration data 1523 * @port_cap: port capabilities 1524 * @drm_edid: EDID 1525 * @aux: DisplayPort AUX channel 1526 * 1527 */ 1528 void drm_dp_downstream_debug(struct seq_file *m, 1529 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1530 const u8 port_cap[4], 1531 const struct drm_edid *drm_edid, 1532 struct drm_dp_aux *aux) 1533 { 1534 bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 1535 DP_DETAILED_CAP_INFO_AVAILABLE; 1536 int clk; 1537 int bpc; 1538 char id[7]; 1539 int len; 1540 uint8_t rev[2]; 1541 int type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 1542 bool branch_device = drm_dp_is_branch(dpcd); 1543 1544 seq_printf(m, "\tDP branch device present: %s\n", 1545 str_yes_no(branch_device)); 1546 1547 if (!branch_device) 1548 return; 1549 1550 switch (type) { 1551 case DP_DS_PORT_TYPE_DP: 1552 seq_puts(m, "\t\tType: DisplayPort\n"); 1553 break; 1554 case DP_DS_PORT_TYPE_VGA: 1555 seq_puts(m, "\t\tType: VGA\n"); 1556 break; 1557 case DP_DS_PORT_TYPE_DVI: 1558 seq_puts(m, "\t\tType: DVI\n"); 1559 break; 1560 case DP_DS_PORT_TYPE_HDMI: 1561 seq_puts(m, "\t\tType: HDMI\n"); 1562 break; 1563 case DP_DS_PORT_TYPE_NON_EDID: 1564 seq_puts(m, "\t\tType: others without EDID support\n"); 1565 break; 1566 case DP_DS_PORT_TYPE_DP_DUALMODE: 1567 seq_puts(m, "\t\tType: DP++\n"); 1568 break; 1569 case DP_DS_PORT_TYPE_WIRELESS: 1570 seq_puts(m, "\t\tType: Wireless\n"); 1571 break; 1572 default: 1573 seq_puts(m, "\t\tType: N/A\n"); 1574 } 1575 1576 memset(id, 0, sizeof(id)); 1577 drm_dp_downstream_id(aux, id); 1578 seq_printf(m, "\t\tID: %s\n", id); 1579 1580 len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1); 1581 if (len > 0) 1582 seq_printf(m, "\t\tHW: %d.%d\n", 1583 (rev[0] & 0xf0) >> 4, rev[0] & 0xf); 1584 1585 len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2); 1586 if (len > 0) 1587 seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]); 1588 1589 if (detailed_cap_info) { 1590 clk = drm_dp_downstream_max_dotclock(dpcd, port_cap); 1591 if (clk > 0) 1592 seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk); 1593 1594 clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, drm_edid); 1595 if (clk > 0) 1596 seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk); 1597 1598 clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, drm_edid); 1599 if (clk > 0) 1600 seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk); 1601 1602 bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, drm_edid); 1603 1604 if (bpc > 0) 1605 seq_printf(m, "\t\tMax bpc: %d\n", bpc); 1606 } 1607 } 1608 EXPORT_SYMBOL(drm_dp_downstream_debug); 1609 1610 /** 1611 * drm_dp_subconnector_type() - get DP branch device type 1612 * @dpcd: DisplayPort configuration data 1613 * @port_cap: port capabilities 1614 */ 1615 enum drm_mode_subconnector 1616 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1617 const u8 port_cap[4]) 1618 { 1619 int type; 1620 if (!drm_dp_is_branch(dpcd)) 1621 return DRM_MODE_SUBCONNECTOR_Native; 1622 /* DP 1.0 approach */ 1623 if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) { 1624 type = dpcd[DP_DOWNSTREAMPORT_PRESENT] & 1625 DP_DWN_STRM_PORT_TYPE_MASK; 1626 1627 switch (type) { 1628 case DP_DWN_STRM_PORT_TYPE_TMDS: 1629 /* Can be HDMI or DVI-D, DVI-D is a safer option */ 1630 return DRM_MODE_SUBCONNECTOR_DVID; 1631 case DP_DWN_STRM_PORT_TYPE_ANALOG: 1632 /* Can be VGA or DVI-A, VGA is more popular */ 1633 return DRM_MODE_SUBCONNECTOR_VGA; 1634 case DP_DWN_STRM_PORT_TYPE_DP: 1635 return DRM_MODE_SUBCONNECTOR_DisplayPort; 1636 case DP_DWN_STRM_PORT_TYPE_OTHER: 1637 default: 1638 return DRM_MODE_SUBCONNECTOR_Unknown; 1639 } 1640 } 1641 type = port_cap[0] & DP_DS_PORT_TYPE_MASK; 1642 1643 switch (type) { 1644 case DP_DS_PORT_TYPE_DP: 1645 case DP_DS_PORT_TYPE_DP_DUALMODE: 1646 return DRM_MODE_SUBCONNECTOR_DisplayPort; 1647 case DP_DS_PORT_TYPE_VGA: 1648 return DRM_MODE_SUBCONNECTOR_VGA; 1649 case DP_DS_PORT_TYPE_DVI: 1650 return DRM_MODE_SUBCONNECTOR_DVID; 1651 case DP_DS_PORT_TYPE_HDMI: 1652 return DRM_MODE_SUBCONNECTOR_HDMIA; 1653 case DP_DS_PORT_TYPE_WIRELESS: 1654 return DRM_MODE_SUBCONNECTOR_Wireless; 1655 case DP_DS_PORT_TYPE_NON_EDID: 1656 default: 1657 return DRM_MODE_SUBCONNECTOR_Unknown; 1658 } 1659 } 1660 EXPORT_SYMBOL(drm_dp_subconnector_type); 1661 1662 /** 1663 * drm_dp_set_subconnector_property - set subconnector for DP connector 1664 * @connector: connector to set property on 1665 * @status: connector status 1666 * @dpcd: DisplayPort configuration data 1667 * @port_cap: port capabilities 1668 * 1669 * Called by a driver on every detect event. 1670 */ 1671 void drm_dp_set_subconnector_property(struct drm_connector *connector, 1672 enum drm_connector_status status, 1673 const u8 *dpcd, 1674 const u8 port_cap[4]) 1675 { 1676 enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown; 1677 1678 if (status == connector_status_connected) 1679 subconnector = drm_dp_subconnector_type(dpcd, port_cap); 1680 drm_object_property_set_value(&connector->base, 1681 connector->dev->mode_config.dp_subconnector_property, 1682 subconnector); 1683 } 1684 EXPORT_SYMBOL(drm_dp_set_subconnector_property); 1685 1686 /** 1687 * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink 1688 * count 1689 * @connector: The DRM connector to check 1690 * @dpcd: A cached copy of the connector's DPCD RX capabilities 1691 * @desc: A cached copy of the connector's DP descriptor 1692 * 1693 * See also: drm_dp_read_sink_count() 1694 * 1695 * Returns: %True if the (e)DP connector has a valid sink count that should 1696 * be probed, %false otherwise. 1697 */ 1698 bool drm_dp_read_sink_count_cap(struct drm_connector *connector, 1699 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 1700 const struct drm_dp_desc *desc) 1701 { 1702 /* Some eDP panels don't set a valid value for the sink count */ 1703 return connector->connector_type != DRM_MODE_CONNECTOR_eDP && 1704 dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 && 1705 dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && 1706 !drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT); 1707 } 1708 EXPORT_SYMBOL(drm_dp_read_sink_count_cap); 1709 1710 /** 1711 * drm_dp_read_sink_count() - Retrieve the sink count for a given sink 1712 * @aux: The DP AUX channel to use 1713 * 1714 * See also: drm_dp_read_sink_count_cap() 1715 * 1716 * Returns: The current sink count reported by @aux, or a negative error code 1717 * otherwise. 1718 */ 1719 int drm_dp_read_sink_count(struct drm_dp_aux *aux) 1720 { 1721 u8 count; 1722 int ret; 1723 1724 ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count); 1725 if (ret < 0) 1726 return ret; 1727 if (ret != 1) 1728 return -EIO; 1729 1730 return DP_GET_SINK_COUNT(count); 1731 } 1732 EXPORT_SYMBOL(drm_dp_read_sink_count); 1733 1734 /* 1735 * I2C-over-AUX implementation 1736 */ 1737 1738 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter) 1739 { 1740 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | 1741 I2C_FUNC_SMBUS_READ_BLOCK_DATA | 1742 I2C_FUNC_SMBUS_BLOCK_PROC_CALL | 1743 I2C_FUNC_10BIT_ADDR; 1744 } 1745 1746 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg) 1747 { 1748 /* 1749 * In case of i2c defer or short i2c ack reply to a write, 1750 * we need to switch to WRITE_STATUS_UPDATE to drain the 1751 * rest of the message 1752 */ 1753 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) { 1754 msg->request &= DP_AUX_I2C_MOT; 1755 msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE; 1756 } 1757 } 1758 1759 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */ 1760 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */ 1761 #define AUX_STOP_LEN 4 1762 #define AUX_CMD_LEN 4 1763 #define AUX_ADDRESS_LEN 20 1764 #define AUX_REPLY_PAD_LEN 4 1765 #define AUX_LENGTH_LEN 8 1766 1767 /* 1768 * Calculate the duration of the AUX request/reply in usec. Gives the 1769 * "best" case estimate, ie. successful while as short as possible. 1770 */ 1771 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg) 1772 { 1773 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 1774 AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN; 1775 1776 if ((msg->request & DP_AUX_I2C_READ) == 0) 1777 len += msg->size * 8; 1778 1779 return len; 1780 } 1781 1782 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg) 1783 { 1784 int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN + 1785 AUX_CMD_LEN + AUX_REPLY_PAD_LEN; 1786 1787 /* 1788 * For read we expect what was asked. For writes there will 1789 * be 0 or 1 data bytes. Assume 0 for the "best" case. 1790 */ 1791 if (msg->request & DP_AUX_I2C_READ) 1792 len += msg->size * 8; 1793 1794 return len; 1795 } 1796 1797 #define I2C_START_LEN 1 1798 #define I2C_STOP_LEN 1 1799 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */ 1800 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */ 1801 1802 /* 1803 * Calculate the length of the i2c transfer in usec, assuming 1804 * the i2c bus speed is as specified. Gives the "worst" 1805 * case estimate, ie. successful while as long as possible. 1806 * Doesn't account the "MOT" bit, and instead assumes each 1807 * message includes a START, ADDRESS and STOP. Neither does it 1808 * account for additional random variables such as clock stretching. 1809 */ 1810 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg, 1811 int i2c_speed_khz) 1812 { 1813 /* AUX bitrate is 1MHz, i2c bitrate as specified */ 1814 return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN + 1815 msg->size * I2C_DATA_LEN + 1816 I2C_STOP_LEN) * 1000, i2c_speed_khz); 1817 } 1818 1819 /* 1820 * Determine how many retries should be attempted to successfully transfer 1821 * the specified message, based on the estimated durations of the 1822 * i2c and AUX transfers. 1823 */ 1824 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg, 1825 int i2c_speed_khz) 1826 { 1827 int aux_time_us = drm_dp_aux_req_duration(msg) + 1828 drm_dp_aux_reply_duration(msg); 1829 int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz); 1830 1831 return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL); 1832 } 1833 1834 /* 1835 * FIXME currently assumes 10 kHz as some real world devices seem 1836 * to require it. We should query/set the speed via DPCD if supported. 1837 */ 1838 static int dp_aux_i2c_speed_khz __read_mostly = 10; 1839 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644); 1840 MODULE_PARM_DESC(dp_aux_i2c_speed_khz, 1841 "Assumed speed of the i2c bus in kHz, (1-400, default 10)"); 1842 1843 /* 1844 * Transfer a single I2C-over-AUX message and handle various error conditions, 1845 * retrying the transaction as appropriate. It is assumed that the 1846 * &drm_dp_aux.transfer function does not modify anything in the msg other than the 1847 * reply field. 1848 * 1849 * Returns bytes transferred on success, or a negative error code on failure. 1850 */ 1851 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1852 { 1853 unsigned int retry, defer_i2c; 1854 int ret; 1855 /* 1856 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device 1857 * is required to retry at least seven times upon receiving AUX_DEFER 1858 * before giving up the AUX transaction. 1859 * 1860 * We also try to account for the i2c bus speed. 1861 */ 1862 int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz)); 1863 1864 for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) { 1865 ret = aux->transfer(aux, msg); 1866 if (ret < 0) { 1867 if (ret == -EBUSY) 1868 continue; 1869 1870 /* 1871 * While timeouts can be errors, they're usually normal 1872 * behavior (for instance, when a driver tries to 1873 * communicate with a non-existent DisplayPort device). 1874 * Avoid spamming the kernel log with timeout errors. 1875 */ 1876 if (ret == -ETIMEDOUT) 1877 drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n", 1878 aux->name); 1879 else 1880 drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n", 1881 aux->name, ret); 1882 return ret; 1883 } 1884 1885 1886 switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) { 1887 case DP_AUX_NATIVE_REPLY_ACK: 1888 /* 1889 * For I2C-over-AUX transactions this isn't enough, we 1890 * need to check for the I2C ACK reply. 1891 */ 1892 break; 1893 1894 case DP_AUX_NATIVE_REPLY_NACK: 1895 drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n", 1896 aux->name, ret, msg->size); 1897 return -EREMOTEIO; 1898 1899 case DP_AUX_NATIVE_REPLY_DEFER: 1900 drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name); 1901 /* 1902 * We could check for I2C bit rate capabilities and if 1903 * available adjust this interval. We could also be 1904 * more careful with DP-to-legacy adapters where a 1905 * long legacy cable may force very low I2C bit rates. 1906 * 1907 * For now just defer for long enough to hopefully be 1908 * safe for all use-cases. 1909 */ 1910 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 1911 continue; 1912 1913 default: 1914 drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n", 1915 aux->name, msg->reply); 1916 return -EREMOTEIO; 1917 } 1918 1919 switch (msg->reply & DP_AUX_I2C_REPLY_MASK) { 1920 case DP_AUX_I2C_REPLY_ACK: 1921 /* 1922 * Both native ACK and I2C ACK replies received. We 1923 * can assume the transfer was successful. 1924 */ 1925 if (ret != msg->size) 1926 drm_dp_i2c_msg_write_status_update(msg); 1927 return ret; 1928 1929 case DP_AUX_I2C_REPLY_NACK: 1930 drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n", 1931 aux->name, ret, msg->size); 1932 aux->i2c_nack_count++; 1933 return -EREMOTEIO; 1934 1935 case DP_AUX_I2C_REPLY_DEFER: 1936 drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name); 1937 /* DP Compliance Test 4.2.2.5 Requirement: 1938 * Must have at least 7 retries for I2C defers on the 1939 * transaction to pass this test 1940 */ 1941 aux->i2c_defer_count++; 1942 if (defer_i2c < 7) 1943 defer_i2c++; 1944 usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100); 1945 drm_dp_i2c_msg_write_status_update(msg); 1946 1947 continue; 1948 1949 default: 1950 drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n", 1951 aux->name, msg->reply); 1952 return -EREMOTEIO; 1953 } 1954 } 1955 1956 drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name); 1957 return -EREMOTEIO; 1958 } 1959 1960 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg, 1961 const struct i2c_msg *i2c_msg) 1962 { 1963 msg->request = (i2c_msg->flags & I2C_M_RD) ? 1964 DP_AUX_I2C_READ : DP_AUX_I2C_WRITE; 1965 if (!(i2c_msg->flags & I2C_M_STOP)) 1966 msg->request |= DP_AUX_I2C_MOT; 1967 } 1968 1969 /* 1970 * Keep retrying drm_dp_i2c_do_msg until all data has been transferred. 1971 * 1972 * Returns an error code on failure, or a recommended transfer size on success. 1973 */ 1974 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg) 1975 { 1976 int err, ret = orig_msg->size; 1977 struct drm_dp_aux_msg msg = *orig_msg; 1978 1979 while (msg.size > 0) { 1980 err = drm_dp_i2c_do_msg(aux, &msg); 1981 if (err <= 0) 1982 return err == 0 ? -EPROTO : err; 1983 1984 if (err < msg.size && err < ret) { 1985 drm_dbg_kms(aux->drm_dev, 1986 "%s: Partial I2C reply: requested %zu bytes got %d bytes\n", 1987 aux->name, msg.size, err); 1988 ret = err; 1989 } 1990 1991 msg.size -= err; 1992 msg.buffer += err; 1993 } 1994 1995 return ret; 1996 } 1997 1998 /* 1999 * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX 2000 * packets to be as large as possible. If not, the I2C transactions never 2001 * succeed. Hence the default is maximum. 2002 */ 2003 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES; 2004 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644); 2005 MODULE_PARM_DESC(dp_aux_i2c_transfer_size, 2006 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)"); 2007 2008 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs, 2009 int num) 2010 { 2011 struct drm_dp_aux *aux = adapter->algo_data; 2012 unsigned int i, j; 2013 unsigned transfer_size; 2014 struct drm_dp_aux_msg msg; 2015 int err = 0; 2016 2017 if (aux->powered_down) 2018 return -EBUSY; 2019 2020 dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES); 2021 2022 memset(&msg, 0, sizeof(msg)); 2023 2024 for (i = 0; i < num; i++) { 2025 msg.address = msgs[i].addr; 2026 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 2027 /* Send a bare address packet to start the transaction. 2028 * Zero sized messages specify an address only (bare 2029 * address) transaction. 2030 */ 2031 msg.buffer = NULL; 2032 msg.size = 0; 2033 err = drm_dp_i2c_do_msg(aux, &msg); 2034 2035 /* 2036 * Reset msg.request in case in case it got 2037 * changed into a WRITE_STATUS_UPDATE. 2038 */ 2039 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 2040 2041 if (err < 0) 2042 break; 2043 /* We want each transaction to be as large as possible, but 2044 * we'll go to smaller sizes if the hardware gives us a 2045 * short reply. 2046 */ 2047 transfer_size = dp_aux_i2c_transfer_size; 2048 for (j = 0; j < msgs[i].len; j += msg.size) { 2049 msg.buffer = msgs[i].buf + j; 2050 msg.size = min(transfer_size, msgs[i].len - j); 2051 2052 err = drm_dp_i2c_drain_msg(aux, &msg); 2053 2054 /* 2055 * Reset msg.request in case in case it got 2056 * changed into a WRITE_STATUS_UPDATE. 2057 */ 2058 drm_dp_i2c_msg_set_request(&msg, &msgs[i]); 2059 2060 if (err < 0) 2061 break; 2062 transfer_size = err; 2063 } 2064 if (err < 0) 2065 break; 2066 } 2067 if (err >= 0) 2068 err = num; 2069 /* Send a bare address packet to close out the transaction. 2070 * Zero sized messages specify an address only (bare 2071 * address) transaction. 2072 */ 2073 msg.request &= ~DP_AUX_I2C_MOT; 2074 msg.buffer = NULL; 2075 msg.size = 0; 2076 (void)drm_dp_i2c_do_msg(aux, &msg); 2077 2078 return err; 2079 } 2080 2081 static const struct i2c_algorithm drm_dp_i2c_algo = { 2082 .functionality = drm_dp_i2c_functionality, 2083 .master_xfer = drm_dp_i2c_xfer, 2084 }; 2085 2086 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c) 2087 { 2088 return container_of(i2c, struct drm_dp_aux, ddc); 2089 } 2090 2091 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags) 2092 { 2093 mutex_lock(&i2c_to_aux(i2c)->hw_mutex); 2094 } 2095 2096 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags) 2097 { 2098 return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex); 2099 } 2100 2101 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags) 2102 { 2103 mutex_unlock(&i2c_to_aux(i2c)->hw_mutex); 2104 } 2105 2106 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = { 2107 .lock_bus = lock_bus, 2108 .trylock_bus = trylock_bus, 2109 .unlock_bus = unlock_bus, 2110 }; 2111 2112 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc) 2113 { 2114 u8 buf, count; 2115 int ret; 2116 2117 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 2118 if (ret < 0) 2119 return ret; 2120 2121 WARN_ON(!(buf & DP_TEST_SINK_START)); 2122 2123 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf); 2124 if (ret < 0) 2125 return ret; 2126 2127 count = buf & DP_TEST_COUNT_MASK; 2128 if (count == aux->crc_count) 2129 return -EAGAIN; /* No CRC yet */ 2130 2131 aux->crc_count = count; 2132 2133 /* 2134 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes 2135 * per component (RGB or CrYCb). 2136 */ 2137 ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6); 2138 if (ret < 0) 2139 return ret; 2140 2141 return 0; 2142 } 2143 2144 static void drm_dp_aux_crc_work(struct work_struct *work) 2145 { 2146 struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux, 2147 crc_work); 2148 struct drm_crtc *crtc; 2149 u8 crc_bytes[6]; 2150 uint32_t crcs[3]; 2151 int ret; 2152 2153 if (WARN_ON(!aux->crtc)) 2154 return; 2155 2156 crtc = aux->crtc; 2157 while (crtc->crc.opened) { 2158 drm_crtc_wait_one_vblank(crtc); 2159 if (!crtc->crc.opened) 2160 break; 2161 2162 ret = drm_dp_aux_get_crc(aux, crc_bytes); 2163 if (ret == -EAGAIN) { 2164 usleep_range(1000, 2000); 2165 ret = drm_dp_aux_get_crc(aux, crc_bytes); 2166 } 2167 2168 if (ret == -EAGAIN) { 2169 drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n", 2170 aux->name, ret); 2171 continue; 2172 } else if (ret) { 2173 drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret); 2174 continue; 2175 } 2176 2177 crcs[0] = crc_bytes[0] | crc_bytes[1] << 8; 2178 crcs[1] = crc_bytes[2] | crc_bytes[3] << 8; 2179 crcs[2] = crc_bytes[4] | crc_bytes[5] << 8; 2180 drm_crtc_add_crc_entry(crtc, false, 0, crcs); 2181 } 2182 } 2183 2184 /** 2185 * drm_dp_remote_aux_init() - minimally initialise a remote aux channel 2186 * @aux: DisplayPort AUX channel 2187 * 2188 * Used for remote aux channel in general. Merely initialize the crc work 2189 * struct. 2190 */ 2191 void drm_dp_remote_aux_init(struct drm_dp_aux *aux) 2192 { 2193 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 2194 } 2195 EXPORT_SYMBOL(drm_dp_remote_aux_init); 2196 2197 /** 2198 * drm_dp_aux_init() - minimally initialise an aux channel 2199 * @aux: DisplayPort AUX channel 2200 * 2201 * If you need to use the drm_dp_aux's i2c adapter prior to registering it with 2202 * the outside world, call drm_dp_aux_init() first. For drivers which are 2203 * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a 2204 * &drm_connector), you must still call drm_dp_aux_register() once the connector 2205 * has been registered to allow userspace access to the auxiliary DP channel. 2206 * Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as 2207 * early as possible so that the &drm_device that corresponds to the AUX adapter 2208 * may be mentioned in debugging output from the DRM DP helpers. 2209 * 2210 * For devices which use a separate platform device for their AUX adapters, this 2211 * may be called as early as required by the driver. 2212 * 2213 */ 2214 void drm_dp_aux_init(struct drm_dp_aux *aux) 2215 { 2216 mutex_init(&aux->hw_mutex); 2217 mutex_init(&aux->cec.lock); 2218 INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work); 2219 2220 aux->ddc.algo = &drm_dp_i2c_algo; 2221 aux->ddc.algo_data = aux; 2222 aux->ddc.retries = 3; 2223 2224 aux->ddc.lock_ops = &drm_dp_i2c_lock_ops; 2225 } 2226 EXPORT_SYMBOL(drm_dp_aux_init); 2227 2228 /** 2229 * drm_dp_aux_register() - initialise and register aux channel 2230 * @aux: DisplayPort AUX channel 2231 * 2232 * Automatically calls drm_dp_aux_init() if this hasn't been done yet. This 2233 * should only be called once the parent of @aux, &drm_dp_aux.dev, is 2234 * initialized. For devices which are grandparents of their AUX channels, 2235 * &drm_dp_aux.dev will typically be the &drm_connector &device which 2236 * corresponds to @aux. For these devices, it's advised to call 2237 * drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to 2238 * call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister. 2239 * Functions which don't follow this will likely Oops when 2240 * %CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV is enabled. 2241 * 2242 * For devices where the AUX channel is a device that exists independently of 2243 * the &drm_device that uses it, such as SoCs and bridge devices, it is 2244 * recommended to call drm_dp_aux_register() after a &drm_device has been 2245 * assigned to &drm_dp_aux.drm_dev, and likewise to call 2246 * drm_dp_aux_unregister() once the &drm_device should no longer be associated 2247 * with the AUX channel (e.g. on bridge detach). 2248 * 2249 * Drivers which need to use the aux channel before either of the two points 2250 * mentioned above need to call drm_dp_aux_init() in order to use the AUX 2251 * channel before registration. 2252 * 2253 * Returns 0 on success or a negative error code on failure. 2254 */ 2255 int drm_dp_aux_register(struct drm_dp_aux *aux) 2256 { 2257 int ret; 2258 2259 WARN_ON_ONCE(!aux->drm_dev); 2260 2261 if (!aux->ddc.algo) 2262 drm_dp_aux_init(aux); 2263 2264 aux->ddc.owner = THIS_MODULE; 2265 aux->ddc.dev.parent = aux->dev; 2266 2267 strscpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev), 2268 sizeof(aux->ddc.name)); 2269 2270 ret = drm_dp_aux_register_devnode(aux); 2271 if (ret) 2272 return ret; 2273 2274 ret = i2c_add_adapter(&aux->ddc); 2275 if (ret) { 2276 drm_dp_aux_unregister_devnode(aux); 2277 return ret; 2278 } 2279 2280 return 0; 2281 } 2282 EXPORT_SYMBOL(drm_dp_aux_register); 2283 2284 /** 2285 * drm_dp_aux_unregister() - unregister an AUX adapter 2286 * @aux: DisplayPort AUX channel 2287 */ 2288 void drm_dp_aux_unregister(struct drm_dp_aux *aux) 2289 { 2290 drm_dp_aux_unregister_devnode(aux); 2291 i2c_del_adapter(&aux->ddc); 2292 } 2293 EXPORT_SYMBOL(drm_dp_aux_unregister); 2294 2295 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x) 2296 2297 /** 2298 * drm_dp_psr_setup_time() - PSR setup in time usec 2299 * @psr_cap: PSR capabilities from DPCD 2300 * 2301 * Returns: 2302 * PSR setup time for the panel in microseconds, negative 2303 * error code on failure. 2304 */ 2305 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE]) 2306 { 2307 static const u16 psr_setup_time_us[] = { 2308 PSR_SETUP_TIME(330), 2309 PSR_SETUP_TIME(275), 2310 PSR_SETUP_TIME(220), 2311 PSR_SETUP_TIME(165), 2312 PSR_SETUP_TIME(110), 2313 PSR_SETUP_TIME(55), 2314 PSR_SETUP_TIME(0), 2315 }; 2316 int i; 2317 2318 i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT; 2319 if (i >= ARRAY_SIZE(psr_setup_time_us)) 2320 return -EINVAL; 2321 2322 return psr_setup_time_us[i]; 2323 } 2324 EXPORT_SYMBOL(drm_dp_psr_setup_time); 2325 2326 #undef PSR_SETUP_TIME 2327 2328 /** 2329 * drm_dp_start_crc() - start capture of frame CRCs 2330 * @aux: DisplayPort AUX channel 2331 * @crtc: CRTC displaying the frames whose CRCs are to be captured 2332 * 2333 * Returns 0 on success or a negative error code on failure. 2334 */ 2335 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc) 2336 { 2337 u8 buf; 2338 int ret; 2339 2340 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 2341 if (ret < 0) 2342 return ret; 2343 2344 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START); 2345 if (ret < 0) 2346 return ret; 2347 2348 aux->crc_count = 0; 2349 aux->crtc = crtc; 2350 schedule_work(&aux->crc_work); 2351 2352 return 0; 2353 } 2354 EXPORT_SYMBOL(drm_dp_start_crc); 2355 2356 /** 2357 * drm_dp_stop_crc() - stop capture of frame CRCs 2358 * @aux: DisplayPort AUX channel 2359 * 2360 * Returns 0 on success or a negative error code on failure. 2361 */ 2362 int drm_dp_stop_crc(struct drm_dp_aux *aux) 2363 { 2364 u8 buf; 2365 int ret; 2366 2367 ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf); 2368 if (ret < 0) 2369 return ret; 2370 2371 ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START); 2372 if (ret < 0) 2373 return ret; 2374 2375 flush_work(&aux->crc_work); 2376 aux->crtc = NULL; 2377 2378 return 0; 2379 } 2380 EXPORT_SYMBOL(drm_dp_stop_crc); 2381 2382 struct dpcd_quirk { 2383 u8 oui[3]; 2384 u8 device_id[6]; 2385 bool is_branch; 2386 u32 quirks; 2387 }; 2388 2389 #define OUI(first, second, third) { (first), (second), (third) } 2390 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \ 2391 { (first), (second), (third), (fourth), (fifth), (sixth) } 2392 2393 #define DEVICE_ID_ANY DEVICE_ID(0, 0, 0, 0, 0, 0) 2394 2395 static const struct dpcd_quirk dpcd_quirk_list[] = { 2396 /* Analogix 7737 needs reduced M and N at HBR2 link rates */ 2397 { OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 2398 /* LG LP140WF6-SPM1 eDP panel */ 2399 { OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) }, 2400 /* Apple panels need some additional handling to support PSR */ 2401 { OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) }, 2402 /* CH7511 seems to leave SINK_COUNT zeroed */ 2403 { OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) }, 2404 /* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */ 2405 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) }, 2406 /* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */ 2407 { OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) }, 2408 /* MediaTek panels (at least in U3224KBA) require DSC for modes with a short HBLANK on UHBR links. */ 2409 { OUI(0x00, 0x0C, 0xE7), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) }, 2410 /* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */ 2411 { OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) }, 2412 }; 2413 2414 #undef OUI 2415 2416 /* 2417 * Get a bit mask of DPCD quirks for the sink/branch device identified by 2418 * ident. The quirk data is shared but it's up to the drivers to act on the 2419 * data. 2420 * 2421 * For now, only the OUI (first three bytes) is used, but this may be extended 2422 * to device identification string and hardware/firmware revisions later. 2423 */ 2424 static u32 2425 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch) 2426 { 2427 const struct dpcd_quirk *quirk; 2428 u32 quirks = 0; 2429 int i; 2430 u8 any_device[] = DEVICE_ID_ANY; 2431 2432 for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) { 2433 quirk = &dpcd_quirk_list[i]; 2434 2435 if (quirk->is_branch != is_branch) 2436 continue; 2437 2438 if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0) 2439 continue; 2440 2441 if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 && 2442 memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0) 2443 continue; 2444 2445 quirks |= quirk->quirks; 2446 } 2447 2448 return quirks; 2449 } 2450 2451 #undef DEVICE_ID_ANY 2452 #undef DEVICE_ID 2453 2454 static int drm_dp_read_ident(struct drm_dp_aux *aux, unsigned int offset, 2455 struct drm_dp_dpcd_ident *ident) 2456 { 2457 int ret; 2458 2459 ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident)); 2460 2461 return ret < 0 ? ret : 0; 2462 } 2463 2464 static void drm_dp_dump_desc(struct drm_dp_aux *aux, 2465 const char *device_name, const struct drm_dp_desc *desc) 2466 { 2467 const struct drm_dp_dpcd_ident *ident = &desc->ident; 2468 2469 drm_dbg_kms(aux->drm_dev, 2470 "%s: %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n", 2471 aux->name, device_name, 2472 (int)sizeof(ident->oui), ident->oui, 2473 (int)strnlen(ident->device_id, sizeof(ident->device_id)), ident->device_id, 2474 ident->hw_rev >> 4, ident->hw_rev & 0xf, 2475 ident->sw_major_rev, ident->sw_minor_rev, 2476 desc->quirks); 2477 } 2478 2479 /** 2480 * drm_dp_read_desc - read sink/branch descriptor from DPCD 2481 * @aux: DisplayPort AUX channel 2482 * @desc: Device descriptor to fill from DPCD 2483 * @is_branch: true for branch devices, false for sink devices 2484 * 2485 * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the 2486 * identification. 2487 * 2488 * Returns 0 on success or a negative error code on failure. 2489 */ 2490 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc, 2491 bool is_branch) 2492 { 2493 struct drm_dp_dpcd_ident *ident = &desc->ident; 2494 unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI; 2495 int ret; 2496 2497 ret = drm_dp_read_ident(aux, offset, ident); 2498 if (ret < 0) 2499 return ret; 2500 2501 desc->quirks = drm_dp_get_quirks(ident, is_branch); 2502 2503 drm_dp_dump_desc(aux, is_branch ? "DP branch" : "DP sink", desc); 2504 2505 return 0; 2506 } 2507 EXPORT_SYMBOL(drm_dp_read_desc); 2508 2509 /** 2510 * drm_dp_dump_lttpr_desc - read and dump the DPCD descriptor for an LTTPR PHY 2511 * @aux: DisplayPort AUX channel 2512 * @dp_phy: LTTPR PHY instance 2513 * 2514 * Read the DPCD LTTPR PHY descriptor for @dp_phy and print a debug message 2515 * with its details to dmesg. 2516 * 2517 * Returns 0 on success or a negative error code on failure. 2518 */ 2519 int drm_dp_dump_lttpr_desc(struct drm_dp_aux *aux, enum drm_dp_phy dp_phy) 2520 { 2521 struct drm_dp_desc desc = {}; 2522 int ret; 2523 2524 if (drm_WARN_ON(aux->drm_dev, dp_phy < DP_PHY_LTTPR1 || dp_phy > DP_MAX_LTTPR_COUNT)) 2525 return -EINVAL; 2526 2527 ret = drm_dp_read_ident(aux, DP_OUI_PHY_REPEATER(dp_phy), &desc.ident); 2528 if (ret < 0) 2529 return ret; 2530 2531 drm_dp_dump_desc(aux, drm_dp_phy_name(dp_phy), &desc); 2532 2533 return 0; 2534 } 2535 EXPORT_SYMBOL(drm_dp_dump_lttpr_desc); 2536 2537 /** 2538 * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment 2539 * @dsc_dpcd: DSC capabilities from DPCD 2540 * 2541 * Returns the bpp precision supported by the DP sink. 2542 */ 2543 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 2544 { 2545 u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; 2546 2547 switch (bpp_increment_dpcd) { 2548 case DP_DSC_BITS_PER_PIXEL_1_16: 2549 return 16; 2550 case DP_DSC_BITS_PER_PIXEL_1_8: 2551 return 8; 2552 case DP_DSC_BITS_PER_PIXEL_1_4: 2553 return 4; 2554 case DP_DSC_BITS_PER_PIXEL_1_2: 2555 return 2; 2556 case DP_DSC_BITS_PER_PIXEL_1_1: 2557 return 1; 2558 } 2559 2560 return 0; 2561 } 2562 EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr); 2563 2564 /** 2565 * drm_dp_dsc_sink_max_slice_count() - Get the max slice count 2566 * supported by the DSC sink. 2567 * @dsc_dpcd: DSC capabilities from DPCD 2568 * @is_edp: true if its eDP, false for DP 2569 * 2570 * Read the slice capabilities DPCD register from DSC sink to get 2571 * the maximum slice count supported. This is used to populate 2572 * the DSC parameters in the &struct drm_dsc_config by the driver. 2573 * Driver creates an infoframe using these parameters to populate 2574 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2575 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2576 * 2577 * Returns: 2578 * Maximum slice count supported by DSC sink or 0 its invalid 2579 */ 2580 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 2581 bool is_edp) 2582 { 2583 u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT]; 2584 2585 if (is_edp) { 2586 /* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */ 2587 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2588 return 4; 2589 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2590 return 2; 2591 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2592 return 1; 2593 } else { 2594 /* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */ 2595 u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT]; 2596 2597 if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK) 2598 return 24; 2599 if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK) 2600 return 20; 2601 if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK) 2602 return 16; 2603 if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK) 2604 return 12; 2605 if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK) 2606 return 10; 2607 if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK) 2608 return 8; 2609 if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK) 2610 return 6; 2611 if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK) 2612 return 4; 2613 if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK) 2614 return 2; 2615 if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK) 2616 return 1; 2617 } 2618 2619 return 0; 2620 } 2621 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); 2622 2623 /** 2624 * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits 2625 * @dsc_dpcd: DSC capabilities from DPCD 2626 * 2627 * Read the DSC DPCD register to parse the line buffer depth in bits which is 2628 * number of bits of precision within the decoder line buffer supported by 2629 * the DSC sink. This is used to populate the DSC parameters in the 2630 * &struct drm_dsc_config by the driver. 2631 * Driver creates an infoframe using these parameters to populate 2632 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2633 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2634 * 2635 * Returns: 2636 * Line buffer depth supported by DSC panel or 0 its invalid 2637 */ 2638 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) 2639 { 2640 u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT]; 2641 2642 switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) { 2643 case DP_DSC_LINE_BUF_BIT_DEPTH_9: 2644 return 9; 2645 case DP_DSC_LINE_BUF_BIT_DEPTH_10: 2646 return 10; 2647 case DP_DSC_LINE_BUF_BIT_DEPTH_11: 2648 return 11; 2649 case DP_DSC_LINE_BUF_BIT_DEPTH_12: 2650 return 12; 2651 case DP_DSC_LINE_BUF_BIT_DEPTH_13: 2652 return 13; 2653 case DP_DSC_LINE_BUF_BIT_DEPTH_14: 2654 return 14; 2655 case DP_DSC_LINE_BUF_BIT_DEPTH_15: 2656 return 15; 2657 case DP_DSC_LINE_BUF_BIT_DEPTH_16: 2658 return 16; 2659 case DP_DSC_LINE_BUF_BIT_DEPTH_8: 2660 return 8; 2661 } 2662 2663 return 0; 2664 } 2665 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth); 2666 2667 /** 2668 * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component 2669 * values supported by the DSC sink. 2670 * @dsc_dpcd: DSC capabilities from DPCD 2671 * @dsc_bpc: An array to be filled by this helper with supported 2672 * input bpcs. 2673 * 2674 * Read the DSC DPCD from the sink device to parse the supported bits per 2675 * component values. This is used to populate the DSC parameters 2676 * in the &struct drm_dsc_config by the driver. 2677 * Driver creates an infoframe using these parameters to populate 2678 * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC 2679 * infoframe using the helper function drm_dsc_pps_infoframe_pack() 2680 * 2681 * Returns: 2682 * Number of input BPC values parsed from the DPCD 2683 */ 2684 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], 2685 u8 dsc_bpc[3]) 2686 { 2687 int num_bpc = 0; 2688 u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT]; 2689 2690 if (!drm_dp_sink_supports_dsc(dsc_dpcd)) 2691 return 0; 2692 2693 if (color_depth & DP_DSC_12_BPC) 2694 dsc_bpc[num_bpc++] = 12; 2695 if (color_depth & DP_DSC_10_BPC) 2696 dsc_bpc[num_bpc++] = 10; 2697 2698 /* A DP DSC Sink device shall support 8 bpc. */ 2699 dsc_bpc[num_bpc++] = 8; 2700 2701 return num_bpc; 2702 } 2703 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs); 2704 2705 static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux, 2706 const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address, 2707 u8 *buf, int buf_size) 2708 { 2709 /* 2710 * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns 2711 * corrupted values when reading from the 0xF0000- range with a block 2712 * size bigger than 1. 2713 */ 2714 int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size; 2715 int offset; 2716 int ret; 2717 2718 for (offset = 0; offset < buf_size; offset += block_size) { 2719 ret = drm_dp_dpcd_read(aux, 2720 address + offset, 2721 &buf[offset], block_size); 2722 if (ret < 0) 2723 return ret; 2724 2725 WARN_ON(ret != block_size); 2726 } 2727 2728 return 0; 2729 } 2730 2731 /** 2732 * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities 2733 * @aux: DisplayPort AUX channel 2734 * @dpcd: DisplayPort configuration data 2735 * @caps: buffer to return the capability info in 2736 * 2737 * Read capabilities common to all LTTPRs. 2738 * 2739 * Returns 0 on success or a negative error code on failure. 2740 */ 2741 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux, 2742 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2743 u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2744 { 2745 return drm_dp_read_lttpr_regs(aux, dpcd, 2746 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV, 2747 caps, DP_LTTPR_COMMON_CAP_SIZE); 2748 } 2749 EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps); 2750 2751 /** 2752 * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY 2753 * @aux: DisplayPort AUX channel 2754 * @dpcd: DisplayPort configuration data 2755 * @dp_phy: LTTPR PHY to read the capabilities for 2756 * @caps: buffer to return the capability info in 2757 * 2758 * Read the capabilities for the given LTTPR PHY. 2759 * 2760 * Returns 0 on success or a negative error code on failure. 2761 */ 2762 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux, 2763 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 2764 enum drm_dp_phy dp_phy, 2765 u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2766 { 2767 return drm_dp_read_lttpr_regs(aux, dpcd, 2768 DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy), 2769 caps, DP_LTTPR_PHY_CAP_SIZE); 2770 } 2771 EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps); 2772 2773 static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r) 2774 { 2775 return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV]; 2776 } 2777 2778 /** 2779 * drm_dp_lttpr_count - get the number of detected LTTPRs 2780 * @caps: LTTPR common capabilities 2781 * 2782 * Get the number of detected LTTPRs from the LTTPR common capabilities info. 2783 * 2784 * Returns: 2785 * -ERANGE if more than supported number (8) of LTTPRs are detected 2786 * -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value 2787 * otherwise the number of detected LTTPRs 2788 */ 2789 int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2790 { 2791 u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT); 2792 2793 switch (hweight8(count)) { 2794 case 0: 2795 return 0; 2796 case 1: 2797 return 8 - ilog2(count); 2798 case 8: 2799 return -ERANGE; 2800 default: 2801 return -EINVAL; 2802 } 2803 } 2804 EXPORT_SYMBOL(drm_dp_lttpr_count); 2805 2806 /** 2807 * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs 2808 * @caps: LTTPR common capabilities 2809 * 2810 * Returns the maximum link rate supported by all detected LTTPRs. 2811 */ 2812 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2813 { 2814 u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER); 2815 2816 return drm_dp_bw_code_to_link_rate(rate); 2817 } 2818 EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate); 2819 2820 /** 2821 * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs 2822 * @caps: LTTPR common capabilities 2823 * 2824 * Returns the maximum lane count supported by all detected LTTPRs. 2825 */ 2826 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE]) 2827 { 2828 u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER); 2829 2830 return max_lanes & DP_MAX_LANE_COUNT_MASK; 2831 } 2832 EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count); 2833 2834 /** 2835 * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support 2836 * @caps: LTTPR PHY capabilities 2837 * 2838 * Returns true if the @caps for an LTTPR TX PHY indicate support for 2839 * voltage swing level 3. 2840 */ 2841 bool 2842 drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2843 { 2844 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1); 2845 2846 return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED; 2847 } 2848 EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported); 2849 2850 /** 2851 * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support 2852 * @caps: LTTPR PHY capabilities 2853 * 2854 * Returns true if the @caps for an LTTPR TX PHY indicate support for 2855 * pre-emphasis level 3. 2856 */ 2857 bool 2858 drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE]) 2859 { 2860 u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1); 2861 2862 return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED; 2863 } 2864 EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported); 2865 2866 /** 2867 * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink. 2868 * @aux: DisplayPort AUX channel 2869 * @data: DP phy compliance test parameters. 2870 * 2871 * Returns 0 on success or a negative error code on failure. 2872 */ 2873 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux, 2874 struct drm_dp_phy_test_params *data) 2875 { 2876 int err; 2877 u8 rate, lanes; 2878 2879 err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate); 2880 if (err < 0) 2881 return err; 2882 data->link_rate = drm_dp_bw_code_to_link_rate(rate); 2883 2884 err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes); 2885 if (err < 0) 2886 return err; 2887 data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK; 2888 2889 if (lanes & DP_ENHANCED_FRAME_CAP) 2890 data->enhanced_frame_cap = true; 2891 2892 err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern); 2893 if (err < 0) 2894 return err; 2895 2896 switch (data->phy_pattern) { 2897 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: 2898 err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0, 2899 &data->custom80, sizeof(data->custom80)); 2900 if (err < 0) 2901 return err; 2902 2903 break; 2904 case DP_PHY_TEST_PATTERN_CP2520: 2905 err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET, 2906 &data->hbr2_reset, 2907 sizeof(data->hbr2_reset)); 2908 if (err < 0) 2909 return err; 2910 } 2911 2912 return 0; 2913 } 2914 EXPORT_SYMBOL(drm_dp_get_phy_test_pattern); 2915 2916 /** 2917 * drm_dp_set_phy_test_pattern() - set the pattern to the sink. 2918 * @aux: DisplayPort AUX channel 2919 * @data: DP phy compliance test parameters. 2920 * @dp_rev: DP revision to use for compliance testing 2921 * 2922 * Returns 0 on success or a negative error code on failure. 2923 */ 2924 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux, 2925 struct drm_dp_phy_test_params *data, u8 dp_rev) 2926 { 2927 int err, i; 2928 u8 test_pattern; 2929 2930 test_pattern = data->phy_pattern; 2931 if (dp_rev < 0x12) { 2932 test_pattern = (test_pattern << 2) & 2933 DP_LINK_QUAL_PATTERN_11_MASK; 2934 err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, 2935 test_pattern); 2936 if (err < 0) 2937 return err; 2938 } else { 2939 for (i = 0; i < data->num_lanes; i++) { 2940 err = drm_dp_dpcd_writeb(aux, 2941 DP_LINK_QUAL_LANE0_SET + i, 2942 test_pattern); 2943 if (err < 0) 2944 return err; 2945 } 2946 } 2947 2948 return 0; 2949 } 2950 EXPORT_SYMBOL(drm_dp_set_phy_test_pattern); 2951 2952 static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat) 2953 { 2954 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED) 2955 return "Invalid"; 2956 2957 switch (pixelformat) { 2958 case DP_PIXELFORMAT_RGB: 2959 return "RGB"; 2960 case DP_PIXELFORMAT_YUV444: 2961 return "YUV444"; 2962 case DP_PIXELFORMAT_YUV422: 2963 return "YUV422"; 2964 case DP_PIXELFORMAT_YUV420: 2965 return "YUV420"; 2966 case DP_PIXELFORMAT_Y_ONLY: 2967 return "Y_ONLY"; 2968 case DP_PIXELFORMAT_RAW: 2969 return "RAW"; 2970 default: 2971 return "Reserved"; 2972 } 2973 } 2974 2975 static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat, 2976 enum dp_colorimetry colorimetry) 2977 { 2978 if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED) 2979 return "Invalid"; 2980 2981 switch (colorimetry) { 2982 case DP_COLORIMETRY_DEFAULT: 2983 switch (pixelformat) { 2984 case DP_PIXELFORMAT_RGB: 2985 return "sRGB"; 2986 case DP_PIXELFORMAT_YUV444: 2987 case DP_PIXELFORMAT_YUV422: 2988 case DP_PIXELFORMAT_YUV420: 2989 return "BT.601"; 2990 case DP_PIXELFORMAT_Y_ONLY: 2991 return "DICOM PS3.14"; 2992 case DP_PIXELFORMAT_RAW: 2993 return "Custom Color Profile"; 2994 default: 2995 return "Reserved"; 2996 } 2997 case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */ 2998 switch (pixelformat) { 2999 case DP_PIXELFORMAT_RGB: 3000 return "Wide Fixed"; 3001 case DP_PIXELFORMAT_YUV444: 3002 case DP_PIXELFORMAT_YUV422: 3003 case DP_PIXELFORMAT_YUV420: 3004 return "BT.709"; 3005 default: 3006 return "Reserved"; 3007 } 3008 case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */ 3009 switch (pixelformat) { 3010 case DP_PIXELFORMAT_RGB: 3011 return "Wide Float"; 3012 case DP_PIXELFORMAT_YUV444: 3013 case DP_PIXELFORMAT_YUV422: 3014 case DP_PIXELFORMAT_YUV420: 3015 return "xvYCC 601"; 3016 default: 3017 return "Reserved"; 3018 } 3019 case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */ 3020 switch (pixelformat) { 3021 case DP_PIXELFORMAT_RGB: 3022 return "OpRGB"; 3023 case DP_PIXELFORMAT_YUV444: 3024 case DP_PIXELFORMAT_YUV422: 3025 case DP_PIXELFORMAT_YUV420: 3026 return "xvYCC 709"; 3027 default: 3028 return "Reserved"; 3029 } 3030 case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */ 3031 switch (pixelformat) { 3032 case DP_PIXELFORMAT_RGB: 3033 return "DCI-P3"; 3034 case DP_PIXELFORMAT_YUV444: 3035 case DP_PIXELFORMAT_YUV422: 3036 case DP_PIXELFORMAT_YUV420: 3037 return "sYCC 601"; 3038 default: 3039 return "Reserved"; 3040 } 3041 case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */ 3042 switch (pixelformat) { 3043 case DP_PIXELFORMAT_RGB: 3044 return "Custom Profile"; 3045 case DP_PIXELFORMAT_YUV444: 3046 case DP_PIXELFORMAT_YUV422: 3047 case DP_PIXELFORMAT_YUV420: 3048 return "OpYCC 601"; 3049 default: 3050 return "Reserved"; 3051 } 3052 case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */ 3053 switch (pixelformat) { 3054 case DP_PIXELFORMAT_RGB: 3055 return "BT.2020 RGB"; 3056 case DP_PIXELFORMAT_YUV444: 3057 case DP_PIXELFORMAT_YUV422: 3058 case DP_PIXELFORMAT_YUV420: 3059 return "BT.2020 CYCC"; 3060 default: 3061 return "Reserved"; 3062 } 3063 case DP_COLORIMETRY_BT2020_YCC: 3064 switch (pixelformat) { 3065 case DP_PIXELFORMAT_YUV444: 3066 case DP_PIXELFORMAT_YUV422: 3067 case DP_PIXELFORMAT_YUV420: 3068 return "BT.2020 YCC"; 3069 default: 3070 return "Reserved"; 3071 } 3072 default: 3073 return "Invalid"; 3074 } 3075 } 3076 3077 static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range) 3078 { 3079 switch (dynamic_range) { 3080 case DP_DYNAMIC_RANGE_VESA: 3081 return "VESA range"; 3082 case DP_DYNAMIC_RANGE_CTA: 3083 return "CTA range"; 3084 default: 3085 return "Invalid"; 3086 } 3087 } 3088 3089 static const char *dp_content_type_get_name(enum dp_content_type content_type) 3090 { 3091 switch (content_type) { 3092 case DP_CONTENT_TYPE_NOT_DEFINED: 3093 return "Not defined"; 3094 case DP_CONTENT_TYPE_GRAPHICS: 3095 return "Graphics"; 3096 case DP_CONTENT_TYPE_PHOTO: 3097 return "Photo"; 3098 case DP_CONTENT_TYPE_VIDEO: 3099 return "Video"; 3100 case DP_CONTENT_TYPE_GAME: 3101 return "Game"; 3102 default: 3103 return "Reserved"; 3104 } 3105 } 3106 3107 void drm_dp_vsc_sdp_log(struct drm_printer *p, const struct drm_dp_vsc_sdp *vsc) 3108 { 3109 drm_printf(p, "DP SDP: VSC, revision %u, length %u\n", 3110 vsc->revision, vsc->length); 3111 drm_printf(p, " pixelformat: %s\n", 3112 dp_pixelformat_get_name(vsc->pixelformat)); 3113 drm_printf(p, " colorimetry: %s\n", 3114 dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry)); 3115 drm_printf(p, " bpc: %u\n", vsc->bpc); 3116 drm_printf(p, " dynamic range: %s\n", 3117 dp_dynamic_range_get_name(vsc->dynamic_range)); 3118 drm_printf(p, " content type: %s\n", 3119 dp_content_type_get_name(vsc->content_type)); 3120 } 3121 EXPORT_SYMBOL(drm_dp_vsc_sdp_log); 3122 3123 void drm_dp_as_sdp_log(struct drm_printer *p, const struct drm_dp_as_sdp *as_sdp) 3124 { 3125 drm_printf(p, "DP SDP: AS_SDP, revision %u, length %u\n", 3126 as_sdp->revision, as_sdp->length); 3127 drm_printf(p, " vtotal: %d\n", as_sdp->vtotal); 3128 drm_printf(p, " target_rr: %d\n", as_sdp->target_rr); 3129 drm_printf(p, " duration_incr_ms: %d\n", as_sdp->duration_incr_ms); 3130 drm_printf(p, " duration_decr_ms: %d\n", as_sdp->duration_decr_ms); 3131 drm_printf(p, " operation_mode: %d\n", as_sdp->mode); 3132 } 3133 EXPORT_SYMBOL(drm_dp_as_sdp_log); 3134 3135 /** 3136 * drm_dp_as_sdp_supported() - check if adaptive sync sdp is supported 3137 * @aux: DisplayPort AUX channel 3138 * @dpcd: DisplayPort configuration data 3139 * 3140 * Returns true if adaptive sync sdp is supported, else returns false 3141 */ 3142 bool drm_dp_as_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 3143 { 3144 u8 rx_feature; 3145 3146 if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13) 3147 return false; 3148 3149 if (drm_dp_dpcd_readb(aux, DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1, 3150 &rx_feature) != 1) { 3151 drm_dbg_dp(aux->drm_dev, 3152 "Failed to read DP_DPRX_FEATURE_ENUMERATION_LIST_CONT_1\n"); 3153 return false; 3154 } 3155 3156 return (rx_feature & DP_ADAPTIVE_SYNC_SDP_SUPPORTED); 3157 } 3158 EXPORT_SYMBOL(drm_dp_as_sdp_supported); 3159 3160 /** 3161 * drm_dp_vsc_sdp_supported() - check if vsc sdp is supported 3162 * @aux: DisplayPort AUX channel 3163 * @dpcd: DisplayPort configuration data 3164 * 3165 * Returns true if vsc sdp is supported, else returns false 3166 */ 3167 bool drm_dp_vsc_sdp_supported(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 3168 { 3169 u8 rx_feature; 3170 3171 if (dpcd[DP_DPCD_REV] < DP_DPCD_REV_13) 3172 return false; 3173 3174 if (drm_dp_dpcd_readb(aux, DP_DPRX_FEATURE_ENUMERATION_LIST, &rx_feature) != 1) { 3175 drm_dbg_dp(aux->drm_dev, "failed to read DP_DPRX_FEATURE_ENUMERATION_LIST\n"); 3176 return false; 3177 } 3178 3179 return (rx_feature & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED); 3180 } 3181 EXPORT_SYMBOL(drm_dp_vsc_sdp_supported); 3182 3183 /** 3184 * drm_dp_vsc_sdp_pack() - pack a given vsc sdp into generic dp_sdp 3185 * @vsc: vsc sdp initialized according to its purpose as defined in 3186 * table 2-118 - table 2-120 in DP 1.4a specification 3187 * @sdp: valid handle to the generic dp_sdp which will be packed 3188 * 3189 * Returns length of sdp on success and error code on failure 3190 */ 3191 ssize_t drm_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 3192 struct dp_sdp *sdp) 3193 { 3194 size_t length = sizeof(struct dp_sdp); 3195 3196 memset(sdp, 0, sizeof(struct dp_sdp)); 3197 3198 /* 3199 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 3200 * VSC SDP Header Bytes 3201 */ 3202 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */ 3203 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */ 3204 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */ 3205 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ 3206 3207 if (vsc->revision == 0x6) { 3208 sdp->db[0] = 1; 3209 sdp->db[3] = 1; 3210 } 3211 3212 /* 3213 * Revision 0x5 and revision 0x7 supports Pixel Encoding/Colorimetry 3214 * Format as per DP 1.4a spec and DP 2.0 respectively. 3215 */ 3216 if (!(vsc->revision == 0x5 || vsc->revision == 0x7)) 3217 goto out; 3218 3219 /* VSC SDP Payload for DB16 through DB18 */ 3220 /* Pixel Encoding and Colorimetry Formats */ 3221 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */ 3222 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */ 3223 3224 switch (vsc->bpc) { 3225 case 6: 3226 /* 6bpc: 0x0 */ 3227 break; 3228 case 8: 3229 sdp->db[17] = 0x1; /* DB17[3:0] */ 3230 break; 3231 case 10: 3232 sdp->db[17] = 0x2; 3233 break; 3234 case 12: 3235 sdp->db[17] = 0x3; 3236 break; 3237 case 16: 3238 sdp->db[17] = 0x4; 3239 break; 3240 default: 3241 WARN(1, "Missing case %d\n", vsc->bpc); 3242 return -EINVAL; 3243 } 3244 3245 /* Dynamic Range and Component Bit Depth */ 3246 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 3247 sdp->db[17] |= 0x80; /* DB17[7] */ 3248 3249 /* Content Type */ 3250 sdp->db[18] = vsc->content_type & 0x7; 3251 3252 out: 3253 return length; 3254 } 3255 EXPORT_SYMBOL(drm_dp_vsc_sdp_pack); 3256 3257 /** 3258 * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON 3259 * @dpcd: DisplayPort configuration data 3260 * @port_cap: port capabilities 3261 * 3262 * Returns maximum frl bandwidth supported by PCON in GBPS, 3263 * returns 0 if not supported. 3264 */ 3265 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE], 3266 const u8 port_cap[4]) 3267 { 3268 int bw; 3269 u8 buf; 3270 3271 buf = port_cap[2]; 3272 bw = buf & DP_PCON_MAX_FRL_BW; 3273 3274 switch (bw) { 3275 case DP_PCON_MAX_9GBPS: 3276 return 9; 3277 case DP_PCON_MAX_18GBPS: 3278 return 18; 3279 case DP_PCON_MAX_24GBPS: 3280 return 24; 3281 case DP_PCON_MAX_32GBPS: 3282 return 32; 3283 case DP_PCON_MAX_40GBPS: 3284 return 40; 3285 case DP_PCON_MAX_48GBPS: 3286 return 48; 3287 case DP_PCON_MAX_0GBPS: 3288 default: 3289 return 0; 3290 } 3291 3292 return 0; 3293 } 3294 EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw); 3295 3296 /** 3297 * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL. 3298 * @aux: DisplayPort AUX channel 3299 * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY. 3300 * 3301 * Returns 0 if success, else returns negative error code. 3302 */ 3303 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd) 3304 { 3305 int ret; 3306 u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE | 3307 DP_PCON_ENABLE_LINK_FRL_MODE; 3308 3309 if (enable_frl_ready_hpd) 3310 buf |= DP_PCON_ENABLE_HPD_READY; 3311 3312 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3313 3314 return ret; 3315 } 3316 EXPORT_SYMBOL(drm_dp_pcon_frl_prepare); 3317 3318 /** 3319 * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL 3320 * @aux: DisplayPort AUX channel 3321 * 3322 * Returns true if success, else returns false. 3323 */ 3324 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux) 3325 { 3326 int ret; 3327 u8 buf; 3328 3329 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf); 3330 if (ret < 0) 3331 return false; 3332 3333 if (buf & DP_PCON_FRL_READY) 3334 return true; 3335 3336 return false; 3337 } 3338 EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready); 3339 3340 /** 3341 * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1 3342 * @aux: DisplayPort AUX channel 3343 * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink 3344 * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential. 3345 * In Concurrent Mode, the FRL link bring up can be done along with 3346 * DP Link training. In Sequential mode, the FRL link bring up is done prior to 3347 * the DP Link training. 3348 * 3349 * Returns 0 if success, else returns negative error code. 3350 */ 3351 3352 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps, 3353 u8 frl_mode) 3354 { 3355 int ret; 3356 u8 buf; 3357 3358 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf); 3359 if (ret < 0) 3360 return ret; 3361 3362 if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK) 3363 buf |= DP_PCON_ENABLE_CONCURRENT_LINK; 3364 else 3365 buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK; 3366 3367 switch (max_frl_gbps) { 3368 case 9: 3369 buf |= DP_PCON_ENABLE_MAX_BW_9GBPS; 3370 break; 3371 case 18: 3372 buf |= DP_PCON_ENABLE_MAX_BW_18GBPS; 3373 break; 3374 case 24: 3375 buf |= DP_PCON_ENABLE_MAX_BW_24GBPS; 3376 break; 3377 case 32: 3378 buf |= DP_PCON_ENABLE_MAX_BW_32GBPS; 3379 break; 3380 case 40: 3381 buf |= DP_PCON_ENABLE_MAX_BW_40GBPS; 3382 break; 3383 case 48: 3384 buf |= DP_PCON_ENABLE_MAX_BW_48GBPS; 3385 break; 3386 case 0: 3387 buf |= DP_PCON_ENABLE_MAX_BW_0GBPS; 3388 break; 3389 default: 3390 return -EINVAL; 3391 } 3392 3393 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3394 if (ret < 0) 3395 return ret; 3396 3397 return 0; 3398 } 3399 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1); 3400 3401 /** 3402 * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2 3403 * @aux: DisplayPort AUX channel 3404 * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink 3405 * @frl_type : FRL training type, can be Extended, or Normal. 3406 * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask 3407 * starting from min, and stops when link training is successful. In Extended 3408 * FRL training, all frl bw selected in the mask are trained by the PCON. 3409 * 3410 * Returns 0 if success, else returns negative error code. 3411 */ 3412 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask, 3413 u8 frl_type) 3414 { 3415 int ret; 3416 u8 buf = max_frl_mask; 3417 3418 if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED) 3419 buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED; 3420 else 3421 buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED; 3422 3423 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf); 3424 if (ret < 0) 3425 return ret; 3426 3427 return 0; 3428 } 3429 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2); 3430 3431 /** 3432 * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration. 3433 * @aux: DisplayPort AUX channel 3434 * 3435 * Returns 0 if success, else returns negative error code. 3436 */ 3437 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux) 3438 { 3439 int ret; 3440 3441 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0); 3442 if (ret < 0) 3443 return ret; 3444 3445 return 0; 3446 } 3447 EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config); 3448 3449 /** 3450 * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL 3451 * @aux: DisplayPort AUX channel 3452 * 3453 * Returns 0 if success, else returns negative error code. 3454 */ 3455 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux) 3456 { 3457 int ret; 3458 u8 buf = 0; 3459 3460 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf); 3461 if (ret < 0) 3462 return ret; 3463 if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) { 3464 drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n", 3465 aux->name); 3466 return -EINVAL; 3467 } 3468 buf |= DP_PCON_ENABLE_HDMI_LINK; 3469 ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf); 3470 if (ret < 0) 3471 return ret; 3472 3473 return 0; 3474 } 3475 EXPORT_SYMBOL(drm_dp_pcon_frl_enable); 3476 3477 /** 3478 * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active. 3479 * @aux: DisplayPort AUX channel 3480 * 3481 * Returns true if link is active else returns false. 3482 */ 3483 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux) 3484 { 3485 u8 buf; 3486 int ret; 3487 3488 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf); 3489 if (ret < 0) 3490 return false; 3491 3492 return buf & DP_PCON_HDMI_TX_LINK_ACTIVE; 3493 } 3494 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active); 3495 3496 /** 3497 * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE 3498 * @aux: DisplayPort AUX channel 3499 * @frl_trained_mask: pointer to store bitmask of the trained bw configuration. 3500 * Valid only if the MODE returned is FRL. For Normal Link training mode 3501 * only 1 of the bits will be set, but in case of Extended mode, more than 3502 * one bits can be set. 3503 * 3504 * Returns the link mode : TMDS or FRL on success, else returns negative error 3505 * code. 3506 */ 3507 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask) 3508 { 3509 u8 buf; 3510 int mode; 3511 int ret; 3512 3513 ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf); 3514 if (ret < 0) 3515 return ret; 3516 3517 mode = buf & DP_PCON_HDMI_LINK_MODE; 3518 3519 if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode) 3520 *frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1; 3521 3522 return mode; 3523 } 3524 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode); 3525 3526 /** 3527 * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane 3528 * during link failure between PCON and HDMI sink 3529 * @aux: DisplayPort AUX channel 3530 * @connector: DRM connector 3531 * code. 3532 **/ 3533 3534 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux, 3535 struct drm_connector *connector) 3536 { 3537 u8 buf, error_count; 3538 int i, num_error; 3539 struct drm_hdmi_info *hdmi = &connector->display_info.hdmi; 3540 3541 for (i = 0; i < hdmi->max_lanes; i++) { 3542 if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0) 3543 return; 3544 3545 error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK; 3546 switch (error_count) { 3547 case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS: 3548 num_error = 100; 3549 break; 3550 case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS: 3551 num_error = 10; 3552 break; 3553 case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS: 3554 num_error = 3; 3555 break; 3556 default: 3557 num_error = 0; 3558 } 3559 3560 drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d", 3561 aux->name, num_error, i); 3562 } 3563 } 3564 EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count); 3565 3566 /* 3567 * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2 3568 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3569 * 3570 * Returns true is PCON encoder is DSC 1.2 else returns false. 3571 */ 3572 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3573 { 3574 u8 buf; 3575 u8 major_v, minor_v; 3576 3577 buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER]; 3578 major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT; 3579 minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT; 3580 3581 if (major_v == 1 && minor_v == 2) 3582 return true; 3583 3584 return false; 3585 } 3586 EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2); 3587 3588 /* 3589 * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder 3590 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3591 * 3592 * Returns maximum no. of slices supported by the PCON DSC Encoder. 3593 */ 3594 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3595 { 3596 u8 slice_cap1, slice_cap2; 3597 3598 slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER]; 3599 slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER]; 3600 3601 if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC) 3602 return 24; 3603 if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC) 3604 return 20; 3605 if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC) 3606 return 16; 3607 if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC) 3608 return 12; 3609 if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC) 3610 return 10; 3611 if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC) 3612 return 8; 3613 if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC) 3614 return 6; 3615 if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC) 3616 return 4; 3617 if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC) 3618 return 2; 3619 if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC) 3620 return 1; 3621 3622 return 0; 3623 } 3624 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices); 3625 3626 /* 3627 * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder 3628 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3629 * 3630 * Returns maximum width of the slices in pixel width i.e. no. of pixels x 320. 3631 */ 3632 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3633 { 3634 u8 buf; 3635 3636 buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER]; 3637 3638 return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER; 3639 } 3640 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width); 3641 3642 /* 3643 * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder 3644 * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder 3645 * 3646 * Returns the bpp precision supported by the PCON encoder. 3647 */ 3648 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE]) 3649 { 3650 u8 buf; 3651 3652 buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER]; 3653 3654 switch (buf & DP_PCON_DSC_BPP_INCR_MASK) { 3655 case DP_PCON_DSC_ONE_16TH_BPP: 3656 return 16; 3657 case DP_PCON_DSC_ONE_8TH_BPP: 3658 return 8; 3659 case DP_PCON_DSC_ONE_4TH_BPP: 3660 return 4; 3661 case DP_PCON_DSC_ONE_HALF_BPP: 3662 return 2; 3663 case DP_PCON_DSC_ONE_BPP: 3664 return 1; 3665 } 3666 3667 return 0; 3668 } 3669 EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr); 3670 3671 static 3672 int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config) 3673 { 3674 u8 buf; 3675 int ret; 3676 3677 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf); 3678 if (ret < 0) 3679 return ret; 3680 3681 buf |= DP_PCON_ENABLE_DSC_ENCODER; 3682 3683 if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) { 3684 buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK; 3685 buf |= pps_buf_config << 2; 3686 } 3687 3688 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf); 3689 if (ret < 0) 3690 return ret; 3691 3692 return 0; 3693 } 3694 3695 /** 3696 * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters 3697 * for DSC1.2 between PCON & HDMI2.1 sink 3698 * @aux: DisplayPort AUX channel 3699 * 3700 * Returns 0 on success, else returns negative error code. 3701 */ 3702 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux) 3703 { 3704 int ret; 3705 3706 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED); 3707 if (ret < 0) 3708 return ret; 3709 3710 return 0; 3711 } 3712 EXPORT_SYMBOL(drm_dp_pcon_pps_default); 3713 3714 /** 3715 * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for 3716 * HDMI sink 3717 * @aux: DisplayPort AUX channel 3718 * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON. 3719 * 3720 * Returns 0 on success, else returns negative error code. 3721 */ 3722 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128]) 3723 { 3724 int ret; 3725 3726 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128); 3727 if (ret < 0) 3728 return ret; 3729 3730 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER); 3731 if (ret < 0) 3732 return ret; 3733 3734 return 0; 3735 } 3736 EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf); 3737 3738 /* 3739 * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder 3740 * override registers 3741 * @aux: DisplayPort AUX channel 3742 * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height, 3743 * bits_per_pixel. 3744 * 3745 * Returns 0 on success, else returns negative error code. 3746 */ 3747 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6]) 3748 { 3749 int ret; 3750 3751 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2); 3752 if (ret < 0) 3753 return ret; 3754 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2); 3755 if (ret < 0) 3756 return ret; 3757 ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2); 3758 if (ret < 0) 3759 return ret; 3760 3761 ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER); 3762 if (ret < 0) 3763 return ret; 3764 3765 return 0; 3766 } 3767 EXPORT_SYMBOL(drm_dp_pcon_pps_override_param); 3768 3769 /* 3770 * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr 3771 * @aux: displayPort AUX channel 3772 * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable. 3773 * 3774 * Returns 0 on success, else returns negative error code. 3775 */ 3776 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc) 3777 { 3778 int ret; 3779 u8 buf; 3780 3781 ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf); 3782 if (ret < 0) 3783 return ret; 3784 3785 if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK) 3786 buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK); 3787 else 3788 buf &= ~DP_CONVERSION_RGB_YCBCR_MASK; 3789 3790 ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf); 3791 if (ret < 0) 3792 return ret; 3793 3794 return 0; 3795 } 3796 EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr); 3797 3798 /** 3799 * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX 3800 * @aux: The DP AUX channel to use 3801 * @bl: Backlight capability info from drm_edp_backlight_init() 3802 * @level: The brightness level to set 3803 * 3804 * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must 3805 * already have been enabled by the driver by calling drm_edp_backlight_enable(). 3806 * 3807 * Returns: %0 on success, negative error code on failure 3808 */ 3809 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3810 u16 level) 3811 { 3812 int ret; 3813 u8 buf[2] = { 0 }; 3814 3815 /* The panel uses the PWM for controlling brightness levels */ 3816 if (!bl->aux_set) 3817 return 0; 3818 3819 if (bl->lsb_reg_used) { 3820 buf[0] = (level & 0xff00) >> 8; 3821 buf[1] = (level & 0x00ff); 3822 } else { 3823 buf[0] = level; 3824 } 3825 3826 ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf)); 3827 if (ret != sizeof(buf)) { 3828 drm_err(aux->drm_dev, 3829 "%s: Failed to write aux backlight level: %d\n", 3830 aux->name, ret); 3831 return ret < 0 ? ret : -EIO; 3832 } 3833 3834 return 0; 3835 } 3836 EXPORT_SYMBOL(drm_edp_backlight_set_level); 3837 3838 static int 3839 drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3840 bool enable) 3841 { 3842 int ret; 3843 u8 buf; 3844 3845 /* This panel uses the EDP_BL_PWR GPIO for enablement */ 3846 if (!bl->aux_enable) 3847 return 0; 3848 3849 ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf); 3850 if (ret != 1) { 3851 drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n", 3852 aux->name, ret); 3853 return ret < 0 ? ret : -EIO; 3854 } 3855 if (enable) 3856 buf |= DP_EDP_BACKLIGHT_ENABLE; 3857 else 3858 buf &= ~DP_EDP_BACKLIGHT_ENABLE; 3859 3860 ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf); 3861 if (ret != 1) { 3862 drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n", 3863 aux->name, ret); 3864 return ret < 0 ? ret : -EIO; 3865 } 3866 3867 return 0; 3868 } 3869 3870 /** 3871 * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD 3872 * @aux: The DP AUX channel to use 3873 * @bl: Backlight capability info from drm_edp_backlight_init() 3874 * @level: The initial backlight level to set via AUX, if there is one 3875 * 3876 * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally 3877 * restoring any important backlight state such as the given backlight level, the brightness byte 3878 * count, backlight frequency, etc. 3879 * 3880 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require 3881 * that the driver handle enabling/disabling the panel through implementation-specific means using 3882 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false, 3883 * this function becomes a no-op, and the driver is expected to handle powering the panel on using 3884 * the EDP_BL_PWR GPIO. 3885 * 3886 * Returns: %0 on success, negative error code on failure. 3887 */ 3888 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl, 3889 const u16 level) 3890 { 3891 int ret; 3892 u8 dpcd_buf; 3893 3894 if (bl->aux_set) 3895 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD; 3896 else 3897 dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM; 3898 3899 if (bl->pwmgen_bit_count) { 3900 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count); 3901 if (ret != 1) 3902 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", 3903 aux->name, ret); 3904 } 3905 3906 if (bl->pwm_freq_pre_divider) { 3907 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider); 3908 if (ret != 1) 3909 drm_dbg_kms(aux->drm_dev, 3910 "%s: Failed to write aux backlight frequency: %d\n", 3911 aux->name, ret); 3912 else 3913 dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE; 3914 } 3915 3916 ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf); 3917 if (ret != 1) { 3918 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n", 3919 aux->name, ret); 3920 return ret < 0 ? ret : -EIO; 3921 } 3922 3923 ret = drm_edp_backlight_set_level(aux, bl, level); 3924 if (ret < 0) 3925 return ret; 3926 ret = drm_edp_backlight_set_enable(aux, bl, true); 3927 if (ret < 0) 3928 return ret; 3929 3930 return 0; 3931 } 3932 EXPORT_SYMBOL(drm_edp_backlight_enable); 3933 3934 /** 3935 * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported 3936 * @aux: The DP AUX channel to use 3937 * @bl: Backlight capability info from drm_edp_backlight_init() 3938 * 3939 * This function handles disabling DPCD backlight controls on a panel over AUX. 3940 * 3941 * Note that certain panels do not support being enabled or disabled via DPCD, but instead require 3942 * that the driver handle enabling/disabling the panel through implementation-specific means using 3943 * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false, 3944 * this function becomes a no-op, and the driver is expected to handle powering the panel off using 3945 * the EDP_BL_PWR GPIO. 3946 * 3947 * Returns: %0 on success or no-op, negative error code on failure. 3948 */ 3949 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl) 3950 { 3951 int ret; 3952 3953 ret = drm_edp_backlight_set_enable(aux, bl, false); 3954 if (ret < 0) 3955 return ret; 3956 3957 return 0; 3958 } 3959 EXPORT_SYMBOL(drm_edp_backlight_disable); 3960 3961 static inline int 3962 drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 3963 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]) 3964 { 3965 int fxp, fxp_min, fxp_max, fxp_actual, f = 1; 3966 int ret; 3967 u8 pn, pn_min, pn_max; 3968 3969 if (!bl->aux_set) 3970 return 0; 3971 3972 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn); 3973 if (ret != 1) { 3974 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n", 3975 aux->name, ret); 3976 return -ENODEV; 3977 } 3978 3979 pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 3980 bl->max = (1 << pn) - 1; 3981 if (!driver_pwm_freq_hz) 3982 return 0; 3983 3984 /* 3985 * Set PWM Frequency divider to match desired frequency provided by the driver. 3986 * The PWM Frequency is calculated as 27Mhz / (F x P). 3987 * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the 3988 * EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h) 3989 * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the 3990 * EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h) 3991 */ 3992 3993 /* Find desired value of (F x P) 3994 * Note that, if F x P is out of supported range, the maximum value or minimum value will 3995 * applied automatically. So no need to check that. 3996 */ 3997 fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz); 3998 3999 /* Use highest possible value of Pn for more granularity of brightness adjustment while 4000 * satisfying the conditions below. 4001 * - Pn is in the range of Pn_min and Pn_max 4002 * - F is in the range of 1 and 255 4003 * - FxP is within 25% of desired value. 4004 * Note: 25% is arbitrary value and may need some tweak. 4005 */ 4006 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min); 4007 if (ret != 1) { 4008 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n", 4009 aux->name, ret); 4010 return 0; 4011 } 4012 ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max); 4013 if (ret != 1) { 4014 drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n", 4015 aux->name, ret); 4016 return 0; 4017 } 4018 pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 4019 pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK; 4020 4021 /* Ensure frequency is within 25% of desired value */ 4022 fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4); 4023 fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4); 4024 if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) { 4025 drm_dbg_kms(aux->drm_dev, 4026 "%s: Driver defined backlight frequency (%d) out of range\n", 4027 aux->name, driver_pwm_freq_hz); 4028 return 0; 4029 } 4030 4031 for (pn = pn_max; pn >= pn_min; pn--) { 4032 f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255); 4033 fxp_actual = f << pn; 4034 if (fxp_min <= fxp_actual && fxp_actual <= fxp_max) 4035 break; 4036 } 4037 4038 ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn); 4039 if (ret != 1) { 4040 drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n", 4041 aux->name, ret); 4042 return 0; 4043 } 4044 bl->pwmgen_bit_count = pn; 4045 bl->max = (1 << pn) - 1; 4046 4047 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) { 4048 bl->pwm_freq_pre_divider = f; 4049 drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n", 4050 aux->name, driver_pwm_freq_hz); 4051 } 4052 4053 return 0; 4054 } 4055 4056 static inline int 4057 drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 4058 u8 *current_mode) 4059 { 4060 int ret; 4061 u8 buf[2]; 4062 u8 mode_reg; 4063 4064 ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg); 4065 if (ret != 1) { 4066 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n", 4067 aux->name, ret); 4068 return ret < 0 ? ret : -EIO; 4069 } 4070 4071 *current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK); 4072 if (!bl->aux_set) 4073 return 0; 4074 4075 if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) { 4076 int size = 1 + bl->lsb_reg_used; 4077 4078 ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size); 4079 if (ret != size) { 4080 drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n", 4081 aux->name, ret); 4082 return ret < 0 ? ret : -EIO; 4083 } 4084 4085 if (bl->lsb_reg_used) 4086 return (buf[0] << 8) | buf[1]; 4087 else 4088 return buf[0]; 4089 } 4090 4091 /* 4092 * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and 4093 * the driver should assume max brightness 4094 */ 4095 return bl->max; 4096 } 4097 4098 /** 4099 * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight 4100 * interface. 4101 * @aux: The DP aux device to use for probing 4102 * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight 4103 * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz 4104 * @edp_dpcd: A cached copy of the eDP DPCD 4105 * @current_level: Where to store the probed brightness level, if any 4106 * @current_mode: Where to store the currently set backlight control mode 4107 * 4108 * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities, 4109 * along with also probing the current and maximum supported brightness levels. 4110 * 4111 * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the 4112 * default frequency from the panel is used. 4113 * 4114 * Returns: %0 on success, negative error code on failure. 4115 */ 4116 int 4117 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl, 4118 u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE], 4119 u16 *current_level, u8 *current_mode) 4120 { 4121 int ret; 4122 4123 if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP) 4124 bl->aux_enable = true; 4125 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP) 4126 bl->aux_set = true; 4127 if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT) 4128 bl->lsb_reg_used = true; 4129 4130 /* Sanity check caps */ 4131 if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) { 4132 drm_dbg_kms(aux->drm_dev, 4133 "%s: Panel supports neither AUX or PWM brightness control? Aborting\n", 4134 aux->name); 4135 return -EINVAL; 4136 } 4137 4138 ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd); 4139 if (ret < 0) 4140 return ret; 4141 4142 ret = drm_edp_backlight_probe_state(aux, bl, current_mode); 4143 if (ret < 0) 4144 return ret; 4145 *current_level = ret; 4146 4147 drm_dbg_kms(aux->drm_dev, 4148 "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n", 4149 aux->name, bl->aux_set, bl->aux_enable, *current_mode); 4150 if (bl->aux_set) { 4151 drm_dbg_kms(aux->drm_dev, 4152 "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n", 4153 aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider, 4154 bl->lsb_reg_used); 4155 } 4156 4157 return 0; 4158 } 4159 EXPORT_SYMBOL(drm_edp_backlight_init); 4160 4161 #if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \ 4162 (IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE)) 4163 4164 static int dp_aux_backlight_update_status(struct backlight_device *bd) 4165 { 4166 struct dp_aux_backlight *bl = bl_get_data(bd); 4167 u16 brightness = backlight_get_brightness(bd); 4168 int ret = 0; 4169 4170 if (!backlight_is_blank(bd)) { 4171 if (!bl->enabled) { 4172 drm_edp_backlight_enable(bl->aux, &bl->info, brightness); 4173 bl->enabled = true; 4174 return 0; 4175 } 4176 ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness); 4177 } else { 4178 if (bl->enabled) { 4179 drm_edp_backlight_disable(bl->aux, &bl->info); 4180 bl->enabled = false; 4181 } 4182 } 4183 4184 return ret; 4185 } 4186 4187 static const struct backlight_ops dp_aux_bl_ops = { 4188 .update_status = dp_aux_backlight_update_status, 4189 }; 4190 4191 /** 4192 * drm_panel_dp_aux_backlight - create and use DP AUX backlight 4193 * @panel: DRM panel 4194 * @aux: The DP AUX channel to use 4195 * 4196 * Use this function to create and handle backlight if your panel 4197 * supports backlight control over DP AUX channel using DPCD 4198 * registers as per VESA's standard backlight control interface. 4199 * 4200 * When the panel is enabled backlight will be enabled after a 4201 * successful call to &drm_panel_funcs.enable() 4202 * 4203 * When the panel is disabled backlight will be disabled before the 4204 * call to &drm_panel_funcs.disable(). 4205 * 4206 * A typical implementation for a panel driver supporting backlight 4207 * control over DP AUX will call this function at probe time. 4208 * Backlight will then be handled transparently without requiring 4209 * any intervention from the driver. 4210 * 4211 * drm_panel_dp_aux_backlight() must be called after the call to drm_panel_init(). 4212 * 4213 * Return: 0 on success or a negative error code on failure. 4214 */ 4215 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux) 4216 { 4217 struct dp_aux_backlight *bl; 4218 struct backlight_properties props = { 0 }; 4219 u16 current_level; 4220 u8 current_mode; 4221 u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE]; 4222 int ret; 4223 4224 if (!panel || !panel->dev || !aux) 4225 return -EINVAL; 4226 4227 ret = drm_dp_dpcd_read(aux, DP_EDP_DPCD_REV, edp_dpcd, 4228 EDP_DISPLAY_CTL_CAP_SIZE); 4229 if (ret < 0) 4230 return ret; 4231 4232 if (!drm_edp_backlight_supported(edp_dpcd)) { 4233 DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n"); 4234 return 0; 4235 } 4236 4237 bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL); 4238 if (!bl) 4239 return -ENOMEM; 4240 4241 bl->aux = aux; 4242 4243 ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd, 4244 ¤t_level, ¤t_mode); 4245 if (ret < 0) 4246 return ret; 4247 4248 props.type = BACKLIGHT_RAW; 4249 props.brightness = current_level; 4250 props.max_brightness = bl->info.max; 4251 4252 bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight", 4253 panel->dev, bl, 4254 &dp_aux_bl_ops, &props); 4255 if (IS_ERR(bl->base)) 4256 return PTR_ERR(bl->base); 4257 4258 backlight_disable(bl->base); 4259 4260 panel->backlight = bl->base; 4261 4262 return 0; 4263 } 4264 EXPORT_SYMBOL(drm_panel_dp_aux_backlight); 4265 4266 #endif 4267 4268 /* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */ 4269 static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16, 4270 int symbol_size, bool is_mst) 4271 { 4272 int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count); 4273 int align = is_mst ? 4 / lane_count : 1; 4274 4275 return ALIGN(cycles, align); 4276 } 4277 4278 static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count, 4279 int bpp_x16, int symbol_size, bool is_mst) 4280 { 4281 int slice_pixels = DIV_ROUND_UP(pixels, slice_count); 4282 int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels, 4283 bpp_x16, symbol_size, is_mst); 4284 int slice_eoc_cycles = is_mst ? 4 / lane_count : 1; 4285 4286 return slice_count * (slice_data_cycles + slice_eoc_cycles); 4287 } 4288 4289 /** 4290 * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream 4291 * @lane_count: DP link lane count 4292 * @hactive: pixel count of the active period in one scanline of the stream 4293 * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set 4294 * @bpp_x16: bits per pixel in .4 binary fixed point 4295 * @flags: DRM_DP_OVERHEAD_x flags 4296 * 4297 * Calculate the BW allocation overhead of a DP link stream, depending 4298 * on the link's 4299 * - @lane_count 4300 * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST) 4301 * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR) 4302 * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC) 4303 * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK) 4304 * as well as the stream's 4305 * - @hactive timing 4306 * - @bpp_x16 color depth 4307 * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC). 4308 * Note that this overhead doesn't account for the 8b/10b, 128b/132b 4309 * channel coding efficiency, for that see 4310 * @drm_dp_link_bw_channel_coding_efficiency(). 4311 * 4312 * Returns the overhead as 100% + overhead% in 1ppm units. 4313 */ 4314 int drm_dp_bw_overhead(int lane_count, int hactive, 4315 int dsc_slice_count, 4316 int bpp_x16, unsigned long flags) 4317 { 4318 int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8; 4319 bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST; 4320 u32 overhead = 1000000; 4321 int symbol_cycles; 4322 4323 if (lane_count == 0 || hactive == 0 || bpp_x16 == 0) { 4324 DRM_DEBUG_KMS("Invalid BW overhead params: lane_count %d, hactive %d, bpp_x16 " FXP_Q4_FMT "\n", 4325 lane_count, hactive, 4326 FXP_Q4_ARGS(bpp_x16)); 4327 return 0; 4328 } 4329 4330 /* 4331 * DP Standard v2.1 2.6.4.1 4332 * SSC downspread and ref clock variation margin: 4333 * 5300ppm + 300ppm ~ 0.6% 4334 */ 4335 if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK) 4336 overhead += 6000; 4337 4338 /* 4339 * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4: 4340 * FEC symbol insertions for 8b/10b channel coding: 4341 * After each 250 data symbols on 2-4 lanes: 4342 * 250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ (256 byte FEC block) 4343 * After each 2 x 250 data symbols on 1 lane: 4344 * 2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block) 4345 * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks: 4346 * 256 * 256 bytes + 1 FEC_PM 4347 * or 4348 * 128 * 512 bytes + 1 FEC_PM 4349 * (256 * 6 + 1) / (256 * 250) = 2.4015625 % 4350 */ 4351 if (flags & DRM_DP_BW_OVERHEAD_FEC) 4352 overhead += 24016; 4353 4354 /* 4355 * DP Standard v2.1 2.7.9, 5.9.7 4356 * The FEC overhead for UHBR is accounted for in its 96.71% channel 4357 * coding efficiency. 4358 */ 4359 WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) && 4360 (flags & DRM_DP_BW_OVERHEAD_FEC)); 4361 4362 if (flags & DRM_DP_BW_OVERHEAD_DSC) 4363 symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive, 4364 dsc_slice_count, 4365 bpp_x16, symbol_size, 4366 is_mst); 4367 else 4368 symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive, 4369 bpp_x16, symbol_size, 4370 is_mst); 4371 4372 return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count, 4373 overhead * 16), 4374 hactive * bpp_x16); 4375 } 4376 EXPORT_SYMBOL(drm_dp_bw_overhead); 4377 4378 /** 4379 * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency 4380 * @is_uhbr: Whether the link has a 128b/132b channel coding 4381 * 4382 * Return the channel coding efficiency of the given DP link type, which is 4383 * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes 4384 * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead 4385 * and for 128b/132b any link or PHY level control symbol insertion overhead 4386 * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the 4387 * corresponding FEC overhead is BW allocation specific, included in the value 4388 * returned by drm_dp_bw_overhead(). 4389 * 4390 * Returns the efficiency in the 100%/coding-overhead% ratio in 4391 * 1ppm units. 4392 */ 4393 int drm_dp_bw_channel_coding_efficiency(bool is_uhbr) 4394 { 4395 if (is_uhbr) 4396 return 967100; 4397 else 4398 /* 4399 * Note that on 8b/10b MST the efficiency is only 4400 * 78.75% due to the 1 out of 64 MTPH packet overhead, 4401 * not accounted for here. 4402 */ 4403 return 800000; 4404 } 4405 EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency); 4406 4407 /** 4408 * drm_dp_max_dprx_data_rate - Get the max data bandwidth of a DPRX sink 4409 * @max_link_rate: max DPRX link rate in 10kbps units 4410 * @max_lanes: max DPRX lane count 4411 * 4412 * Given a link rate and lanes, get the data bandwidth. 4413 * 4414 * Data bandwidth is the actual payload rate, which depends on the data 4415 * bandwidth efficiency and the link rate. 4416 * 4417 * Note that protocol layers above the DPRX link level considered here can 4418 * further limit the maximum data rate. Such layers are the MST topology (with 4419 * limits on the link between the source and first branch device as well as on 4420 * the whole MST path until the DPRX link) and (Thunderbolt) DP tunnels - 4421 * which in turn can encapsulate an MST link with its own limit - with each 4422 * SST or MST encapsulated tunnel sharing the BW of a tunnel group. 4423 * 4424 * Returns the maximum data rate in kBps units. 4425 */ 4426 int drm_dp_max_dprx_data_rate(int max_link_rate, int max_lanes) 4427 { 4428 int ch_coding_efficiency = 4429 drm_dp_bw_channel_coding_efficiency(drm_dp_is_uhbr_rate(max_link_rate)); 4430 4431 return DIV_ROUND_DOWN_ULL(mul_u32_u32(max_link_rate * 10 * max_lanes, 4432 ch_coding_efficiency), 4433 1000000 * 8); 4434 } 4435 EXPORT_SYMBOL(drm_dp_max_dprx_data_rate); 4436