xref: /linux/drivers/gpu/drm/display/drm_dp_helper.c (revision 2b0cfa6e49566c8fa6759734cf821aa6e8271a9e)
1 /*
2  * Copyright © 2009 Keith Packard
3  *
4  * Permission to use, copy, modify, distribute, and sell this software and its
5  * documentation for any purpose is hereby granted without fee, provided that
6  * the above copyright notice appear in all copies and that both that copyright
7  * notice and this permission notice appear in supporting documentation, and
8  * that the name of the copyright holders not be used in advertising or
9  * publicity pertaining to distribution of the software without specific,
10  * written prior permission.  The copyright holders make no representations
11  * about the suitability of this software for any purpose.  It is provided "as
12  * is" without express or implied warranty.
13  *
14  * THE COPYRIGHT HOLDERS DISCLAIM ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
15  * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
16  * EVENT SHALL THE COPYRIGHT HOLDERS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
17  * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE,
18  * DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
19  * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR PERFORMANCE
20  * OF THIS SOFTWARE.
21  */
22 
23 #include <linux/backlight.h>
24 #include <linux/delay.h>
25 #include <linux/errno.h>
26 #include <linux/i2c.h>
27 #include <linux/init.h>
28 #include <linux/kernel.h>
29 #include <linux/module.h>
30 #include <linux/sched.h>
31 #include <linux/seq_file.h>
32 #include <linux/string_helpers.h>
33 #include <linux/dynamic_debug.h>
34 
35 #include <drm/display/drm_dp_helper.h>
36 #include <drm/display/drm_dp_mst_helper.h>
37 #include <drm/drm_edid.h>
38 #include <drm/drm_print.h>
39 #include <drm/drm_vblank.h>
40 #include <drm/drm_panel.h>
41 
42 #include "drm_dp_helper_internal.h"
43 
44 DECLARE_DYNDBG_CLASSMAP(drm_debug_classes, DD_CLASS_TYPE_DISJOINT_BITS, 0,
45 			"DRM_UT_CORE",
46 			"DRM_UT_DRIVER",
47 			"DRM_UT_KMS",
48 			"DRM_UT_PRIME",
49 			"DRM_UT_ATOMIC",
50 			"DRM_UT_VBL",
51 			"DRM_UT_STATE",
52 			"DRM_UT_LEASE",
53 			"DRM_UT_DP",
54 			"DRM_UT_DRMRES");
55 
56 struct dp_aux_backlight {
57 	struct backlight_device *base;
58 	struct drm_dp_aux *aux;
59 	struct drm_edp_backlight_info info;
60 	bool enabled;
61 };
62 
63 /**
64  * DOC: dp helpers
65  *
66  * These functions contain some common logic and helpers at various abstraction
67  * levels to deal with Display Port sink devices and related things like DP aux
68  * channel transfers, EDID reading over DP aux channels, decoding certain DPCD
69  * blocks, ...
70  */
71 
72 /* Helpers for DP link training */
73 static u8 dp_link_status(const u8 link_status[DP_LINK_STATUS_SIZE], int r)
74 {
75 	return link_status[r - DP_LANE0_1_STATUS];
76 }
77 
78 static u8 dp_get_lane_status(const u8 link_status[DP_LINK_STATUS_SIZE],
79 			     int lane)
80 {
81 	int i = DP_LANE0_1_STATUS + (lane >> 1);
82 	int s = (lane & 1) * 4;
83 	u8 l = dp_link_status(link_status, i);
84 
85 	return (l >> s) & 0xf;
86 }
87 
88 bool drm_dp_channel_eq_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
89 			  int lane_count)
90 {
91 	u8 lane_align;
92 	u8 lane_status;
93 	int lane;
94 
95 	lane_align = dp_link_status(link_status,
96 				    DP_LANE_ALIGN_STATUS_UPDATED);
97 	if ((lane_align & DP_INTERLANE_ALIGN_DONE) == 0)
98 		return false;
99 	for (lane = 0; lane < lane_count; lane++) {
100 		lane_status = dp_get_lane_status(link_status, lane);
101 		if ((lane_status & DP_CHANNEL_EQ_BITS) != DP_CHANNEL_EQ_BITS)
102 			return false;
103 	}
104 	return true;
105 }
106 EXPORT_SYMBOL(drm_dp_channel_eq_ok);
107 
108 bool drm_dp_clock_recovery_ok(const u8 link_status[DP_LINK_STATUS_SIZE],
109 			      int lane_count)
110 {
111 	int lane;
112 	u8 lane_status;
113 
114 	for (lane = 0; lane < lane_count; lane++) {
115 		lane_status = dp_get_lane_status(link_status, lane);
116 		if ((lane_status & DP_LANE_CR_DONE) == 0)
117 			return false;
118 	}
119 	return true;
120 }
121 EXPORT_SYMBOL(drm_dp_clock_recovery_ok);
122 
123 u8 drm_dp_get_adjust_request_voltage(const u8 link_status[DP_LINK_STATUS_SIZE],
124 				     int lane)
125 {
126 	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
127 	int s = ((lane & 1) ?
128 		 DP_ADJUST_VOLTAGE_SWING_LANE1_SHIFT :
129 		 DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT);
130 	u8 l = dp_link_status(link_status, i);
131 
132 	return ((l >> s) & 0x3) << DP_TRAIN_VOLTAGE_SWING_SHIFT;
133 }
134 EXPORT_SYMBOL(drm_dp_get_adjust_request_voltage);
135 
136 u8 drm_dp_get_adjust_request_pre_emphasis(const u8 link_status[DP_LINK_STATUS_SIZE],
137 					  int lane)
138 {
139 	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
140 	int s = ((lane & 1) ?
141 		 DP_ADJUST_PRE_EMPHASIS_LANE1_SHIFT :
142 		 DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT);
143 	u8 l = dp_link_status(link_status, i);
144 
145 	return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT;
146 }
147 EXPORT_SYMBOL(drm_dp_get_adjust_request_pre_emphasis);
148 
149 /* DP 2.0 128b/132b */
150 u8 drm_dp_get_adjust_tx_ffe_preset(const u8 link_status[DP_LINK_STATUS_SIZE],
151 				   int lane)
152 {
153 	int i = DP_ADJUST_REQUEST_LANE0_1 + (lane >> 1);
154 	int s = ((lane & 1) ?
155 		 DP_ADJUST_TX_FFE_PRESET_LANE1_SHIFT :
156 		 DP_ADJUST_TX_FFE_PRESET_LANE0_SHIFT);
157 	u8 l = dp_link_status(link_status, i);
158 
159 	return (l >> s) & 0xf;
160 }
161 EXPORT_SYMBOL(drm_dp_get_adjust_tx_ffe_preset);
162 
163 /* DP 2.0 errata for 128b/132b */
164 bool drm_dp_128b132b_lane_channel_eq_done(const u8 link_status[DP_LINK_STATUS_SIZE],
165 					  int lane_count)
166 {
167 	u8 lane_align, lane_status;
168 	int lane;
169 
170 	lane_align = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
171 	if (!(lane_align & DP_INTERLANE_ALIGN_DONE))
172 		return false;
173 
174 	for (lane = 0; lane < lane_count; lane++) {
175 		lane_status = dp_get_lane_status(link_status, lane);
176 		if (!(lane_status & DP_LANE_CHANNEL_EQ_DONE))
177 			return false;
178 	}
179 	return true;
180 }
181 EXPORT_SYMBOL(drm_dp_128b132b_lane_channel_eq_done);
182 
183 /* DP 2.0 errata for 128b/132b */
184 bool drm_dp_128b132b_lane_symbol_locked(const u8 link_status[DP_LINK_STATUS_SIZE],
185 					int lane_count)
186 {
187 	u8 lane_status;
188 	int lane;
189 
190 	for (lane = 0; lane < lane_count; lane++) {
191 		lane_status = dp_get_lane_status(link_status, lane);
192 		if (!(lane_status & DP_LANE_SYMBOL_LOCKED))
193 			return false;
194 	}
195 	return true;
196 }
197 EXPORT_SYMBOL(drm_dp_128b132b_lane_symbol_locked);
198 
199 /* DP 2.0 errata for 128b/132b */
200 bool drm_dp_128b132b_eq_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
201 {
202 	u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
203 
204 	return status & DP_128B132B_DPRX_EQ_INTERLANE_ALIGN_DONE;
205 }
206 EXPORT_SYMBOL(drm_dp_128b132b_eq_interlane_align_done);
207 
208 /* DP 2.0 errata for 128b/132b */
209 bool drm_dp_128b132b_cds_interlane_align_done(const u8 link_status[DP_LINK_STATUS_SIZE])
210 {
211 	u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
212 
213 	return status & DP_128B132B_DPRX_CDS_INTERLANE_ALIGN_DONE;
214 }
215 EXPORT_SYMBOL(drm_dp_128b132b_cds_interlane_align_done);
216 
217 /* DP 2.0 errata for 128b/132b */
218 bool drm_dp_128b132b_link_training_failed(const u8 link_status[DP_LINK_STATUS_SIZE])
219 {
220 	u8 status = dp_link_status(link_status, DP_LANE_ALIGN_STATUS_UPDATED);
221 
222 	return status & DP_128B132B_LT_FAILED;
223 }
224 EXPORT_SYMBOL(drm_dp_128b132b_link_training_failed);
225 
226 static int __8b10b_clock_recovery_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
227 {
228 	if (rd_interval > 4)
229 		drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",
230 			    aux->name, rd_interval);
231 
232 	if (rd_interval == 0)
233 		return 100;
234 
235 	return rd_interval * 4 * USEC_PER_MSEC;
236 }
237 
238 static int __8b10b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
239 {
240 	if (rd_interval > 4)
241 		drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x (max 4)\n",
242 			    aux->name, rd_interval);
243 
244 	if (rd_interval == 0)
245 		return 400;
246 
247 	return rd_interval * 4 * USEC_PER_MSEC;
248 }
249 
250 static int __128b132b_channel_eq_delay_us(const struct drm_dp_aux *aux, u8 rd_interval)
251 {
252 	switch (rd_interval) {
253 	default:
254 		drm_dbg_kms(aux->drm_dev, "%s: invalid AUX interval 0x%02x\n",
255 			    aux->name, rd_interval);
256 		fallthrough;
257 	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_400_US:
258 		return 400;
259 	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_4_MS:
260 		return 4000;
261 	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_8_MS:
262 		return 8000;
263 	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_12_MS:
264 		return 12000;
265 	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_16_MS:
266 		return 16000;
267 	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_32_MS:
268 		return 32000;
269 	case DP_128B132B_TRAINING_AUX_RD_INTERVAL_64_MS:
270 		return 64000;
271 	}
272 }
273 
274 /*
275  * The link training delays are different for:
276  *
277  *  - Clock recovery vs. channel equalization
278  *  - DPRX vs. LTTPR
279  *  - 128b/132b vs. 8b/10b
280  *  - DPCD rev 1.3 vs. later
281  *
282  * Get the correct delay in us, reading DPCD if necessary.
283  */
284 static int __read_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
285 			enum drm_dp_phy dp_phy, bool uhbr, bool cr)
286 {
287 	int (*parse)(const struct drm_dp_aux *aux, u8 rd_interval);
288 	unsigned int offset;
289 	u8 rd_interval, mask;
290 
291 	if (dp_phy == DP_PHY_DPRX) {
292 		if (uhbr) {
293 			if (cr)
294 				return 100;
295 
296 			offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL;
297 			mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
298 			parse = __128b132b_channel_eq_delay_us;
299 		} else {
300 			if (cr && dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
301 				return 100;
302 
303 			offset = DP_TRAINING_AUX_RD_INTERVAL;
304 			mask = DP_TRAINING_AUX_RD_MASK;
305 			if (cr)
306 				parse = __8b10b_clock_recovery_delay_us;
307 			else
308 				parse = __8b10b_channel_eq_delay_us;
309 		}
310 	} else {
311 		if (uhbr) {
312 			offset = DP_128B132B_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy);
313 			mask = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
314 			parse = __128b132b_channel_eq_delay_us;
315 		} else {
316 			if (cr)
317 				return 100;
318 
319 			offset = DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy);
320 			mask = DP_TRAINING_AUX_RD_MASK;
321 			parse = __8b10b_channel_eq_delay_us;
322 		}
323 	}
324 
325 	if (offset < DP_RECEIVER_CAP_SIZE) {
326 		rd_interval = dpcd[offset];
327 	} else {
328 		if (drm_dp_dpcd_readb(aux, offset, &rd_interval) != 1) {
329 			drm_dbg_kms(aux->drm_dev, "%s: failed rd interval read\n",
330 				    aux->name);
331 			/* arbitrary default delay */
332 			return 400;
333 		}
334 	}
335 
336 	return parse(aux, rd_interval & mask);
337 }
338 
339 int drm_dp_read_clock_recovery_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
340 				     enum drm_dp_phy dp_phy, bool uhbr)
341 {
342 	return __read_delay(aux, dpcd, dp_phy, uhbr, true);
343 }
344 EXPORT_SYMBOL(drm_dp_read_clock_recovery_delay);
345 
346 int drm_dp_read_channel_eq_delay(struct drm_dp_aux *aux, const u8 dpcd[DP_RECEIVER_CAP_SIZE],
347 				 enum drm_dp_phy dp_phy, bool uhbr)
348 {
349 	return __read_delay(aux, dpcd, dp_phy, uhbr, false);
350 }
351 EXPORT_SYMBOL(drm_dp_read_channel_eq_delay);
352 
353 /* Per DP 2.0 Errata */
354 int drm_dp_128b132b_read_aux_rd_interval(struct drm_dp_aux *aux)
355 {
356 	int unit;
357 	u8 val;
358 
359 	if (drm_dp_dpcd_readb(aux, DP_128B132B_TRAINING_AUX_RD_INTERVAL, &val) != 1) {
360 		drm_err(aux->drm_dev, "%s: failed rd interval read\n",
361 			aux->name);
362 		/* default to max */
363 		val = DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
364 	}
365 
366 	unit = (val & DP_128B132B_TRAINING_AUX_RD_INTERVAL_1MS_UNIT) ? 1 : 2;
367 	val &= DP_128B132B_TRAINING_AUX_RD_INTERVAL_MASK;
368 
369 	return (val + 1) * unit * 1000;
370 }
371 EXPORT_SYMBOL(drm_dp_128b132b_read_aux_rd_interval);
372 
373 void drm_dp_link_train_clock_recovery_delay(const struct drm_dp_aux *aux,
374 					    const u8 dpcd[DP_RECEIVER_CAP_SIZE])
375 {
376 	u8 rd_interval = dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
377 		DP_TRAINING_AUX_RD_MASK;
378 	int delay_us;
379 
380 	if (dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
381 		delay_us = 100;
382 	else
383 		delay_us = __8b10b_clock_recovery_delay_us(aux, rd_interval);
384 
385 	usleep_range(delay_us, delay_us * 2);
386 }
387 EXPORT_SYMBOL(drm_dp_link_train_clock_recovery_delay);
388 
389 static void __drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
390 						 u8 rd_interval)
391 {
392 	int delay_us = __8b10b_channel_eq_delay_us(aux, rd_interval);
393 
394 	usleep_range(delay_us, delay_us * 2);
395 }
396 
397 void drm_dp_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
398 					const u8 dpcd[DP_RECEIVER_CAP_SIZE])
399 {
400 	__drm_dp_link_train_channel_eq_delay(aux,
401 					     dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
402 					     DP_TRAINING_AUX_RD_MASK);
403 }
404 EXPORT_SYMBOL(drm_dp_link_train_channel_eq_delay);
405 
406 /**
407  * drm_dp_phy_name() - Get the name of the given DP PHY
408  * @dp_phy: The DP PHY identifier
409  *
410  * Given the @dp_phy, get a user friendly name of the DP PHY, either "DPRX" or
411  * "LTTPR <N>", or "<INVALID DP PHY>" on errors. The returned string is always
412  * non-NULL and valid.
413  *
414  * Returns: Name of the DP PHY.
415  */
416 const char *drm_dp_phy_name(enum drm_dp_phy dp_phy)
417 {
418 	static const char * const phy_names[] = {
419 		[DP_PHY_DPRX] = "DPRX",
420 		[DP_PHY_LTTPR1] = "LTTPR 1",
421 		[DP_PHY_LTTPR2] = "LTTPR 2",
422 		[DP_PHY_LTTPR3] = "LTTPR 3",
423 		[DP_PHY_LTTPR4] = "LTTPR 4",
424 		[DP_PHY_LTTPR5] = "LTTPR 5",
425 		[DP_PHY_LTTPR6] = "LTTPR 6",
426 		[DP_PHY_LTTPR7] = "LTTPR 7",
427 		[DP_PHY_LTTPR8] = "LTTPR 8",
428 	};
429 
430 	if (dp_phy < 0 || dp_phy >= ARRAY_SIZE(phy_names) ||
431 	    WARN_ON(!phy_names[dp_phy]))
432 		return "<INVALID DP PHY>";
433 
434 	return phy_names[dp_phy];
435 }
436 EXPORT_SYMBOL(drm_dp_phy_name);
437 
438 void drm_dp_lttpr_link_train_clock_recovery_delay(void)
439 {
440 	usleep_range(100, 200);
441 }
442 EXPORT_SYMBOL(drm_dp_lttpr_link_train_clock_recovery_delay);
443 
444 static u8 dp_lttpr_phy_cap(const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE], int r)
445 {
446 	return phy_cap[r - DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1];
447 }
448 
449 void drm_dp_lttpr_link_train_channel_eq_delay(const struct drm_dp_aux *aux,
450 					      const u8 phy_cap[DP_LTTPR_PHY_CAP_SIZE])
451 {
452 	u8 interval = dp_lttpr_phy_cap(phy_cap,
453 				       DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER1) &
454 		      DP_TRAINING_AUX_RD_MASK;
455 
456 	__drm_dp_link_train_channel_eq_delay(aux, interval);
457 }
458 EXPORT_SYMBOL(drm_dp_lttpr_link_train_channel_eq_delay);
459 
460 u8 drm_dp_link_rate_to_bw_code(int link_rate)
461 {
462 	switch (link_rate) {
463 	case 1000000:
464 		return DP_LINK_BW_10;
465 	case 1350000:
466 		return DP_LINK_BW_13_5;
467 	case 2000000:
468 		return DP_LINK_BW_20;
469 	default:
470 		/* Spec says link_bw = link_rate / 0.27Gbps */
471 		return link_rate / 27000;
472 	}
473 }
474 EXPORT_SYMBOL(drm_dp_link_rate_to_bw_code);
475 
476 int drm_dp_bw_code_to_link_rate(u8 link_bw)
477 {
478 	switch (link_bw) {
479 	case DP_LINK_BW_10:
480 		return 1000000;
481 	case DP_LINK_BW_13_5:
482 		return 1350000;
483 	case DP_LINK_BW_20:
484 		return 2000000;
485 	default:
486 		/* Spec says link_rate = link_bw * 0.27Gbps */
487 		return link_bw * 27000;
488 	}
489 }
490 EXPORT_SYMBOL(drm_dp_bw_code_to_link_rate);
491 
492 #define AUX_RETRY_INTERVAL 500 /* us */
493 
494 static inline void
495 drm_dp_dump_access(const struct drm_dp_aux *aux,
496 		   u8 request, uint offset, void *buffer, int ret)
497 {
498 	const char *arrow = request == DP_AUX_NATIVE_READ ? "->" : "<-";
499 
500 	if (ret > 0)
501 		drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d) %*ph\n",
502 			   aux->name, offset, arrow, ret, min(ret, 20), buffer);
503 	else
504 		drm_dbg_dp(aux->drm_dev, "%s: 0x%05x AUX %s (ret=%3d)\n",
505 			   aux->name, offset, arrow, ret);
506 }
507 
508 /**
509  * DOC: dp helpers
510  *
511  * The DisplayPort AUX channel is an abstraction to allow generic, driver-
512  * independent access to AUX functionality. Drivers can take advantage of
513  * this by filling in the fields of the drm_dp_aux structure.
514  *
515  * Transactions are described using a hardware-independent drm_dp_aux_msg
516  * structure, which is passed into a driver's .transfer() implementation.
517  * Both native and I2C-over-AUX transactions are supported.
518  */
519 
520 static int drm_dp_dpcd_access(struct drm_dp_aux *aux, u8 request,
521 			      unsigned int offset, void *buffer, size_t size)
522 {
523 	struct drm_dp_aux_msg msg;
524 	unsigned int retry, native_reply;
525 	int err = 0, ret = 0;
526 
527 	memset(&msg, 0, sizeof(msg));
528 	msg.address = offset;
529 	msg.request = request;
530 	msg.buffer = buffer;
531 	msg.size = size;
532 
533 	mutex_lock(&aux->hw_mutex);
534 
535 	/*
536 	 * The specification doesn't give any recommendation on how often to
537 	 * retry native transactions. We used to retry 7 times like for
538 	 * aux i2c transactions but real world devices this wasn't
539 	 * sufficient, bump to 32 which makes Dell 4k monitors happier.
540 	 */
541 	for (retry = 0; retry < 32; retry++) {
542 		if (ret != 0 && ret != -ETIMEDOUT) {
543 			usleep_range(AUX_RETRY_INTERVAL,
544 				     AUX_RETRY_INTERVAL + 100);
545 		}
546 
547 		ret = aux->transfer(aux, &msg);
548 		if (ret >= 0) {
549 			native_reply = msg.reply & DP_AUX_NATIVE_REPLY_MASK;
550 			if (native_reply == DP_AUX_NATIVE_REPLY_ACK) {
551 				if (ret == size)
552 					goto unlock;
553 
554 				ret = -EPROTO;
555 			} else
556 				ret = -EIO;
557 		}
558 
559 		/*
560 		 * We want the error we return to be the error we received on
561 		 * the first transaction, since we may get a different error the
562 		 * next time we retry
563 		 */
564 		if (!err)
565 			err = ret;
566 	}
567 
568 	drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up. First error: %d\n",
569 		    aux->name, err);
570 	ret = err;
571 
572 unlock:
573 	mutex_unlock(&aux->hw_mutex);
574 	return ret;
575 }
576 
577 /**
578  * drm_dp_dpcd_probe() - probe a given DPCD address with a 1-byte read access
579  * @aux: DisplayPort AUX channel (SST)
580  * @offset: address of the register to probe
581  *
582  * Probe the provided DPCD address by reading 1 byte from it. The function can
583  * be used to trigger some side-effect the read access has, like waking up the
584  * sink, without the need for the read-out value.
585  *
586  * Returns 0 if the read access suceeded, or a negative error code on failure.
587  */
588 int drm_dp_dpcd_probe(struct drm_dp_aux *aux, unsigned int offset)
589 {
590 	u8 buffer;
591 	int ret;
592 
593 	ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, 1);
594 	WARN_ON(ret == 0);
595 
596 	drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, &buffer, ret);
597 
598 	return ret < 0 ? ret : 0;
599 }
600 EXPORT_SYMBOL(drm_dp_dpcd_probe);
601 
602 /**
603  * drm_dp_dpcd_read() - read a series of bytes from the DPCD
604  * @aux: DisplayPort AUX channel (SST or MST)
605  * @offset: address of the (first) register to read
606  * @buffer: buffer to store the register values
607  * @size: number of bytes in @buffer
608  *
609  * Returns the number of bytes transferred on success, or a negative error
610  * code on failure. -EIO is returned if the request was NAKed by the sink or
611  * if the retry count was exceeded. If not all bytes were transferred, this
612  * function returns -EPROTO. Errors from the underlying AUX channel transfer
613  * function, with the exception of -EBUSY (which causes the transaction to
614  * be retried), are propagated to the caller.
615  */
616 ssize_t drm_dp_dpcd_read(struct drm_dp_aux *aux, unsigned int offset,
617 			 void *buffer, size_t size)
618 {
619 	int ret;
620 
621 	/*
622 	 * HP ZR24w corrupts the first DPCD access after entering power save
623 	 * mode. Eg. on a read, the entire buffer will be filled with the same
624 	 * byte. Do a throw away read to avoid corrupting anything we care
625 	 * about. Afterwards things will work correctly until the monitor
626 	 * gets woken up and subsequently re-enters power save mode.
627 	 *
628 	 * The user pressing any button on the monitor is enough to wake it
629 	 * up, so there is no particularly good place to do the workaround.
630 	 * We just have to do it before any DPCD access and hope that the
631 	 * monitor doesn't power down exactly after the throw away read.
632 	 */
633 	if (!aux->is_remote) {
634 		ret = drm_dp_dpcd_probe(aux, DP_DPCD_REV);
635 		if (ret < 0)
636 			return ret;
637 	}
638 
639 	if (aux->is_remote)
640 		ret = drm_dp_mst_dpcd_read(aux, offset, buffer, size);
641 	else
642 		ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_READ, offset,
643 					 buffer, size);
644 
645 	drm_dp_dump_access(aux, DP_AUX_NATIVE_READ, offset, buffer, ret);
646 	return ret;
647 }
648 EXPORT_SYMBOL(drm_dp_dpcd_read);
649 
650 /**
651  * drm_dp_dpcd_write() - write a series of bytes to the DPCD
652  * @aux: DisplayPort AUX channel (SST or MST)
653  * @offset: address of the (first) register to write
654  * @buffer: buffer containing the values to write
655  * @size: number of bytes in @buffer
656  *
657  * Returns the number of bytes transferred on success, or a negative error
658  * code on failure. -EIO is returned if the request was NAKed by the sink or
659  * if the retry count was exceeded. If not all bytes were transferred, this
660  * function returns -EPROTO. Errors from the underlying AUX channel transfer
661  * function, with the exception of -EBUSY (which causes the transaction to
662  * be retried), are propagated to the caller.
663  */
664 ssize_t drm_dp_dpcd_write(struct drm_dp_aux *aux, unsigned int offset,
665 			  void *buffer, size_t size)
666 {
667 	int ret;
668 
669 	if (aux->is_remote)
670 		ret = drm_dp_mst_dpcd_write(aux, offset, buffer, size);
671 	else
672 		ret = drm_dp_dpcd_access(aux, DP_AUX_NATIVE_WRITE, offset,
673 					 buffer, size);
674 
675 	drm_dp_dump_access(aux, DP_AUX_NATIVE_WRITE, offset, buffer, ret);
676 	return ret;
677 }
678 EXPORT_SYMBOL(drm_dp_dpcd_write);
679 
680 /**
681  * drm_dp_dpcd_read_link_status() - read DPCD link status (bytes 0x202-0x207)
682  * @aux: DisplayPort AUX channel
683  * @status: buffer to store the link status in (must be at least 6 bytes)
684  *
685  * Returns the number of bytes transferred on success or a negative error
686  * code on failure.
687  */
688 int drm_dp_dpcd_read_link_status(struct drm_dp_aux *aux,
689 				 u8 status[DP_LINK_STATUS_SIZE])
690 {
691 	return drm_dp_dpcd_read(aux, DP_LANE0_1_STATUS, status,
692 				DP_LINK_STATUS_SIZE);
693 }
694 EXPORT_SYMBOL(drm_dp_dpcd_read_link_status);
695 
696 /**
697  * drm_dp_dpcd_read_phy_link_status - get the link status information for a DP PHY
698  * @aux: DisplayPort AUX channel
699  * @dp_phy: the DP PHY to get the link status for
700  * @link_status: buffer to return the status in
701  *
702  * Fetch the AUX DPCD registers for the DPRX or an LTTPR PHY link status. The
703  * layout of the returned @link_status matches the DPCD register layout of the
704  * DPRX PHY link status.
705  *
706  * Returns 0 if the information was read successfully or a negative error code
707  * on failure.
708  */
709 int drm_dp_dpcd_read_phy_link_status(struct drm_dp_aux *aux,
710 				     enum drm_dp_phy dp_phy,
711 				     u8 link_status[DP_LINK_STATUS_SIZE])
712 {
713 	int ret;
714 
715 	if (dp_phy == DP_PHY_DPRX) {
716 		ret = drm_dp_dpcd_read(aux,
717 				       DP_LANE0_1_STATUS,
718 				       link_status,
719 				       DP_LINK_STATUS_SIZE);
720 
721 		if (ret < 0)
722 			return ret;
723 
724 		WARN_ON(ret != DP_LINK_STATUS_SIZE);
725 
726 		return 0;
727 	}
728 
729 	ret = drm_dp_dpcd_read(aux,
730 			       DP_LANE0_1_STATUS_PHY_REPEATER(dp_phy),
731 			       link_status,
732 			       DP_LINK_STATUS_SIZE - 1);
733 
734 	if (ret < 0)
735 		return ret;
736 
737 	WARN_ON(ret != DP_LINK_STATUS_SIZE - 1);
738 
739 	/* Convert the LTTPR to the sink PHY link status layout */
740 	memmove(&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS + 1],
741 		&link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS],
742 		DP_LINK_STATUS_SIZE - (DP_SINK_STATUS - DP_LANE0_1_STATUS) - 1);
743 	link_status[DP_SINK_STATUS - DP_LANE0_1_STATUS] = 0;
744 
745 	return 0;
746 }
747 EXPORT_SYMBOL(drm_dp_dpcd_read_phy_link_status);
748 
749 static bool is_edid_digital_input_dp(const struct drm_edid *drm_edid)
750 {
751 	/* FIXME: get rid of drm_edid_raw() */
752 	const struct edid *edid = drm_edid_raw(drm_edid);
753 
754 	return edid && edid->revision >= 4 &&
755 		edid->input & DRM_EDID_INPUT_DIGITAL &&
756 		(edid->input & DRM_EDID_DIGITAL_TYPE_MASK) == DRM_EDID_DIGITAL_TYPE_DP;
757 }
758 
759 /**
760  * drm_dp_downstream_is_type() - is the downstream facing port of certain type?
761  * @dpcd: DisplayPort configuration data
762  * @port_cap: port capabilities
763  * @type: port type to be checked. Can be:
764  * 	  %DP_DS_PORT_TYPE_DP, %DP_DS_PORT_TYPE_VGA, %DP_DS_PORT_TYPE_DVI,
765  * 	  %DP_DS_PORT_TYPE_HDMI, %DP_DS_PORT_TYPE_NON_EDID,
766  *	  %DP_DS_PORT_TYPE_DP_DUALMODE or %DP_DS_PORT_TYPE_WIRELESS.
767  *
768  * Caveat: Only works with DPCD 1.1+ port caps.
769  *
770  * Returns: whether the downstream facing port matches the type.
771  */
772 bool drm_dp_downstream_is_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
773 			       const u8 port_cap[4], u8 type)
774 {
775 	return drm_dp_is_branch(dpcd) &&
776 		dpcd[DP_DPCD_REV] >= 0x11 &&
777 		(port_cap[0] & DP_DS_PORT_TYPE_MASK) == type;
778 }
779 EXPORT_SYMBOL(drm_dp_downstream_is_type);
780 
781 /**
782  * drm_dp_downstream_is_tmds() - is the downstream facing port TMDS?
783  * @dpcd: DisplayPort configuration data
784  * @port_cap: port capabilities
785  * @drm_edid: EDID
786  *
787  * Returns: whether the downstream facing port is TMDS (HDMI/DVI).
788  */
789 bool drm_dp_downstream_is_tmds(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
790 			       const u8 port_cap[4],
791 			       const struct drm_edid *drm_edid)
792 {
793 	if (dpcd[DP_DPCD_REV] < 0x11) {
794 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
795 		case DP_DWN_STRM_PORT_TYPE_TMDS:
796 			return true;
797 		default:
798 			return false;
799 		}
800 	}
801 
802 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
803 	case DP_DS_PORT_TYPE_DP_DUALMODE:
804 		if (is_edid_digital_input_dp(drm_edid))
805 			return false;
806 		fallthrough;
807 	case DP_DS_PORT_TYPE_DVI:
808 	case DP_DS_PORT_TYPE_HDMI:
809 		return true;
810 	default:
811 		return false;
812 	}
813 }
814 EXPORT_SYMBOL(drm_dp_downstream_is_tmds);
815 
816 /**
817  * drm_dp_send_real_edid_checksum() - send back real edid checksum value
818  * @aux: DisplayPort AUX channel
819  * @real_edid_checksum: real edid checksum for the last block
820  *
821  * Returns:
822  * True on success
823  */
824 bool drm_dp_send_real_edid_checksum(struct drm_dp_aux *aux,
825 				    u8 real_edid_checksum)
826 {
827 	u8 link_edid_read = 0, auto_test_req = 0, test_resp = 0;
828 
829 	if (drm_dp_dpcd_read(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
830 			     &auto_test_req, 1) < 1) {
831 		drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
832 			aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
833 		return false;
834 	}
835 	auto_test_req &= DP_AUTOMATED_TEST_REQUEST;
836 
837 	if (drm_dp_dpcd_read(aux, DP_TEST_REQUEST, &link_edid_read, 1) < 1) {
838 		drm_err(aux->drm_dev, "%s: DPCD failed read at register 0x%x\n",
839 			aux->name, DP_TEST_REQUEST);
840 		return false;
841 	}
842 	link_edid_read &= DP_TEST_LINK_EDID_READ;
843 
844 	if (!auto_test_req || !link_edid_read) {
845 		drm_dbg_kms(aux->drm_dev, "%s: Source DUT does not support TEST_EDID_READ\n",
846 			    aux->name);
847 		return false;
848 	}
849 
850 	if (drm_dp_dpcd_write(aux, DP_DEVICE_SERVICE_IRQ_VECTOR,
851 			      &auto_test_req, 1) < 1) {
852 		drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
853 			aux->name, DP_DEVICE_SERVICE_IRQ_VECTOR);
854 		return false;
855 	}
856 
857 	/* send back checksum for the last edid extension block data */
858 	if (drm_dp_dpcd_write(aux, DP_TEST_EDID_CHECKSUM,
859 			      &real_edid_checksum, 1) < 1) {
860 		drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
861 			aux->name, DP_TEST_EDID_CHECKSUM);
862 		return false;
863 	}
864 
865 	test_resp |= DP_TEST_EDID_CHECKSUM_WRITE;
866 	if (drm_dp_dpcd_write(aux, DP_TEST_RESPONSE, &test_resp, 1) < 1) {
867 		drm_err(aux->drm_dev, "%s: DPCD failed write at register 0x%x\n",
868 			aux->name, DP_TEST_RESPONSE);
869 		return false;
870 	}
871 
872 	return true;
873 }
874 EXPORT_SYMBOL(drm_dp_send_real_edid_checksum);
875 
876 static u8 drm_dp_downstream_port_count(const u8 dpcd[DP_RECEIVER_CAP_SIZE])
877 {
878 	u8 port_count = dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_PORT_COUNT_MASK;
879 
880 	if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE && port_count > 4)
881 		port_count = 4;
882 
883 	return port_count;
884 }
885 
886 static int drm_dp_read_extended_dpcd_caps(struct drm_dp_aux *aux,
887 					  u8 dpcd[DP_RECEIVER_CAP_SIZE])
888 {
889 	u8 dpcd_ext[DP_RECEIVER_CAP_SIZE];
890 	int ret;
891 
892 	/*
893 	 * Prior to DP1.3 the bit represented by
894 	 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
895 	 * If it is set DP_DPCD_REV at 0000h could be at a value less than
896 	 * the true capability of the panel. The only way to check is to
897 	 * then compare 0000h and 2200h.
898 	 */
899 	if (!(dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
900 	      DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT))
901 		return 0;
902 
903 	ret = drm_dp_dpcd_read(aux, DP_DP13_DPCD_REV, &dpcd_ext,
904 			       sizeof(dpcd_ext));
905 	if (ret < 0)
906 		return ret;
907 	if (ret != sizeof(dpcd_ext))
908 		return -EIO;
909 
910 	if (dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) {
911 		drm_dbg_kms(aux->drm_dev,
912 			    "%s: Extended DPCD rev less than base DPCD rev (%d > %d)\n",
913 			    aux->name, dpcd[DP_DPCD_REV], dpcd_ext[DP_DPCD_REV]);
914 		return 0;
915 	}
916 
917 	if (!memcmp(dpcd, dpcd_ext, sizeof(dpcd_ext)))
918 		return 0;
919 
920 	drm_dbg_kms(aux->drm_dev, "%s: Base DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
921 
922 	memcpy(dpcd, dpcd_ext, sizeof(dpcd_ext));
923 
924 	return 0;
925 }
926 
927 /**
928  * drm_dp_read_dpcd_caps() - read DPCD caps and extended DPCD caps if
929  * available
930  * @aux: DisplayPort AUX channel
931  * @dpcd: Buffer to store the resulting DPCD in
932  *
933  * Attempts to read the base DPCD caps for @aux. Additionally, this function
934  * checks for and reads the extended DPRX caps (%DP_DP13_DPCD_REV) if
935  * present.
936  *
937  * Returns: %0 if the DPCD was read successfully, negative error code
938  * otherwise.
939  */
940 int drm_dp_read_dpcd_caps(struct drm_dp_aux *aux,
941 			  u8 dpcd[DP_RECEIVER_CAP_SIZE])
942 {
943 	int ret;
944 
945 	ret = drm_dp_dpcd_read(aux, DP_DPCD_REV, dpcd, DP_RECEIVER_CAP_SIZE);
946 	if (ret < 0)
947 		return ret;
948 	if (ret != DP_RECEIVER_CAP_SIZE || dpcd[DP_DPCD_REV] == 0)
949 		return -EIO;
950 
951 	ret = drm_dp_read_extended_dpcd_caps(aux, dpcd);
952 	if (ret < 0)
953 		return ret;
954 
955 	drm_dbg_kms(aux->drm_dev, "%s: DPCD: %*ph\n", aux->name, DP_RECEIVER_CAP_SIZE, dpcd);
956 
957 	return ret;
958 }
959 EXPORT_SYMBOL(drm_dp_read_dpcd_caps);
960 
961 /**
962  * drm_dp_read_downstream_info() - read DPCD downstream port info if available
963  * @aux: DisplayPort AUX channel
964  * @dpcd: A cached copy of the port's DPCD
965  * @downstream_ports: buffer to store the downstream port info in
966  *
967  * See also:
968  * drm_dp_downstream_max_clock()
969  * drm_dp_downstream_max_bpc()
970  *
971  * Returns: 0 if either the downstream port info was read successfully or
972  * there was no downstream info to read, or a negative error code otherwise.
973  */
974 int drm_dp_read_downstream_info(struct drm_dp_aux *aux,
975 				const u8 dpcd[DP_RECEIVER_CAP_SIZE],
976 				u8 downstream_ports[DP_MAX_DOWNSTREAM_PORTS])
977 {
978 	int ret;
979 	u8 len;
980 
981 	memset(downstream_ports, 0, DP_MAX_DOWNSTREAM_PORTS);
982 
983 	/* No downstream info to read */
984 	if (!drm_dp_is_branch(dpcd) || dpcd[DP_DPCD_REV] == DP_DPCD_REV_10)
985 		return 0;
986 
987 	/* Some branches advertise having 0 downstream ports, despite also advertising they have a
988 	 * downstream port present. The DP spec isn't clear on if this is allowed or not, but since
989 	 * some branches do it we need to handle it regardless.
990 	 */
991 	len = drm_dp_downstream_port_count(dpcd);
992 	if (!len)
993 		return 0;
994 
995 	if (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE)
996 		len *= 4;
997 
998 	ret = drm_dp_dpcd_read(aux, DP_DOWNSTREAM_PORT_0, downstream_ports, len);
999 	if (ret < 0)
1000 		return ret;
1001 	if (ret != len)
1002 		return -EIO;
1003 
1004 	drm_dbg_kms(aux->drm_dev, "%s: DPCD DFP: %*ph\n", aux->name, len, downstream_ports);
1005 
1006 	return 0;
1007 }
1008 EXPORT_SYMBOL(drm_dp_read_downstream_info);
1009 
1010 /**
1011  * drm_dp_downstream_max_dotclock() - extract downstream facing port max dot clock
1012  * @dpcd: DisplayPort configuration data
1013  * @port_cap: port capabilities
1014  *
1015  * Returns: Downstream facing port max dot clock in kHz on success,
1016  * or 0 if max clock not defined
1017  */
1018 int drm_dp_downstream_max_dotclock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1019 				   const u8 port_cap[4])
1020 {
1021 	if (!drm_dp_is_branch(dpcd))
1022 		return 0;
1023 
1024 	if (dpcd[DP_DPCD_REV] < 0x11)
1025 		return 0;
1026 
1027 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1028 	case DP_DS_PORT_TYPE_VGA:
1029 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1030 			return 0;
1031 		return port_cap[1] * 8000;
1032 	default:
1033 		return 0;
1034 	}
1035 }
1036 EXPORT_SYMBOL(drm_dp_downstream_max_dotclock);
1037 
1038 /**
1039  * drm_dp_downstream_max_tmds_clock() - extract downstream facing port max TMDS clock
1040  * @dpcd: DisplayPort configuration data
1041  * @port_cap: port capabilities
1042  * @drm_edid: EDID
1043  *
1044  * Returns: HDMI/DVI downstream facing port max TMDS clock in kHz on success,
1045  * or 0 if max TMDS clock not defined
1046  */
1047 int drm_dp_downstream_max_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1048 				     const u8 port_cap[4],
1049 				     const struct drm_edid *drm_edid)
1050 {
1051 	if (!drm_dp_is_branch(dpcd))
1052 		return 0;
1053 
1054 	if (dpcd[DP_DPCD_REV] < 0x11) {
1055 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1056 		case DP_DWN_STRM_PORT_TYPE_TMDS:
1057 			return 165000;
1058 		default:
1059 			return 0;
1060 		}
1061 	}
1062 
1063 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1064 	case DP_DS_PORT_TYPE_DP_DUALMODE:
1065 		if (is_edid_digital_input_dp(drm_edid))
1066 			return 0;
1067 		/*
1068 		 * It's left up to the driver to check the
1069 		 * DP dual mode adapter's max TMDS clock.
1070 		 *
1071 		 * Unfortunately it looks like branch devices
1072 		 * may not fordward that the DP dual mode i2c
1073 		 * access so we just usually get i2c nak :(
1074 		 */
1075 		fallthrough;
1076 	case DP_DS_PORT_TYPE_HDMI:
1077 		 /*
1078 		  * We should perhaps assume 165 MHz when detailed cap
1079 		  * info is not available. But looks like many typical
1080 		  * branch devices fall into that category and so we'd
1081 		  * probably end up with users complaining that they can't
1082 		  * get high resolution modes with their favorite dongle.
1083 		  *
1084 		  * So let's limit to 300 MHz instead since DPCD 1.4
1085 		  * HDMI 2.0 DFPs are required to have the detailed cap
1086 		  * info. So it's more likely we're dealing with a HDMI 1.4
1087 		  * compatible* device here.
1088 		  */
1089 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1090 			return 300000;
1091 		return port_cap[1] * 2500;
1092 	case DP_DS_PORT_TYPE_DVI:
1093 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1094 			return 165000;
1095 		/* FIXME what to do about DVI dual link? */
1096 		return port_cap[1] * 2500;
1097 	default:
1098 		return 0;
1099 	}
1100 }
1101 EXPORT_SYMBOL(drm_dp_downstream_max_tmds_clock);
1102 
1103 /**
1104  * drm_dp_downstream_min_tmds_clock() - extract downstream facing port min TMDS clock
1105  * @dpcd: DisplayPort configuration data
1106  * @port_cap: port capabilities
1107  * @drm_edid: EDID
1108  *
1109  * Returns: HDMI/DVI downstream facing port min TMDS clock in kHz on success,
1110  * or 0 if max TMDS clock not defined
1111  */
1112 int drm_dp_downstream_min_tmds_clock(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1113 				     const u8 port_cap[4],
1114 				     const struct drm_edid *drm_edid)
1115 {
1116 	if (!drm_dp_is_branch(dpcd))
1117 		return 0;
1118 
1119 	if (dpcd[DP_DPCD_REV] < 0x11) {
1120 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1121 		case DP_DWN_STRM_PORT_TYPE_TMDS:
1122 			return 25000;
1123 		default:
1124 			return 0;
1125 		}
1126 	}
1127 
1128 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1129 	case DP_DS_PORT_TYPE_DP_DUALMODE:
1130 		if (is_edid_digital_input_dp(drm_edid))
1131 			return 0;
1132 		fallthrough;
1133 	case DP_DS_PORT_TYPE_DVI:
1134 	case DP_DS_PORT_TYPE_HDMI:
1135 		/*
1136 		 * Unclear whether the protocol converter could
1137 		 * utilize pixel replication. Assume it won't.
1138 		 */
1139 		return 25000;
1140 	default:
1141 		return 0;
1142 	}
1143 }
1144 EXPORT_SYMBOL(drm_dp_downstream_min_tmds_clock);
1145 
1146 /**
1147  * drm_dp_downstream_max_bpc() - extract downstream facing port max
1148  *                               bits per component
1149  * @dpcd: DisplayPort configuration data
1150  * @port_cap: downstream facing port capabilities
1151  * @drm_edid: EDID
1152  *
1153  * Returns: Max bpc on success or 0 if max bpc not defined
1154  */
1155 int drm_dp_downstream_max_bpc(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1156 			      const u8 port_cap[4],
1157 			      const struct drm_edid *drm_edid)
1158 {
1159 	if (!drm_dp_is_branch(dpcd))
1160 		return 0;
1161 
1162 	if (dpcd[DP_DPCD_REV] < 0x11) {
1163 		switch (dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_TYPE_MASK) {
1164 		case DP_DWN_STRM_PORT_TYPE_DP:
1165 			return 0;
1166 		default:
1167 			return 8;
1168 		}
1169 	}
1170 
1171 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1172 	case DP_DS_PORT_TYPE_DP:
1173 		return 0;
1174 	case DP_DS_PORT_TYPE_DP_DUALMODE:
1175 		if (is_edid_digital_input_dp(drm_edid))
1176 			return 0;
1177 		fallthrough;
1178 	case DP_DS_PORT_TYPE_HDMI:
1179 	case DP_DS_PORT_TYPE_DVI:
1180 	case DP_DS_PORT_TYPE_VGA:
1181 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1182 			return 8;
1183 
1184 		switch (port_cap[2] & DP_DS_MAX_BPC_MASK) {
1185 		case DP_DS_8BPC:
1186 			return 8;
1187 		case DP_DS_10BPC:
1188 			return 10;
1189 		case DP_DS_12BPC:
1190 			return 12;
1191 		case DP_DS_16BPC:
1192 			return 16;
1193 		default:
1194 			return 8;
1195 		}
1196 		break;
1197 	default:
1198 		return 8;
1199 	}
1200 }
1201 EXPORT_SYMBOL(drm_dp_downstream_max_bpc);
1202 
1203 /**
1204  * drm_dp_downstream_420_passthrough() - determine downstream facing port
1205  *                                       YCbCr 4:2:0 pass-through capability
1206  * @dpcd: DisplayPort configuration data
1207  * @port_cap: downstream facing port capabilities
1208  *
1209  * Returns: whether the downstream facing port can pass through YCbCr 4:2:0
1210  */
1211 bool drm_dp_downstream_420_passthrough(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1212 				       const u8 port_cap[4])
1213 {
1214 	if (!drm_dp_is_branch(dpcd))
1215 		return false;
1216 
1217 	if (dpcd[DP_DPCD_REV] < 0x13)
1218 		return false;
1219 
1220 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1221 	case DP_DS_PORT_TYPE_DP:
1222 		return true;
1223 	case DP_DS_PORT_TYPE_HDMI:
1224 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1225 			return false;
1226 
1227 		return port_cap[3] & DP_DS_HDMI_YCBCR420_PASS_THROUGH;
1228 	default:
1229 		return false;
1230 	}
1231 }
1232 EXPORT_SYMBOL(drm_dp_downstream_420_passthrough);
1233 
1234 /**
1235  * drm_dp_downstream_444_to_420_conversion() - determine downstream facing port
1236  *                                             YCbCr 4:4:4->4:2:0 conversion capability
1237  * @dpcd: DisplayPort configuration data
1238  * @port_cap: downstream facing port capabilities
1239  *
1240  * Returns: whether the downstream facing port can convert YCbCr 4:4:4 to 4:2:0
1241  */
1242 bool drm_dp_downstream_444_to_420_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1243 					     const u8 port_cap[4])
1244 {
1245 	if (!drm_dp_is_branch(dpcd))
1246 		return false;
1247 
1248 	if (dpcd[DP_DPCD_REV] < 0x13)
1249 		return false;
1250 
1251 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1252 	case DP_DS_PORT_TYPE_HDMI:
1253 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1254 			return false;
1255 
1256 		return port_cap[3] & DP_DS_HDMI_YCBCR444_TO_420_CONV;
1257 	default:
1258 		return false;
1259 	}
1260 }
1261 EXPORT_SYMBOL(drm_dp_downstream_444_to_420_conversion);
1262 
1263 /**
1264  * drm_dp_downstream_rgb_to_ycbcr_conversion() - determine downstream facing port
1265  *                                               RGB->YCbCr conversion capability
1266  * @dpcd: DisplayPort configuration data
1267  * @port_cap: downstream facing port capabilities
1268  * @color_spc: Colorspace for which conversion cap is sought
1269  *
1270  * Returns: whether the downstream facing port can convert RGB->YCbCr for a given
1271  * colorspace.
1272  */
1273 bool drm_dp_downstream_rgb_to_ycbcr_conversion(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1274 					       const u8 port_cap[4],
1275 					       u8 color_spc)
1276 {
1277 	if (!drm_dp_is_branch(dpcd))
1278 		return false;
1279 
1280 	if (dpcd[DP_DPCD_REV] < 0x13)
1281 		return false;
1282 
1283 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1284 	case DP_DS_PORT_TYPE_HDMI:
1285 		if ((dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DETAILED_CAP_INFO_AVAILABLE) == 0)
1286 			return false;
1287 
1288 		return port_cap[3] & color_spc;
1289 	default:
1290 		return false;
1291 	}
1292 }
1293 EXPORT_SYMBOL(drm_dp_downstream_rgb_to_ycbcr_conversion);
1294 
1295 /**
1296  * drm_dp_downstream_mode() - return a mode for downstream facing port
1297  * @dev: DRM device
1298  * @dpcd: DisplayPort configuration data
1299  * @port_cap: port capabilities
1300  *
1301  * Provides a suitable mode for downstream facing ports without EDID.
1302  *
1303  * Returns: A new drm_display_mode on success or NULL on failure
1304  */
1305 struct drm_display_mode *
1306 drm_dp_downstream_mode(struct drm_device *dev,
1307 		       const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1308 		       const u8 port_cap[4])
1309 
1310 {
1311 	u8 vic;
1312 
1313 	if (!drm_dp_is_branch(dpcd))
1314 		return NULL;
1315 
1316 	if (dpcd[DP_DPCD_REV] < 0x11)
1317 		return NULL;
1318 
1319 	switch (port_cap[0] & DP_DS_PORT_TYPE_MASK) {
1320 	case DP_DS_PORT_TYPE_NON_EDID:
1321 		switch (port_cap[0] & DP_DS_NON_EDID_MASK) {
1322 		case DP_DS_NON_EDID_720x480i_60:
1323 			vic = 6;
1324 			break;
1325 		case DP_DS_NON_EDID_720x480i_50:
1326 			vic = 21;
1327 			break;
1328 		case DP_DS_NON_EDID_1920x1080i_60:
1329 			vic = 5;
1330 			break;
1331 		case DP_DS_NON_EDID_1920x1080i_50:
1332 			vic = 20;
1333 			break;
1334 		case DP_DS_NON_EDID_1280x720_60:
1335 			vic = 4;
1336 			break;
1337 		case DP_DS_NON_EDID_1280x720_50:
1338 			vic = 19;
1339 			break;
1340 		default:
1341 			return NULL;
1342 		}
1343 		return drm_display_mode_from_cea_vic(dev, vic);
1344 	default:
1345 		return NULL;
1346 	}
1347 }
1348 EXPORT_SYMBOL(drm_dp_downstream_mode);
1349 
1350 /**
1351  * drm_dp_downstream_id() - identify branch device
1352  * @aux: DisplayPort AUX channel
1353  * @id: DisplayPort branch device id
1354  *
1355  * Returns branch device id on success or NULL on failure
1356  */
1357 int drm_dp_downstream_id(struct drm_dp_aux *aux, char id[6])
1358 {
1359 	return drm_dp_dpcd_read(aux, DP_BRANCH_ID, id, 6);
1360 }
1361 EXPORT_SYMBOL(drm_dp_downstream_id);
1362 
1363 /**
1364  * drm_dp_downstream_debug() - debug DP branch devices
1365  * @m: pointer for debugfs file
1366  * @dpcd: DisplayPort configuration data
1367  * @port_cap: port capabilities
1368  * @drm_edid: EDID
1369  * @aux: DisplayPort AUX channel
1370  *
1371  */
1372 void drm_dp_downstream_debug(struct seq_file *m,
1373 			     const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1374 			     const u8 port_cap[4],
1375 			     const struct drm_edid *drm_edid,
1376 			     struct drm_dp_aux *aux)
1377 {
1378 	bool detailed_cap_info = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1379 				 DP_DETAILED_CAP_INFO_AVAILABLE;
1380 	int clk;
1381 	int bpc;
1382 	char id[7];
1383 	int len;
1384 	uint8_t rev[2];
1385 	int type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1386 	bool branch_device = drm_dp_is_branch(dpcd);
1387 
1388 	seq_printf(m, "\tDP branch device present: %s\n",
1389 		   str_yes_no(branch_device));
1390 
1391 	if (!branch_device)
1392 		return;
1393 
1394 	switch (type) {
1395 	case DP_DS_PORT_TYPE_DP:
1396 		seq_puts(m, "\t\tType: DisplayPort\n");
1397 		break;
1398 	case DP_DS_PORT_TYPE_VGA:
1399 		seq_puts(m, "\t\tType: VGA\n");
1400 		break;
1401 	case DP_DS_PORT_TYPE_DVI:
1402 		seq_puts(m, "\t\tType: DVI\n");
1403 		break;
1404 	case DP_DS_PORT_TYPE_HDMI:
1405 		seq_puts(m, "\t\tType: HDMI\n");
1406 		break;
1407 	case DP_DS_PORT_TYPE_NON_EDID:
1408 		seq_puts(m, "\t\tType: others without EDID support\n");
1409 		break;
1410 	case DP_DS_PORT_TYPE_DP_DUALMODE:
1411 		seq_puts(m, "\t\tType: DP++\n");
1412 		break;
1413 	case DP_DS_PORT_TYPE_WIRELESS:
1414 		seq_puts(m, "\t\tType: Wireless\n");
1415 		break;
1416 	default:
1417 		seq_puts(m, "\t\tType: N/A\n");
1418 	}
1419 
1420 	memset(id, 0, sizeof(id));
1421 	drm_dp_downstream_id(aux, id);
1422 	seq_printf(m, "\t\tID: %s\n", id);
1423 
1424 	len = drm_dp_dpcd_read(aux, DP_BRANCH_HW_REV, &rev[0], 1);
1425 	if (len > 0)
1426 		seq_printf(m, "\t\tHW: %d.%d\n",
1427 			   (rev[0] & 0xf0) >> 4, rev[0] & 0xf);
1428 
1429 	len = drm_dp_dpcd_read(aux, DP_BRANCH_SW_REV, rev, 2);
1430 	if (len > 0)
1431 		seq_printf(m, "\t\tSW: %d.%d\n", rev[0], rev[1]);
1432 
1433 	if (detailed_cap_info) {
1434 		clk = drm_dp_downstream_max_dotclock(dpcd, port_cap);
1435 		if (clk > 0)
1436 			seq_printf(m, "\t\tMax dot clock: %d kHz\n", clk);
1437 
1438 		clk = drm_dp_downstream_max_tmds_clock(dpcd, port_cap, drm_edid);
1439 		if (clk > 0)
1440 			seq_printf(m, "\t\tMax TMDS clock: %d kHz\n", clk);
1441 
1442 		clk = drm_dp_downstream_min_tmds_clock(dpcd, port_cap, drm_edid);
1443 		if (clk > 0)
1444 			seq_printf(m, "\t\tMin TMDS clock: %d kHz\n", clk);
1445 
1446 		bpc = drm_dp_downstream_max_bpc(dpcd, port_cap, drm_edid);
1447 
1448 		if (bpc > 0)
1449 			seq_printf(m, "\t\tMax bpc: %d\n", bpc);
1450 	}
1451 }
1452 EXPORT_SYMBOL(drm_dp_downstream_debug);
1453 
1454 /**
1455  * drm_dp_subconnector_type() - get DP branch device type
1456  * @dpcd: DisplayPort configuration data
1457  * @port_cap: port capabilities
1458  */
1459 enum drm_mode_subconnector
1460 drm_dp_subconnector_type(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1461 			 const u8 port_cap[4])
1462 {
1463 	int type;
1464 	if (!drm_dp_is_branch(dpcd))
1465 		return DRM_MODE_SUBCONNECTOR_Native;
1466 	/* DP 1.0 approach */
1467 	if (dpcd[DP_DPCD_REV] == DP_DPCD_REV_10) {
1468 		type = dpcd[DP_DOWNSTREAMPORT_PRESENT] &
1469 		       DP_DWN_STRM_PORT_TYPE_MASK;
1470 
1471 		switch (type) {
1472 		case DP_DWN_STRM_PORT_TYPE_TMDS:
1473 			/* Can be HDMI or DVI-D, DVI-D is a safer option */
1474 			return DRM_MODE_SUBCONNECTOR_DVID;
1475 		case DP_DWN_STRM_PORT_TYPE_ANALOG:
1476 			/* Can be VGA or DVI-A, VGA is more popular */
1477 			return DRM_MODE_SUBCONNECTOR_VGA;
1478 		case DP_DWN_STRM_PORT_TYPE_DP:
1479 			return DRM_MODE_SUBCONNECTOR_DisplayPort;
1480 		case DP_DWN_STRM_PORT_TYPE_OTHER:
1481 		default:
1482 			return DRM_MODE_SUBCONNECTOR_Unknown;
1483 		}
1484 	}
1485 	type = port_cap[0] & DP_DS_PORT_TYPE_MASK;
1486 
1487 	switch (type) {
1488 	case DP_DS_PORT_TYPE_DP:
1489 	case DP_DS_PORT_TYPE_DP_DUALMODE:
1490 		return DRM_MODE_SUBCONNECTOR_DisplayPort;
1491 	case DP_DS_PORT_TYPE_VGA:
1492 		return DRM_MODE_SUBCONNECTOR_VGA;
1493 	case DP_DS_PORT_TYPE_DVI:
1494 		return DRM_MODE_SUBCONNECTOR_DVID;
1495 	case DP_DS_PORT_TYPE_HDMI:
1496 		return DRM_MODE_SUBCONNECTOR_HDMIA;
1497 	case DP_DS_PORT_TYPE_WIRELESS:
1498 		return DRM_MODE_SUBCONNECTOR_Wireless;
1499 	case DP_DS_PORT_TYPE_NON_EDID:
1500 	default:
1501 		return DRM_MODE_SUBCONNECTOR_Unknown;
1502 	}
1503 }
1504 EXPORT_SYMBOL(drm_dp_subconnector_type);
1505 
1506 /**
1507  * drm_dp_set_subconnector_property - set subconnector for DP connector
1508  * @connector: connector to set property on
1509  * @status: connector status
1510  * @dpcd: DisplayPort configuration data
1511  * @port_cap: port capabilities
1512  *
1513  * Called by a driver on every detect event.
1514  */
1515 void drm_dp_set_subconnector_property(struct drm_connector *connector,
1516 				      enum drm_connector_status status,
1517 				      const u8 *dpcd,
1518 				      const u8 port_cap[4])
1519 {
1520 	enum drm_mode_subconnector subconnector = DRM_MODE_SUBCONNECTOR_Unknown;
1521 
1522 	if (status == connector_status_connected)
1523 		subconnector = drm_dp_subconnector_type(dpcd, port_cap);
1524 	drm_object_property_set_value(&connector->base,
1525 			connector->dev->mode_config.dp_subconnector_property,
1526 			subconnector);
1527 }
1528 EXPORT_SYMBOL(drm_dp_set_subconnector_property);
1529 
1530 /**
1531  * drm_dp_read_sink_count_cap() - Check whether a given connector has a valid sink
1532  * count
1533  * @connector: The DRM connector to check
1534  * @dpcd: A cached copy of the connector's DPCD RX capabilities
1535  * @desc: A cached copy of the connector's DP descriptor
1536  *
1537  * See also: drm_dp_read_sink_count()
1538  *
1539  * Returns: %True if the (e)DP connector has a valid sink count that should
1540  * be probed, %false otherwise.
1541  */
1542 bool drm_dp_read_sink_count_cap(struct drm_connector *connector,
1543 				const u8 dpcd[DP_RECEIVER_CAP_SIZE],
1544 				const struct drm_dp_desc *desc)
1545 {
1546 	/* Some eDP panels don't set a valid value for the sink count */
1547 	return connector->connector_type != DRM_MODE_CONNECTOR_eDP &&
1548 		dpcd[DP_DPCD_REV] >= DP_DPCD_REV_11 &&
1549 		dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT &&
1550 		!drm_dp_has_quirk(desc, DP_DPCD_QUIRK_NO_SINK_COUNT);
1551 }
1552 EXPORT_SYMBOL(drm_dp_read_sink_count_cap);
1553 
1554 /**
1555  * drm_dp_read_sink_count() - Retrieve the sink count for a given sink
1556  * @aux: The DP AUX channel to use
1557  *
1558  * See also: drm_dp_read_sink_count_cap()
1559  *
1560  * Returns: The current sink count reported by @aux, or a negative error code
1561  * otherwise.
1562  */
1563 int drm_dp_read_sink_count(struct drm_dp_aux *aux)
1564 {
1565 	u8 count;
1566 	int ret;
1567 
1568 	ret = drm_dp_dpcd_readb(aux, DP_SINK_COUNT, &count);
1569 	if (ret < 0)
1570 		return ret;
1571 	if (ret != 1)
1572 		return -EIO;
1573 
1574 	return DP_GET_SINK_COUNT(count);
1575 }
1576 EXPORT_SYMBOL(drm_dp_read_sink_count);
1577 
1578 /*
1579  * I2C-over-AUX implementation
1580  */
1581 
1582 static u32 drm_dp_i2c_functionality(struct i2c_adapter *adapter)
1583 {
1584 	return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1585 	       I2C_FUNC_SMBUS_READ_BLOCK_DATA |
1586 	       I2C_FUNC_SMBUS_BLOCK_PROC_CALL |
1587 	       I2C_FUNC_10BIT_ADDR;
1588 }
1589 
1590 static void drm_dp_i2c_msg_write_status_update(struct drm_dp_aux_msg *msg)
1591 {
1592 	/*
1593 	 * In case of i2c defer or short i2c ack reply to a write,
1594 	 * we need to switch to WRITE_STATUS_UPDATE to drain the
1595 	 * rest of the message
1596 	 */
1597 	if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE) {
1598 		msg->request &= DP_AUX_I2C_MOT;
1599 		msg->request |= DP_AUX_I2C_WRITE_STATUS_UPDATE;
1600 	}
1601 }
1602 
1603 #define AUX_PRECHARGE_LEN 10 /* 10 to 16 */
1604 #define AUX_SYNC_LEN (16 + 4) /* preamble + AUX_SYNC_END */
1605 #define AUX_STOP_LEN 4
1606 #define AUX_CMD_LEN 4
1607 #define AUX_ADDRESS_LEN 20
1608 #define AUX_REPLY_PAD_LEN 4
1609 #define AUX_LENGTH_LEN 8
1610 
1611 /*
1612  * Calculate the duration of the AUX request/reply in usec. Gives the
1613  * "best" case estimate, ie. successful while as short as possible.
1614  */
1615 static int drm_dp_aux_req_duration(const struct drm_dp_aux_msg *msg)
1616 {
1617 	int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1618 		AUX_CMD_LEN + AUX_ADDRESS_LEN + AUX_LENGTH_LEN;
1619 
1620 	if ((msg->request & DP_AUX_I2C_READ) == 0)
1621 		len += msg->size * 8;
1622 
1623 	return len;
1624 }
1625 
1626 static int drm_dp_aux_reply_duration(const struct drm_dp_aux_msg *msg)
1627 {
1628 	int len = AUX_PRECHARGE_LEN + AUX_SYNC_LEN + AUX_STOP_LEN +
1629 		AUX_CMD_LEN + AUX_REPLY_PAD_LEN;
1630 
1631 	/*
1632 	 * For read we expect what was asked. For writes there will
1633 	 * be 0 or 1 data bytes. Assume 0 for the "best" case.
1634 	 */
1635 	if (msg->request & DP_AUX_I2C_READ)
1636 		len += msg->size * 8;
1637 
1638 	return len;
1639 }
1640 
1641 #define I2C_START_LEN 1
1642 #define I2C_STOP_LEN 1
1643 #define I2C_ADDR_LEN 9 /* ADDRESS + R/W + ACK/NACK */
1644 #define I2C_DATA_LEN 9 /* DATA + ACK/NACK */
1645 
1646 /*
1647  * Calculate the length of the i2c transfer in usec, assuming
1648  * the i2c bus speed is as specified. Gives the "worst"
1649  * case estimate, ie. successful while as long as possible.
1650  * Doesn't account the "MOT" bit, and instead assumes each
1651  * message includes a START, ADDRESS and STOP. Neither does it
1652  * account for additional random variables such as clock stretching.
1653  */
1654 static int drm_dp_i2c_msg_duration(const struct drm_dp_aux_msg *msg,
1655 				   int i2c_speed_khz)
1656 {
1657 	/* AUX bitrate is 1MHz, i2c bitrate as specified */
1658 	return DIV_ROUND_UP((I2C_START_LEN + I2C_ADDR_LEN +
1659 			     msg->size * I2C_DATA_LEN +
1660 			     I2C_STOP_LEN) * 1000, i2c_speed_khz);
1661 }
1662 
1663 /*
1664  * Determine how many retries should be attempted to successfully transfer
1665  * the specified message, based on the estimated durations of the
1666  * i2c and AUX transfers.
1667  */
1668 static int drm_dp_i2c_retry_count(const struct drm_dp_aux_msg *msg,
1669 			      int i2c_speed_khz)
1670 {
1671 	int aux_time_us = drm_dp_aux_req_duration(msg) +
1672 		drm_dp_aux_reply_duration(msg);
1673 	int i2c_time_us = drm_dp_i2c_msg_duration(msg, i2c_speed_khz);
1674 
1675 	return DIV_ROUND_UP(i2c_time_us, aux_time_us + AUX_RETRY_INTERVAL);
1676 }
1677 
1678 /*
1679  * FIXME currently assumes 10 kHz as some real world devices seem
1680  * to require it. We should query/set the speed via DPCD if supported.
1681  */
1682 static int dp_aux_i2c_speed_khz __read_mostly = 10;
1683 module_param_unsafe(dp_aux_i2c_speed_khz, int, 0644);
1684 MODULE_PARM_DESC(dp_aux_i2c_speed_khz,
1685 		 "Assumed speed of the i2c bus in kHz, (1-400, default 10)");
1686 
1687 /*
1688  * Transfer a single I2C-over-AUX message and handle various error conditions,
1689  * retrying the transaction as appropriate.  It is assumed that the
1690  * &drm_dp_aux.transfer function does not modify anything in the msg other than the
1691  * reply field.
1692  *
1693  * Returns bytes transferred on success, or a negative error code on failure.
1694  */
1695 static int drm_dp_i2c_do_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
1696 {
1697 	unsigned int retry, defer_i2c;
1698 	int ret;
1699 	/*
1700 	 * DP1.2 sections 2.7.7.1.5.6.1 and 2.7.7.1.6.6.1: A DP Source device
1701 	 * is required to retry at least seven times upon receiving AUX_DEFER
1702 	 * before giving up the AUX transaction.
1703 	 *
1704 	 * We also try to account for the i2c bus speed.
1705 	 */
1706 	int max_retries = max(7, drm_dp_i2c_retry_count(msg, dp_aux_i2c_speed_khz));
1707 
1708 	for (retry = 0, defer_i2c = 0; retry < (max_retries + defer_i2c); retry++) {
1709 		ret = aux->transfer(aux, msg);
1710 		if (ret < 0) {
1711 			if (ret == -EBUSY)
1712 				continue;
1713 
1714 			/*
1715 			 * While timeouts can be errors, they're usually normal
1716 			 * behavior (for instance, when a driver tries to
1717 			 * communicate with a non-existent DisplayPort device).
1718 			 * Avoid spamming the kernel log with timeout errors.
1719 			 */
1720 			if (ret == -ETIMEDOUT)
1721 				drm_dbg_kms_ratelimited(aux->drm_dev, "%s: transaction timed out\n",
1722 							aux->name);
1723 			else
1724 				drm_dbg_kms(aux->drm_dev, "%s: transaction failed: %d\n",
1725 					    aux->name, ret);
1726 			return ret;
1727 		}
1728 
1729 
1730 		switch (msg->reply & DP_AUX_NATIVE_REPLY_MASK) {
1731 		case DP_AUX_NATIVE_REPLY_ACK:
1732 			/*
1733 			 * For I2C-over-AUX transactions this isn't enough, we
1734 			 * need to check for the I2C ACK reply.
1735 			 */
1736 			break;
1737 
1738 		case DP_AUX_NATIVE_REPLY_NACK:
1739 			drm_dbg_kms(aux->drm_dev, "%s: native nack (result=%d, size=%zu)\n",
1740 				    aux->name, ret, msg->size);
1741 			return -EREMOTEIO;
1742 
1743 		case DP_AUX_NATIVE_REPLY_DEFER:
1744 			drm_dbg_kms(aux->drm_dev, "%s: native defer\n", aux->name);
1745 			/*
1746 			 * We could check for I2C bit rate capabilities and if
1747 			 * available adjust this interval. We could also be
1748 			 * more careful with DP-to-legacy adapters where a
1749 			 * long legacy cable may force very low I2C bit rates.
1750 			 *
1751 			 * For now just defer for long enough to hopefully be
1752 			 * safe for all use-cases.
1753 			 */
1754 			usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1755 			continue;
1756 
1757 		default:
1758 			drm_err(aux->drm_dev, "%s: invalid native reply %#04x\n",
1759 				aux->name, msg->reply);
1760 			return -EREMOTEIO;
1761 		}
1762 
1763 		switch (msg->reply & DP_AUX_I2C_REPLY_MASK) {
1764 		case DP_AUX_I2C_REPLY_ACK:
1765 			/*
1766 			 * Both native ACK and I2C ACK replies received. We
1767 			 * can assume the transfer was successful.
1768 			 */
1769 			if (ret != msg->size)
1770 				drm_dp_i2c_msg_write_status_update(msg);
1771 			return ret;
1772 
1773 		case DP_AUX_I2C_REPLY_NACK:
1774 			drm_dbg_kms(aux->drm_dev, "%s: I2C nack (result=%d, size=%zu)\n",
1775 				    aux->name, ret, msg->size);
1776 			aux->i2c_nack_count++;
1777 			return -EREMOTEIO;
1778 
1779 		case DP_AUX_I2C_REPLY_DEFER:
1780 			drm_dbg_kms(aux->drm_dev, "%s: I2C defer\n", aux->name);
1781 			/* DP Compliance Test 4.2.2.5 Requirement:
1782 			 * Must have at least 7 retries for I2C defers on the
1783 			 * transaction to pass this test
1784 			 */
1785 			aux->i2c_defer_count++;
1786 			if (defer_i2c < 7)
1787 				defer_i2c++;
1788 			usleep_range(AUX_RETRY_INTERVAL, AUX_RETRY_INTERVAL + 100);
1789 			drm_dp_i2c_msg_write_status_update(msg);
1790 
1791 			continue;
1792 
1793 		default:
1794 			drm_err(aux->drm_dev, "%s: invalid I2C reply %#04x\n",
1795 				aux->name, msg->reply);
1796 			return -EREMOTEIO;
1797 		}
1798 	}
1799 
1800 	drm_dbg_kms(aux->drm_dev, "%s: Too many retries, giving up\n", aux->name);
1801 	return -EREMOTEIO;
1802 }
1803 
1804 static void drm_dp_i2c_msg_set_request(struct drm_dp_aux_msg *msg,
1805 				       const struct i2c_msg *i2c_msg)
1806 {
1807 	msg->request = (i2c_msg->flags & I2C_M_RD) ?
1808 		DP_AUX_I2C_READ : DP_AUX_I2C_WRITE;
1809 	if (!(i2c_msg->flags & I2C_M_STOP))
1810 		msg->request |= DP_AUX_I2C_MOT;
1811 }
1812 
1813 /*
1814  * Keep retrying drm_dp_i2c_do_msg until all data has been transferred.
1815  *
1816  * Returns an error code on failure, or a recommended transfer size on success.
1817  */
1818 static int drm_dp_i2c_drain_msg(struct drm_dp_aux *aux, struct drm_dp_aux_msg *orig_msg)
1819 {
1820 	int err, ret = orig_msg->size;
1821 	struct drm_dp_aux_msg msg = *orig_msg;
1822 
1823 	while (msg.size > 0) {
1824 		err = drm_dp_i2c_do_msg(aux, &msg);
1825 		if (err <= 0)
1826 			return err == 0 ? -EPROTO : err;
1827 
1828 		if (err < msg.size && err < ret) {
1829 			drm_dbg_kms(aux->drm_dev,
1830 				    "%s: Partial I2C reply: requested %zu bytes got %d bytes\n",
1831 				    aux->name, msg.size, err);
1832 			ret = err;
1833 		}
1834 
1835 		msg.size -= err;
1836 		msg.buffer += err;
1837 	}
1838 
1839 	return ret;
1840 }
1841 
1842 /*
1843  * Bizlink designed DP->DVI-D Dual Link adapters require the I2C over AUX
1844  * packets to be as large as possible. If not, the I2C transactions never
1845  * succeed. Hence the default is maximum.
1846  */
1847 static int dp_aux_i2c_transfer_size __read_mostly = DP_AUX_MAX_PAYLOAD_BYTES;
1848 module_param_unsafe(dp_aux_i2c_transfer_size, int, 0644);
1849 MODULE_PARM_DESC(dp_aux_i2c_transfer_size,
1850 		 "Number of bytes to transfer in a single I2C over DP AUX CH message, (1-16, default 16)");
1851 
1852 static int drm_dp_i2c_xfer(struct i2c_adapter *adapter, struct i2c_msg *msgs,
1853 			   int num)
1854 {
1855 	struct drm_dp_aux *aux = adapter->algo_data;
1856 	unsigned int i, j;
1857 	unsigned transfer_size;
1858 	struct drm_dp_aux_msg msg;
1859 	int err = 0;
1860 
1861 	dp_aux_i2c_transfer_size = clamp(dp_aux_i2c_transfer_size, 1, DP_AUX_MAX_PAYLOAD_BYTES);
1862 
1863 	memset(&msg, 0, sizeof(msg));
1864 
1865 	for (i = 0; i < num; i++) {
1866 		msg.address = msgs[i].addr;
1867 		drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1868 		/* Send a bare address packet to start the transaction.
1869 		 * Zero sized messages specify an address only (bare
1870 		 * address) transaction.
1871 		 */
1872 		msg.buffer = NULL;
1873 		msg.size = 0;
1874 		err = drm_dp_i2c_do_msg(aux, &msg);
1875 
1876 		/*
1877 		 * Reset msg.request in case in case it got
1878 		 * changed into a WRITE_STATUS_UPDATE.
1879 		 */
1880 		drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1881 
1882 		if (err < 0)
1883 			break;
1884 		/* We want each transaction to be as large as possible, but
1885 		 * we'll go to smaller sizes if the hardware gives us a
1886 		 * short reply.
1887 		 */
1888 		transfer_size = dp_aux_i2c_transfer_size;
1889 		for (j = 0; j < msgs[i].len; j += msg.size) {
1890 			msg.buffer = msgs[i].buf + j;
1891 			msg.size = min(transfer_size, msgs[i].len - j);
1892 
1893 			err = drm_dp_i2c_drain_msg(aux, &msg);
1894 
1895 			/*
1896 			 * Reset msg.request in case in case it got
1897 			 * changed into a WRITE_STATUS_UPDATE.
1898 			 */
1899 			drm_dp_i2c_msg_set_request(&msg, &msgs[i]);
1900 
1901 			if (err < 0)
1902 				break;
1903 			transfer_size = err;
1904 		}
1905 		if (err < 0)
1906 			break;
1907 	}
1908 	if (err >= 0)
1909 		err = num;
1910 	/* Send a bare address packet to close out the transaction.
1911 	 * Zero sized messages specify an address only (bare
1912 	 * address) transaction.
1913 	 */
1914 	msg.request &= ~DP_AUX_I2C_MOT;
1915 	msg.buffer = NULL;
1916 	msg.size = 0;
1917 	(void)drm_dp_i2c_do_msg(aux, &msg);
1918 
1919 	return err;
1920 }
1921 
1922 static const struct i2c_algorithm drm_dp_i2c_algo = {
1923 	.functionality = drm_dp_i2c_functionality,
1924 	.master_xfer = drm_dp_i2c_xfer,
1925 };
1926 
1927 static struct drm_dp_aux *i2c_to_aux(struct i2c_adapter *i2c)
1928 {
1929 	return container_of(i2c, struct drm_dp_aux, ddc);
1930 }
1931 
1932 static void lock_bus(struct i2c_adapter *i2c, unsigned int flags)
1933 {
1934 	mutex_lock(&i2c_to_aux(i2c)->hw_mutex);
1935 }
1936 
1937 static int trylock_bus(struct i2c_adapter *i2c, unsigned int flags)
1938 {
1939 	return mutex_trylock(&i2c_to_aux(i2c)->hw_mutex);
1940 }
1941 
1942 static void unlock_bus(struct i2c_adapter *i2c, unsigned int flags)
1943 {
1944 	mutex_unlock(&i2c_to_aux(i2c)->hw_mutex);
1945 }
1946 
1947 static const struct i2c_lock_operations drm_dp_i2c_lock_ops = {
1948 	.lock_bus = lock_bus,
1949 	.trylock_bus = trylock_bus,
1950 	.unlock_bus = unlock_bus,
1951 };
1952 
1953 static int drm_dp_aux_get_crc(struct drm_dp_aux *aux, u8 *crc)
1954 {
1955 	u8 buf, count;
1956 	int ret;
1957 
1958 	ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
1959 	if (ret < 0)
1960 		return ret;
1961 
1962 	WARN_ON(!(buf & DP_TEST_SINK_START));
1963 
1964 	ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK_MISC, &buf);
1965 	if (ret < 0)
1966 		return ret;
1967 
1968 	count = buf & DP_TEST_COUNT_MASK;
1969 	if (count == aux->crc_count)
1970 		return -EAGAIN; /* No CRC yet */
1971 
1972 	aux->crc_count = count;
1973 
1974 	/*
1975 	 * At DP_TEST_CRC_R_CR, there's 6 bytes containing CRC data, 2 bytes
1976 	 * per component (RGB or CrYCb).
1977 	 */
1978 	ret = drm_dp_dpcd_read(aux, DP_TEST_CRC_R_CR, crc, 6);
1979 	if (ret < 0)
1980 		return ret;
1981 
1982 	return 0;
1983 }
1984 
1985 static void drm_dp_aux_crc_work(struct work_struct *work)
1986 {
1987 	struct drm_dp_aux *aux = container_of(work, struct drm_dp_aux,
1988 					      crc_work);
1989 	struct drm_crtc *crtc;
1990 	u8 crc_bytes[6];
1991 	uint32_t crcs[3];
1992 	int ret;
1993 
1994 	if (WARN_ON(!aux->crtc))
1995 		return;
1996 
1997 	crtc = aux->crtc;
1998 	while (crtc->crc.opened) {
1999 		drm_crtc_wait_one_vblank(crtc);
2000 		if (!crtc->crc.opened)
2001 			break;
2002 
2003 		ret = drm_dp_aux_get_crc(aux, crc_bytes);
2004 		if (ret == -EAGAIN) {
2005 			usleep_range(1000, 2000);
2006 			ret = drm_dp_aux_get_crc(aux, crc_bytes);
2007 		}
2008 
2009 		if (ret == -EAGAIN) {
2010 			drm_dbg_kms(aux->drm_dev, "%s: Get CRC failed after retrying: %d\n",
2011 				    aux->name, ret);
2012 			continue;
2013 		} else if (ret) {
2014 			drm_dbg_kms(aux->drm_dev, "%s: Failed to get a CRC: %d\n", aux->name, ret);
2015 			continue;
2016 		}
2017 
2018 		crcs[0] = crc_bytes[0] | crc_bytes[1] << 8;
2019 		crcs[1] = crc_bytes[2] | crc_bytes[3] << 8;
2020 		crcs[2] = crc_bytes[4] | crc_bytes[5] << 8;
2021 		drm_crtc_add_crc_entry(crtc, false, 0, crcs);
2022 	}
2023 }
2024 
2025 /**
2026  * drm_dp_remote_aux_init() - minimally initialise a remote aux channel
2027  * @aux: DisplayPort AUX channel
2028  *
2029  * Used for remote aux channel in general. Merely initialize the crc work
2030  * struct.
2031  */
2032 void drm_dp_remote_aux_init(struct drm_dp_aux *aux)
2033 {
2034 	INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
2035 }
2036 EXPORT_SYMBOL(drm_dp_remote_aux_init);
2037 
2038 /**
2039  * drm_dp_aux_init() - minimally initialise an aux channel
2040  * @aux: DisplayPort AUX channel
2041  *
2042  * If you need to use the drm_dp_aux's i2c adapter prior to registering it with
2043  * the outside world, call drm_dp_aux_init() first. For drivers which are
2044  * grandparents to their AUX adapters (e.g. the AUX adapter is parented by a
2045  * &drm_connector), you must still call drm_dp_aux_register() once the connector
2046  * has been registered to allow userspace access to the auxiliary DP channel.
2047  * Likewise, for such drivers you should also assign &drm_dp_aux.drm_dev as
2048  * early as possible so that the &drm_device that corresponds to the AUX adapter
2049  * may be mentioned in debugging output from the DRM DP helpers.
2050  *
2051  * For devices which use a separate platform device for their AUX adapters, this
2052  * may be called as early as required by the driver.
2053  *
2054  */
2055 void drm_dp_aux_init(struct drm_dp_aux *aux)
2056 {
2057 	mutex_init(&aux->hw_mutex);
2058 	mutex_init(&aux->cec.lock);
2059 	INIT_WORK(&aux->crc_work, drm_dp_aux_crc_work);
2060 
2061 	aux->ddc.algo = &drm_dp_i2c_algo;
2062 	aux->ddc.algo_data = aux;
2063 	aux->ddc.retries = 3;
2064 
2065 	aux->ddc.lock_ops = &drm_dp_i2c_lock_ops;
2066 }
2067 EXPORT_SYMBOL(drm_dp_aux_init);
2068 
2069 /**
2070  * drm_dp_aux_register() - initialise and register aux channel
2071  * @aux: DisplayPort AUX channel
2072  *
2073  * Automatically calls drm_dp_aux_init() if this hasn't been done yet. This
2074  * should only be called once the parent of @aux, &drm_dp_aux.dev, is
2075  * initialized. For devices which are grandparents of their AUX channels,
2076  * &drm_dp_aux.dev will typically be the &drm_connector &device which
2077  * corresponds to @aux. For these devices, it's advised to call
2078  * drm_dp_aux_register() in &drm_connector_funcs.late_register, and likewise to
2079  * call drm_dp_aux_unregister() in &drm_connector_funcs.early_unregister.
2080  * Functions which don't follow this will likely Oops when
2081  * %CONFIG_DRM_DP_AUX_CHARDEV is enabled.
2082  *
2083  * For devices where the AUX channel is a device that exists independently of
2084  * the &drm_device that uses it, such as SoCs and bridge devices, it is
2085  * recommended to call drm_dp_aux_register() after a &drm_device has been
2086  * assigned to &drm_dp_aux.drm_dev, and likewise to call
2087  * drm_dp_aux_unregister() once the &drm_device should no longer be associated
2088  * with the AUX channel (e.g. on bridge detach).
2089  *
2090  * Drivers which need to use the aux channel before either of the two points
2091  * mentioned above need to call drm_dp_aux_init() in order to use the AUX
2092  * channel before registration.
2093  *
2094  * Returns 0 on success or a negative error code on failure.
2095  */
2096 int drm_dp_aux_register(struct drm_dp_aux *aux)
2097 {
2098 	int ret;
2099 
2100 	WARN_ON_ONCE(!aux->drm_dev);
2101 
2102 	if (!aux->ddc.algo)
2103 		drm_dp_aux_init(aux);
2104 
2105 	aux->ddc.owner = THIS_MODULE;
2106 	aux->ddc.dev.parent = aux->dev;
2107 
2108 	strscpy(aux->ddc.name, aux->name ? aux->name : dev_name(aux->dev),
2109 		sizeof(aux->ddc.name));
2110 
2111 	ret = drm_dp_aux_register_devnode(aux);
2112 	if (ret)
2113 		return ret;
2114 
2115 	ret = i2c_add_adapter(&aux->ddc);
2116 	if (ret) {
2117 		drm_dp_aux_unregister_devnode(aux);
2118 		return ret;
2119 	}
2120 
2121 	return 0;
2122 }
2123 EXPORT_SYMBOL(drm_dp_aux_register);
2124 
2125 /**
2126  * drm_dp_aux_unregister() - unregister an AUX adapter
2127  * @aux: DisplayPort AUX channel
2128  */
2129 void drm_dp_aux_unregister(struct drm_dp_aux *aux)
2130 {
2131 	drm_dp_aux_unregister_devnode(aux);
2132 	i2c_del_adapter(&aux->ddc);
2133 }
2134 EXPORT_SYMBOL(drm_dp_aux_unregister);
2135 
2136 #define PSR_SETUP_TIME(x) [DP_PSR_SETUP_TIME_ ## x >> DP_PSR_SETUP_TIME_SHIFT] = (x)
2137 
2138 /**
2139  * drm_dp_psr_setup_time() - PSR setup in time usec
2140  * @psr_cap: PSR capabilities from DPCD
2141  *
2142  * Returns:
2143  * PSR setup time for the panel in microseconds,  negative
2144  * error code on failure.
2145  */
2146 int drm_dp_psr_setup_time(const u8 psr_cap[EDP_PSR_RECEIVER_CAP_SIZE])
2147 {
2148 	static const u16 psr_setup_time_us[] = {
2149 		PSR_SETUP_TIME(330),
2150 		PSR_SETUP_TIME(275),
2151 		PSR_SETUP_TIME(220),
2152 		PSR_SETUP_TIME(165),
2153 		PSR_SETUP_TIME(110),
2154 		PSR_SETUP_TIME(55),
2155 		PSR_SETUP_TIME(0),
2156 	};
2157 	int i;
2158 
2159 	i = (psr_cap[1] & DP_PSR_SETUP_TIME_MASK) >> DP_PSR_SETUP_TIME_SHIFT;
2160 	if (i >= ARRAY_SIZE(psr_setup_time_us))
2161 		return -EINVAL;
2162 
2163 	return psr_setup_time_us[i];
2164 }
2165 EXPORT_SYMBOL(drm_dp_psr_setup_time);
2166 
2167 #undef PSR_SETUP_TIME
2168 
2169 /**
2170  * drm_dp_start_crc() - start capture of frame CRCs
2171  * @aux: DisplayPort AUX channel
2172  * @crtc: CRTC displaying the frames whose CRCs are to be captured
2173  *
2174  * Returns 0 on success or a negative error code on failure.
2175  */
2176 int drm_dp_start_crc(struct drm_dp_aux *aux, struct drm_crtc *crtc)
2177 {
2178 	u8 buf;
2179 	int ret;
2180 
2181 	ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
2182 	if (ret < 0)
2183 		return ret;
2184 
2185 	ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf | DP_TEST_SINK_START);
2186 	if (ret < 0)
2187 		return ret;
2188 
2189 	aux->crc_count = 0;
2190 	aux->crtc = crtc;
2191 	schedule_work(&aux->crc_work);
2192 
2193 	return 0;
2194 }
2195 EXPORT_SYMBOL(drm_dp_start_crc);
2196 
2197 /**
2198  * drm_dp_stop_crc() - stop capture of frame CRCs
2199  * @aux: DisplayPort AUX channel
2200  *
2201  * Returns 0 on success or a negative error code on failure.
2202  */
2203 int drm_dp_stop_crc(struct drm_dp_aux *aux)
2204 {
2205 	u8 buf;
2206 	int ret;
2207 
2208 	ret = drm_dp_dpcd_readb(aux, DP_TEST_SINK, &buf);
2209 	if (ret < 0)
2210 		return ret;
2211 
2212 	ret = drm_dp_dpcd_writeb(aux, DP_TEST_SINK, buf & ~DP_TEST_SINK_START);
2213 	if (ret < 0)
2214 		return ret;
2215 
2216 	flush_work(&aux->crc_work);
2217 	aux->crtc = NULL;
2218 
2219 	return 0;
2220 }
2221 EXPORT_SYMBOL(drm_dp_stop_crc);
2222 
2223 struct dpcd_quirk {
2224 	u8 oui[3];
2225 	u8 device_id[6];
2226 	bool is_branch;
2227 	u32 quirks;
2228 };
2229 
2230 #define OUI(first, second, third) { (first), (second), (third) }
2231 #define DEVICE_ID(first, second, third, fourth, fifth, sixth) \
2232 	{ (first), (second), (third), (fourth), (fifth), (sixth) }
2233 
2234 #define DEVICE_ID_ANY	DEVICE_ID(0, 0, 0, 0, 0, 0)
2235 
2236 static const struct dpcd_quirk dpcd_quirk_list[] = {
2237 	/* Analogix 7737 needs reduced M and N at HBR2 link rates */
2238 	{ OUI(0x00, 0x22, 0xb9), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
2239 	/* LG LP140WF6-SPM1 eDP panel */
2240 	{ OUI(0x00, 0x22, 0xb9), DEVICE_ID('s', 'i', 'v', 'a', 'r', 'T'), false, BIT(DP_DPCD_QUIRK_CONSTANT_N) },
2241 	/* Apple panels need some additional handling to support PSR */
2242 	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID_ANY, false, BIT(DP_DPCD_QUIRK_NO_PSR) },
2243 	/* CH7511 seems to leave SINK_COUNT zeroed */
2244 	{ OUI(0x00, 0x00, 0x00), DEVICE_ID('C', 'H', '7', '5', '1', '1'), false, BIT(DP_DPCD_QUIRK_NO_SINK_COUNT) },
2245 	/* Synaptics DP1.4 MST hubs can support DSC without virtual DPCD */
2246 	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_DSC_WITHOUT_VIRTUAL_DPCD) },
2247 	/* Synaptics DP1.4 MST hubs require DSC for some modes on which it applies HBLANK expansion. */
2248 	{ OUI(0x90, 0xCC, 0x24), DEVICE_ID_ANY, true, BIT(DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC) },
2249 	/* Apple MacBookPro 2017 15 inch eDP Retina panel reports too low DP_MAX_LINK_RATE */
2250 	{ OUI(0x00, 0x10, 0xfa), DEVICE_ID(101, 68, 21, 101, 98, 97), false, BIT(DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS) },
2251 };
2252 
2253 #undef OUI
2254 
2255 /*
2256  * Get a bit mask of DPCD quirks for the sink/branch device identified by
2257  * ident. The quirk data is shared but it's up to the drivers to act on the
2258  * data.
2259  *
2260  * For now, only the OUI (first three bytes) is used, but this may be extended
2261  * to device identification string and hardware/firmware revisions later.
2262  */
2263 static u32
2264 drm_dp_get_quirks(const struct drm_dp_dpcd_ident *ident, bool is_branch)
2265 {
2266 	const struct dpcd_quirk *quirk;
2267 	u32 quirks = 0;
2268 	int i;
2269 	u8 any_device[] = DEVICE_ID_ANY;
2270 
2271 	for (i = 0; i < ARRAY_SIZE(dpcd_quirk_list); i++) {
2272 		quirk = &dpcd_quirk_list[i];
2273 
2274 		if (quirk->is_branch != is_branch)
2275 			continue;
2276 
2277 		if (memcmp(quirk->oui, ident->oui, sizeof(ident->oui)) != 0)
2278 			continue;
2279 
2280 		if (memcmp(quirk->device_id, any_device, sizeof(any_device)) != 0 &&
2281 		    memcmp(quirk->device_id, ident->device_id, sizeof(ident->device_id)) != 0)
2282 			continue;
2283 
2284 		quirks |= quirk->quirks;
2285 	}
2286 
2287 	return quirks;
2288 }
2289 
2290 #undef DEVICE_ID_ANY
2291 #undef DEVICE_ID
2292 
2293 /**
2294  * drm_dp_read_desc - read sink/branch descriptor from DPCD
2295  * @aux: DisplayPort AUX channel
2296  * @desc: Device descriptor to fill from DPCD
2297  * @is_branch: true for branch devices, false for sink devices
2298  *
2299  * Read DPCD 0x400 (sink) or 0x500 (branch) into @desc. Also debug log the
2300  * identification.
2301  *
2302  * Returns 0 on success or a negative error code on failure.
2303  */
2304 int drm_dp_read_desc(struct drm_dp_aux *aux, struct drm_dp_desc *desc,
2305 		     bool is_branch)
2306 {
2307 	struct drm_dp_dpcd_ident *ident = &desc->ident;
2308 	unsigned int offset = is_branch ? DP_BRANCH_OUI : DP_SINK_OUI;
2309 	int ret, dev_id_len;
2310 
2311 	ret = drm_dp_dpcd_read(aux, offset, ident, sizeof(*ident));
2312 	if (ret < 0)
2313 		return ret;
2314 
2315 	desc->quirks = drm_dp_get_quirks(ident, is_branch);
2316 
2317 	dev_id_len = strnlen(ident->device_id, sizeof(ident->device_id));
2318 
2319 	drm_dbg_kms(aux->drm_dev,
2320 		    "%s: DP %s: OUI %*phD dev-ID %*pE HW-rev %d.%d SW-rev %d.%d quirks 0x%04x\n",
2321 		    aux->name, is_branch ? "branch" : "sink",
2322 		    (int)sizeof(ident->oui), ident->oui, dev_id_len,
2323 		    ident->device_id, ident->hw_rev >> 4, ident->hw_rev & 0xf,
2324 		    ident->sw_major_rev, ident->sw_minor_rev, desc->quirks);
2325 
2326 	return 0;
2327 }
2328 EXPORT_SYMBOL(drm_dp_read_desc);
2329 
2330 /**
2331  * drm_dp_dsc_sink_bpp_incr() - Get bits per pixel increment
2332  * @dsc_dpcd: DSC capabilities from DPCD
2333  *
2334  * Returns the bpp precision supported by the DP sink.
2335  */
2336 u8 drm_dp_dsc_sink_bpp_incr(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2337 {
2338 	u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT];
2339 
2340 	switch (bpp_increment_dpcd) {
2341 	case DP_DSC_BITS_PER_PIXEL_1_16:
2342 		return 16;
2343 	case DP_DSC_BITS_PER_PIXEL_1_8:
2344 		return 8;
2345 	case DP_DSC_BITS_PER_PIXEL_1_4:
2346 		return 4;
2347 	case DP_DSC_BITS_PER_PIXEL_1_2:
2348 		return 2;
2349 	case DP_DSC_BITS_PER_PIXEL_1_1:
2350 		return 1;
2351 	}
2352 
2353 	return 0;
2354 }
2355 EXPORT_SYMBOL(drm_dp_dsc_sink_bpp_incr);
2356 
2357 /**
2358  * drm_dp_dsc_sink_max_slice_count() - Get the max slice count
2359  * supported by the DSC sink.
2360  * @dsc_dpcd: DSC capabilities from DPCD
2361  * @is_edp: true if its eDP, false for DP
2362  *
2363  * Read the slice capabilities DPCD register from DSC sink to get
2364  * the maximum slice count supported. This is used to populate
2365  * the DSC parameters in the &struct drm_dsc_config by the driver.
2366  * Driver creates an infoframe using these parameters to populate
2367  * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2368  * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2369  *
2370  * Returns:
2371  * Maximum slice count supported by DSC sink or 0 its invalid
2372  */
2373 u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2374 				   bool is_edp)
2375 {
2376 	u8 slice_cap1 = dsc_dpcd[DP_DSC_SLICE_CAP_1 - DP_DSC_SUPPORT];
2377 
2378 	if (is_edp) {
2379 		/* For eDP, register DSC_SLICE_CAPABILITIES_1 gives slice count */
2380 		if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2381 			return 4;
2382 		if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2383 			return 2;
2384 		if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2385 			return 1;
2386 	} else {
2387 		/* For DP, use values from DSC_SLICE_CAP_1 and DSC_SLICE_CAP2 */
2388 		u8 slice_cap2 = dsc_dpcd[DP_DSC_SLICE_CAP_2 - DP_DSC_SUPPORT];
2389 
2390 		if (slice_cap2 & DP_DSC_24_PER_DP_DSC_SINK)
2391 			return 24;
2392 		if (slice_cap2 & DP_DSC_20_PER_DP_DSC_SINK)
2393 			return 20;
2394 		if (slice_cap2 & DP_DSC_16_PER_DP_DSC_SINK)
2395 			return 16;
2396 		if (slice_cap1 & DP_DSC_12_PER_DP_DSC_SINK)
2397 			return 12;
2398 		if (slice_cap1 & DP_DSC_10_PER_DP_DSC_SINK)
2399 			return 10;
2400 		if (slice_cap1 & DP_DSC_8_PER_DP_DSC_SINK)
2401 			return 8;
2402 		if (slice_cap1 & DP_DSC_6_PER_DP_DSC_SINK)
2403 			return 6;
2404 		if (slice_cap1 & DP_DSC_4_PER_DP_DSC_SINK)
2405 			return 4;
2406 		if (slice_cap1 & DP_DSC_2_PER_DP_DSC_SINK)
2407 			return 2;
2408 		if (slice_cap1 & DP_DSC_1_PER_DP_DSC_SINK)
2409 			return 1;
2410 	}
2411 
2412 	return 0;
2413 }
2414 EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count);
2415 
2416 /**
2417  * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits
2418  * @dsc_dpcd: DSC capabilities from DPCD
2419  *
2420  * Read the DSC DPCD register to parse the line buffer depth in bits which is
2421  * number of bits of precision within the decoder line buffer supported by
2422  * the DSC sink. This is used to populate the DSC parameters in the
2423  * &struct drm_dsc_config by the driver.
2424  * Driver creates an infoframe using these parameters to populate
2425  * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2426  * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2427  *
2428  * Returns:
2429  * Line buffer depth supported by DSC panel or 0 its invalid
2430  */
2431 u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE])
2432 {
2433 	u8 line_buf_depth = dsc_dpcd[DP_DSC_LINE_BUF_BIT_DEPTH - DP_DSC_SUPPORT];
2434 
2435 	switch (line_buf_depth & DP_DSC_LINE_BUF_BIT_DEPTH_MASK) {
2436 	case DP_DSC_LINE_BUF_BIT_DEPTH_9:
2437 		return 9;
2438 	case DP_DSC_LINE_BUF_BIT_DEPTH_10:
2439 		return 10;
2440 	case DP_DSC_LINE_BUF_BIT_DEPTH_11:
2441 		return 11;
2442 	case DP_DSC_LINE_BUF_BIT_DEPTH_12:
2443 		return 12;
2444 	case DP_DSC_LINE_BUF_BIT_DEPTH_13:
2445 		return 13;
2446 	case DP_DSC_LINE_BUF_BIT_DEPTH_14:
2447 		return 14;
2448 	case DP_DSC_LINE_BUF_BIT_DEPTH_15:
2449 		return 15;
2450 	case DP_DSC_LINE_BUF_BIT_DEPTH_16:
2451 		return 16;
2452 	case DP_DSC_LINE_BUF_BIT_DEPTH_8:
2453 		return 8;
2454 	}
2455 
2456 	return 0;
2457 }
2458 EXPORT_SYMBOL(drm_dp_dsc_sink_line_buf_depth);
2459 
2460 /**
2461  * drm_dp_dsc_sink_supported_input_bpcs() - Get all the input bits per component
2462  * values supported by the DSC sink.
2463  * @dsc_dpcd: DSC capabilities from DPCD
2464  * @dsc_bpc: An array to be filled by this helper with supported
2465  *           input bpcs.
2466  *
2467  * Read the DSC DPCD from the sink device to parse the supported bits per
2468  * component values. This is used to populate the DSC parameters
2469  * in the &struct drm_dsc_config by the driver.
2470  * Driver creates an infoframe using these parameters to populate
2471  * &struct drm_dsc_pps_infoframe. These are sent to the sink using DSC
2472  * infoframe using the helper function drm_dsc_pps_infoframe_pack()
2473  *
2474  * Returns:
2475  * Number of input BPC values parsed from the DPCD
2476  */
2477 int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE],
2478 					 u8 dsc_bpc[3])
2479 {
2480 	int num_bpc = 0;
2481 	u8 color_depth = dsc_dpcd[DP_DSC_DEC_COLOR_DEPTH_CAP - DP_DSC_SUPPORT];
2482 
2483 	if (!drm_dp_sink_supports_dsc(dsc_dpcd))
2484 		return 0;
2485 
2486 	if (color_depth & DP_DSC_12_BPC)
2487 		dsc_bpc[num_bpc++] = 12;
2488 	if (color_depth & DP_DSC_10_BPC)
2489 		dsc_bpc[num_bpc++] = 10;
2490 
2491 	/* A DP DSC Sink device shall support 8 bpc. */
2492 	dsc_bpc[num_bpc++] = 8;
2493 
2494 	return num_bpc;
2495 }
2496 EXPORT_SYMBOL(drm_dp_dsc_sink_supported_input_bpcs);
2497 
2498 static int drm_dp_read_lttpr_regs(struct drm_dp_aux *aux,
2499 				  const u8 dpcd[DP_RECEIVER_CAP_SIZE], int address,
2500 				  u8 *buf, int buf_size)
2501 {
2502 	/*
2503 	 * At least the DELL P2715Q monitor with a DPCD_REV < 0x14 returns
2504 	 * corrupted values when reading from the 0xF0000- range with a block
2505 	 * size bigger than 1.
2506 	 */
2507 	int block_size = dpcd[DP_DPCD_REV] < 0x14 ? 1 : buf_size;
2508 	int offset;
2509 	int ret;
2510 
2511 	for (offset = 0; offset < buf_size; offset += block_size) {
2512 		ret = drm_dp_dpcd_read(aux,
2513 				       address + offset,
2514 				       &buf[offset], block_size);
2515 		if (ret < 0)
2516 			return ret;
2517 
2518 		WARN_ON(ret != block_size);
2519 	}
2520 
2521 	return 0;
2522 }
2523 
2524 /**
2525  * drm_dp_read_lttpr_common_caps - read the LTTPR common capabilities
2526  * @aux: DisplayPort AUX channel
2527  * @dpcd: DisplayPort configuration data
2528  * @caps: buffer to return the capability info in
2529  *
2530  * Read capabilities common to all LTTPRs.
2531  *
2532  * Returns 0 on success or a negative error code on failure.
2533  */
2534 int drm_dp_read_lttpr_common_caps(struct drm_dp_aux *aux,
2535 				  const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2536 				  u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2537 {
2538 	return drm_dp_read_lttpr_regs(aux, dpcd,
2539 				      DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV,
2540 				      caps, DP_LTTPR_COMMON_CAP_SIZE);
2541 }
2542 EXPORT_SYMBOL(drm_dp_read_lttpr_common_caps);
2543 
2544 /**
2545  * drm_dp_read_lttpr_phy_caps - read the capabilities for a given LTTPR PHY
2546  * @aux: DisplayPort AUX channel
2547  * @dpcd: DisplayPort configuration data
2548  * @dp_phy: LTTPR PHY to read the capabilities for
2549  * @caps: buffer to return the capability info in
2550  *
2551  * Read the capabilities for the given LTTPR PHY.
2552  *
2553  * Returns 0 on success or a negative error code on failure.
2554  */
2555 int drm_dp_read_lttpr_phy_caps(struct drm_dp_aux *aux,
2556 			       const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2557 			       enum drm_dp_phy dp_phy,
2558 			       u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2559 {
2560 	return drm_dp_read_lttpr_regs(aux, dpcd,
2561 				      DP_TRAINING_AUX_RD_INTERVAL_PHY_REPEATER(dp_phy),
2562 				      caps, DP_LTTPR_PHY_CAP_SIZE);
2563 }
2564 EXPORT_SYMBOL(drm_dp_read_lttpr_phy_caps);
2565 
2566 static u8 dp_lttpr_common_cap(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE], int r)
2567 {
2568 	return caps[r - DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV];
2569 }
2570 
2571 /**
2572  * drm_dp_lttpr_count - get the number of detected LTTPRs
2573  * @caps: LTTPR common capabilities
2574  *
2575  * Get the number of detected LTTPRs from the LTTPR common capabilities info.
2576  *
2577  * Returns:
2578  *   -ERANGE if more than supported number (8) of LTTPRs are detected
2579  *   -EINVAL if the DP_PHY_REPEATER_CNT register contains an invalid value
2580  *   otherwise the number of detected LTTPRs
2581  */
2582 int drm_dp_lttpr_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2583 {
2584 	u8 count = dp_lttpr_common_cap(caps, DP_PHY_REPEATER_CNT);
2585 
2586 	switch (hweight8(count)) {
2587 	case 0:
2588 		return 0;
2589 	case 1:
2590 		return 8 - ilog2(count);
2591 	case 8:
2592 		return -ERANGE;
2593 	default:
2594 		return -EINVAL;
2595 	}
2596 }
2597 EXPORT_SYMBOL(drm_dp_lttpr_count);
2598 
2599 /**
2600  * drm_dp_lttpr_max_link_rate - get the maximum link rate supported by all LTTPRs
2601  * @caps: LTTPR common capabilities
2602  *
2603  * Returns the maximum link rate supported by all detected LTTPRs.
2604  */
2605 int drm_dp_lttpr_max_link_rate(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2606 {
2607 	u8 rate = dp_lttpr_common_cap(caps, DP_MAX_LINK_RATE_PHY_REPEATER);
2608 
2609 	return drm_dp_bw_code_to_link_rate(rate);
2610 }
2611 EXPORT_SYMBOL(drm_dp_lttpr_max_link_rate);
2612 
2613 /**
2614  * drm_dp_lttpr_max_lane_count - get the maximum lane count supported by all LTTPRs
2615  * @caps: LTTPR common capabilities
2616  *
2617  * Returns the maximum lane count supported by all detected LTTPRs.
2618  */
2619 int drm_dp_lttpr_max_lane_count(const u8 caps[DP_LTTPR_COMMON_CAP_SIZE])
2620 {
2621 	u8 max_lanes = dp_lttpr_common_cap(caps, DP_MAX_LANE_COUNT_PHY_REPEATER);
2622 
2623 	return max_lanes & DP_MAX_LANE_COUNT_MASK;
2624 }
2625 EXPORT_SYMBOL(drm_dp_lttpr_max_lane_count);
2626 
2627 /**
2628  * drm_dp_lttpr_voltage_swing_level_3_supported - check for LTTPR vswing3 support
2629  * @caps: LTTPR PHY capabilities
2630  *
2631  * Returns true if the @caps for an LTTPR TX PHY indicate support for
2632  * voltage swing level 3.
2633  */
2634 bool
2635 drm_dp_lttpr_voltage_swing_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2636 {
2637 	u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2638 
2639 	return txcap & DP_VOLTAGE_SWING_LEVEL_3_SUPPORTED;
2640 }
2641 EXPORT_SYMBOL(drm_dp_lttpr_voltage_swing_level_3_supported);
2642 
2643 /**
2644  * drm_dp_lttpr_pre_emphasis_level_3_supported - check for LTTPR preemph3 support
2645  * @caps: LTTPR PHY capabilities
2646  *
2647  * Returns true if the @caps for an LTTPR TX PHY indicate support for
2648  * pre-emphasis level 3.
2649  */
2650 bool
2651 drm_dp_lttpr_pre_emphasis_level_3_supported(const u8 caps[DP_LTTPR_PHY_CAP_SIZE])
2652 {
2653 	u8 txcap = dp_lttpr_phy_cap(caps, DP_TRANSMITTER_CAPABILITY_PHY_REPEATER1);
2654 
2655 	return txcap & DP_PRE_EMPHASIS_LEVEL_3_SUPPORTED;
2656 }
2657 EXPORT_SYMBOL(drm_dp_lttpr_pre_emphasis_level_3_supported);
2658 
2659 /**
2660  * drm_dp_get_phy_test_pattern() - get the requested pattern from the sink.
2661  * @aux: DisplayPort AUX channel
2662  * @data: DP phy compliance test parameters.
2663  *
2664  * Returns 0 on success or a negative error code on failure.
2665  */
2666 int drm_dp_get_phy_test_pattern(struct drm_dp_aux *aux,
2667 				struct drm_dp_phy_test_params *data)
2668 {
2669 	int err;
2670 	u8 rate, lanes;
2671 
2672 	err = drm_dp_dpcd_readb(aux, DP_TEST_LINK_RATE, &rate);
2673 	if (err < 0)
2674 		return err;
2675 	data->link_rate = drm_dp_bw_code_to_link_rate(rate);
2676 
2677 	err = drm_dp_dpcd_readb(aux, DP_TEST_LANE_COUNT, &lanes);
2678 	if (err < 0)
2679 		return err;
2680 	data->num_lanes = lanes & DP_MAX_LANE_COUNT_MASK;
2681 
2682 	if (lanes & DP_ENHANCED_FRAME_CAP)
2683 		data->enhanced_frame_cap = true;
2684 
2685 	err = drm_dp_dpcd_readb(aux, DP_PHY_TEST_PATTERN, &data->phy_pattern);
2686 	if (err < 0)
2687 		return err;
2688 
2689 	switch (data->phy_pattern) {
2690 	case DP_PHY_TEST_PATTERN_80BIT_CUSTOM:
2691 		err = drm_dp_dpcd_read(aux, DP_TEST_80BIT_CUSTOM_PATTERN_7_0,
2692 				       &data->custom80, sizeof(data->custom80));
2693 		if (err < 0)
2694 			return err;
2695 
2696 		break;
2697 	case DP_PHY_TEST_PATTERN_CP2520:
2698 		err = drm_dp_dpcd_read(aux, DP_TEST_HBR2_SCRAMBLER_RESET,
2699 				       &data->hbr2_reset,
2700 				       sizeof(data->hbr2_reset));
2701 		if (err < 0)
2702 			return err;
2703 	}
2704 
2705 	return 0;
2706 }
2707 EXPORT_SYMBOL(drm_dp_get_phy_test_pattern);
2708 
2709 /**
2710  * drm_dp_set_phy_test_pattern() - set the pattern to the sink.
2711  * @aux: DisplayPort AUX channel
2712  * @data: DP phy compliance test parameters.
2713  * @dp_rev: DP revision to use for compliance testing
2714  *
2715  * Returns 0 on success or a negative error code on failure.
2716  */
2717 int drm_dp_set_phy_test_pattern(struct drm_dp_aux *aux,
2718 				struct drm_dp_phy_test_params *data, u8 dp_rev)
2719 {
2720 	int err, i;
2721 	u8 test_pattern;
2722 
2723 	test_pattern = data->phy_pattern;
2724 	if (dp_rev < 0x12) {
2725 		test_pattern = (test_pattern << 2) &
2726 			       DP_LINK_QUAL_PATTERN_11_MASK;
2727 		err = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET,
2728 					 test_pattern);
2729 		if (err < 0)
2730 			return err;
2731 	} else {
2732 		for (i = 0; i < data->num_lanes; i++) {
2733 			err = drm_dp_dpcd_writeb(aux,
2734 						 DP_LINK_QUAL_LANE0_SET + i,
2735 						 test_pattern);
2736 			if (err < 0)
2737 				return err;
2738 		}
2739 	}
2740 
2741 	return 0;
2742 }
2743 EXPORT_SYMBOL(drm_dp_set_phy_test_pattern);
2744 
2745 static const char *dp_pixelformat_get_name(enum dp_pixelformat pixelformat)
2746 {
2747 	if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2748 		return "Invalid";
2749 
2750 	switch (pixelformat) {
2751 	case DP_PIXELFORMAT_RGB:
2752 		return "RGB";
2753 	case DP_PIXELFORMAT_YUV444:
2754 		return "YUV444";
2755 	case DP_PIXELFORMAT_YUV422:
2756 		return "YUV422";
2757 	case DP_PIXELFORMAT_YUV420:
2758 		return "YUV420";
2759 	case DP_PIXELFORMAT_Y_ONLY:
2760 		return "Y_ONLY";
2761 	case DP_PIXELFORMAT_RAW:
2762 		return "RAW";
2763 	default:
2764 		return "Reserved";
2765 	}
2766 }
2767 
2768 static const char *dp_colorimetry_get_name(enum dp_pixelformat pixelformat,
2769 					   enum dp_colorimetry colorimetry)
2770 {
2771 	if (pixelformat < 0 || pixelformat > DP_PIXELFORMAT_RESERVED)
2772 		return "Invalid";
2773 
2774 	switch (colorimetry) {
2775 	case DP_COLORIMETRY_DEFAULT:
2776 		switch (pixelformat) {
2777 		case DP_PIXELFORMAT_RGB:
2778 			return "sRGB";
2779 		case DP_PIXELFORMAT_YUV444:
2780 		case DP_PIXELFORMAT_YUV422:
2781 		case DP_PIXELFORMAT_YUV420:
2782 			return "BT.601";
2783 		case DP_PIXELFORMAT_Y_ONLY:
2784 			return "DICOM PS3.14";
2785 		case DP_PIXELFORMAT_RAW:
2786 			return "Custom Color Profile";
2787 		default:
2788 			return "Reserved";
2789 		}
2790 	case DP_COLORIMETRY_RGB_WIDE_FIXED: /* and DP_COLORIMETRY_BT709_YCC */
2791 		switch (pixelformat) {
2792 		case DP_PIXELFORMAT_RGB:
2793 			return "Wide Fixed";
2794 		case DP_PIXELFORMAT_YUV444:
2795 		case DP_PIXELFORMAT_YUV422:
2796 		case DP_PIXELFORMAT_YUV420:
2797 			return "BT.709";
2798 		default:
2799 			return "Reserved";
2800 		}
2801 	case DP_COLORIMETRY_RGB_WIDE_FLOAT: /* and DP_COLORIMETRY_XVYCC_601 */
2802 		switch (pixelformat) {
2803 		case DP_PIXELFORMAT_RGB:
2804 			return "Wide Float";
2805 		case DP_PIXELFORMAT_YUV444:
2806 		case DP_PIXELFORMAT_YUV422:
2807 		case DP_PIXELFORMAT_YUV420:
2808 			return "xvYCC 601";
2809 		default:
2810 			return "Reserved";
2811 		}
2812 	case DP_COLORIMETRY_OPRGB: /* and DP_COLORIMETRY_XVYCC_709 */
2813 		switch (pixelformat) {
2814 		case DP_PIXELFORMAT_RGB:
2815 			return "OpRGB";
2816 		case DP_PIXELFORMAT_YUV444:
2817 		case DP_PIXELFORMAT_YUV422:
2818 		case DP_PIXELFORMAT_YUV420:
2819 			return "xvYCC 709";
2820 		default:
2821 			return "Reserved";
2822 		}
2823 	case DP_COLORIMETRY_DCI_P3_RGB: /* and DP_COLORIMETRY_SYCC_601 */
2824 		switch (pixelformat) {
2825 		case DP_PIXELFORMAT_RGB:
2826 			return "DCI-P3";
2827 		case DP_PIXELFORMAT_YUV444:
2828 		case DP_PIXELFORMAT_YUV422:
2829 		case DP_PIXELFORMAT_YUV420:
2830 			return "sYCC 601";
2831 		default:
2832 			return "Reserved";
2833 		}
2834 	case DP_COLORIMETRY_RGB_CUSTOM: /* and DP_COLORIMETRY_OPYCC_601 */
2835 		switch (pixelformat) {
2836 		case DP_PIXELFORMAT_RGB:
2837 			return "Custom Profile";
2838 		case DP_PIXELFORMAT_YUV444:
2839 		case DP_PIXELFORMAT_YUV422:
2840 		case DP_PIXELFORMAT_YUV420:
2841 			return "OpYCC 601";
2842 		default:
2843 			return "Reserved";
2844 		}
2845 	case DP_COLORIMETRY_BT2020_RGB: /* and DP_COLORIMETRY_BT2020_CYCC */
2846 		switch (pixelformat) {
2847 		case DP_PIXELFORMAT_RGB:
2848 			return "BT.2020 RGB";
2849 		case DP_PIXELFORMAT_YUV444:
2850 		case DP_PIXELFORMAT_YUV422:
2851 		case DP_PIXELFORMAT_YUV420:
2852 			return "BT.2020 CYCC";
2853 		default:
2854 			return "Reserved";
2855 		}
2856 	case DP_COLORIMETRY_BT2020_YCC:
2857 		switch (pixelformat) {
2858 		case DP_PIXELFORMAT_YUV444:
2859 		case DP_PIXELFORMAT_YUV422:
2860 		case DP_PIXELFORMAT_YUV420:
2861 			return "BT.2020 YCC";
2862 		default:
2863 			return "Reserved";
2864 		}
2865 	default:
2866 		return "Invalid";
2867 	}
2868 }
2869 
2870 static const char *dp_dynamic_range_get_name(enum dp_dynamic_range dynamic_range)
2871 {
2872 	switch (dynamic_range) {
2873 	case DP_DYNAMIC_RANGE_VESA:
2874 		return "VESA range";
2875 	case DP_DYNAMIC_RANGE_CTA:
2876 		return "CTA range";
2877 	default:
2878 		return "Invalid";
2879 	}
2880 }
2881 
2882 static const char *dp_content_type_get_name(enum dp_content_type content_type)
2883 {
2884 	switch (content_type) {
2885 	case DP_CONTENT_TYPE_NOT_DEFINED:
2886 		return "Not defined";
2887 	case DP_CONTENT_TYPE_GRAPHICS:
2888 		return "Graphics";
2889 	case DP_CONTENT_TYPE_PHOTO:
2890 		return "Photo";
2891 	case DP_CONTENT_TYPE_VIDEO:
2892 		return "Video";
2893 	case DP_CONTENT_TYPE_GAME:
2894 		return "Game";
2895 	default:
2896 		return "Reserved";
2897 	}
2898 }
2899 
2900 void drm_dp_vsc_sdp_log(const char *level, struct device *dev,
2901 			const struct drm_dp_vsc_sdp *vsc)
2902 {
2903 #define DP_SDP_LOG(fmt, ...) dev_printk(level, dev, fmt, ##__VA_ARGS__)
2904 	DP_SDP_LOG("DP SDP: %s, revision %u, length %u\n", "VSC",
2905 		   vsc->revision, vsc->length);
2906 	DP_SDP_LOG("    pixelformat: %s\n",
2907 		   dp_pixelformat_get_name(vsc->pixelformat));
2908 	DP_SDP_LOG("    colorimetry: %s\n",
2909 		   dp_colorimetry_get_name(vsc->pixelformat, vsc->colorimetry));
2910 	DP_SDP_LOG("    bpc: %u\n", vsc->bpc);
2911 	DP_SDP_LOG("    dynamic range: %s\n",
2912 		   dp_dynamic_range_get_name(vsc->dynamic_range));
2913 	DP_SDP_LOG("    content type: %s\n",
2914 		   dp_content_type_get_name(vsc->content_type));
2915 #undef DP_SDP_LOG
2916 }
2917 EXPORT_SYMBOL(drm_dp_vsc_sdp_log);
2918 
2919 /**
2920  * drm_dp_get_pcon_max_frl_bw() - maximum frl supported by PCON
2921  * @dpcd: DisplayPort configuration data
2922  * @port_cap: port capabilities
2923  *
2924  * Returns maximum frl bandwidth supported by PCON in GBPS,
2925  * returns 0 if not supported.
2926  */
2927 int drm_dp_get_pcon_max_frl_bw(const u8 dpcd[DP_RECEIVER_CAP_SIZE],
2928 			       const u8 port_cap[4])
2929 {
2930 	int bw;
2931 	u8 buf;
2932 
2933 	buf = port_cap[2];
2934 	bw = buf & DP_PCON_MAX_FRL_BW;
2935 
2936 	switch (bw) {
2937 	case DP_PCON_MAX_9GBPS:
2938 		return 9;
2939 	case DP_PCON_MAX_18GBPS:
2940 		return 18;
2941 	case DP_PCON_MAX_24GBPS:
2942 		return 24;
2943 	case DP_PCON_MAX_32GBPS:
2944 		return 32;
2945 	case DP_PCON_MAX_40GBPS:
2946 		return 40;
2947 	case DP_PCON_MAX_48GBPS:
2948 		return 48;
2949 	case DP_PCON_MAX_0GBPS:
2950 	default:
2951 		return 0;
2952 	}
2953 
2954 	return 0;
2955 }
2956 EXPORT_SYMBOL(drm_dp_get_pcon_max_frl_bw);
2957 
2958 /**
2959  * drm_dp_pcon_frl_prepare() - Prepare PCON for FRL.
2960  * @aux: DisplayPort AUX channel
2961  * @enable_frl_ready_hpd: Configure DP_PCON_ENABLE_HPD_READY.
2962  *
2963  * Returns 0 if success, else returns negative error code.
2964  */
2965 int drm_dp_pcon_frl_prepare(struct drm_dp_aux *aux, bool enable_frl_ready_hpd)
2966 {
2967 	int ret;
2968 	u8 buf = DP_PCON_ENABLE_SOURCE_CTL_MODE |
2969 		 DP_PCON_ENABLE_LINK_FRL_MODE;
2970 
2971 	if (enable_frl_ready_hpd)
2972 		buf |= DP_PCON_ENABLE_HPD_READY;
2973 
2974 	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
2975 
2976 	return ret;
2977 }
2978 EXPORT_SYMBOL(drm_dp_pcon_frl_prepare);
2979 
2980 /**
2981  * drm_dp_pcon_is_frl_ready() - Is PCON ready for FRL
2982  * @aux: DisplayPort AUX channel
2983  *
2984  * Returns true if success, else returns false.
2985  */
2986 bool drm_dp_pcon_is_frl_ready(struct drm_dp_aux *aux)
2987 {
2988 	int ret;
2989 	u8 buf;
2990 
2991 	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
2992 	if (ret < 0)
2993 		return false;
2994 
2995 	if (buf & DP_PCON_FRL_READY)
2996 		return true;
2997 
2998 	return false;
2999 }
3000 EXPORT_SYMBOL(drm_dp_pcon_is_frl_ready);
3001 
3002 /**
3003  * drm_dp_pcon_frl_configure_1() - Set HDMI LINK Configuration-Step1
3004  * @aux: DisplayPort AUX channel
3005  * @max_frl_gbps: maximum frl bw to be configured between PCON and HDMI sink
3006  * @frl_mode: FRL Training mode, it can be either Concurrent or Sequential.
3007  * In Concurrent Mode, the FRL link bring up can be done along with
3008  * DP Link training. In Sequential mode, the FRL link bring up is done prior to
3009  * the DP Link training.
3010  *
3011  * Returns 0 if success, else returns negative error code.
3012  */
3013 
3014 int drm_dp_pcon_frl_configure_1(struct drm_dp_aux *aux, int max_frl_gbps,
3015 				u8 frl_mode)
3016 {
3017 	int ret;
3018 	u8 buf;
3019 
3020 	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
3021 	if (ret < 0)
3022 		return ret;
3023 
3024 	if (frl_mode == DP_PCON_ENABLE_CONCURRENT_LINK)
3025 		buf |= DP_PCON_ENABLE_CONCURRENT_LINK;
3026 	else
3027 		buf &= ~DP_PCON_ENABLE_CONCURRENT_LINK;
3028 
3029 	switch (max_frl_gbps) {
3030 	case 9:
3031 		buf |=  DP_PCON_ENABLE_MAX_BW_9GBPS;
3032 		break;
3033 	case 18:
3034 		buf |=  DP_PCON_ENABLE_MAX_BW_18GBPS;
3035 		break;
3036 	case 24:
3037 		buf |=  DP_PCON_ENABLE_MAX_BW_24GBPS;
3038 		break;
3039 	case 32:
3040 		buf |=  DP_PCON_ENABLE_MAX_BW_32GBPS;
3041 		break;
3042 	case 40:
3043 		buf |=  DP_PCON_ENABLE_MAX_BW_40GBPS;
3044 		break;
3045 	case 48:
3046 		buf |=  DP_PCON_ENABLE_MAX_BW_48GBPS;
3047 		break;
3048 	case 0:
3049 		buf |=  DP_PCON_ENABLE_MAX_BW_0GBPS;
3050 		break;
3051 	default:
3052 		return -EINVAL;
3053 	}
3054 
3055 	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3056 	if (ret < 0)
3057 		return ret;
3058 
3059 	return 0;
3060 }
3061 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_1);
3062 
3063 /**
3064  * drm_dp_pcon_frl_configure_2() - Set HDMI Link configuration Step-2
3065  * @aux: DisplayPort AUX channel
3066  * @max_frl_mask : Max FRL BW to be tried by the PCON with HDMI Sink
3067  * @frl_type : FRL training type, can be Extended, or Normal.
3068  * In Normal FRL training, the PCON tries each frl bw from the max_frl_mask
3069  * starting from min, and stops when link training is successful. In Extended
3070  * FRL training, all frl bw selected in the mask are trained by the PCON.
3071  *
3072  * Returns 0 if success, else returns negative error code.
3073  */
3074 int drm_dp_pcon_frl_configure_2(struct drm_dp_aux *aux, int max_frl_mask,
3075 				u8 frl_type)
3076 {
3077 	int ret;
3078 	u8 buf = max_frl_mask;
3079 
3080 	if (frl_type == DP_PCON_FRL_LINK_TRAIN_EXTENDED)
3081 		buf |= DP_PCON_FRL_LINK_TRAIN_EXTENDED;
3082 	else
3083 		buf &= ~DP_PCON_FRL_LINK_TRAIN_EXTENDED;
3084 
3085 	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_2, buf);
3086 	if (ret < 0)
3087 		return ret;
3088 
3089 	return 0;
3090 }
3091 EXPORT_SYMBOL(drm_dp_pcon_frl_configure_2);
3092 
3093 /**
3094  * drm_dp_pcon_reset_frl_config() - Re-Set HDMI Link configuration.
3095  * @aux: DisplayPort AUX channel
3096  *
3097  * Returns 0 if success, else returns negative error code.
3098  */
3099 int drm_dp_pcon_reset_frl_config(struct drm_dp_aux *aux)
3100 {
3101 	int ret;
3102 
3103 	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, 0x0);
3104 	if (ret < 0)
3105 		return ret;
3106 
3107 	return 0;
3108 }
3109 EXPORT_SYMBOL(drm_dp_pcon_reset_frl_config);
3110 
3111 /**
3112  * drm_dp_pcon_frl_enable() - Enable HDMI link through FRL
3113  * @aux: DisplayPort AUX channel
3114  *
3115  * Returns 0 if success, else returns negative error code.
3116  */
3117 int drm_dp_pcon_frl_enable(struct drm_dp_aux *aux)
3118 {
3119 	int ret;
3120 	u8 buf = 0;
3121 
3122 	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf);
3123 	if (ret < 0)
3124 		return ret;
3125 	if (!(buf & DP_PCON_ENABLE_SOURCE_CTL_MODE)) {
3126 		drm_dbg_kms(aux->drm_dev, "%s: PCON in Autonomous mode, can't enable FRL\n",
3127 			    aux->name);
3128 		return -EINVAL;
3129 	}
3130 	buf |= DP_PCON_ENABLE_HDMI_LINK;
3131 	ret = drm_dp_dpcd_writeb(aux, DP_PCON_HDMI_LINK_CONFIG_1, buf);
3132 	if (ret < 0)
3133 		return ret;
3134 
3135 	return 0;
3136 }
3137 EXPORT_SYMBOL(drm_dp_pcon_frl_enable);
3138 
3139 /**
3140  * drm_dp_pcon_hdmi_link_active() - check if the PCON HDMI LINK status is active.
3141  * @aux: DisplayPort AUX channel
3142  *
3143  * Returns true if link is active else returns false.
3144  */
3145 bool drm_dp_pcon_hdmi_link_active(struct drm_dp_aux *aux)
3146 {
3147 	u8 buf;
3148 	int ret;
3149 
3150 	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_TX_LINK_STATUS, &buf);
3151 	if (ret < 0)
3152 		return false;
3153 
3154 	return buf & DP_PCON_HDMI_TX_LINK_ACTIVE;
3155 }
3156 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_active);
3157 
3158 /**
3159  * drm_dp_pcon_hdmi_link_mode() - get the PCON HDMI LINK MODE
3160  * @aux: DisplayPort AUX channel
3161  * @frl_trained_mask: pointer to store bitmask of the trained bw configuration.
3162  * Valid only if the MODE returned is FRL. For Normal Link training mode
3163  * only 1 of the bits will be set, but in case of Extended mode, more than
3164  * one bits can be set.
3165  *
3166  * Returns the link mode : TMDS or FRL on success, else returns negative error
3167  * code.
3168  */
3169 int drm_dp_pcon_hdmi_link_mode(struct drm_dp_aux *aux, u8 *frl_trained_mask)
3170 {
3171 	u8 buf;
3172 	int mode;
3173 	int ret;
3174 
3175 	ret = drm_dp_dpcd_readb(aux, DP_PCON_HDMI_POST_FRL_STATUS, &buf);
3176 	if (ret < 0)
3177 		return ret;
3178 
3179 	mode = buf & DP_PCON_HDMI_LINK_MODE;
3180 
3181 	if (frl_trained_mask && DP_PCON_HDMI_MODE_FRL == mode)
3182 		*frl_trained_mask = (buf & DP_PCON_HDMI_FRL_TRAINED_BW) >> 1;
3183 
3184 	return mode;
3185 }
3186 EXPORT_SYMBOL(drm_dp_pcon_hdmi_link_mode);
3187 
3188 /**
3189  * drm_dp_pcon_hdmi_frl_link_error_count() - print the error count per lane
3190  * during link failure between PCON and HDMI sink
3191  * @aux: DisplayPort AUX channel
3192  * @connector: DRM connector
3193  * code.
3194  **/
3195 
3196 void drm_dp_pcon_hdmi_frl_link_error_count(struct drm_dp_aux *aux,
3197 					   struct drm_connector *connector)
3198 {
3199 	u8 buf, error_count;
3200 	int i, num_error;
3201 	struct drm_hdmi_info *hdmi = &connector->display_info.hdmi;
3202 
3203 	for (i = 0; i < hdmi->max_lanes; i++) {
3204 		if (drm_dp_dpcd_readb(aux, DP_PCON_HDMI_ERROR_STATUS_LN0 + i, &buf) < 0)
3205 			return;
3206 
3207 		error_count = buf & DP_PCON_HDMI_ERROR_COUNT_MASK;
3208 		switch (error_count) {
3209 		case DP_PCON_HDMI_ERROR_COUNT_HUNDRED_PLUS:
3210 			num_error = 100;
3211 			break;
3212 		case DP_PCON_HDMI_ERROR_COUNT_TEN_PLUS:
3213 			num_error = 10;
3214 			break;
3215 		case DP_PCON_HDMI_ERROR_COUNT_THREE_PLUS:
3216 			num_error = 3;
3217 			break;
3218 		default:
3219 			num_error = 0;
3220 		}
3221 
3222 		drm_err(aux->drm_dev, "%s: More than %d errors since the last read for lane %d",
3223 			aux->name, num_error, i);
3224 	}
3225 }
3226 EXPORT_SYMBOL(drm_dp_pcon_hdmi_frl_link_error_count);
3227 
3228 /*
3229  * drm_dp_pcon_enc_is_dsc_1_2 - Does PCON Encoder supports DSC 1.2
3230  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3231  *
3232  * Returns true is PCON encoder is DSC 1.2 else returns false.
3233  */
3234 bool drm_dp_pcon_enc_is_dsc_1_2(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3235 {
3236 	u8 buf;
3237 	u8 major_v, minor_v;
3238 
3239 	buf = pcon_dsc_dpcd[DP_PCON_DSC_VERSION - DP_PCON_DSC_ENCODER];
3240 	major_v = (buf & DP_PCON_DSC_MAJOR_MASK) >> DP_PCON_DSC_MAJOR_SHIFT;
3241 	minor_v = (buf & DP_PCON_DSC_MINOR_MASK) >> DP_PCON_DSC_MINOR_SHIFT;
3242 
3243 	if (major_v == 1 && minor_v == 2)
3244 		return true;
3245 
3246 	return false;
3247 }
3248 EXPORT_SYMBOL(drm_dp_pcon_enc_is_dsc_1_2);
3249 
3250 /*
3251  * drm_dp_pcon_dsc_max_slices - Get max slices supported by PCON DSC Encoder
3252  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3253  *
3254  * Returns maximum no. of slices supported by the PCON DSC Encoder.
3255  */
3256 int drm_dp_pcon_dsc_max_slices(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3257 {
3258 	u8 slice_cap1, slice_cap2;
3259 
3260 	slice_cap1 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_1 - DP_PCON_DSC_ENCODER];
3261 	slice_cap2 = pcon_dsc_dpcd[DP_PCON_DSC_SLICE_CAP_2 - DP_PCON_DSC_ENCODER];
3262 
3263 	if (slice_cap2 & DP_PCON_DSC_24_PER_DSC_ENC)
3264 		return 24;
3265 	if (slice_cap2 & DP_PCON_DSC_20_PER_DSC_ENC)
3266 		return 20;
3267 	if (slice_cap2 & DP_PCON_DSC_16_PER_DSC_ENC)
3268 		return 16;
3269 	if (slice_cap1 & DP_PCON_DSC_12_PER_DSC_ENC)
3270 		return 12;
3271 	if (slice_cap1 & DP_PCON_DSC_10_PER_DSC_ENC)
3272 		return 10;
3273 	if (slice_cap1 & DP_PCON_DSC_8_PER_DSC_ENC)
3274 		return 8;
3275 	if (slice_cap1 & DP_PCON_DSC_6_PER_DSC_ENC)
3276 		return 6;
3277 	if (slice_cap1 & DP_PCON_DSC_4_PER_DSC_ENC)
3278 		return 4;
3279 	if (slice_cap1 & DP_PCON_DSC_2_PER_DSC_ENC)
3280 		return 2;
3281 	if (slice_cap1 & DP_PCON_DSC_1_PER_DSC_ENC)
3282 		return 1;
3283 
3284 	return 0;
3285 }
3286 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slices);
3287 
3288 /*
3289  * drm_dp_pcon_dsc_max_slice_width() - Get max slice width for Pcon DSC encoder
3290  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3291  *
3292  * Returns maximum width of the slices in pixel width i.e. no. of pixels x 320.
3293  */
3294 int drm_dp_pcon_dsc_max_slice_width(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3295 {
3296 	u8 buf;
3297 
3298 	buf = pcon_dsc_dpcd[DP_PCON_DSC_MAX_SLICE_WIDTH - DP_PCON_DSC_ENCODER];
3299 
3300 	return buf * DP_DSC_SLICE_WIDTH_MULTIPLIER;
3301 }
3302 EXPORT_SYMBOL(drm_dp_pcon_dsc_max_slice_width);
3303 
3304 /*
3305  * drm_dp_pcon_dsc_bpp_incr() - Get bits per pixel increment for PCON DSC encoder
3306  * @pcon_dsc_dpcd: DSC capabilities of the PCON DSC Encoder
3307  *
3308  * Returns the bpp precision supported by the PCON encoder.
3309  */
3310 int drm_dp_pcon_dsc_bpp_incr(const u8 pcon_dsc_dpcd[DP_PCON_DSC_ENCODER_CAP_SIZE])
3311 {
3312 	u8 buf;
3313 
3314 	buf = pcon_dsc_dpcd[DP_PCON_DSC_BPP_INCR - DP_PCON_DSC_ENCODER];
3315 
3316 	switch (buf & DP_PCON_DSC_BPP_INCR_MASK) {
3317 	case DP_PCON_DSC_ONE_16TH_BPP:
3318 		return 16;
3319 	case DP_PCON_DSC_ONE_8TH_BPP:
3320 		return 8;
3321 	case DP_PCON_DSC_ONE_4TH_BPP:
3322 		return 4;
3323 	case DP_PCON_DSC_ONE_HALF_BPP:
3324 		return 2;
3325 	case DP_PCON_DSC_ONE_BPP:
3326 		return 1;
3327 	}
3328 
3329 	return 0;
3330 }
3331 EXPORT_SYMBOL(drm_dp_pcon_dsc_bpp_incr);
3332 
3333 static
3334 int drm_dp_pcon_configure_dsc_enc(struct drm_dp_aux *aux, u8 pps_buf_config)
3335 {
3336 	u8 buf;
3337 	int ret;
3338 
3339 	ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
3340 	if (ret < 0)
3341 		return ret;
3342 
3343 	buf |= DP_PCON_ENABLE_DSC_ENCODER;
3344 
3345 	if (pps_buf_config <= DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER) {
3346 		buf &= ~DP_PCON_ENCODER_PPS_OVERRIDE_MASK;
3347 		buf |= pps_buf_config << 2;
3348 	}
3349 
3350 	ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
3351 	if (ret < 0)
3352 		return ret;
3353 
3354 	return 0;
3355 }
3356 
3357 /**
3358  * drm_dp_pcon_pps_default() - Let PCON fill the default pps parameters
3359  * for DSC1.2 between PCON & HDMI2.1 sink
3360  * @aux: DisplayPort AUX channel
3361  *
3362  * Returns 0 on success, else returns negative error code.
3363  */
3364 int drm_dp_pcon_pps_default(struct drm_dp_aux *aux)
3365 {
3366 	int ret;
3367 
3368 	ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_DISABLED);
3369 	if (ret < 0)
3370 		return ret;
3371 
3372 	return 0;
3373 }
3374 EXPORT_SYMBOL(drm_dp_pcon_pps_default);
3375 
3376 /**
3377  * drm_dp_pcon_pps_override_buf() - Configure PPS encoder override buffer for
3378  * HDMI sink
3379  * @aux: DisplayPort AUX channel
3380  * @pps_buf: 128 bytes to be written into PPS buffer for HDMI sink by PCON.
3381  *
3382  * Returns 0 on success, else returns negative error code.
3383  */
3384 int drm_dp_pcon_pps_override_buf(struct drm_dp_aux *aux, u8 pps_buf[128])
3385 {
3386 	int ret;
3387 
3388 	ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVERRIDE_BASE, &pps_buf, 128);
3389 	if (ret < 0)
3390 		return ret;
3391 
3392 	ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3393 	if (ret < 0)
3394 		return ret;
3395 
3396 	return 0;
3397 }
3398 EXPORT_SYMBOL(drm_dp_pcon_pps_override_buf);
3399 
3400 /*
3401  * drm_dp_pcon_pps_override_param() - Write PPS parameters to DSC encoder
3402  * override registers
3403  * @aux: DisplayPort AUX channel
3404  * @pps_param: 3 Parameters (2 Bytes each) : Slice Width, Slice Height,
3405  * bits_per_pixel.
3406  *
3407  * Returns 0 on success, else returns negative error code.
3408  */
3409 int drm_dp_pcon_pps_override_param(struct drm_dp_aux *aux, u8 pps_param[6])
3410 {
3411 	int ret;
3412 
3413 	ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_HEIGHT, &pps_param[0], 2);
3414 	if (ret < 0)
3415 		return ret;
3416 	ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_SLICE_WIDTH, &pps_param[2], 2);
3417 	if (ret < 0)
3418 		return ret;
3419 	ret = drm_dp_dpcd_write(aux, DP_PCON_HDMI_PPS_OVRD_BPP, &pps_param[4], 2);
3420 	if (ret < 0)
3421 		return ret;
3422 
3423 	ret = drm_dp_pcon_configure_dsc_enc(aux, DP_PCON_ENC_PPS_OVERRIDE_EN_BUFFER);
3424 	if (ret < 0)
3425 		return ret;
3426 
3427 	return 0;
3428 }
3429 EXPORT_SYMBOL(drm_dp_pcon_pps_override_param);
3430 
3431 /*
3432  * drm_dp_pcon_convert_rgb_to_ycbcr() - Configure the PCon to convert RGB to Ycbcr
3433  * @aux: displayPort AUX channel
3434  * @color_spc: Color-space/s for which conversion is to be enabled, 0 for disable.
3435  *
3436  * Returns 0 on success, else returns negative error code.
3437  */
3438 int drm_dp_pcon_convert_rgb_to_ycbcr(struct drm_dp_aux *aux, u8 color_spc)
3439 {
3440 	int ret;
3441 	u8 buf;
3442 
3443 	ret = drm_dp_dpcd_readb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, &buf);
3444 	if (ret < 0)
3445 		return ret;
3446 
3447 	if (color_spc & DP_CONVERSION_RGB_YCBCR_MASK)
3448 		buf |= (color_spc & DP_CONVERSION_RGB_YCBCR_MASK);
3449 	else
3450 		buf &= ~DP_CONVERSION_RGB_YCBCR_MASK;
3451 
3452 	ret = drm_dp_dpcd_writeb(aux, DP_PROTOCOL_CONVERTER_CONTROL_2, buf);
3453 	if (ret < 0)
3454 		return ret;
3455 
3456 	return 0;
3457 }
3458 EXPORT_SYMBOL(drm_dp_pcon_convert_rgb_to_ycbcr);
3459 
3460 /**
3461  * drm_edp_backlight_set_level() - Set the backlight level of an eDP panel via AUX
3462  * @aux: The DP AUX channel to use
3463  * @bl: Backlight capability info from drm_edp_backlight_init()
3464  * @level: The brightness level to set
3465  *
3466  * Sets the brightness level of an eDP panel's backlight. Note that the panel's backlight must
3467  * already have been enabled by the driver by calling drm_edp_backlight_enable().
3468  *
3469  * Returns: %0 on success, negative error code on failure
3470  */
3471 int drm_edp_backlight_set_level(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3472 				u16 level)
3473 {
3474 	int ret;
3475 	u8 buf[2] = { 0 };
3476 
3477 	/* The panel uses the PWM for controlling brightness levels */
3478 	if (!bl->aux_set)
3479 		return 0;
3480 
3481 	if (bl->lsb_reg_used) {
3482 		buf[0] = (level & 0xff00) >> 8;
3483 		buf[1] = (level & 0x00ff);
3484 	} else {
3485 		buf[0] = level;
3486 	}
3487 
3488 	ret = drm_dp_dpcd_write(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, sizeof(buf));
3489 	if (ret != sizeof(buf)) {
3490 		drm_err(aux->drm_dev,
3491 			"%s: Failed to write aux backlight level: %d\n",
3492 			aux->name, ret);
3493 		return ret < 0 ? ret : -EIO;
3494 	}
3495 
3496 	return 0;
3497 }
3498 EXPORT_SYMBOL(drm_edp_backlight_set_level);
3499 
3500 static int
3501 drm_edp_backlight_set_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3502 			     bool enable)
3503 {
3504 	int ret;
3505 	u8 buf;
3506 
3507 	/* This panel uses the EDP_BL_PWR GPIO for enablement */
3508 	if (!bl->aux_enable)
3509 		return 0;
3510 
3511 	ret = drm_dp_dpcd_readb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, &buf);
3512 	if (ret != 1) {
3513 		drm_err(aux->drm_dev, "%s: Failed to read eDP display control register: %d\n",
3514 			aux->name, ret);
3515 		return ret < 0 ? ret : -EIO;
3516 	}
3517 	if (enable)
3518 		buf |= DP_EDP_BACKLIGHT_ENABLE;
3519 	else
3520 		buf &= ~DP_EDP_BACKLIGHT_ENABLE;
3521 
3522 	ret = drm_dp_dpcd_writeb(aux, DP_EDP_DISPLAY_CONTROL_REGISTER, buf);
3523 	if (ret != 1) {
3524 		drm_err(aux->drm_dev, "%s: Failed to write eDP display control register: %d\n",
3525 			aux->name, ret);
3526 		return ret < 0 ? ret : -EIO;
3527 	}
3528 
3529 	return 0;
3530 }
3531 
3532 /**
3533  * drm_edp_backlight_enable() - Enable an eDP panel's backlight using DPCD
3534  * @aux: The DP AUX channel to use
3535  * @bl: Backlight capability info from drm_edp_backlight_init()
3536  * @level: The initial backlight level to set via AUX, if there is one
3537  *
3538  * This function handles enabling DPCD backlight controls on a panel over DPCD, while additionally
3539  * restoring any important backlight state such as the given backlight level, the brightness byte
3540  * count, backlight frequency, etc.
3541  *
3542  * Note that certain panels do not support being enabled or disabled via DPCD, but instead require
3543  * that the driver handle enabling/disabling the panel through implementation-specific means using
3544  * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
3545  * this function becomes a no-op, and the driver is expected to handle powering the panel on using
3546  * the EDP_BL_PWR GPIO.
3547  *
3548  * Returns: %0 on success, negative error code on failure.
3549  */
3550 int drm_edp_backlight_enable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl,
3551 			     const u16 level)
3552 {
3553 	int ret;
3554 	u8 dpcd_buf;
3555 
3556 	if (bl->aux_set)
3557 		dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD;
3558 	else
3559 		dpcd_buf = DP_EDP_BACKLIGHT_CONTROL_MODE_PWM;
3560 
3561 	if (bl->pwmgen_bit_count) {
3562 		ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, bl->pwmgen_bit_count);
3563 		if (ret != 1)
3564 			drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
3565 				    aux->name, ret);
3566 	}
3567 
3568 	if (bl->pwm_freq_pre_divider) {
3569 		ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_FREQ_SET, bl->pwm_freq_pre_divider);
3570 		if (ret != 1)
3571 			drm_dbg_kms(aux->drm_dev,
3572 				    "%s: Failed to write aux backlight frequency: %d\n",
3573 				    aux->name, ret);
3574 		else
3575 			dpcd_buf |= DP_EDP_BACKLIGHT_FREQ_AUX_SET_ENABLE;
3576 	}
3577 
3578 	ret = drm_dp_dpcd_writeb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, dpcd_buf);
3579 	if (ret != 1) {
3580 		drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux backlight mode: %d\n",
3581 			    aux->name, ret);
3582 		return ret < 0 ? ret : -EIO;
3583 	}
3584 
3585 	ret = drm_edp_backlight_set_level(aux, bl, level);
3586 	if (ret < 0)
3587 		return ret;
3588 	ret = drm_edp_backlight_set_enable(aux, bl, true);
3589 	if (ret < 0)
3590 		return ret;
3591 
3592 	return 0;
3593 }
3594 EXPORT_SYMBOL(drm_edp_backlight_enable);
3595 
3596 /**
3597  * drm_edp_backlight_disable() - Disable an eDP backlight using DPCD, if supported
3598  * @aux: The DP AUX channel to use
3599  * @bl: Backlight capability info from drm_edp_backlight_init()
3600  *
3601  * This function handles disabling DPCD backlight controls on a panel over AUX.
3602  *
3603  * Note that certain panels do not support being enabled or disabled via DPCD, but instead require
3604  * that the driver handle enabling/disabling the panel through implementation-specific means using
3605  * the EDP_BL_PWR GPIO. For such panels, &drm_edp_backlight_info.aux_enable will be set to %false,
3606  * this function becomes a no-op, and the driver is expected to handle powering the panel off using
3607  * the EDP_BL_PWR GPIO.
3608  *
3609  * Returns: %0 on success or no-op, negative error code on failure.
3610  */
3611 int drm_edp_backlight_disable(struct drm_dp_aux *aux, const struct drm_edp_backlight_info *bl)
3612 {
3613 	int ret;
3614 
3615 	ret = drm_edp_backlight_set_enable(aux, bl, false);
3616 	if (ret < 0)
3617 		return ret;
3618 
3619 	return 0;
3620 }
3621 EXPORT_SYMBOL(drm_edp_backlight_disable);
3622 
3623 static inline int
3624 drm_edp_backlight_probe_max(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3625 			    u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE])
3626 {
3627 	int fxp, fxp_min, fxp_max, fxp_actual, f = 1;
3628 	int ret;
3629 	u8 pn, pn_min, pn_max;
3630 
3631 	if (!bl->aux_set)
3632 		return 0;
3633 
3634 	ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT, &pn);
3635 	if (ret != 1) {
3636 		drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap: %d\n",
3637 			    aux->name, ret);
3638 		return -ENODEV;
3639 	}
3640 
3641 	pn &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3642 	bl->max = (1 << pn) - 1;
3643 	if (!driver_pwm_freq_hz)
3644 		return 0;
3645 
3646 	/*
3647 	 * Set PWM Frequency divider to match desired frequency provided by the driver.
3648 	 * The PWM Frequency is calculated as 27Mhz / (F x P).
3649 	 * - Where F = PWM Frequency Pre-Divider value programmed by field 7:0 of the
3650 	 *             EDP_BACKLIGHT_FREQ_SET register (DPCD Address 00728h)
3651 	 * - Where P = 2^Pn, where Pn is the value programmed by field 4:0 of the
3652 	 *             EDP_PWMGEN_BIT_COUNT register (DPCD Address 00724h)
3653 	 */
3654 
3655 	/* Find desired value of (F x P)
3656 	 * Note that, if F x P is out of supported range, the maximum value or minimum value will
3657 	 * applied automatically. So no need to check that.
3658 	 */
3659 	fxp = DIV_ROUND_CLOSEST(1000 * DP_EDP_BACKLIGHT_FREQ_BASE_KHZ, driver_pwm_freq_hz);
3660 
3661 	/* Use highest possible value of Pn for more granularity of brightness adjustment while
3662 	 * satisfying the conditions below.
3663 	 * - Pn is in the range of Pn_min and Pn_max
3664 	 * - F is in the range of 1 and 255
3665 	 * - FxP is within 25% of desired value.
3666 	 *   Note: 25% is arbitrary value and may need some tweak.
3667 	 */
3668 	ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MIN, &pn_min);
3669 	if (ret != 1) {
3670 		drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap min: %d\n",
3671 			    aux->name, ret);
3672 		return 0;
3673 	}
3674 	ret = drm_dp_dpcd_readb(aux, DP_EDP_PWMGEN_BIT_COUNT_CAP_MAX, &pn_max);
3675 	if (ret != 1) {
3676 		drm_dbg_kms(aux->drm_dev, "%s: Failed to read pwmgen bit count cap max: %d\n",
3677 			    aux->name, ret);
3678 		return 0;
3679 	}
3680 	pn_min &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3681 	pn_max &= DP_EDP_PWMGEN_BIT_COUNT_MASK;
3682 
3683 	/* Ensure frequency is within 25% of desired value */
3684 	fxp_min = DIV_ROUND_CLOSEST(fxp * 3, 4);
3685 	fxp_max = DIV_ROUND_CLOSEST(fxp * 5, 4);
3686 	if (fxp_min < (1 << pn_min) || (255 << pn_max) < fxp_max) {
3687 		drm_dbg_kms(aux->drm_dev,
3688 			    "%s: Driver defined backlight frequency (%d) out of range\n",
3689 			    aux->name, driver_pwm_freq_hz);
3690 		return 0;
3691 	}
3692 
3693 	for (pn = pn_max; pn >= pn_min; pn--) {
3694 		f = clamp(DIV_ROUND_CLOSEST(fxp, 1 << pn), 1, 255);
3695 		fxp_actual = f << pn;
3696 		if (fxp_min <= fxp_actual && fxp_actual <= fxp_max)
3697 			break;
3698 	}
3699 
3700 	ret = drm_dp_dpcd_writeb(aux, DP_EDP_PWMGEN_BIT_COUNT, pn);
3701 	if (ret != 1) {
3702 		drm_dbg_kms(aux->drm_dev, "%s: Failed to write aux pwmgen bit count: %d\n",
3703 			    aux->name, ret);
3704 		return 0;
3705 	}
3706 	bl->pwmgen_bit_count = pn;
3707 	bl->max = (1 << pn) - 1;
3708 
3709 	if (edp_dpcd[2] & DP_EDP_BACKLIGHT_FREQ_AUX_SET_CAP) {
3710 		bl->pwm_freq_pre_divider = f;
3711 		drm_dbg_kms(aux->drm_dev, "%s: Using backlight frequency from driver (%dHz)\n",
3712 			    aux->name, driver_pwm_freq_hz);
3713 	}
3714 
3715 	return 0;
3716 }
3717 
3718 static inline int
3719 drm_edp_backlight_probe_state(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3720 			      u8 *current_mode)
3721 {
3722 	int ret;
3723 	u8 buf[2];
3724 	u8 mode_reg;
3725 
3726 	ret = drm_dp_dpcd_readb(aux, DP_EDP_BACKLIGHT_MODE_SET_REGISTER, &mode_reg);
3727 	if (ret != 1) {
3728 		drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight mode: %d\n",
3729 			    aux->name, ret);
3730 		return ret < 0 ? ret : -EIO;
3731 	}
3732 
3733 	*current_mode = (mode_reg & DP_EDP_BACKLIGHT_CONTROL_MODE_MASK);
3734 	if (!bl->aux_set)
3735 		return 0;
3736 
3737 	if (*current_mode == DP_EDP_BACKLIGHT_CONTROL_MODE_DPCD) {
3738 		int size = 1 + bl->lsb_reg_used;
3739 
3740 		ret = drm_dp_dpcd_read(aux, DP_EDP_BACKLIGHT_BRIGHTNESS_MSB, buf, size);
3741 		if (ret != size) {
3742 			drm_dbg_kms(aux->drm_dev, "%s: Failed to read backlight level: %d\n",
3743 				    aux->name, ret);
3744 			return ret < 0 ? ret : -EIO;
3745 		}
3746 
3747 		if (bl->lsb_reg_used)
3748 			return (buf[0] << 8) | buf[1];
3749 		else
3750 			return buf[0];
3751 	}
3752 
3753 	/*
3754 	 * If we're not in DPCD control mode yet, the programmed brightness value is meaningless and
3755 	 * the driver should assume max brightness
3756 	 */
3757 	return bl->max;
3758 }
3759 
3760 /**
3761  * drm_edp_backlight_init() - Probe a display panel's TCON using the standard VESA eDP backlight
3762  * interface.
3763  * @aux: The DP aux device to use for probing
3764  * @bl: The &drm_edp_backlight_info struct to fill out with information on the backlight
3765  * @driver_pwm_freq_hz: Optional PWM frequency from the driver in hz
3766  * @edp_dpcd: A cached copy of the eDP DPCD
3767  * @current_level: Where to store the probed brightness level, if any
3768  * @current_mode: Where to store the currently set backlight control mode
3769  *
3770  * Initializes a &drm_edp_backlight_info struct by probing @aux for it's backlight capabilities,
3771  * along with also probing the current and maximum supported brightness levels.
3772  *
3773  * If @driver_pwm_freq_hz is non-zero, this will be used as the backlight frequency. Otherwise, the
3774  * default frequency from the panel is used.
3775  *
3776  * Returns: %0 on success, negative error code on failure.
3777  */
3778 int
3779 drm_edp_backlight_init(struct drm_dp_aux *aux, struct drm_edp_backlight_info *bl,
3780 		       u16 driver_pwm_freq_hz, const u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE],
3781 		       u16 *current_level, u8 *current_mode)
3782 {
3783 	int ret;
3784 
3785 	if (edp_dpcd[1] & DP_EDP_BACKLIGHT_AUX_ENABLE_CAP)
3786 		bl->aux_enable = true;
3787 	if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_AUX_SET_CAP)
3788 		bl->aux_set = true;
3789 	if (edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_BYTE_COUNT)
3790 		bl->lsb_reg_used = true;
3791 
3792 	/* Sanity check caps */
3793 	if (!bl->aux_set && !(edp_dpcd[2] & DP_EDP_BACKLIGHT_BRIGHTNESS_PWM_PIN_CAP)) {
3794 		drm_dbg_kms(aux->drm_dev,
3795 			    "%s: Panel supports neither AUX or PWM brightness control? Aborting\n",
3796 			    aux->name);
3797 		return -EINVAL;
3798 	}
3799 
3800 	ret = drm_edp_backlight_probe_max(aux, bl, driver_pwm_freq_hz, edp_dpcd);
3801 	if (ret < 0)
3802 		return ret;
3803 
3804 	ret = drm_edp_backlight_probe_state(aux, bl, current_mode);
3805 	if (ret < 0)
3806 		return ret;
3807 	*current_level = ret;
3808 
3809 	drm_dbg_kms(aux->drm_dev,
3810 		    "%s: Found backlight: aux_set=%d aux_enable=%d mode=%d\n",
3811 		    aux->name, bl->aux_set, bl->aux_enable, *current_mode);
3812 	if (bl->aux_set) {
3813 		drm_dbg_kms(aux->drm_dev,
3814 			    "%s: Backlight caps: level=%d/%d pwm_freq_pre_divider=%d lsb_reg_used=%d\n",
3815 			    aux->name, *current_level, bl->max, bl->pwm_freq_pre_divider,
3816 			    bl->lsb_reg_used);
3817 	}
3818 
3819 	return 0;
3820 }
3821 EXPORT_SYMBOL(drm_edp_backlight_init);
3822 
3823 #if IS_BUILTIN(CONFIG_BACKLIGHT_CLASS_DEVICE) || \
3824 	(IS_MODULE(CONFIG_DRM_KMS_HELPER) && IS_MODULE(CONFIG_BACKLIGHT_CLASS_DEVICE))
3825 
3826 static int dp_aux_backlight_update_status(struct backlight_device *bd)
3827 {
3828 	struct dp_aux_backlight *bl = bl_get_data(bd);
3829 	u16 brightness = backlight_get_brightness(bd);
3830 	int ret = 0;
3831 
3832 	if (!backlight_is_blank(bd)) {
3833 		if (!bl->enabled) {
3834 			drm_edp_backlight_enable(bl->aux, &bl->info, brightness);
3835 			bl->enabled = true;
3836 			return 0;
3837 		}
3838 		ret = drm_edp_backlight_set_level(bl->aux, &bl->info, brightness);
3839 	} else {
3840 		if (bl->enabled) {
3841 			drm_edp_backlight_disable(bl->aux, &bl->info);
3842 			bl->enabled = false;
3843 		}
3844 	}
3845 
3846 	return ret;
3847 }
3848 
3849 static const struct backlight_ops dp_aux_bl_ops = {
3850 	.update_status = dp_aux_backlight_update_status,
3851 };
3852 
3853 /**
3854  * drm_panel_dp_aux_backlight - create and use DP AUX backlight
3855  * @panel: DRM panel
3856  * @aux: The DP AUX channel to use
3857  *
3858  * Use this function to create and handle backlight if your panel
3859  * supports backlight control over DP AUX channel using DPCD
3860  * registers as per VESA's standard backlight control interface.
3861  *
3862  * When the panel is enabled backlight will be enabled after a
3863  * successful call to &drm_panel_funcs.enable()
3864  *
3865  * When the panel is disabled backlight will be disabled before the
3866  * call to &drm_panel_funcs.disable().
3867  *
3868  * A typical implementation for a panel driver supporting backlight
3869  * control over DP AUX will call this function at probe time.
3870  * Backlight will then be handled transparently without requiring
3871  * any intervention from the driver.
3872  *
3873  * drm_panel_dp_aux_backlight() must be called after the call to drm_panel_init().
3874  *
3875  * Return: 0 on success or a negative error code on failure.
3876  */
3877 int drm_panel_dp_aux_backlight(struct drm_panel *panel, struct drm_dp_aux *aux)
3878 {
3879 	struct dp_aux_backlight *bl;
3880 	struct backlight_properties props = { 0 };
3881 	u16 current_level;
3882 	u8 current_mode;
3883 	u8 edp_dpcd[EDP_DISPLAY_CTL_CAP_SIZE];
3884 	int ret;
3885 
3886 	if (!panel || !panel->dev || !aux)
3887 		return -EINVAL;
3888 
3889 	ret = drm_dp_dpcd_read(aux, DP_EDP_DPCD_REV, edp_dpcd,
3890 			       EDP_DISPLAY_CTL_CAP_SIZE);
3891 	if (ret < 0)
3892 		return ret;
3893 
3894 	if (!drm_edp_backlight_supported(edp_dpcd)) {
3895 		DRM_DEV_INFO(panel->dev, "DP AUX backlight is not supported\n");
3896 		return 0;
3897 	}
3898 
3899 	bl = devm_kzalloc(panel->dev, sizeof(*bl), GFP_KERNEL);
3900 	if (!bl)
3901 		return -ENOMEM;
3902 
3903 	bl->aux = aux;
3904 
3905 	ret = drm_edp_backlight_init(aux, &bl->info, 0, edp_dpcd,
3906 				     &current_level, &current_mode);
3907 	if (ret < 0)
3908 		return ret;
3909 
3910 	props.type = BACKLIGHT_RAW;
3911 	props.brightness = current_level;
3912 	props.max_brightness = bl->info.max;
3913 
3914 	bl->base = devm_backlight_device_register(panel->dev, "dp_aux_backlight",
3915 						  panel->dev, bl,
3916 						  &dp_aux_bl_ops, &props);
3917 	if (IS_ERR(bl->base))
3918 		return PTR_ERR(bl->base);
3919 
3920 	backlight_disable(bl->base);
3921 
3922 	panel->backlight = bl->base;
3923 
3924 	return 0;
3925 }
3926 EXPORT_SYMBOL(drm_panel_dp_aux_backlight);
3927 
3928 #endif
3929 
3930 /* See DP Standard v2.1 2.6.4.4.1.1, 2.8.4.4, 2.8.7 */
3931 static int drm_dp_link_symbol_cycles(int lane_count, int pixels, int bpp_x16,
3932 				     int symbol_size, bool is_mst)
3933 {
3934 	int cycles = DIV_ROUND_UP(pixels * bpp_x16, 16 * symbol_size * lane_count);
3935 	int align = is_mst ? 4 / lane_count : 1;
3936 
3937 	return ALIGN(cycles, align);
3938 }
3939 
3940 static int drm_dp_link_dsc_symbol_cycles(int lane_count, int pixels, int slice_count,
3941 					 int bpp_x16, int symbol_size, bool is_mst)
3942 {
3943 	int slice_pixels = DIV_ROUND_UP(pixels, slice_count);
3944 	int slice_data_cycles = drm_dp_link_symbol_cycles(lane_count, slice_pixels,
3945 							  bpp_x16, symbol_size, is_mst);
3946 	int slice_eoc_cycles = is_mst ? 4 / lane_count : 1;
3947 
3948 	return slice_count * (slice_data_cycles + slice_eoc_cycles);
3949 }
3950 
3951 /**
3952  * drm_dp_bw_overhead - Calculate the BW overhead of a DP link stream
3953  * @lane_count: DP link lane count
3954  * @hactive: pixel count of the active period in one scanline of the stream
3955  * @dsc_slice_count: DSC slice count if @flags/DRM_DP_LINK_BW_OVERHEAD_DSC is set
3956  * @bpp_x16: bits per pixel in .4 binary fixed point
3957  * @flags: DRM_DP_OVERHEAD_x flags
3958  *
3959  * Calculate the BW allocation overhead of a DP link stream, depending
3960  * on the link's
3961  * - @lane_count
3962  * - SST/MST mode (@flags / %DRM_DP_OVERHEAD_MST)
3963  * - symbol size (@flags / %DRM_DP_OVERHEAD_UHBR)
3964  * - FEC mode (@flags / %DRM_DP_OVERHEAD_FEC)
3965  * - SSC/REF_CLK mode (@flags / %DRM_DP_OVERHEAD_SSC_REF_CLK)
3966  * as well as the stream's
3967  * - @hactive timing
3968  * - @bpp_x16 color depth
3969  * - compression mode (@flags / %DRM_DP_OVERHEAD_DSC).
3970  * Note that this overhead doesn't account for the 8b/10b, 128b/132b
3971  * channel coding efficiency, for that see
3972  * @drm_dp_link_bw_channel_coding_efficiency().
3973  *
3974  * Returns the overhead as 100% + overhead% in 1ppm units.
3975  */
3976 int drm_dp_bw_overhead(int lane_count, int hactive,
3977 		       int dsc_slice_count,
3978 		       int bpp_x16, unsigned long flags)
3979 {
3980 	int symbol_size = flags & DRM_DP_BW_OVERHEAD_UHBR ? 32 : 8;
3981 	bool is_mst = flags & DRM_DP_BW_OVERHEAD_MST;
3982 	u32 overhead = 1000000;
3983 	int symbol_cycles;
3984 
3985 	/*
3986 	 * DP Standard v2.1 2.6.4.1
3987 	 * SSC downspread and ref clock variation margin:
3988 	 *   5300ppm + 300ppm ~ 0.6%
3989 	 */
3990 	if (flags & DRM_DP_BW_OVERHEAD_SSC_REF_CLK)
3991 		overhead += 6000;
3992 
3993 	/*
3994 	 * DP Standard v2.1 2.6.4.1.1, 3.5.1.5.4:
3995 	 * FEC symbol insertions for 8b/10b channel coding:
3996 	 * After each 250 data symbols on 2-4 lanes:
3997 	 *   250 LL + 5 FEC_PARITY_PH + 1 CD_ADJ   (256 byte FEC block)
3998 	 * After each 2 x 250 data symbols on 1 lane:
3999 	 *   2 * 250 LL + 11 FEC_PARITY_PH + 1 CD_ADJ (512 byte FEC block)
4000 	 * After 256 (2-4 lanes) or 128 (1 lane) FEC blocks:
4001 	 *   256 * 256 bytes + 1 FEC_PM
4002 	 * or
4003 	 *   128 * 512 bytes + 1 FEC_PM
4004 	 * (256 * 6 + 1) / (256 * 250) = 2.4015625 %
4005 	 */
4006 	if (flags & DRM_DP_BW_OVERHEAD_FEC)
4007 		overhead += 24016;
4008 
4009 	/*
4010 	 * DP Standard v2.1 2.7.9, 5.9.7
4011 	 * The FEC overhead for UHBR is accounted for in its 96.71% channel
4012 	 * coding efficiency.
4013 	 */
4014 	WARN_ON((flags & DRM_DP_BW_OVERHEAD_UHBR) &&
4015 		(flags & DRM_DP_BW_OVERHEAD_FEC));
4016 
4017 	if (flags & DRM_DP_BW_OVERHEAD_DSC)
4018 		symbol_cycles = drm_dp_link_dsc_symbol_cycles(lane_count, hactive,
4019 							      dsc_slice_count,
4020 							      bpp_x16, symbol_size,
4021 							      is_mst);
4022 	else
4023 		symbol_cycles = drm_dp_link_symbol_cycles(lane_count, hactive,
4024 							  bpp_x16, symbol_size,
4025 							  is_mst);
4026 
4027 	return DIV_ROUND_UP_ULL(mul_u32_u32(symbol_cycles * symbol_size * lane_count,
4028 					    overhead * 16),
4029 				hactive * bpp_x16);
4030 }
4031 EXPORT_SYMBOL(drm_dp_bw_overhead);
4032 
4033 /**
4034  * drm_dp_bw_channel_coding_efficiency - Get a DP link's channel coding efficiency
4035  * @is_uhbr: Whether the link has a 128b/132b channel coding
4036  *
4037  * Return the channel coding efficiency of the given DP link type, which is
4038  * either 8b/10b or 128b/132b (aka UHBR). The corresponding overhead includes
4039  * the 8b -> 10b, 128b -> 132b pixel data to link symbol conversion overhead
4040  * and for 128b/132b any link or PHY level control symbol insertion overhead
4041  * (LLCP, FEC, PHY sync, see DP Standard v2.1 3.5.2.18). For 8b/10b the
4042  * corresponding FEC overhead is BW allocation specific, included in the value
4043  * returned by drm_dp_bw_overhead().
4044  *
4045  * Returns the efficiency in the 100%/coding-overhead% ratio in
4046  * 1ppm units.
4047  */
4048 int drm_dp_bw_channel_coding_efficiency(bool is_uhbr)
4049 {
4050 	if (is_uhbr)
4051 		return 967100;
4052 	else
4053 		/*
4054 		 * Note that on 8b/10b MST the efficiency is only
4055 		 * 78.75% due to the 1 out of 64 MTPH packet overhead,
4056 		 * not accounted for here.
4057 		 */
4058 		return 800000;
4059 }
4060 EXPORT_SYMBOL(drm_dp_bw_channel_coding_efficiency);
4061