1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf 5 */ 6 7 #include <linux/atomic.h> 8 #include <linux/auxiliary_bus.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/debugfs.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/i2c.h> 16 #include <linux/iopoll.h> 17 #include <linux/module.h> 18 #include <linux/of_graph.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/pwm.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 24 #include <linux/unaligned.h> 25 26 #include <drm/display/drm_dp_aux_bus.h> 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_bridge.h> 31 #include <drm/drm_bridge_connector.h> 32 #include <drm/drm_edid.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_of.h> 35 #include <drm/drm_print.h> 36 #include <drm/drm_probe_helper.h> 37 38 #define SN_DEVICE_ID_REGS 0x00 /* up to 0x07 */ 39 #define SN_DEVICE_REV_REG 0x08 40 #define SN_DPPLL_SRC_REG 0x0A 41 #define DPPLL_CLK_SRC_DSICLK BIT(0) 42 #define REFCLK_FREQ_MASK GENMASK(3, 1) 43 #define REFCLK_FREQ(x) ((x) << 1) 44 #define DPPLL_SRC_DP_PLL_LOCK BIT(7) 45 #define SN_PLL_ENABLE_REG 0x0D 46 #define SN_DSI_LANES_REG 0x10 47 #define CHA_DSI_LANES_MASK GENMASK(4, 3) 48 #define CHA_DSI_LANES(x) ((x) << 3) 49 #define SN_DSIA_CLK_FREQ_REG 0x12 50 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20 51 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24 52 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C 53 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D 54 #define CHA_HSYNC_POLARITY BIT(7) 55 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30 56 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31 57 #define CHA_VSYNC_POLARITY BIT(7) 58 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34 59 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36 60 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38 61 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A 62 #define SN_LN_ASSIGN_REG 0x59 63 #define LN_ASSIGN_WIDTH 2 64 #define SN_ENH_FRAME_REG 0x5A 65 #define VSTREAM_ENABLE BIT(3) 66 #define LN_POLRS_OFFSET 4 67 #define LN_POLRS_MASK 0xf0 68 #define SN_DATA_FORMAT_REG 0x5B 69 #define BPP_18_RGB BIT(0) 70 #define SN_HPD_DISABLE_REG 0x5C 71 #define HPD_DISABLE BIT(0) 72 #define HPD_DEBOUNCED_STATE BIT(4) 73 #define SN_GPIO_IO_REG 0x5E 74 #define SN_GPIO_INPUT_SHIFT 4 75 #define SN_GPIO_OUTPUT_SHIFT 0 76 #define SN_GPIO_CTRL_REG 0x5F 77 #define SN_GPIO_MUX_INPUT 0 78 #define SN_GPIO_MUX_OUTPUT 1 79 #define SN_GPIO_MUX_SPECIAL 2 80 #define SN_GPIO_MUX_MASK 0x3 81 #define SN_AUX_WDATA_REG(x) (0x64 + (x)) 82 #define SN_AUX_ADDR_19_16_REG 0x74 83 #define SN_AUX_ADDR_15_8_REG 0x75 84 #define SN_AUX_ADDR_7_0_REG 0x76 85 #define SN_AUX_ADDR_MASK GENMASK(19, 0) 86 #define SN_AUX_LENGTH_REG 0x77 87 #define SN_AUX_CMD_REG 0x78 88 #define AUX_CMD_SEND BIT(0) 89 #define AUX_CMD_REQ(x) ((x) << 4) 90 #define SN_AUX_RDATA_REG(x) (0x79 + (x)) 91 #define SN_SSC_CONFIG_REG 0x93 92 #define DP_NUM_LANES_MASK GENMASK(5, 4) 93 #define DP_NUM_LANES(x) ((x) << 4) 94 #define SN_DATARATE_CONFIG_REG 0x94 95 #define DP_DATARATE_MASK GENMASK(7, 5) 96 #define DP_DATARATE(x) ((x) << 5) 97 #define SN_TRAINING_SETTING_REG 0x95 98 #define SCRAMBLE_DISABLE BIT(4) 99 #define SN_ML_TX_MODE_REG 0x96 100 #define ML_TX_MAIN_LINK_OFF 0 101 #define ML_TX_NORMAL_MODE BIT(0) 102 #define SN_PWM_PRE_DIV_REG 0xA0 103 #define SN_BACKLIGHT_SCALE_REG 0xA1 104 #define BACKLIGHT_SCALE_MAX 0xFFFF 105 #define SN_BACKLIGHT_REG 0xA3 106 #define SN_PWM_EN_INV_REG 0xA5 107 #define SN_PWM_INV_MASK BIT(0) 108 #define SN_PWM_EN_MASK BIT(1) 109 #define SN_AUX_CMD_STATUS_REG 0xF4 110 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3) 111 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5) 112 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6) 113 114 #define MIN_DSI_CLK_FREQ_MHZ 40 115 116 /* fudge factor required to account for 8b/10b encoding */ 117 #define DP_CLK_FUDGE_NUM 10 118 #define DP_CLK_FUDGE_DEN 8 119 120 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */ 121 #define SN_AUX_MAX_PAYLOAD_BYTES 16 122 123 #define SN_REGULATOR_SUPPLY_NUM 4 124 125 #define SN_MAX_DP_LANES 4 126 #define SN_NUM_GPIOS 4 127 #define SN_GPIO_PHYSICAL_OFFSET 1 128 129 #define SN_LINK_TRAINING_TRIES 10 130 131 #define SN_PWM_GPIO_IDX 3 /* 4th GPIO */ 132 133 /** 134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver. 135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality. 136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality. 137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality. 138 * @pwm_aux: AUX-bus sub device for PWM controller functionality. 139 * 140 * @dev: Pointer to the top level (i2c) device. 141 * @regmap: Regmap for accessing i2c. 142 * @aux: Our aux channel. 143 * @bridge: Our bridge. 144 * @connector: Our connector. 145 * @host_node: Remote DSI node. 146 * @dsi: Our MIPI DSI source. 147 * @refclk: Our reference clock. 148 * @next_bridge: The bridge on the eDP side. 149 * @enable_gpio: The GPIO we toggle to enable the bridge. 150 * @supplies: Data for bulk enabling/disabling our regulators. 151 * @dp_lanes: Count of dp_lanes we're using. 152 * @ln_assign: Value to program to the LN_ASSIGN register. 153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG. 154 * @comms_enabled: If true then communication over the aux channel is enabled. 155 * @comms_mutex: Protects modification of comms_enabled. 156 * 157 * @gchip: If we expose our GPIOs, this is used. 158 * @gchip_output: A cache of whether we've set GPIOs to output. This 159 * serves double-duty of keeping track of the direction and 160 * also keeping track of whether we've incremented the 161 * pm_runtime reference count for this pin, which we do 162 * whenever a pin is configured as an output. This is a 163 * bitmap so we can do atomic ops on it without an extra 164 * lock so concurrent users of our 4 GPIOs don't stomp on 165 * each other's read-modify-write. 166 * 167 * @pchip: pwm_chip if the PWM is exposed. 168 * @pwm_enabled: Used to track if the PWM signal is currently enabled. 169 * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM. 170 * @pwm_refclk_freq: Cache for the reference clock input to the PWM. 171 */ 172 struct ti_sn65dsi86 { 173 struct auxiliary_device *bridge_aux; 174 struct auxiliary_device *gpio_aux; 175 struct auxiliary_device *aux_aux; 176 struct auxiliary_device *pwm_aux; 177 178 struct device *dev; 179 struct regmap *regmap; 180 struct drm_dp_aux aux; 181 struct drm_bridge bridge; 182 struct drm_connector *connector; 183 struct device_node *host_node; 184 struct mipi_dsi_device *dsi; 185 struct clk *refclk; 186 struct drm_bridge *next_bridge; 187 struct gpio_desc *enable_gpio; 188 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM]; 189 int dp_lanes; 190 u8 ln_assign; 191 u8 ln_polrs; 192 bool comms_enabled; 193 struct mutex comms_mutex; 194 195 #if defined(CONFIG_OF_GPIO) 196 struct gpio_chip gchip; 197 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS); 198 #endif 199 #if IS_REACHABLE(CONFIG_PWM) 200 struct pwm_chip *pchip; 201 bool pwm_enabled; 202 atomic_t pwm_pin_busy; 203 #endif 204 unsigned int pwm_refclk_freq; 205 }; 206 207 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = { 208 { .range_min = 0, .range_max = 0xFF }, 209 }; 210 211 static const struct regmap_access_table ti_sn_bridge_volatile_table = { 212 .yes_ranges = ti_sn65dsi86_volatile_ranges, 213 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges), 214 }; 215 216 static const struct regmap_config ti_sn65dsi86_regmap_config = { 217 .reg_bits = 8, 218 .val_bits = 8, 219 .volatile_table = &ti_sn_bridge_volatile_table, 220 .cache_type = REGCACHE_NONE, 221 .max_register = 0xFF, 222 }; 223 224 static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata, 225 unsigned int reg, u16 *val) 226 { 227 u8 buf[2]; 228 int ret; 229 230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 231 if (ret) 232 return ret; 233 234 *val = buf[0] | (buf[1] << 8); 235 236 return 0; 237 } 238 239 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata, 240 unsigned int reg, u16 val) 241 { 242 u8 buf[2] = { val & 0xff, val >> 8 }; 243 244 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 245 } 246 247 static struct drm_display_mode * 248 get_new_adjusted_display_mode(struct drm_bridge *bridge, 249 struct drm_atomic_state *state) 250 { 251 struct drm_connector *connector = 252 drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 253 struct drm_connector_state *conn_state = 254 drm_atomic_get_new_connector_state(state, connector); 255 struct drm_crtc_state *crtc_state = 256 drm_atomic_get_new_crtc_state(state, conn_state->crtc); 257 258 return &crtc_state->adjusted_mode; 259 } 260 261 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata, 262 struct drm_atomic_state *state) 263 { 264 u32 bit_rate_khz, clk_freq_khz; 265 struct drm_display_mode *mode = 266 get_new_adjusted_display_mode(&pdata->bridge, state); 267 268 bit_rate_khz = mode->clock * 269 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 270 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2); 271 272 return clk_freq_khz; 273 } 274 275 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */ 276 static const u32 ti_sn_bridge_refclk_lut[] = { 277 12000000, 278 19200000, 279 26000000, 280 27000000, 281 38400000, 282 }; 283 284 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */ 285 static const u32 ti_sn_bridge_dsiclk_lut[] = { 286 468000000, 287 384000000, 288 416000000, 289 486000000, 290 460800000, 291 }; 292 293 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata, 294 struct drm_atomic_state *state) 295 { 296 int i; 297 u32 refclk_rate; 298 const u32 *refclk_lut; 299 size_t refclk_lut_size; 300 301 if (pdata->refclk) { 302 refclk_rate = clk_get_rate(pdata->refclk); 303 refclk_lut = ti_sn_bridge_refclk_lut; 304 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut); 305 clk_prepare_enable(pdata->refclk); 306 } else { 307 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata, state) * 1000; 308 refclk_lut = ti_sn_bridge_dsiclk_lut; 309 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut); 310 } 311 312 /* for i equals to refclk_lut_size means default frequency */ 313 for (i = 0; i < refclk_lut_size; i++) 314 if (refclk_lut[i] == refclk_rate) 315 break; 316 317 /* avoid buffer overflow and "1" is the default rate in the datasheet. */ 318 if (i >= refclk_lut_size) 319 i = 1; 320 321 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK, 322 REFCLK_FREQ(i)); 323 324 /* 325 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG, 326 * regardless of its actual sourcing. 327 */ 328 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i]; 329 } 330 331 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata, 332 struct drm_atomic_state *state) 333 { 334 mutex_lock(&pdata->comms_mutex); 335 336 /* configure bridge ref_clk */ 337 ti_sn_bridge_set_refclk_freq(pdata, state); 338 339 /* 340 * HPD on this bridge chip is a bit useless. This is an eDP bridge 341 * so the HPD is an internal signal that's only there to signal that 342 * the panel is done powering up. ...but the bridge chip debounces 343 * this signal by between 100 ms and 400 ms (depending on process, 344 * voltage, and temperate--I measured it at about 200 ms). One 345 * particular panel asserted HPD 84 ms after it was powered on meaning 346 * that we saw HPD 284 ms after power on. ...but the same panel said 347 * that instead of looking at HPD you could just hardcode a delay of 348 * 200 ms. We'll assume that the panel driver will have the hardcoded 349 * delay in its prepare and always disable HPD. 350 * 351 * If HPD somehow makes sense on some future panel we'll have to 352 * change this to be conditional on someone specifying that HPD should 353 * be used. 354 */ 355 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE, 356 HPD_DISABLE); 357 358 pdata->comms_enabled = true; 359 360 mutex_unlock(&pdata->comms_mutex); 361 } 362 363 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata) 364 { 365 mutex_lock(&pdata->comms_mutex); 366 367 pdata->comms_enabled = false; 368 clk_disable_unprepare(pdata->refclk); 369 370 mutex_unlock(&pdata->comms_mutex); 371 } 372 373 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev) 374 { 375 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 376 int ret; 377 378 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 379 if (ret) { 380 DRM_ERROR("failed to enable supplies %d\n", ret); 381 return ret; 382 } 383 384 /* td2: min 100 us after regulators before enabling the GPIO */ 385 usleep_range(100, 110); 386 387 gpiod_set_value_cansleep(pdata->enable_gpio, 1); 388 389 /* 390 * If we have a reference clock we can enable communication w/ the 391 * panel (including the aux channel) w/out any need for an input clock 392 * so we can do it in resume which lets us read the EDID before 393 * pre_enable(). Without a reference clock we need the MIPI reference 394 * clock so reading early doesn't work. 395 */ 396 if (pdata->refclk) 397 ti_sn65dsi86_enable_comms(pdata, NULL); 398 399 return ret; 400 } 401 402 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev) 403 { 404 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 405 int ret; 406 407 if (pdata->refclk) 408 ti_sn65dsi86_disable_comms(pdata); 409 410 gpiod_set_value_cansleep(pdata->enable_gpio, 0); 411 412 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 413 if (ret) 414 DRM_ERROR("failed to disable supplies %d\n", ret); 415 416 return ret; 417 } 418 419 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = { 420 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL) 421 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 422 pm_runtime_force_resume) 423 }; 424 425 static int status_show(struct seq_file *s, void *data) 426 { 427 struct ti_sn65dsi86 *pdata = s->private; 428 unsigned int reg, val; 429 430 seq_puts(s, "STATUS REGISTERS:\n"); 431 432 pm_runtime_get_sync(pdata->dev); 433 434 /* IRQ Status Registers, see Table 31 in datasheet */ 435 for (reg = 0xf0; reg <= 0xf8; reg++) { 436 regmap_read(pdata->regmap, reg, &val); 437 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val); 438 } 439 440 pm_runtime_put_autosuspend(pdata->dev); 441 442 return 0; 443 } 444 DEFINE_SHOW_ATTRIBUTE(status); 445 446 /* ----------------------------------------------------------------------------- 447 * Auxiliary Devices (*not* AUX) 448 */ 449 450 static void ti_sn65dsi86_uninit_aux(void *data) 451 { 452 auxiliary_device_uninit(data); 453 } 454 455 static void ti_sn65dsi86_delete_aux(void *data) 456 { 457 auxiliary_device_delete(data); 458 } 459 460 static void ti_sn65dsi86_aux_device_release(struct device *dev) 461 { 462 struct auxiliary_device *aux = container_of(dev, struct auxiliary_device, dev); 463 464 kfree(aux); 465 } 466 467 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata, 468 struct auxiliary_device **aux_out, 469 const char *name) 470 { 471 struct device *dev = pdata->dev; 472 const struct i2c_client *client = to_i2c_client(dev); 473 struct auxiliary_device *aux; 474 int ret; 475 476 aux = kzalloc(sizeof(*aux), GFP_KERNEL); 477 if (!aux) 478 return -ENOMEM; 479 480 aux->name = name; 481 aux->id = (client->adapter->nr << 10) | client->addr; 482 aux->dev.parent = dev; 483 aux->dev.release = ti_sn65dsi86_aux_device_release; 484 device_set_of_node_from_dev(&aux->dev, dev); 485 ret = auxiliary_device_init(aux); 486 if (ret) { 487 kfree(aux); 488 return ret; 489 } 490 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_uninit_aux, aux); 491 if (ret) 492 return ret; 493 494 ret = auxiliary_device_add(aux); 495 if (ret) 496 return ret; 497 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_delete_aux, aux); 498 if (!ret) 499 *aux_out = aux; 500 501 return ret; 502 } 503 504 /* ----------------------------------------------------------------------------- 505 * AUX Adapter 506 */ 507 508 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux) 509 { 510 return container_of(aux, struct ti_sn65dsi86, aux); 511 } 512 513 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux, 514 struct drm_dp_aux_msg *msg) 515 { 516 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux); 517 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); 518 u32 request_val = AUX_CMD_REQ(msg->request); 519 u8 *buf = msg->buffer; 520 unsigned int len = msg->size; 521 unsigned int short_len; 522 unsigned int val; 523 int ret; 524 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG]; 525 526 if (len > SN_AUX_MAX_PAYLOAD_BYTES) 527 return -EINVAL; 528 529 pm_runtime_get_sync(pdata->dev); 530 mutex_lock(&pdata->comms_mutex); 531 532 /* 533 * If someone tries to do a DDC over AUX transaction before pre_enable() 534 * on a device without a dedicated reference clock then we just can't 535 * do it. Fail right away. This prevents non-refclk users from reading 536 * the EDID before enabling the panel but such is life. 537 */ 538 if (!pdata->comms_enabled) { 539 ret = -EIO; 540 goto exit; 541 } 542 543 switch (request) { 544 case DP_AUX_NATIVE_WRITE: 545 case DP_AUX_I2C_WRITE: 546 case DP_AUX_NATIVE_READ: 547 case DP_AUX_I2C_READ: 548 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val); 549 /* Assume it's good */ 550 msg->reply = 0; 551 break; 552 default: 553 ret = -EINVAL; 554 goto exit; 555 } 556 557 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32)); 558 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len, 559 addr_len); 560 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len, 561 ARRAY_SIZE(addr_len)); 562 563 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) 564 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len); 565 566 /* Clear old status bits before start so we don't get confused */ 567 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG, 568 AUX_IRQ_STATUS_NAT_I2C_FAIL | 569 AUX_IRQ_STATUS_AUX_RPLY_TOUT | 570 AUX_IRQ_STATUS_AUX_SHORT); 571 572 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND); 573 574 /* Zero delay loop because i2c transactions are slow already */ 575 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val, 576 !(val & AUX_CMD_SEND), 0, 50 * 1000); 577 if (ret) 578 goto exit; 579 580 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val); 581 if (ret) 582 goto exit; 583 584 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) { 585 /* 586 * The hardware tried the message seven times per the DP spec 587 * but it hit a timeout. We ignore defers here because they're 588 * handled in hardware. 589 */ 590 ret = -ETIMEDOUT; 591 goto exit; 592 } 593 594 if (val & AUX_IRQ_STATUS_AUX_SHORT) { 595 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &short_len); 596 len = min(len, short_len); 597 if (ret) 598 goto exit; 599 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) { 600 switch (request) { 601 case DP_AUX_I2C_WRITE: 602 case DP_AUX_I2C_READ: 603 msg->reply |= DP_AUX_I2C_REPLY_NACK; 604 break; 605 case DP_AUX_NATIVE_READ: 606 case DP_AUX_NATIVE_WRITE: 607 msg->reply |= DP_AUX_NATIVE_REPLY_NACK; 608 break; 609 } 610 len = 0; 611 goto exit; 612 } 613 614 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0) 615 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len); 616 617 exit: 618 mutex_unlock(&pdata->comms_mutex); 619 pm_runtime_mark_last_busy(pdata->dev); 620 pm_runtime_put_autosuspend(pdata->dev); 621 622 if (ret) 623 return ret; 624 return len; 625 } 626 627 static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us) 628 { 629 /* 630 * The HPD in this chip is a bit useless (See comment in 631 * ti_sn65dsi86_enable_comms) so if our driver is expected to wait 632 * for HPD, we just assume it's asserted after the wait_us delay. 633 * 634 * In case we are asked to wait forever (wait_us=0) take conservative 635 * 500ms delay. 636 */ 637 if (wait_us == 0) 638 wait_us = 500000; 639 640 usleep_range(wait_us, wait_us + 1000); 641 642 return 0; 643 } 644 645 static int ti_sn_aux_probe(struct auxiliary_device *adev, 646 const struct auxiliary_device_id *id) 647 { 648 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 649 int ret; 650 651 pdata->aux.name = "ti-sn65dsi86-aux"; 652 pdata->aux.dev = &adev->dev; 653 pdata->aux.transfer = ti_sn_aux_transfer; 654 pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted; 655 drm_dp_aux_init(&pdata->aux); 656 657 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux); 658 if (ret) 659 return ret; 660 661 /* 662 * The eDP to MIPI bridge parts don't work until the AUX channel is 663 * setup so we don't add it in the main driver probe, we add it now. 664 */ 665 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge"); 666 } 667 668 static const struct auxiliary_device_id ti_sn_aux_id_table[] = { 669 { .name = "ti_sn65dsi86.aux", }, 670 {}, 671 }; 672 673 static struct auxiliary_driver ti_sn_aux_driver = { 674 .name = "aux", 675 .probe = ti_sn_aux_probe, 676 .id_table = ti_sn_aux_id_table, 677 }; 678 679 /*------------------------------------------------------------------------------ 680 * DRM Bridge 681 */ 682 683 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge) 684 { 685 return container_of(bridge, struct ti_sn65dsi86, bridge); 686 } 687 688 static int ti_sn_attach_host(struct auxiliary_device *adev, struct ti_sn65dsi86 *pdata) 689 { 690 int val; 691 struct mipi_dsi_host *host; 692 struct mipi_dsi_device *dsi; 693 struct device *dev = pdata->dev; 694 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge", 695 .channel = 0, 696 .node = NULL, 697 }; 698 699 host = of_find_mipi_dsi_host_by_node(pdata->host_node); 700 if (!host) 701 return -EPROBE_DEFER; 702 703 dsi = devm_mipi_dsi_device_register_full(&adev->dev, host, &info); 704 if (IS_ERR(dsi)) 705 return PTR_ERR(dsi); 706 707 /* TODO: setting to 4 MIPI lanes always for now */ 708 dsi->lanes = 4; 709 dsi->format = MIPI_DSI_FMT_RGB888; 710 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; 711 712 /* check if continuous dsi clock is required or not */ 713 pm_runtime_get_sync(dev); 714 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val); 715 pm_runtime_put_autosuspend(dev); 716 if (!(val & DPPLL_CLK_SRC_DSICLK)) 717 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; 718 719 pdata->dsi = dsi; 720 721 return devm_mipi_dsi_attach(&adev->dev, dsi); 722 } 723 724 static int ti_sn_bridge_attach(struct drm_bridge *bridge, 725 struct drm_encoder *encoder, 726 enum drm_bridge_attach_flags flags) 727 { 728 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 729 int ret; 730 731 pdata->aux.drm_dev = bridge->dev; 732 ret = drm_dp_aux_register(&pdata->aux); 733 if (ret < 0) { 734 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret); 735 return ret; 736 } 737 738 /* 739 * Attach the next bridge. 740 * We never want the next bridge to *also* create a connector. 741 */ 742 ret = drm_bridge_attach(encoder, pdata->next_bridge, 743 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); 744 if (ret < 0) 745 goto err_initted_aux; 746 747 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 748 return 0; 749 750 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev, 751 pdata->bridge.encoder); 752 if (IS_ERR(pdata->connector)) { 753 ret = PTR_ERR(pdata->connector); 754 goto err_initted_aux; 755 } 756 757 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder); 758 759 return 0; 760 761 err_initted_aux: 762 drm_dp_aux_unregister(&pdata->aux); 763 return ret; 764 } 765 766 static void ti_sn_bridge_detach(struct drm_bridge *bridge) 767 { 768 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux); 769 } 770 771 static enum drm_mode_status 772 ti_sn_bridge_mode_valid(struct drm_bridge *bridge, 773 const struct drm_display_info *info, 774 const struct drm_display_mode *mode) 775 { 776 /* maximum supported resolution is 4K at 60 fps */ 777 if (mode->clock > 594000) 778 return MODE_CLOCK_HIGH; 779 780 /* 781 * The front and back porch registers are 8 bits, and pulse width 782 * registers are 15 bits, so reject any modes with larger periods. 783 */ 784 785 if ((mode->hsync_start - mode->hdisplay) > 0xff) 786 return MODE_HBLANK_WIDE; 787 788 if ((mode->vsync_start - mode->vdisplay) > 0xff) 789 return MODE_VBLANK_WIDE; 790 791 if ((mode->hsync_end - mode->hsync_start) > 0x7fff) 792 return MODE_HSYNC_WIDE; 793 794 if ((mode->vsync_end - mode->vsync_start) > 0x7fff) 795 return MODE_VSYNC_WIDE; 796 797 if ((mode->htotal - mode->hsync_end) > 0xff) 798 return MODE_HBLANK_WIDE; 799 800 if ((mode->vtotal - mode->vsync_end) > 0xff) 801 return MODE_VBLANK_WIDE; 802 803 return MODE_OK; 804 } 805 806 static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge, 807 struct drm_atomic_state *state) 808 { 809 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 810 811 /* disable video stream */ 812 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0); 813 } 814 815 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata, 816 struct drm_atomic_state *state) 817 { 818 unsigned int bit_rate_mhz, clk_freq_mhz; 819 unsigned int val; 820 struct drm_display_mode *mode = 821 get_new_adjusted_display_mode(&pdata->bridge, state); 822 823 /* set DSIA clk frequency */ 824 bit_rate_mhz = (mode->clock / 1000) * 825 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 826 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); 827 828 /* for each increment in val, frequency increases by 5MHz */ 829 val = (MIN_DSI_CLK_FREQ_MHZ / 5) + 830 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); 831 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); 832 } 833 834 static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector) 835 { 836 if (connector->display_info.bpc <= 6) 837 return 18; 838 else 839 return 24; 840 } 841 842 /* 843 * LUT index corresponds to register value and 844 * LUT values corresponds to dp data rate supported 845 * by the bridge in Mbps unit. 846 */ 847 static const unsigned int ti_sn_bridge_dp_rate_lut[] = { 848 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 849 }; 850 851 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata, 852 struct drm_atomic_state *state, 853 unsigned int bpp) 854 { 855 unsigned int bit_rate_khz, dp_rate_mhz; 856 unsigned int i; 857 struct drm_display_mode *mode = 858 get_new_adjusted_display_mode(&pdata->bridge, state); 859 860 /* Calculate minimum bit rate based on our pixel clock. */ 861 bit_rate_khz = mode->clock * bpp; 862 863 /* Calculate minimum DP data rate, taking 80% as per DP spec */ 864 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM, 865 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN); 866 867 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) 868 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz) 869 break; 870 871 return i; 872 } 873 874 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata) 875 { 876 unsigned int valid_rates = 0; 877 unsigned int rate_per_200khz; 878 unsigned int rate_mhz; 879 u8 dpcd_val; 880 int ret; 881 int i, j; 882 883 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val); 884 if (ret != 1) { 885 DRM_DEV_ERROR(pdata->dev, 886 "Can't read eDP rev (%d), assuming 1.1\n", ret); 887 dpcd_val = DP_EDP_11; 888 } 889 890 if (dpcd_val >= DP_EDP_14) { 891 /* eDP 1.4 devices must provide a custom table */ 892 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 893 894 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES, 895 sink_rates, sizeof(sink_rates)); 896 897 if (ret != sizeof(sink_rates)) { 898 DRM_DEV_ERROR(pdata->dev, 899 "Can't read supported rate table (%d)\n", ret); 900 901 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */ 902 memset(sink_rates, 0, sizeof(sink_rates)); 903 } 904 905 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 906 rate_per_200khz = le16_to_cpu(sink_rates[i]); 907 908 if (!rate_per_200khz) 909 break; 910 911 rate_mhz = rate_per_200khz * 200 / 1000; 912 for (j = 0; 913 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 914 j++) { 915 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz) 916 valid_rates |= BIT(j); 917 } 918 } 919 920 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) { 921 if (valid_rates & BIT(i)) 922 return valid_rates; 923 } 924 DRM_DEV_ERROR(pdata->dev, 925 "No matching eDP rates in table; falling back\n"); 926 } 927 928 /* On older versions best we can do is use DP_MAX_LINK_RATE */ 929 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val); 930 if (ret != 1) { 931 DRM_DEV_ERROR(pdata->dev, 932 "Can't read max rate (%d); assuming 5.4 GHz\n", 933 ret); 934 dpcd_val = DP_LINK_BW_5_4; 935 } 936 937 switch (dpcd_val) { 938 default: 939 DRM_DEV_ERROR(pdata->dev, 940 "Unexpected max rate (%#x); assuming 5.4 GHz\n", 941 (int)dpcd_val); 942 fallthrough; 943 case DP_LINK_BW_5_4: 944 valid_rates |= BIT(7); 945 fallthrough; 946 case DP_LINK_BW_2_7: 947 valid_rates |= BIT(4); 948 fallthrough; 949 case DP_LINK_BW_1_62: 950 valid_rates |= BIT(1); 951 break; 952 } 953 954 return valid_rates; 955 } 956 957 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata, 958 struct drm_atomic_state *state) 959 { 960 struct drm_display_mode *mode = 961 get_new_adjusted_display_mode(&pdata->bridge, state); 962 u8 hsync_polarity = 0, vsync_polarity = 0; 963 964 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 965 hsync_polarity = CHA_HSYNC_POLARITY; 966 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 967 vsync_polarity = CHA_VSYNC_POLARITY; 968 969 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG, 970 mode->hdisplay); 971 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG, 972 mode->vdisplay); 973 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, 974 (mode->hsync_end - mode->hsync_start) & 0xFF); 975 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, 976 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) | 977 hsync_polarity); 978 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, 979 (mode->vsync_end - mode->vsync_start) & 0xFF); 980 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, 981 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) | 982 vsync_polarity); 983 984 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG, 985 (mode->htotal - mode->hsync_end) & 0xFF); 986 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG, 987 (mode->vtotal - mode->vsync_end) & 0xFF); 988 989 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, 990 (mode->hsync_start - mode->hdisplay) & 0xFF); 991 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG, 992 (mode->vsync_start - mode->vdisplay) & 0xFF); 993 994 usleep_range(10000, 10500); /* 10ms delay recommended by spec */ 995 } 996 997 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata) 998 { 999 u8 data; 1000 int ret; 1001 1002 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); 1003 if (ret != 1) { 1004 DRM_DEV_ERROR(pdata->dev, 1005 "Can't read lane count (%d); assuming 4\n", ret); 1006 return 4; 1007 } 1008 1009 return data & DP_LANE_COUNT_MASK; 1010 } 1011 1012 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx, 1013 const char **last_err_str) 1014 { 1015 unsigned int val; 1016 int ret; 1017 int i; 1018 1019 /* set dp clk frequency value */ 1020 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, 1021 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx)); 1022 1023 /* enable DP PLL */ 1024 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); 1025 1026 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, 1027 val & DPPLL_SRC_DP_PLL_LOCK, 1000, 1028 50 * 1000); 1029 if (ret) { 1030 *last_err_str = "DP_PLL_LOCK polling failed"; 1031 goto exit; 1032 } 1033 1034 /* 1035 * We'll try to link train several times. As part of link training 1036 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If 1037 * the panel isn't ready quite it might respond NAK here which means 1038 * we need to try again. 1039 */ 1040 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) { 1041 /* Semi auto link training mode */ 1042 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); 1043 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, 1044 val == ML_TX_MAIN_LINK_OFF || 1045 val == ML_TX_NORMAL_MODE, 1000, 1046 500 * 1000); 1047 if (ret) { 1048 *last_err_str = "Training complete polling failed"; 1049 } else if (val == ML_TX_MAIN_LINK_OFF) { 1050 *last_err_str = "Link training failed, link is off"; 1051 ret = -EIO; 1052 continue; 1053 } 1054 1055 break; 1056 } 1057 1058 /* If we saw quite a few retries, add a note about it */ 1059 if (!ret && i > SN_LINK_TRAINING_TRIES / 2) 1060 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i); 1061 1062 exit: 1063 /* Disable the PLL if we failed */ 1064 if (ret) 1065 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1066 1067 return ret; 1068 } 1069 1070 static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge, 1071 struct drm_atomic_state *state) 1072 { 1073 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1074 struct drm_connector *connector; 1075 const char *last_err_str = "No supported DP rate"; 1076 unsigned int valid_rates; 1077 int dp_rate_idx; 1078 unsigned int val; 1079 int ret = -EINVAL; 1080 int max_dp_lanes; 1081 unsigned int bpp; 1082 1083 connector = drm_atomic_get_new_connector_for_encoder(state, 1084 bridge->encoder); 1085 if (!connector) { 1086 dev_err_ratelimited(pdata->dev, "Could not get the connector\n"); 1087 return; 1088 } 1089 1090 max_dp_lanes = ti_sn_get_max_lanes(pdata); 1091 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes); 1092 1093 /* DSI_A lane config */ 1094 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes); 1095 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, 1096 CHA_DSI_LANES_MASK, val); 1097 1098 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign); 1099 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK, 1100 pdata->ln_polrs << LN_POLRS_OFFSET); 1101 1102 /* set dsi clk frequency value */ 1103 ti_sn_bridge_set_dsi_rate(pdata, state); 1104 1105 /* 1106 * The SN65DSI86 only supports ASSR Display Authentication method and 1107 * this method is enabled for eDP panels. An eDP panel must support this 1108 * authentication method. We need to enable this method in the eDP panel 1109 * at DisplayPort address 0x0010A prior to link training. 1110 * 1111 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays 1112 * we need to disable the scrambler. 1113 */ 1114 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) { 1115 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, 1116 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); 1117 1118 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1119 SCRAMBLE_DISABLE, 0); 1120 } else { 1121 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1122 SCRAMBLE_DISABLE, SCRAMBLE_DISABLE); 1123 } 1124 1125 bpp = ti_sn_bridge_get_bpp(connector); 1126 /* Set the DP output format (18 bpp or 24 bpp) */ 1127 val = bpp == 18 ? BPP_18_RGB : 0; 1128 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); 1129 1130 /* DP lane config */ 1131 val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); 1132 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 1133 val); 1134 1135 valid_rates = ti_sn_bridge_read_valid_rates(pdata); 1136 1137 /* Train until we run out of rates */ 1138 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, state, bpp); 1139 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 1140 dp_rate_idx++) { 1141 if (!(valid_rates & BIT(dp_rate_idx))) 1142 continue; 1143 1144 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str); 1145 if (!ret) 1146 break; 1147 } 1148 if (ret) { 1149 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret); 1150 return; 1151 } 1152 1153 /* config video parameters */ 1154 ti_sn_bridge_set_video_timings(pdata, state); 1155 1156 /* enable video stream */ 1157 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 1158 VSTREAM_ENABLE); 1159 } 1160 1161 static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge, 1162 struct drm_atomic_state *state) 1163 { 1164 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1165 1166 pm_runtime_get_sync(pdata->dev); 1167 1168 if (!pdata->refclk) 1169 ti_sn65dsi86_enable_comms(pdata, state); 1170 1171 /* td7: min 100 us after enable before DSI data */ 1172 usleep_range(100, 110); 1173 } 1174 1175 static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge, 1176 struct drm_atomic_state *state) 1177 { 1178 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1179 1180 /* semi auto link training mode OFF */ 1181 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); 1182 /* Num lanes to 0 as per power sequencing in data sheet */ 1183 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0); 1184 /* disable DP PLL */ 1185 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1186 1187 if (!pdata->refclk) 1188 ti_sn65dsi86_disable_comms(pdata); 1189 1190 pm_runtime_put_sync(pdata->dev); 1191 } 1192 1193 static enum drm_connector_status ti_sn_bridge_detect(struct drm_bridge *bridge) 1194 { 1195 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1196 int val = 0; 1197 1198 pm_runtime_get_sync(pdata->dev); 1199 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val); 1200 pm_runtime_put_autosuspend(pdata->dev); 1201 1202 return val & HPD_DEBOUNCED_STATE ? connector_status_connected 1203 : connector_status_disconnected; 1204 } 1205 1206 static const struct drm_edid *ti_sn_bridge_edid_read(struct drm_bridge *bridge, 1207 struct drm_connector *connector) 1208 { 1209 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1210 1211 return drm_edid_read_ddc(connector, &pdata->aux.ddc); 1212 } 1213 1214 static void ti_sn65dsi86_debugfs_init(struct drm_bridge *bridge, struct dentry *root) 1215 { 1216 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1217 struct dentry *debugfs; 1218 1219 debugfs = debugfs_create_dir(dev_name(pdata->dev), root); 1220 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops); 1221 } 1222 1223 static const struct drm_bridge_funcs ti_sn_bridge_funcs = { 1224 .attach = ti_sn_bridge_attach, 1225 .detach = ti_sn_bridge_detach, 1226 .mode_valid = ti_sn_bridge_mode_valid, 1227 .edid_read = ti_sn_bridge_edid_read, 1228 .detect = ti_sn_bridge_detect, 1229 .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable, 1230 .atomic_enable = ti_sn_bridge_atomic_enable, 1231 .atomic_disable = ti_sn_bridge_atomic_disable, 1232 .atomic_post_disable = ti_sn_bridge_atomic_post_disable, 1233 .atomic_reset = drm_atomic_helper_bridge_reset, 1234 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1235 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1236 .debugfs_init = ti_sn65dsi86_debugfs_init, 1237 }; 1238 1239 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata, 1240 struct device_node *np) 1241 { 1242 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 }; 1243 u32 lane_polarities[SN_MAX_DP_LANES] = { }; 1244 struct device_node *endpoint; 1245 u8 ln_assign = 0; 1246 u8 ln_polrs = 0; 1247 int dp_lanes; 1248 int i; 1249 1250 /* 1251 * Read config from the device tree about lane remapping and lane 1252 * polarities. These are optional and we assume identity map and 1253 * normal polarity if nothing is specified. It's OK to specify just 1254 * data-lanes but not lane-polarities but not vice versa. 1255 * 1256 * Error checking is light (we just make sure we don't crash or 1257 * buffer overrun) and we assume dts is well formed and specifying 1258 * mappings that the hardware supports. 1259 */ 1260 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1261 dp_lanes = drm_of_get_data_lanes_count(endpoint, 1, SN_MAX_DP_LANES); 1262 if (dp_lanes > 0) { 1263 of_property_read_u32_array(endpoint, "data-lanes", 1264 lane_assignments, dp_lanes); 1265 of_property_read_u32_array(endpoint, "lane-polarities", 1266 lane_polarities, dp_lanes); 1267 } else { 1268 dp_lanes = SN_MAX_DP_LANES; 1269 } 1270 of_node_put(endpoint); 1271 1272 /* 1273 * Convert into register format. Loop over all lanes even if 1274 * data-lanes had fewer elements so that we nicely initialize 1275 * the LN_ASSIGN register. 1276 */ 1277 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) { 1278 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i]; 1279 ln_polrs = ln_polrs << 1 | lane_polarities[i]; 1280 } 1281 1282 /* Stash in our struct for when we power on */ 1283 pdata->dp_lanes = dp_lanes; 1284 pdata->ln_assign = ln_assign; 1285 pdata->ln_polrs = ln_polrs; 1286 } 1287 1288 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata) 1289 { 1290 struct device_node *np = pdata->dev->of_node; 1291 1292 pdata->host_node = of_graph_get_remote_node(np, 0, 0); 1293 1294 if (!pdata->host_node) { 1295 DRM_ERROR("remote dsi host node not found\n"); 1296 return -ENODEV; 1297 } 1298 1299 return 0; 1300 } 1301 1302 static int ti_sn_bridge_probe(struct auxiliary_device *adev, 1303 const struct auxiliary_device_id *id) 1304 { 1305 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1306 struct device_node *np = pdata->dev->of_node; 1307 int ret; 1308 1309 pdata->next_bridge = devm_drm_of_get_bridge(&adev->dev, np, 1, 0); 1310 if (IS_ERR(pdata->next_bridge)) 1311 return dev_err_probe(&adev->dev, PTR_ERR(pdata->next_bridge), 1312 "failed to create panel bridge\n"); 1313 1314 ti_sn_bridge_parse_lanes(pdata, np); 1315 1316 ret = ti_sn_bridge_parse_dsi_host(pdata); 1317 if (ret) 1318 return ret; 1319 1320 pdata->bridge.of_node = np; 1321 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort 1322 ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP; 1323 1324 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) 1325 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT; 1326 1327 drm_bridge_add(&pdata->bridge); 1328 1329 ret = ti_sn_attach_host(adev, pdata); 1330 if (ret) { 1331 dev_err_probe(&adev->dev, ret, "failed to attach dsi host\n"); 1332 goto err_remove_bridge; 1333 } 1334 1335 return 0; 1336 1337 err_remove_bridge: 1338 drm_bridge_remove(&pdata->bridge); 1339 return ret; 1340 } 1341 1342 static void ti_sn_bridge_remove(struct auxiliary_device *adev) 1343 { 1344 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1345 1346 if (!pdata) 1347 return; 1348 1349 drm_bridge_remove(&pdata->bridge); 1350 1351 of_node_put(pdata->host_node); 1352 } 1353 1354 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = { 1355 { .name = "ti_sn65dsi86.bridge", }, 1356 {}, 1357 }; 1358 1359 static struct auxiliary_driver ti_sn_bridge_driver = { 1360 .name = "bridge", 1361 .probe = ti_sn_bridge_probe, 1362 .remove = ti_sn_bridge_remove, 1363 .id_table = ti_sn_bridge_id_table, 1364 }; 1365 1366 /* ----------------------------------------------------------------------------- 1367 * PWM Controller 1368 */ 1369 #if IS_REACHABLE(CONFIG_PWM) 1370 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) 1371 { 1372 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0; 1373 } 1374 1375 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) 1376 { 1377 atomic_set(&pdata->pwm_pin_busy, 0); 1378 } 1379 1380 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip) 1381 { 1382 return pwmchip_get_drvdata(chip); 1383 } 1384 1385 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 1386 { 1387 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1388 1389 return ti_sn_pwm_pin_request(pdata); 1390 } 1391 1392 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 1393 { 1394 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1395 1396 ti_sn_pwm_pin_release(pdata); 1397 } 1398 1399 /* 1400 * Limitations: 1401 * - The PWM signal is not driven when the chip is powered down, or in its 1402 * reset state and the driver does not implement the "suspend state" 1403 * described in the documentation. In order to save power, state->enabled is 1404 * interpreted as denoting if the signal is expected to be valid, and is used 1405 * to determine if the chip needs to be kept powered. 1406 * - Changing both period and duty_cycle is not done atomically, neither is the 1407 * multi-byte register updates, so the output might briefly be undefined 1408 * during update. 1409 */ 1410 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 1411 const struct pwm_state *state) 1412 { 1413 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1414 unsigned int pwm_en_inv; 1415 unsigned int backlight; 1416 unsigned int pre_div; 1417 unsigned int scale; 1418 u64 period_max; 1419 u64 period; 1420 int ret; 1421 1422 if (!pdata->pwm_enabled) { 1423 ret = pm_runtime_resume_and_get(pwmchip_parent(chip)); 1424 if (ret < 0) 1425 return ret; 1426 } 1427 1428 if (state->enabled) { 1429 if (!pdata->pwm_enabled) { 1430 /* 1431 * The chip might have been powered down while we 1432 * didn't hold a PM runtime reference, so mux in the 1433 * PWM function on the GPIO pin again. 1434 */ 1435 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1436 SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX), 1437 SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX)); 1438 if (ret) { 1439 dev_err(pwmchip_parent(chip), "failed to mux in PWM function\n"); 1440 goto out; 1441 } 1442 } 1443 1444 /* 1445 * Per the datasheet the PWM frequency is given by: 1446 * 1447 * REFCLK_FREQ 1448 * PWM_FREQ = ----------------------------------- 1449 * PWM_PRE_DIV * BACKLIGHT_SCALE + 1 1450 * 1451 * However, after careful review the author is convinced that 1452 * the documentation has lost some parenthesis around 1453 * "BACKLIGHT_SCALE + 1". 1454 * 1455 * With the period T_pwm = 1/PWM_FREQ this can be written: 1456 * 1457 * T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1) 1458 * 1459 * In order to keep BACKLIGHT_SCALE within its 16 bits, 1460 * PWM_PRE_DIV must be: 1461 * 1462 * T_pwm * REFCLK_FREQ 1463 * PWM_PRE_DIV >= ------------------------- 1464 * BACKLIGHT_SCALE_MAX + 1 1465 * 1466 * To simplify the search and to favour higher resolution of 1467 * the duty cycle over accuracy of the period, the lowest 1468 * possible PWM_PRE_DIV is used. Finally the scale is 1469 * calculated as: 1470 * 1471 * T_pwm * REFCLK_FREQ 1472 * BACKLIGHT_SCALE = ---------------------- - 1 1473 * PWM_PRE_DIV 1474 * 1475 * Here T_pwm is represented in seconds, so appropriate scaling 1476 * to nanoseconds is necessary. 1477 */ 1478 1479 /* Minimum T_pwm is 1 / REFCLK_FREQ */ 1480 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) { 1481 ret = -EINVAL; 1482 goto out; 1483 } 1484 1485 /* 1486 * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ 1487 * Limit period to this to avoid overflows 1488 */ 1489 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1), 1490 pdata->pwm_refclk_freq); 1491 period = min(state->period, period_max); 1492 1493 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq, 1494 (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1)); 1495 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1; 1496 1497 /* 1498 * The documentation has the duty ratio given as: 1499 * 1500 * duty BACKLIGHT 1501 * ------- = --------------------- 1502 * period BACKLIGHT_SCALE + 1 1503 * 1504 * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according 1505 * to definition above and adjusting for nanosecond 1506 * representation of duty cycle gives us: 1507 */ 1508 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq, 1509 (u64)NSEC_PER_SEC * pre_div); 1510 if (backlight > scale) 1511 backlight = scale; 1512 1513 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div); 1514 if (ret) { 1515 dev_err(pwmchip_parent(chip), "failed to update PWM_PRE_DIV\n"); 1516 goto out; 1517 } 1518 1519 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale); 1520 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight); 1521 } 1522 1523 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) | 1524 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED); 1525 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv); 1526 if (ret) { 1527 dev_err(pwmchip_parent(chip), "failed to update PWM_EN/PWM_INV\n"); 1528 goto out; 1529 } 1530 1531 pdata->pwm_enabled = state->enabled; 1532 out: 1533 1534 if (!pdata->pwm_enabled) 1535 pm_runtime_put_sync(pwmchip_parent(chip)); 1536 1537 return ret; 1538 } 1539 1540 static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 1541 struct pwm_state *state) 1542 { 1543 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1544 unsigned int pwm_en_inv; 1545 unsigned int pre_div; 1546 u16 backlight; 1547 u16 scale; 1548 int ret; 1549 1550 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv); 1551 if (ret) 1552 return ret; 1553 1554 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale); 1555 if (ret) 1556 return ret; 1557 1558 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight); 1559 if (ret) 1560 return ret; 1561 1562 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div); 1563 if (ret) 1564 return ret; 1565 1566 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv); 1567 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv)) 1568 state->polarity = PWM_POLARITY_INVERSED; 1569 else 1570 state->polarity = PWM_POLARITY_NORMAL; 1571 1572 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1), 1573 pdata->pwm_refclk_freq); 1574 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight, 1575 pdata->pwm_refclk_freq); 1576 1577 if (state->duty_cycle > state->period) 1578 state->duty_cycle = state->period; 1579 1580 return 0; 1581 } 1582 1583 static const struct pwm_ops ti_sn_pwm_ops = { 1584 .request = ti_sn_pwm_request, 1585 .free = ti_sn_pwm_free, 1586 .apply = ti_sn_pwm_apply, 1587 .get_state = ti_sn_pwm_get_state, 1588 }; 1589 1590 static int ti_sn_pwm_probe(struct auxiliary_device *adev, 1591 const struct auxiliary_device_id *id) 1592 { 1593 struct pwm_chip *chip; 1594 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1595 1596 pdata->pchip = chip = devm_pwmchip_alloc(&adev->dev, 1, 0); 1597 if (IS_ERR(chip)) 1598 return PTR_ERR(chip); 1599 1600 pwmchip_set_drvdata(chip, pdata); 1601 1602 chip->ops = &ti_sn_pwm_ops; 1603 chip->of_xlate = of_pwm_single_xlate; 1604 1605 devm_pm_runtime_enable(&adev->dev); 1606 1607 return pwmchip_add(chip); 1608 } 1609 1610 static void ti_sn_pwm_remove(struct auxiliary_device *adev) 1611 { 1612 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1613 1614 pwmchip_remove(pdata->pchip); 1615 1616 if (pdata->pwm_enabled) 1617 pm_runtime_put_sync(&adev->dev); 1618 } 1619 1620 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = { 1621 { .name = "ti_sn65dsi86.pwm", }, 1622 {}, 1623 }; 1624 1625 static struct auxiliary_driver ti_sn_pwm_driver = { 1626 .name = "pwm", 1627 .probe = ti_sn_pwm_probe, 1628 .remove = ti_sn_pwm_remove, 1629 .id_table = ti_sn_pwm_id_table, 1630 }; 1631 1632 static int __init ti_sn_pwm_register(void) 1633 { 1634 return auxiliary_driver_register(&ti_sn_pwm_driver); 1635 } 1636 1637 static void ti_sn_pwm_unregister(void) 1638 { 1639 auxiliary_driver_unregister(&ti_sn_pwm_driver); 1640 } 1641 1642 #else 1643 static inline int __maybe_unused ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; } 1644 static inline void __maybe_unused ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {} 1645 1646 static inline int ti_sn_pwm_register(void) { return 0; } 1647 static inline void ti_sn_pwm_unregister(void) {} 1648 #endif 1649 1650 /* ----------------------------------------------------------------------------- 1651 * GPIO Controller 1652 */ 1653 #if defined(CONFIG_OF_GPIO) 1654 1655 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip, 1656 const struct of_phandle_args *gpiospec, 1657 u32 *flags) 1658 { 1659 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells)) 1660 return -EINVAL; 1661 1662 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1) 1663 return -EINVAL; 1664 1665 if (flags) 1666 *flags = gpiospec->args[1]; 1667 1668 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET; 1669 } 1670 1671 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip, 1672 unsigned int offset) 1673 { 1674 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1675 1676 /* 1677 * We already have to keep track of the direction because we use 1678 * that to figure out whether we've powered the device. We can 1679 * just return that rather than (maybe) powering up the device 1680 * to ask its direction. 1681 */ 1682 return test_bit(offset, pdata->gchip_output) ? 1683 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1684 } 1685 1686 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset) 1687 { 1688 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1689 unsigned int val; 1690 int ret; 1691 1692 /* 1693 * When the pin is an input we don't forcibly keep the bridge 1694 * powered--we just power it on to read the pin. NOTE: part of 1695 * the reason this works is that the bridge defaults (when 1696 * powered back on) to all 4 GPIOs being configured as GPIO input. 1697 * Also note that if something else is keeping the chip powered the 1698 * pm_runtime functions are lightweight increments of a refcount. 1699 */ 1700 pm_runtime_get_sync(pdata->dev); 1701 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val); 1702 pm_runtime_put_autosuspend(pdata->dev); 1703 1704 if (ret) 1705 return ret; 1706 1707 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset)); 1708 } 1709 1710 static void ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, 1711 int val) 1712 { 1713 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1714 int ret; 1715 1716 if (!test_bit(offset, pdata->gchip_output)) { 1717 dev_err(pdata->dev, "Ignoring GPIO set while input\n"); 1718 return; 1719 } 1720 1721 val &= 1; 1722 ret = regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, 1723 BIT(SN_GPIO_OUTPUT_SHIFT + offset), 1724 val << (SN_GPIO_OUTPUT_SHIFT + offset)); 1725 if (ret) 1726 dev_warn(pdata->dev, 1727 "Failed to set bridge GPIO %u: %d\n", offset, ret); 1728 } 1729 1730 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip, 1731 unsigned int offset) 1732 { 1733 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1734 int shift = offset * 2; 1735 int ret; 1736 1737 if (!test_and_clear_bit(offset, pdata->gchip_output)) 1738 return 0; 1739 1740 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1741 SN_GPIO_MUX_MASK << shift, 1742 SN_GPIO_MUX_INPUT << shift); 1743 if (ret) { 1744 set_bit(offset, pdata->gchip_output); 1745 return ret; 1746 } 1747 1748 /* 1749 * NOTE: if nobody else is powering the device this may fully power 1750 * it off and when it comes back it will have lost all state, but 1751 * that's OK because the default is input and we're now an input. 1752 */ 1753 pm_runtime_put_autosuspend(pdata->dev); 1754 1755 return 0; 1756 } 1757 1758 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, 1759 unsigned int offset, int val) 1760 { 1761 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1762 int shift = offset * 2; 1763 int ret; 1764 1765 if (test_and_set_bit(offset, pdata->gchip_output)) 1766 return 0; 1767 1768 pm_runtime_get_sync(pdata->dev); 1769 1770 /* Set value first to avoid glitching */ 1771 ti_sn_bridge_gpio_set(chip, offset, val); 1772 1773 /* Set direction */ 1774 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1775 SN_GPIO_MUX_MASK << shift, 1776 SN_GPIO_MUX_OUTPUT << shift); 1777 if (ret) { 1778 clear_bit(offset, pdata->gchip_output); 1779 pm_runtime_put_autosuspend(pdata->dev); 1780 } 1781 1782 return ret; 1783 } 1784 1785 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset) 1786 { 1787 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1788 1789 if (offset == SN_PWM_GPIO_IDX) 1790 return ti_sn_pwm_pin_request(pdata); 1791 1792 return 0; 1793 } 1794 1795 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset) 1796 { 1797 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1798 1799 /* We won't keep pm_runtime if we're input, so switch there on free */ 1800 ti_sn_bridge_gpio_direction_input(chip, offset); 1801 1802 if (offset == SN_PWM_GPIO_IDX) 1803 ti_sn_pwm_pin_release(pdata); 1804 } 1805 1806 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = { 1807 "GPIO1", "GPIO2", "GPIO3", "GPIO4" 1808 }; 1809 1810 static int ti_sn_gpio_probe(struct auxiliary_device *adev, 1811 const struct auxiliary_device_id *id) 1812 { 1813 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1814 int ret; 1815 1816 /* Only init if someone is going to use us as a GPIO controller */ 1817 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller")) 1818 return 0; 1819 1820 pdata->gchip.label = dev_name(pdata->dev); 1821 pdata->gchip.parent = pdata->dev; 1822 pdata->gchip.owner = THIS_MODULE; 1823 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate; 1824 pdata->gchip.of_gpio_n_cells = 2; 1825 pdata->gchip.request = ti_sn_bridge_gpio_request; 1826 pdata->gchip.free = ti_sn_bridge_gpio_free; 1827 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction; 1828 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input; 1829 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output; 1830 pdata->gchip.get = ti_sn_bridge_gpio_get; 1831 pdata->gchip.set = ti_sn_bridge_gpio_set; 1832 pdata->gchip.can_sleep = true; 1833 pdata->gchip.names = ti_sn_bridge_gpio_names; 1834 pdata->gchip.ngpio = SN_NUM_GPIOS; 1835 pdata->gchip.base = -1; 1836 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata); 1837 if (ret) 1838 dev_err(pdata->dev, "can't add gpio chip\n"); 1839 1840 return ret; 1841 } 1842 1843 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = { 1844 { .name = "ti_sn65dsi86.gpio", }, 1845 {}, 1846 }; 1847 1848 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table); 1849 1850 static struct auxiliary_driver ti_sn_gpio_driver = { 1851 .name = "gpio", 1852 .probe = ti_sn_gpio_probe, 1853 .id_table = ti_sn_gpio_id_table, 1854 }; 1855 1856 static int __init ti_sn_gpio_register(void) 1857 { 1858 return auxiliary_driver_register(&ti_sn_gpio_driver); 1859 } 1860 1861 static void ti_sn_gpio_unregister(void) 1862 { 1863 auxiliary_driver_unregister(&ti_sn_gpio_driver); 1864 } 1865 1866 #else 1867 1868 static inline int ti_sn_gpio_register(void) { return 0; } 1869 static inline void ti_sn_gpio_unregister(void) {} 1870 1871 #endif 1872 1873 /* ----------------------------------------------------------------------------- 1874 * Probe & Remove 1875 */ 1876 1877 static void ti_sn65dsi86_runtime_disable(void *data) 1878 { 1879 pm_runtime_dont_use_autosuspend(data); 1880 pm_runtime_disable(data); 1881 } 1882 1883 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata) 1884 { 1885 unsigned int i; 1886 const char * const ti_sn_bridge_supply_names[] = { 1887 "vcca", "vcc", "vccio", "vpll", 1888 }; 1889 1890 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++) 1891 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i]; 1892 1893 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM, 1894 pdata->supplies); 1895 } 1896 1897 static int ti_sn65dsi86_probe(struct i2c_client *client) 1898 { 1899 struct device *dev = &client->dev; 1900 struct ti_sn65dsi86 *pdata; 1901 u8 id_buf[8]; 1902 int ret; 1903 1904 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1905 DRM_ERROR("device doesn't support I2C\n"); 1906 return -ENODEV; 1907 } 1908 1909 pdata = devm_drm_bridge_alloc(dev, struct ti_sn65dsi86, bridge, &ti_sn_bridge_funcs); 1910 if (IS_ERR(pdata)) 1911 return PTR_ERR(pdata); 1912 dev_set_drvdata(dev, pdata); 1913 pdata->dev = dev; 1914 1915 mutex_init(&pdata->comms_mutex); 1916 1917 pdata->regmap = devm_regmap_init_i2c(client, 1918 &ti_sn65dsi86_regmap_config); 1919 if (IS_ERR(pdata->regmap)) 1920 return dev_err_probe(dev, PTR_ERR(pdata->regmap), 1921 "regmap i2c init failed\n"); 1922 1923 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable", 1924 GPIOD_OUT_LOW); 1925 if (IS_ERR(pdata->enable_gpio)) 1926 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio), 1927 "failed to get enable gpio from DT\n"); 1928 1929 ret = ti_sn65dsi86_parse_regulators(pdata); 1930 if (ret) 1931 return dev_err_probe(dev, ret, "failed to parse regulators\n"); 1932 1933 pdata->refclk = devm_clk_get_optional(dev, "refclk"); 1934 if (IS_ERR(pdata->refclk)) 1935 return dev_err_probe(dev, PTR_ERR(pdata->refclk), 1936 "failed to get reference clock\n"); 1937 1938 pm_runtime_enable(dev); 1939 pm_runtime_set_autosuspend_delay(pdata->dev, 500); 1940 pm_runtime_use_autosuspend(pdata->dev); 1941 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev); 1942 if (ret) 1943 return ret; 1944 1945 pm_runtime_get_sync(dev); 1946 ret = regmap_bulk_read(pdata->regmap, SN_DEVICE_ID_REGS, id_buf, ARRAY_SIZE(id_buf)); 1947 pm_runtime_put_autosuspend(dev); 1948 if (ret) 1949 return dev_err_probe(dev, ret, "failed to read device id\n"); 1950 1951 /* The ID string is stored backwards */ 1952 if (strncmp(id_buf, "68ISD ", ARRAY_SIZE(id_buf))) 1953 return dev_err_probe(dev, -EOPNOTSUPP, "unsupported device id\n"); 1954 1955 /* 1956 * Break ourselves up into a collection of aux devices. The only real 1957 * motiviation here is to solve the chicken-and-egg problem of probe 1958 * ordering. The bridge wants the panel to be there when it probes. 1959 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards) 1960 * when it probes. The panel and maybe backlight might want the DDC 1961 * bus or the pwm_chip. Having sub-devices allows the some sub devices 1962 * to finish probing even if others return -EPROBE_DEFER and gets us 1963 * around the problems. 1964 */ 1965 1966 if (IS_ENABLED(CONFIG_OF_GPIO)) { 1967 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio"); 1968 if (ret) 1969 return ret; 1970 } 1971 1972 if (IS_REACHABLE(CONFIG_PWM)) { 1973 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm"); 1974 if (ret) 1975 return ret; 1976 } 1977 1978 /* 1979 * NOTE: At the end of the AUX channel probe we'll add the aux device 1980 * for the bridge. This is because the bridge can't be used until the 1981 * AUX channel is there and this is a very simple solution to the 1982 * dependency problem. 1983 */ 1984 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux"); 1985 } 1986 1987 static const struct i2c_device_id ti_sn65dsi86_id[] = { 1988 { "ti,sn65dsi86" }, 1989 {} 1990 }; 1991 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id); 1992 1993 static const struct of_device_id ti_sn65dsi86_match_table[] = { 1994 {.compatible = "ti,sn65dsi86"}, 1995 {}, 1996 }; 1997 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table); 1998 1999 static struct i2c_driver ti_sn65dsi86_driver = { 2000 .driver = { 2001 .name = "ti_sn65dsi86", 2002 .of_match_table = ti_sn65dsi86_match_table, 2003 .pm = &ti_sn65dsi86_pm_ops, 2004 }, 2005 .probe = ti_sn65dsi86_probe, 2006 .id_table = ti_sn65dsi86_id, 2007 }; 2008 2009 static int __init ti_sn65dsi86_init(void) 2010 { 2011 int ret; 2012 2013 ret = i2c_add_driver(&ti_sn65dsi86_driver); 2014 if (ret) 2015 return ret; 2016 2017 ret = ti_sn_gpio_register(); 2018 if (ret) 2019 goto err_main_was_registered; 2020 2021 ret = ti_sn_pwm_register(); 2022 if (ret) 2023 goto err_gpio_was_registered; 2024 2025 ret = auxiliary_driver_register(&ti_sn_aux_driver); 2026 if (ret) 2027 goto err_pwm_was_registered; 2028 2029 ret = auxiliary_driver_register(&ti_sn_bridge_driver); 2030 if (ret) 2031 goto err_aux_was_registered; 2032 2033 return 0; 2034 2035 err_aux_was_registered: 2036 auxiliary_driver_unregister(&ti_sn_aux_driver); 2037 err_pwm_was_registered: 2038 ti_sn_pwm_unregister(); 2039 err_gpio_was_registered: 2040 ti_sn_gpio_unregister(); 2041 err_main_was_registered: 2042 i2c_del_driver(&ti_sn65dsi86_driver); 2043 2044 return ret; 2045 } 2046 module_init(ti_sn65dsi86_init); 2047 2048 static void __exit ti_sn65dsi86_exit(void) 2049 { 2050 auxiliary_driver_unregister(&ti_sn_bridge_driver); 2051 auxiliary_driver_unregister(&ti_sn_aux_driver); 2052 ti_sn_pwm_unregister(); 2053 ti_sn_gpio_unregister(); 2054 i2c_del_driver(&ti_sn65dsi86_driver); 2055 } 2056 module_exit(ti_sn65dsi86_exit); 2057 2058 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>"); 2059 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver"); 2060 MODULE_LICENSE("GPL v2"); 2061