1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf 5 */ 6 7 #include <linux/atomic.h> 8 #include <linux/auxiliary_bus.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/debugfs.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/i2c.h> 16 #include <linux/iopoll.h> 17 #include <linux/module.h> 18 #include <linux/of_graph.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/pwm.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 24 #include <linux/unaligned.h> 25 26 #include <drm/display/drm_dp_aux_bus.h> 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_bridge.h> 31 #include <drm/drm_bridge_connector.h> 32 #include <drm/drm_edid.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_of.h> 35 #include <drm/drm_print.h> 36 #include <drm/drm_probe_helper.h> 37 38 #define SN_DEVICE_ID_REGS 0x00 /* up to 0x07 */ 39 #define SN_DEVICE_REV_REG 0x08 40 #define SN_DPPLL_SRC_REG 0x0A 41 #define DPPLL_CLK_SRC_DSICLK BIT(0) 42 #define REFCLK_FREQ_MASK GENMASK(3, 1) 43 #define REFCLK_FREQ(x) ((x) << 1) 44 #define DPPLL_SRC_DP_PLL_LOCK BIT(7) 45 #define SN_PLL_ENABLE_REG 0x0D 46 #define SN_DSI_LANES_REG 0x10 47 #define CHA_DSI_LANES_MASK GENMASK(4, 3) 48 #define CHA_DSI_LANES(x) ((x) << 3) 49 #define SN_DSIA_CLK_FREQ_REG 0x12 50 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20 51 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24 52 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C 53 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D 54 #define CHA_HSYNC_POLARITY BIT(7) 55 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30 56 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31 57 #define CHA_VSYNC_POLARITY BIT(7) 58 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34 59 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36 60 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38 61 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A 62 #define SN_LN_ASSIGN_REG 0x59 63 #define LN_ASSIGN_WIDTH 2 64 #define SN_ENH_FRAME_REG 0x5A 65 #define VSTREAM_ENABLE BIT(3) 66 #define LN_POLRS_OFFSET 4 67 #define LN_POLRS_MASK 0xf0 68 #define SN_DATA_FORMAT_REG 0x5B 69 #define BPP_18_RGB BIT(0) 70 #define SN_HPD_DISABLE_REG 0x5C 71 #define HPD_DISABLE BIT(0) 72 #define HPD_DEBOUNCED_STATE BIT(4) 73 #define SN_GPIO_IO_REG 0x5E 74 #define SN_GPIO_INPUT_SHIFT 4 75 #define SN_GPIO_OUTPUT_SHIFT 0 76 #define SN_GPIO_CTRL_REG 0x5F 77 #define SN_GPIO_MUX_INPUT 0 78 #define SN_GPIO_MUX_OUTPUT 1 79 #define SN_GPIO_MUX_SPECIAL 2 80 #define SN_GPIO_MUX_MASK 0x3 81 #define SN_AUX_WDATA_REG(x) (0x64 + (x)) 82 #define SN_AUX_ADDR_19_16_REG 0x74 83 #define SN_AUX_ADDR_15_8_REG 0x75 84 #define SN_AUX_ADDR_7_0_REG 0x76 85 #define SN_AUX_ADDR_MASK GENMASK(19, 0) 86 #define SN_AUX_LENGTH_REG 0x77 87 #define SN_AUX_CMD_REG 0x78 88 #define AUX_CMD_SEND BIT(0) 89 #define AUX_CMD_REQ(x) ((x) << 4) 90 #define SN_AUX_RDATA_REG(x) (0x79 + (x)) 91 #define SN_SSC_CONFIG_REG 0x93 92 #define DP_NUM_LANES_MASK GENMASK(5, 4) 93 #define DP_NUM_LANES(x) ((x) << 4) 94 #define SN_DATARATE_CONFIG_REG 0x94 95 #define DP_DATARATE_MASK GENMASK(7, 5) 96 #define DP_DATARATE(x) ((x) << 5) 97 #define SN_TRAINING_SETTING_REG 0x95 98 #define SCRAMBLE_DISABLE BIT(4) 99 #define SN_ML_TX_MODE_REG 0x96 100 #define ML_TX_MAIN_LINK_OFF 0 101 #define ML_TX_NORMAL_MODE BIT(0) 102 #define SN_PWM_PRE_DIV_REG 0xA0 103 #define SN_BACKLIGHT_SCALE_REG 0xA1 104 #define BACKLIGHT_SCALE_MAX 0xFFFF 105 #define SN_BACKLIGHT_REG 0xA3 106 #define SN_PWM_EN_INV_REG 0xA5 107 #define SN_PWM_INV_MASK BIT(0) 108 #define SN_PWM_EN_MASK BIT(1) 109 #define SN_AUX_CMD_STATUS_REG 0xF4 110 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3) 111 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5) 112 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6) 113 114 #define MIN_DSI_CLK_FREQ_MHZ 40 115 116 /* fudge factor required to account for 8b/10b encoding */ 117 #define DP_CLK_FUDGE_NUM 10 118 #define DP_CLK_FUDGE_DEN 8 119 120 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */ 121 #define SN_AUX_MAX_PAYLOAD_BYTES 16 122 123 #define SN_REGULATOR_SUPPLY_NUM 4 124 125 #define SN_MAX_DP_LANES 4 126 #define SN_NUM_GPIOS 4 127 #define SN_GPIO_PHYSICAL_OFFSET 1 128 129 #define SN_LINK_TRAINING_TRIES 10 130 131 #define SN_PWM_GPIO_IDX 3 /* 4th GPIO */ 132 133 /** 134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver. 135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality. 136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality. 137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality. 138 * @pwm_aux: AUX-bus sub device for PWM controller functionality. 139 * 140 * @dev: Pointer to the top level (i2c) device. 141 * @regmap: Regmap for accessing i2c. 142 * @aux: Our aux channel. 143 * @bridge: Our bridge. 144 * @connector: Our connector. 145 * @host_node: Remote DSI node. 146 * @dsi: Our MIPI DSI source. 147 * @refclk: Our reference clock. 148 * @next_bridge: The bridge on the eDP side. 149 * @enable_gpio: The GPIO we toggle to enable the bridge. 150 * @supplies: Data for bulk enabling/disabling our regulators. 151 * @dp_lanes: Count of dp_lanes we're using. 152 * @ln_assign: Value to program to the LN_ASSIGN register. 153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG. 154 * @comms_enabled: If true then communication over the aux channel is enabled. 155 * @comms_mutex: Protects modification of comms_enabled. 156 * 157 * @gchip: If we expose our GPIOs, this is used. 158 * @gchip_output: A cache of whether we've set GPIOs to output. This 159 * serves double-duty of keeping track of the direction and 160 * also keeping track of whether we've incremented the 161 * pm_runtime reference count for this pin, which we do 162 * whenever a pin is configured as an output. This is a 163 * bitmap so we can do atomic ops on it without an extra 164 * lock so concurrent users of our 4 GPIOs don't stomp on 165 * each other's read-modify-write. 166 * 167 * @pchip: pwm_chip if the PWM is exposed. 168 * @pwm_enabled: Used to track if the PWM signal is currently enabled. 169 * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM. 170 * @pwm_refclk_freq: Cache for the reference clock input to the PWM. 171 */ 172 struct ti_sn65dsi86 { 173 struct auxiliary_device *bridge_aux; 174 struct auxiliary_device *gpio_aux; 175 struct auxiliary_device *aux_aux; 176 struct auxiliary_device *pwm_aux; 177 178 struct device *dev; 179 struct regmap *regmap; 180 struct drm_dp_aux aux; 181 struct drm_bridge bridge; 182 struct drm_connector *connector; 183 struct device_node *host_node; 184 struct mipi_dsi_device *dsi; 185 struct clk *refclk; 186 struct drm_bridge *next_bridge; 187 struct gpio_desc *enable_gpio; 188 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM]; 189 int dp_lanes; 190 u8 ln_assign; 191 u8 ln_polrs; 192 bool comms_enabled; 193 struct mutex comms_mutex; 194 195 #if defined(CONFIG_OF_GPIO) 196 struct gpio_chip gchip; 197 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS); 198 #endif 199 #if IS_REACHABLE(CONFIG_PWM) 200 struct pwm_chip *pchip; 201 bool pwm_enabled; 202 atomic_t pwm_pin_busy; 203 #endif 204 unsigned int pwm_refclk_freq; 205 }; 206 207 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = { 208 { .range_min = 0, .range_max = 0xFF }, 209 }; 210 211 static const struct regmap_access_table ti_sn_bridge_volatile_table = { 212 .yes_ranges = ti_sn65dsi86_volatile_ranges, 213 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges), 214 }; 215 216 static const struct regmap_config ti_sn65dsi86_regmap_config = { 217 .reg_bits = 8, 218 .val_bits = 8, 219 .volatile_table = &ti_sn_bridge_volatile_table, 220 .cache_type = REGCACHE_NONE, 221 .max_register = 0xFF, 222 }; 223 224 static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata, 225 unsigned int reg, u16 *val) 226 { 227 u8 buf[2]; 228 int ret; 229 230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 231 if (ret) 232 return ret; 233 234 *val = buf[0] | (buf[1] << 8); 235 236 return 0; 237 } 238 239 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata, 240 unsigned int reg, u16 val) 241 { 242 u8 buf[2] = { val & 0xff, val >> 8 }; 243 244 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 245 } 246 247 static struct drm_display_mode * 248 get_new_adjusted_display_mode(struct drm_bridge *bridge, 249 struct drm_atomic_state *state) 250 { 251 struct drm_connector *connector = 252 drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 253 struct drm_connector_state *conn_state = 254 drm_atomic_get_new_connector_state(state, connector); 255 struct drm_crtc_state *crtc_state = 256 drm_atomic_get_new_crtc_state(state, conn_state->crtc); 257 258 return &crtc_state->adjusted_mode; 259 } 260 261 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata, 262 struct drm_atomic_state *state) 263 { 264 u32 bit_rate_khz, clk_freq_khz; 265 struct drm_display_mode *mode = 266 get_new_adjusted_display_mode(&pdata->bridge, state); 267 268 bit_rate_khz = mode->clock * 269 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 270 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2); 271 272 return clk_freq_khz; 273 } 274 275 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */ 276 static const u32 ti_sn_bridge_refclk_lut[] = { 277 12000000, 278 19200000, 279 26000000, 280 27000000, 281 38400000, 282 }; 283 284 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */ 285 static const u32 ti_sn_bridge_dsiclk_lut[] = { 286 468000000, 287 384000000, 288 416000000, 289 486000000, 290 460800000, 291 }; 292 293 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata, 294 struct drm_atomic_state *state) 295 { 296 int i; 297 u32 refclk_rate; 298 const u32 *refclk_lut; 299 size_t refclk_lut_size; 300 301 if (pdata->refclk) { 302 refclk_rate = clk_get_rate(pdata->refclk); 303 refclk_lut = ti_sn_bridge_refclk_lut; 304 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut); 305 clk_prepare_enable(pdata->refclk); 306 } else { 307 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata, state) * 1000; 308 refclk_lut = ti_sn_bridge_dsiclk_lut; 309 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut); 310 } 311 312 /* for i equals to refclk_lut_size means default frequency */ 313 for (i = 0; i < refclk_lut_size; i++) 314 if (refclk_lut[i] == refclk_rate) 315 break; 316 317 /* avoid buffer overflow and "1" is the default rate in the datasheet. */ 318 if (i >= refclk_lut_size) 319 i = 1; 320 321 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK, 322 REFCLK_FREQ(i)); 323 324 /* 325 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG, 326 * regardless of its actual sourcing. 327 */ 328 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i]; 329 } 330 331 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata, 332 struct drm_atomic_state *state) 333 { 334 mutex_lock(&pdata->comms_mutex); 335 336 /* configure bridge ref_clk */ 337 ti_sn_bridge_set_refclk_freq(pdata, state); 338 339 /* 340 * HPD on this bridge chip is a bit useless. This is an eDP bridge 341 * so the HPD is an internal signal that's only there to signal that 342 * the panel is done powering up. ...but the bridge chip debounces 343 * this signal by between 100 ms and 400 ms (depending on process, 344 * voltage, and temperate--I measured it at about 200 ms). One 345 * particular panel asserted HPD 84 ms after it was powered on meaning 346 * that we saw HPD 284 ms after power on. ...but the same panel said 347 * that instead of looking at HPD you could just hardcode a delay of 348 * 200 ms. We'll assume that the panel driver will have the hardcoded 349 * delay in its prepare and always disable HPD. 350 * 351 * If HPD somehow makes sense on some future panel we'll have to 352 * change this to be conditional on someone specifying that HPD should 353 * be used. 354 */ 355 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE, 356 HPD_DISABLE); 357 358 pdata->comms_enabled = true; 359 360 mutex_unlock(&pdata->comms_mutex); 361 } 362 363 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata) 364 { 365 mutex_lock(&pdata->comms_mutex); 366 367 pdata->comms_enabled = false; 368 clk_disable_unprepare(pdata->refclk); 369 370 mutex_unlock(&pdata->comms_mutex); 371 } 372 373 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev) 374 { 375 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 376 int ret; 377 378 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 379 if (ret) { 380 DRM_ERROR("failed to enable supplies %d\n", ret); 381 return ret; 382 } 383 384 /* td2: min 100 us after regulators before enabling the GPIO */ 385 usleep_range(100, 110); 386 387 gpiod_set_value_cansleep(pdata->enable_gpio, 1); 388 389 /* 390 * If we have a reference clock we can enable communication w/ the 391 * panel (including the aux channel) w/out any need for an input clock 392 * so we can do it in resume which lets us read the EDID before 393 * pre_enable(). Without a reference clock we need the MIPI reference 394 * clock so reading early doesn't work. 395 */ 396 if (pdata->refclk) 397 ti_sn65dsi86_enable_comms(pdata, NULL); 398 399 return ret; 400 } 401 402 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev) 403 { 404 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 405 int ret; 406 407 if (pdata->refclk) 408 ti_sn65dsi86_disable_comms(pdata); 409 410 gpiod_set_value_cansleep(pdata->enable_gpio, 0); 411 412 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 413 if (ret) 414 DRM_ERROR("failed to disable supplies %d\n", ret); 415 416 return ret; 417 } 418 419 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = { 420 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL) 421 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 422 pm_runtime_force_resume) 423 }; 424 425 static int status_show(struct seq_file *s, void *data) 426 { 427 struct ti_sn65dsi86 *pdata = s->private; 428 unsigned int reg, val; 429 430 seq_puts(s, "STATUS REGISTERS:\n"); 431 432 pm_runtime_get_sync(pdata->dev); 433 434 /* IRQ Status Registers, see Table 31 in datasheet */ 435 for (reg = 0xf0; reg <= 0xf8; reg++) { 436 regmap_read(pdata->regmap, reg, &val); 437 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val); 438 } 439 440 pm_runtime_put_autosuspend(pdata->dev); 441 442 return 0; 443 } 444 DEFINE_SHOW_ATTRIBUTE(status); 445 446 /* ----------------------------------------------------------------------------- 447 * Auxiliary Devices (*not* AUX) 448 */ 449 450 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata, 451 struct auxiliary_device **aux_out, 452 const char *name) 453 { 454 struct device *dev = pdata->dev; 455 const struct i2c_client *client = to_i2c_client(dev); 456 struct auxiliary_device *aux; 457 int id; 458 459 id = (client->adapter->nr << 10) | client->addr; 460 aux = __devm_auxiliary_device_create(dev, KBUILD_MODNAME, name, 461 NULL, id); 462 if (!aux) 463 return -ENODEV; 464 465 *aux_out = aux; 466 return 0; 467 } 468 469 /* ----------------------------------------------------------------------------- 470 * AUX Adapter 471 */ 472 473 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux) 474 { 475 return container_of(aux, struct ti_sn65dsi86, aux); 476 } 477 478 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux, 479 struct drm_dp_aux_msg *msg) 480 { 481 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux); 482 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); 483 u32 request_val = AUX_CMD_REQ(msg->request); 484 u8 *buf = msg->buffer; 485 unsigned int len = msg->size; 486 unsigned int short_len; 487 unsigned int val; 488 int ret; 489 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG]; 490 491 if (len > SN_AUX_MAX_PAYLOAD_BYTES) 492 return -EINVAL; 493 494 pm_runtime_get_sync(pdata->dev); 495 mutex_lock(&pdata->comms_mutex); 496 497 /* 498 * If someone tries to do a DDC over AUX transaction before pre_enable() 499 * on a device without a dedicated reference clock then we just can't 500 * do it. Fail right away. This prevents non-refclk users from reading 501 * the EDID before enabling the panel but such is life. 502 */ 503 if (!pdata->comms_enabled) { 504 ret = -EIO; 505 goto exit; 506 } 507 508 switch (request) { 509 case DP_AUX_NATIVE_WRITE: 510 case DP_AUX_I2C_WRITE: 511 case DP_AUX_NATIVE_READ: 512 case DP_AUX_I2C_READ: 513 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val); 514 /* Assume it's good */ 515 msg->reply = 0; 516 break; 517 default: 518 ret = -EINVAL; 519 goto exit; 520 } 521 522 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32)); 523 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len, 524 addr_len); 525 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len, 526 ARRAY_SIZE(addr_len)); 527 528 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) 529 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len); 530 531 /* Clear old status bits before start so we don't get confused */ 532 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG, 533 AUX_IRQ_STATUS_NAT_I2C_FAIL | 534 AUX_IRQ_STATUS_AUX_RPLY_TOUT | 535 AUX_IRQ_STATUS_AUX_SHORT); 536 537 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND); 538 539 /* Zero delay loop because i2c transactions are slow already */ 540 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val, 541 !(val & AUX_CMD_SEND), 0, 50 * 1000); 542 if (ret) 543 goto exit; 544 545 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val); 546 if (ret) 547 goto exit; 548 549 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) { 550 /* 551 * The hardware tried the message seven times per the DP spec 552 * but it hit a timeout. We ignore defers here because they're 553 * handled in hardware. 554 */ 555 ret = -ETIMEDOUT; 556 goto exit; 557 } 558 559 if (val & AUX_IRQ_STATUS_AUX_SHORT) { 560 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &short_len); 561 len = min(len, short_len); 562 if (ret) 563 goto exit; 564 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) { 565 switch (request) { 566 case DP_AUX_I2C_WRITE: 567 case DP_AUX_I2C_READ: 568 msg->reply |= DP_AUX_I2C_REPLY_NACK; 569 break; 570 case DP_AUX_NATIVE_READ: 571 case DP_AUX_NATIVE_WRITE: 572 msg->reply |= DP_AUX_NATIVE_REPLY_NACK; 573 break; 574 } 575 len = 0; 576 goto exit; 577 } 578 579 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0) 580 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len); 581 582 exit: 583 mutex_unlock(&pdata->comms_mutex); 584 pm_runtime_mark_last_busy(pdata->dev); 585 pm_runtime_put_autosuspend(pdata->dev); 586 587 if (ret) 588 return ret; 589 return len; 590 } 591 592 static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us) 593 { 594 /* 595 * The HPD in this chip is a bit useless (See comment in 596 * ti_sn65dsi86_enable_comms) so if our driver is expected to wait 597 * for HPD, we just assume it's asserted after the wait_us delay. 598 * 599 * In case we are asked to wait forever (wait_us=0) take conservative 600 * 500ms delay. 601 */ 602 if (wait_us == 0) 603 wait_us = 500000; 604 605 usleep_range(wait_us, wait_us + 1000); 606 607 return 0; 608 } 609 610 static int ti_sn_aux_probe(struct auxiliary_device *adev, 611 const struct auxiliary_device_id *id) 612 { 613 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 614 int ret; 615 616 pdata->aux.name = "ti-sn65dsi86-aux"; 617 pdata->aux.dev = &adev->dev; 618 pdata->aux.transfer = ti_sn_aux_transfer; 619 pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted; 620 drm_dp_aux_init(&pdata->aux); 621 622 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux); 623 if (ret) 624 return ret; 625 626 /* 627 * The eDP to MIPI bridge parts don't work until the AUX channel is 628 * setup so we don't add it in the main driver probe, we add it now. 629 */ 630 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge"); 631 } 632 633 static const struct auxiliary_device_id ti_sn_aux_id_table[] = { 634 { .name = "ti_sn65dsi86.aux", }, 635 {}, 636 }; 637 638 static struct auxiliary_driver ti_sn_aux_driver = { 639 .name = "aux", 640 .probe = ti_sn_aux_probe, 641 .id_table = ti_sn_aux_id_table, 642 }; 643 644 /*------------------------------------------------------------------------------ 645 * DRM Bridge 646 */ 647 648 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge) 649 { 650 return container_of(bridge, struct ti_sn65dsi86, bridge); 651 } 652 653 static int ti_sn_attach_host(struct auxiliary_device *adev, struct ti_sn65dsi86 *pdata) 654 { 655 int val; 656 struct mipi_dsi_host *host; 657 struct mipi_dsi_device *dsi; 658 struct device *dev = pdata->dev; 659 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge", 660 .channel = 0, 661 .node = NULL, 662 }; 663 664 host = of_find_mipi_dsi_host_by_node(pdata->host_node); 665 if (!host) 666 return -EPROBE_DEFER; 667 668 dsi = devm_mipi_dsi_device_register_full(&adev->dev, host, &info); 669 if (IS_ERR(dsi)) 670 return PTR_ERR(dsi); 671 672 /* TODO: setting to 4 MIPI lanes always for now */ 673 dsi->lanes = 4; 674 dsi->format = MIPI_DSI_FMT_RGB888; 675 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; 676 677 /* check if continuous dsi clock is required or not */ 678 pm_runtime_get_sync(dev); 679 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val); 680 pm_runtime_put_autosuspend(dev); 681 if (!(val & DPPLL_CLK_SRC_DSICLK)) 682 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; 683 684 pdata->dsi = dsi; 685 686 return devm_mipi_dsi_attach(&adev->dev, dsi); 687 } 688 689 static int ti_sn_bridge_attach(struct drm_bridge *bridge, 690 struct drm_encoder *encoder, 691 enum drm_bridge_attach_flags flags) 692 { 693 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 694 int ret; 695 696 pdata->aux.drm_dev = bridge->dev; 697 ret = drm_dp_aux_register(&pdata->aux); 698 if (ret < 0) { 699 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret); 700 return ret; 701 } 702 703 /* 704 * Attach the next bridge. 705 * We never want the next bridge to *also* create a connector. 706 */ 707 ret = drm_bridge_attach(encoder, pdata->next_bridge, 708 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); 709 if (ret < 0) 710 goto err_initted_aux; 711 712 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 713 return 0; 714 715 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev, 716 pdata->bridge.encoder); 717 if (IS_ERR(pdata->connector)) { 718 ret = PTR_ERR(pdata->connector); 719 goto err_initted_aux; 720 } 721 722 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder); 723 724 return 0; 725 726 err_initted_aux: 727 drm_dp_aux_unregister(&pdata->aux); 728 return ret; 729 } 730 731 static void ti_sn_bridge_detach(struct drm_bridge *bridge) 732 { 733 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux); 734 } 735 736 static enum drm_mode_status 737 ti_sn_bridge_mode_valid(struct drm_bridge *bridge, 738 const struct drm_display_info *info, 739 const struct drm_display_mode *mode) 740 { 741 /* maximum supported resolution is 4K at 60 fps */ 742 if (mode->clock > 594000) 743 return MODE_CLOCK_HIGH; 744 745 /* 746 * The front and back porch registers are 8 bits, and pulse width 747 * registers are 15 bits, so reject any modes with larger periods. 748 */ 749 750 if ((mode->hsync_start - mode->hdisplay) > 0xff) 751 return MODE_HBLANK_WIDE; 752 753 if ((mode->vsync_start - mode->vdisplay) > 0xff) 754 return MODE_VBLANK_WIDE; 755 756 if ((mode->hsync_end - mode->hsync_start) > 0x7fff) 757 return MODE_HSYNC_WIDE; 758 759 if ((mode->vsync_end - mode->vsync_start) > 0x7fff) 760 return MODE_VSYNC_WIDE; 761 762 if ((mode->htotal - mode->hsync_end) > 0xff) 763 return MODE_HBLANK_WIDE; 764 765 if ((mode->vtotal - mode->vsync_end) > 0xff) 766 return MODE_VBLANK_WIDE; 767 768 return MODE_OK; 769 } 770 771 static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge, 772 struct drm_atomic_state *state) 773 { 774 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 775 776 /* disable video stream */ 777 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0); 778 } 779 780 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata, 781 struct drm_atomic_state *state) 782 { 783 unsigned int bit_rate_mhz, clk_freq_mhz; 784 unsigned int val; 785 struct drm_display_mode *mode = 786 get_new_adjusted_display_mode(&pdata->bridge, state); 787 788 /* set DSIA clk frequency */ 789 bit_rate_mhz = (mode->clock / 1000) * 790 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 791 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); 792 793 /* for each increment in val, frequency increases by 5MHz */ 794 val = (MIN_DSI_CLK_FREQ_MHZ / 5) + 795 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); 796 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); 797 } 798 799 static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector) 800 { 801 if (connector->display_info.bpc <= 6) 802 return 18; 803 else 804 return 24; 805 } 806 807 /* 808 * LUT index corresponds to register value and 809 * LUT values corresponds to dp data rate supported 810 * by the bridge in Mbps unit. 811 */ 812 static const unsigned int ti_sn_bridge_dp_rate_lut[] = { 813 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 814 }; 815 816 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata, 817 struct drm_atomic_state *state, 818 unsigned int bpp) 819 { 820 unsigned int bit_rate_khz, dp_rate_mhz; 821 unsigned int i; 822 struct drm_display_mode *mode = 823 get_new_adjusted_display_mode(&pdata->bridge, state); 824 825 /* Calculate minimum bit rate based on our pixel clock. */ 826 bit_rate_khz = mode->clock * bpp; 827 828 /* Calculate minimum DP data rate, taking 80% as per DP spec */ 829 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM, 830 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN); 831 832 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) 833 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz) 834 break; 835 836 return i; 837 } 838 839 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata) 840 { 841 unsigned int valid_rates = 0; 842 unsigned int rate_per_200khz; 843 unsigned int rate_mhz; 844 u8 dpcd_val; 845 int ret; 846 int i, j; 847 848 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val); 849 if (ret != 1) { 850 DRM_DEV_ERROR(pdata->dev, 851 "Can't read eDP rev (%d), assuming 1.1\n", ret); 852 dpcd_val = DP_EDP_11; 853 } 854 855 if (dpcd_val >= DP_EDP_14) { 856 /* eDP 1.4 devices must provide a custom table */ 857 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 858 859 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES, 860 sink_rates, sizeof(sink_rates)); 861 862 if (ret != sizeof(sink_rates)) { 863 DRM_DEV_ERROR(pdata->dev, 864 "Can't read supported rate table (%d)\n", ret); 865 866 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */ 867 memset(sink_rates, 0, sizeof(sink_rates)); 868 } 869 870 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 871 rate_per_200khz = le16_to_cpu(sink_rates[i]); 872 873 if (!rate_per_200khz) 874 break; 875 876 rate_mhz = rate_per_200khz * 200 / 1000; 877 for (j = 0; 878 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 879 j++) { 880 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz) 881 valid_rates |= BIT(j); 882 } 883 } 884 885 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) { 886 if (valid_rates & BIT(i)) 887 return valid_rates; 888 } 889 DRM_DEV_ERROR(pdata->dev, 890 "No matching eDP rates in table; falling back\n"); 891 } 892 893 /* On older versions best we can do is use DP_MAX_LINK_RATE */ 894 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val); 895 if (ret != 1) { 896 DRM_DEV_ERROR(pdata->dev, 897 "Can't read max rate (%d); assuming 5.4 GHz\n", 898 ret); 899 dpcd_val = DP_LINK_BW_5_4; 900 } 901 902 switch (dpcd_val) { 903 default: 904 DRM_DEV_ERROR(pdata->dev, 905 "Unexpected max rate (%#x); assuming 5.4 GHz\n", 906 (int)dpcd_val); 907 fallthrough; 908 case DP_LINK_BW_5_4: 909 valid_rates |= BIT(7); 910 fallthrough; 911 case DP_LINK_BW_2_7: 912 valid_rates |= BIT(4); 913 fallthrough; 914 case DP_LINK_BW_1_62: 915 valid_rates |= BIT(1); 916 break; 917 } 918 919 return valid_rates; 920 } 921 922 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata, 923 struct drm_atomic_state *state) 924 { 925 struct drm_display_mode *mode = 926 get_new_adjusted_display_mode(&pdata->bridge, state); 927 u8 hsync_polarity = 0, vsync_polarity = 0; 928 929 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 930 hsync_polarity = CHA_HSYNC_POLARITY; 931 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 932 vsync_polarity = CHA_VSYNC_POLARITY; 933 934 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG, 935 mode->hdisplay); 936 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG, 937 mode->vdisplay); 938 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, 939 (mode->hsync_end - mode->hsync_start) & 0xFF); 940 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, 941 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) | 942 hsync_polarity); 943 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, 944 (mode->vsync_end - mode->vsync_start) & 0xFF); 945 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, 946 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) | 947 vsync_polarity); 948 949 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG, 950 (mode->htotal - mode->hsync_end) & 0xFF); 951 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG, 952 (mode->vtotal - mode->vsync_end) & 0xFF); 953 954 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, 955 (mode->hsync_start - mode->hdisplay) & 0xFF); 956 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG, 957 (mode->vsync_start - mode->vdisplay) & 0xFF); 958 959 usleep_range(10000, 10500); /* 10ms delay recommended by spec */ 960 } 961 962 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata) 963 { 964 u8 data; 965 int ret; 966 967 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); 968 if (ret != 1) { 969 DRM_DEV_ERROR(pdata->dev, 970 "Can't read lane count (%d); assuming 4\n", ret); 971 return 4; 972 } 973 974 return data & DP_LANE_COUNT_MASK; 975 } 976 977 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx, 978 const char **last_err_str) 979 { 980 unsigned int val; 981 int ret; 982 int i; 983 984 /* set dp clk frequency value */ 985 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, 986 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx)); 987 988 /* enable DP PLL */ 989 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); 990 991 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, 992 val & DPPLL_SRC_DP_PLL_LOCK, 1000, 993 50 * 1000); 994 if (ret) { 995 *last_err_str = "DP_PLL_LOCK polling failed"; 996 goto exit; 997 } 998 999 /* 1000 * We'll try to link train several times. As part of link training 1001 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If 1002 * the panel isn't ready quite it might respond NAK here which means 1003 * we need to try again. 1004 */ 1005 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) { 1006 /* Semi auto link training mode */ 1007 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); 1008 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, 1009 val == ML_TX_MAIN_LINK_OFF || 1010 val == ML_TX_NORMAL_MODE, 1000, 1011 500 * 1000); 1012 if (ret) { 1013 *last_err_str = "Training complete polling failed"; 1014 } else if (val == ML_TX_MAIN_LINK_OFF) { 1015 *last_err_str = "Link training failed, link is off"; 1016 ret = -EIO; 1017 continue; 1018 } 1019 1020 break; 1021 } 1022 1023 /* If we saw quite a few retries, add a note about it */ 1024 if (!ret && i > SN_LINK_TRAINING_TRIES / 2) 1025 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i); 1026 1027 exit: 1028 /* Disable the PLL if we failed */ 1029 if (ret) 1030 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1031 1032 return ret; 1033 } 1034 1035 static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge, 1036 struct drm_atomic_state *state) 1037 { 1038 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1039 struct drm_connector *connector; 1040 const char *last_err_str = "No supported DP rate"; 1041 unsigned int valid_rates; 1042 int dp_rate_idx; 1043 unsigned int val; 1044 int ret = -EINVAL; 1045 int max_dp_lanes; 1046 unsigned int bpp; 1047 1048 connector = drm_atomic_get_new_connector_for_encoder(state, 1049 bridge->encoder); 1050 if (!connector) { 1051 dev_err_ratelimited(pdata->dev, "Could not get the connector\n"); 1052 return; 1053 } 1054 1055 max_dp_lanes = ti_sn_get_max_lanes(pdata); 1056 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes); 1057 1058 /* DSI_A lane config */ 1059 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes); 1060 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, 1061 CHA_DSI_LANES_MASK, val); 1062 1063 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign); 1064 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK, 1065 pdata->ln_polrs << LN_POLRS_OFFSET); 1066 1067 /* set dsi clk frequency value */ 1068 ti_sn_bridge_set_dsi_rate(pdata, state); 1069 1070 /* 1071 * The SN65DSI86 only supports ASSR Display Authentication method and 1072 * this method is enabled for eDP panels. An eDP panel must support this 1073 * authentication method. We need to enable this method in the eDP panel 1074 * at DisplayPort address 0x0010A prior to link training. 1075 * 1076 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays 1077 * we need to disable the scrambler. 1078 */ 1079 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) { 1080 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, 1081 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); 1082 1083 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1084 SCRAMBLE_DISABLE, 0); 1085 } else { 1086 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1087 SCRAMBLE_DISABLE, SCRAMBLE_DISABLE); 1088 } 1089 1090 bpp = ti_sn_bridge_get_bpp(connector); 1091 /* Set the DP output format (18 bpp or 24 bpp) */ 1092 val = bpp == 18 ? BPP_18_RGB : 0; 1093 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); 1094 1095 /* DP lane config */ 1096 val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); 1097 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 1098 val); 1099 1100 valid_rates = ti_sn_bridge_read_valid_rates(pdata); 1101 1102 /* Train until we run out of rates */ 1103 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, state, bpp); 1104 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 1105 dp_rate_idx++) { 1106 if (!(valid_rates & BIT(dp_rate_idx))) 1107 continue; 1108 1109 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str); 1110 if (!ret) 1111 break; 1112 } 1113 if (ret) { 1114 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret); 1115 return; 1116 } 1117 1118 /* config video parameters */ 1119 ti_sn_bridge_set_video_timings(pdata, state); 1120 1121 /* enable video stream */ 1122 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 1123 VSTREAM_ENABLE); 1124 } 1125 1126 static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge, 1127 struct drm_atomic_state *state) 1128 { 1129 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1130 1131 pm_runtime_get_sync(pdata->dev); 1132 1133 if (!pdata->refclk) 1134 ti_sn65dsi86_enable_comms(pdata, state); 1135 1136 /* td7: min 100 us after enable before DSI data */ 1137 usleep_range(100, 110); 1138 } 1139 1140 static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge, 1141 struct drm_atomic_state *state) 1142 { 1143 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1144 1145 /* semi auto link training mode OFF */ 1146 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); 1147 /* Num lanes to 0 as per power sequencing in data sheet */ 1148 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0); 1149 /* disable DP PLL */ 1150 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1151 1152 if (!pdata->refclk) 1153 ti_sn65dsi86_disable_comms(pdata); 1154 1155 pm_runtime_put_sync(pdata->dev); 1156 } 1157 1158 static enum drm_connector_status 1159 ti_sn_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 1160 { 1161 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1162 int val = 0; 1163 1164 pm_runtime_get_sync(pdata->dev); 1165 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val); 1166 pm_runtime_put_autosuspend(pdata->dev); 1167 1168 return val & HPD_DEBOUNCED_STATE ? connector_status_connected 1169 : connector_status_disconnected; 1170 } 1171 1172 static const struct drm_edid *ti_sn_bridge_edid_read(struct drm_bridge *bridge, 1173 struct drm_connector *connector) 1174 { 1175 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1176 1177 return drm_edid_read_ddc(connector, &pdata->aux.ddc); 1178 } 1179 1180 static void ti_sn65dsi86_debugfs_init(struct drm_bridge *bridge, struct dentry *root) 1181 { 1182 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1183 struct dentry *debugfs; 1184 1185 debugfs = debugfs_create_dir(dev_name(pdata->dev), root); 1186 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops); 1187 } 1188 1189 static const struct drm_bridge_funcs ti_sn_bridge_funcs = { 1190 .attach = ti_sn_bridge_attach, 1191 .detach = ti_sn_bridge_detach, 1192 .mode_valid = ti_sn_bridge_mode_valid, 1193 .edid_read = ti_sn_bridge_edid_read, 1194 .detect = ti_sn_bridge_detect, 1195 .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable, 1196 .atomic_enable = ti_sn_bridge_atomic_enable, 1197 .atomic_disable = ti_sn_bridge_atomic_disable, 1198 .atomic_post_disable = ti_sn_bridge_atomic_post_disable, 1199 .atomic_reset = drm_atomic_helper_bridge_reset, 1200 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1201 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1202 .debugfs_init = ti_sn65dsi86_debugfs_init, 1203 }; 1204 1205 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata, 1206 struct device_node *np) 1207 { 1208 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 }; 1209 u32 lane_polarities[SN_MAX_DP_LANES] = { }; 1210 struct device_node *endpoint; 1211 u8 ln_assign = 0; 1212 u8 ln_polrs = 0; 1213 int dp_lanes; 1214 int i; 1215 1216 /* 1217 * Read config from the device tree about lane remapping and lane 1218 * polarities. These are optional and we assume identity map and 1219 * normal polarity if nothing is specified. It's OK to specify just 1220 * data-lanes but not lane-polarities but not vice versa. 1221 * 1222 * Error checking is light (we just make sure we don't crash or 1223 * buffer overrun) and we assume dts is well formed and specifying 1224 * mappings that the hardware supports. 1225 */ 1226 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1227 dp_lanes = drm_of_get_data_lanes_count(endpoint, 1, SN_MAX_DP_LANES); 1228 if (dp_lanes > 0) { 1229 of_property_read_u32_array(endpoint, "data-lanes", 1230 lane_assignments, dp_lanes); 1231 of_property_read_u32_array(endpoint, "lane-polarities", 1232 lane_polarities, dp_lanes); 1233 } else { 1234 dp_lanes = SN_MAX_DP_LANES; 1235 } 1236 of_node_put(endpoint); 1237 1238 /* 1239 * Convert into register format. Loop over all lanes even if 1240 * data-lanes had fewer elements so that we nicely initialize 1241 * the LN_ASSIGN register. 1242 */ 1243 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) { 1244 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i]; 1245 ln_polrs = ln_polrs << 1 | lane_polarities[i]; 1246 } 1247 1248 /* Stash in our struct for when we power on */ 1249 pdata->dp_lanes = dp_lanes; 1250 pdata->ln_assign = ln_assign; 1251 pdata->ln_polrs = ln_polrs; 1252 } 1253 1254 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata) 1255 { 1256 struct device_node *np = pdata->dev->of_node; 1257 1258 pdata->host_node = of_graph_get_remote_node(np, 0, 0); 1259 1260 if (!pdata->host_node) { 1261 DRM_ERROR("remote dsi host node not found\n"); 1262 return -ENODEV; 1263 } 1264 1265 return 0; 1266 } 1267 1268 static int ti_sn_bridge_probe(struct auxiliary_device *adev, 1269 const struct auxiliary_device_id *id) 1270 { 1271 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1272 struct device_node *np = pdata->dev->of_node; 1273 int ret; 1274 1275 pdata->next_bridge = devm_drm_of_get_bridge(&adev->dev, np, 1, 0); 1276 if (IS_ERR(pdata->next_bridge)) 1277 return dev_err_probe(&adev->dev, PTR_ERR(pdata->next_bridge), 1278 "failed to create panel bridge\n"); 1279 1280 ti_sn_bridge_parse_lanes(pdata, np); 1281 1282 ret = ti_sn_bridge_parse_dsi_host(pdata); 1283 if (ret) 1284 return ret; 1285 1286 pdata->bridge.of_node = np; 1287 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort 1288 ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP; 1289 1290 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) 1291 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT; 1292 1293 drm_bridge_add(&pdata->bridge); 1294 1295 ret = ti_sn_attach_host(adev, pdata); 1296 if (ret) { 1297 dev_err_probe(&adev->dev, ret, "failed to attach dsi host\n"); 1298 goto err_remove_bridge; 1299 } 1300 1301 return 0; 1302 1303 err_remove_bridge: 1304 drm_bridge_remove(&pdata->bridge); 1305 return ret; 1306 } 1307 1308 static void ti_sn_bridge_remove(struct auxiliary_device *adev) 1309 { 1310 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1311 1312 if (!pdata) 1313 return; 1314 1315 drm_bridge_remove(&pdata->bridge); 1316 1317 of_node_put(pdata->host_node); 1318 } 1319 1320 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = { 1321 { .name = "ti_sn65dsi86.bridge", }, 1322 {}, 1323 }; 1324 1325 static struct auxiliary_driver ti_sn_bridge_driver = { 1326 .name = "bridge", 1327 .probe = ti_sn_bridge_probe, 1328 .remove = ti_sn_bridge_remove, 1329 .id_table = ti_sn_bridge_id_table, 1330 }; 1331 1332 /* ----------------------------------------------------------------------------- 1333 * PWM Controller 1334 */ 1335 #if IS_REACHABLE(CONFIG_PWM) 1336 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) 1337 { 1338 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0; 1339 } 1340 1341 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) 1342 { 1343 atomic_set(&pdata->pwm_pin_busy, 0); 1344 } 1345 1346 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip) 1347 { 1348 return pwmchip_get_drvdata(chip); 1349 } 1350 1351 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 1352 { 1353 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1354 1355 return ti_sn_pwm_pin_request(pdata); 1356 } 1357 1358 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 1359 { 1360 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1361 1362 ti_sn_pwm_pin_release(pdata); 1363 } 1364 1365 /* 1366 * Limitations: 1367 * - The PWM signal is not driven when the chip is powered down, or in its 1368 * reset state and the driver does not implement the "suspend state" 1369 * described in the documentation. In order to save power, state->enabled is 1370 * interpreted as denoting if the signal is expected to be valid, and is used 1371 * to determine if the chip needs to be kept powered. 1372 * - Changing both period and duty_cycle is not done atomically, neither is the 1373 * multi-byte register updates, so the output might briefly be undefined 1374 * during update. 1375 */ 1376 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 1377 const struct pwm_state *state) 1378 { 1379 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1380 unsigned int pwm_en_inv; 1381 unsigned int backlight; 1382 unsigned int pre_div; 1383 unsigned int scale; 1384 u64 period_max; 1385 u64 period; 1386 int ret; 1387 1388 if (!pdata->pwm_enabled) { 1389 ret = pm_runtime_resume_and_get(pwmchip_parent(chip)); 1390 if (ret < 0) 1391 return ret; 1392 } 1393 1394 if (state->enabled) { 1395 if (!pdata->pwm_enabled) { 1396 /* 1397 * The chip might have been powered down while we 1398 * didn't hold a PM runtime reference, so mux in the 1399 * PWM function on the GPIO pin again. 1400 */ 1401 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1402 SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX), 1403 SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX)); 1404 if (ret) { 1405 dev_err(pwmchip_parent(chip), "failed to mux in PWM function\n"); 1406 goto out; 1407 } 1408 } 1409 1410 /* 1411 * Per the datasheet the PWM frequency is given by: 1412 * 1413 * REFCLK_FREQ 1414 * PWM_FREQ = ----------------------------------- 1415 * PWM_PRE_DIV * BACKLIGHT_SCALE + 1 1416 * 1417 * However, after careful review the author is convinced that 1418 * the documentation has lost some parenthesis around 1419 * "BACKLIGHT_SCALE + 1". 1420 * 1421 * With the period T_pwm = 1/PWM_FREQ this can be written: 1422 * 1423 * T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1) 1424 * 1425 * In order to keep BACKLIGHT_SCALE within its 16 bits, 1426 * PWM_PRE_DIV must be: 1427 * 1428 * T_pwm * REFCLK_FREQ 1429 * PWM_PRE_DIV >= ------------------------- 1430 * BACKLIGHT_SCALE_MAX + 1 1431 * 1432 * To simplify the search and to favour higher resolution of 1433 * the duty cycle over accuracy of the period, the lowest 1434 * possible PWM_PRE_DIV is used. Finally the scale is 1435 * calculated as: 1436 * 1437 * T_pwm * REFCLK_FREQ 1438 * BACKLIGHT_SCALE = ---------------------- - 1 1439 * PWM_PRE_DIV 1440 * 1441 * Here T_pwm is represented in seconds, so appropriate scaling 1442 * to nanoseconds is necessary. 1443 */ 1444 1445 /* Minimum T_pwm is 1 / REFCLK_FREQ */ 1446 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) { 1447 ret = -EINVAL; 1448 goto out; 1449 } 1450 1451 /* 1452 * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ 1453 * Limit period to this to avoid overflows 1454 */ 1455 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1), 1456 pdata->pwm_refclk_freq); 1457 period = min(state->period, period_max); 1458 1459 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq, 1460 (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1)); 1461 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1; 1462 1463 /* 1464 * The documentation has the duty ratio given as: 1465 * 1466 * duty BACKLIGHT 1467 * ------- = --------------------- 1468 * period BACKLIGHT_SCALE + 1 1469 * 1470 * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according 1471 * to definition above and adjusting for nanosecond 1472 * representation of duty cycle gives us: 1473 */ 1474 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq, 1475 (u64)NSEC_PER_SEC * pre_div); 1476 if (backlight > scale) 1477 backlight = scale; 1478 1479 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div); 1480 if (ret) { 1481 dev_err(pwmchip_parent(chip), "failed to update PWM_PRE_DIV\n"); 1482 goto out; 1483 } 1484 1485 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale); 1486 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight); 1487 } 1488 1489 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) | 1490 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED); 1491 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv); 1492 if (ret) { 1493 dev_err(pwmchip_parent(chip), "failed to update PWM_EN/PWM_INV\n"); 1494 goto out; 1495 } 1496 1497 pdata->pwm_enabled = state->enabled; 1498 out: 1499 1500 if (!pdata->pwm_enabled) 1501 pm_runtime_put_sync(pwmchip_parent(chip)); 1502 1503 return ret; 1504 } 1505 1506 static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 1507 struct pwm_state *state) 1508 { 1509 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1510 unsigned int pwm_en_inv; 1511 unsigned int pre_div; 1512 u16 backlight; 1513 u16 scale; 1514 int ret; 1515 1516 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv); 1517 if (ret) 1518 return ret; 1519 1520 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale); 1521 if (ret) 1522 return ret; 1523 1524 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight); 1525 if (ret) 1526 return ret; 1527 1528 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div); 1529 if (ret) 1530 return ret; 1531 1532 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv); 1533 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv)) 1534 state->polarity = PWM_POLARITY_INVERSED; 1535 else 1536 state->polarity = PWM_POLARITY_NORMAL; 1537 1538 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1), 1539 pdata->pwm_refclk_freq); 1540 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight, 1541 pdata->pwm_refclk_freq); 1542 1543 if (state->duty_cycle > state->period) 1544 state->duty_cycle = state->period; 1545 1546 return 0; 1547 } 1548 1549 static const struct pwm_ops ti_sn_pwm_ops = { 1550 .request = ti_sn_pwm_request, 1551 .free = ti_sn_pwm_free, 1552 .apply = ti_sn_pwm_apply, 1553 .get_state = ti_sn_pwm_get_state, 1554 }; 1555 1556 static int ti_sn_pwm_probe(struct auxiliary_device *adev, 1557 const struct auxiliary_device_id *id) 1558 { 1559 struct pwm_chip *chip; 1560 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1561 1562 pdata->pchip = chip = devm_pwmchip_alloc(&adev->dev, 1, 0); 1563 if (IS_ERR(chip)) 1564 return PTR_ERR(chip); 1565 1566 pwmchip_set_drvdata(chip, pdata); 1567 1568 chip->ops = &ti_sn_pwm_ops; 1569 chip->of_xlate = of_pwm_single_xlate; 1570 1571 devm_pm_runtime_enable(&adev->dev); 1572 1573 return pwmchip_add(chip); 1574 } 1575 1576 static void ti_sn_pwm_remove(struct auxiliary_device *adev) 1577 { 1578 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1579 1580 pwmchip_remove(pdata->pchip); 1581 1582 if (pdata->pwm_enabled) 1583 pm_runtime_put_sync(&adev->dev); 1584 } 1585 1586 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = { 1587 { .name = "ti_sn65dsi86.pwm", }, 1588 {}, 1589 }; 1590 1591 static struct auxiliary_driver ti_sn_pwm_driver = { 1592 .name = "pwm", 1593 .probe = ti_sn_pwm_probe, 1594 .remove = ti_sn_pwm_remove, 1595 .id_table = ti_sn_pwm_id_table, 1596 }; 1597 1598 static int __init ti_sn_pwm_register(void) 1599 { 1600 return auxiliary_driver_register(&ti_sn_pwm_driver); 1601 } 1602 1603 static void ti_sn_pwm_unregister(void) 1604 { 1605 auxiliary_driver_unregister(&ti_sn_pwm_driver); 1606 } 1607 1608 #else 1609 static inline int __maybe_unused ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; } 1610 static inline void __maybe_unused ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {} 1611 1612 static inline int ti_sn_pwm_register(void) { return 0; } 1613 static inline void ti_sn_pwm_unregister(void) {} 1614 #endif 1615 1616 /* ----------------------------------------------------------------------------- 1617 * GPIO Controller 1618 */ 1619 #if defined(CONFIG_OF_GPIO) 1620 1621 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip, 1622 const struct of_phandle_args *gpiospec, 1623 u32 *flags) 1624 { 1625 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells)) 1626 return -EINVAL; 1627 1628 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1) 1629 return -EINVAL; 1630 1631 if (flags) 1632 *flags = gpiospec->args[1]; 1633 1634 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET; 1635 } 1636 1637 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip, 1638 unsigned int offset) 1639 { 1640 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1641 1642 /* 1643 * We already have to keep track of the direction because we use 1644 * that to figure out whether we've powered the device. We can 1645 * just return that rather than (maybe) powering up the device 1646 * to ask its direction. 1647 */ 1648 return test_bit(offset, pdata->gchip_output) ? 1649 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1650 } 1651 1652 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset) 1653 { 1654 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1655 unsigned int val; 1656 int ret; 1657 1658 /* 1659 * When the pin is an input we don't forcibly keep the bridge 1660 * powered--we just power it on to read the pin. NOTE: part of 1661 * the reason this works is that the bridge defaults (when 1662 * powered back on) to all 4 GPIOs being configured as GPIO input. 1663 * Also note that if something else is keeping the chip powered the 1664 * pm_runtime functions are lightweight increments of a refcount. 1665 */ 1666 pm_runtime_get_sync(pdata->dev); 1667 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val); 1668 pm_runtime_put_autosuspend(pdata->dev); 1669 1670 if (ret) 1671 return ret; 1672 1673 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset)); 1674 } 1675 1676 static int ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, 1677 int val) 1678 { 1679 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1680 1681 val &= 1; 1682 return regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, 1683 BIT(SN_GPIO_OUTPUT_SHIFT + offset), 1684 val << (SN_GPIO_OUTPUT_SHIFT + offset)); 1685 } 1686 1687 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip, 1688 unsigned int offset) 1689 { 1690 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1691 int shift = offset * 2; 1692 int ret; 1693 1694 if (!test_and_clear_bit(offset, pdata->gchip_output)) 1695 return 0; 1696 1697 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1698 SN_GPIO_MUX_MASK << shift, 1699 SN_GPIO_MUX_INPUT << shift); 1700 if (ret) { 1701 set_bit(offset, pdata->gchip_output); 1702 return ret; 1703 } 1704 1705 /* 1706 * NOTE: if nobody else is powering the device this may fully power 1707 * it off and when it comes back it will have lost all state, but 1708 * that's OK because the default is input and we're now an input. 1709 */ 1710 pm_runtime_put_autosuspend(pdata->dev); 1711 1712 return 0; 1713 } 1714 1715 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, 1716 unsigned int offset, int val) 1717 { 1718 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1719 int shift = offset * 2; 1720 int ret; 1721 1722 if (test_and_set_bit(offset, pdata->gchip_output)) 1723 return 0; 1724 1725 pm_runtime_get_sync(pdata->dev); 1726 1727 /* Set value first to avoid glitching */ 1728 ti_sn_bridge_gpio_set(chip, offset, val); 1729 1730 /* Set direction */ 1731 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1732 SN_GPIO_MUX_MASK << shift, 1733 SN_GPIO_MUX_OUTPUT << shift); 1734 if (ret) { 1735 clear_bit(offset, pdata->gchip_output); 1736 pm_runtime_put_autosuspend(pdata->dev); 1737 } 1738 1739 return ret; 1740 } 1741 1742 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset) 1743 { 1744 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1745 1746 if (offset == SN_PWM_GPIO_IDX) 1747 return ti_sn_pwm_pin_request(pdata); 1748 1749 return 0; 1750 } 1751 1752 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset) 1753 { 1754 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1755 1756 /* We won't keep pm_runtime if we're input, so switch there on free */ 1757 ti_sn_bridge_gpio_direction_input(chip, offset); 1758 1759 if (offset == SN_PWM_GPIO_IDX) 1760 ti_sn_pwm_pin_release(pdata); 1761 } 1762 1763 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = { 1764 "GPIO1", "GPIO2", "GPIO3", "GPIO4" 1765 }; 1766 1767 static int ti_sn_gpio_probe(struct auxiliary_device *adev, 1768 const struct auxiliary_device_id *id) 1769 { 1770 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1771 int ret; 1772 1773 /* Only init if someone is going to use us as a GPIO controller */ 1774 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller")) 1775 return 0; 1776 1777 pdata->gchip.label = dev_name(pdata->dev); 1778 pdata->gchip.parent = pdata->dev; 1779 pdata->gchip.owner = THIS_MODULE; 1780 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate; 1781 pdata->gchip.of_gpio_n_cells = 2; 1782 pdata->gchip.request = ti_sn_bridge_gpio_request; 1783 pdata->gchip.free = ti_sn_bridge_gpio_free; 1784 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction; 1785 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input; 1786 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output; 1787 pdata->gchip.get = ti_sn_bridge_gpio_get; 1788 pdata->gchip.set_rv = ti_sn_bridge_gpio_set; 1789 pdata->gchip.can_sleep = true; 1790 pdata->gchip.names = ti_sn_bridge_gpio_names; 1791 pdata->gchip.ngpio = SN_NUM_GPIOS; 1792 pdata->gchip.base = -1; 1793 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata); 1794 if (ret) 1795 dev_err(pdata->dev, "can't add gpio chip\n"); 1796 1797 return ret; 1798 } 1799 1800 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = { 1801 { .name = "ti_sn65dsi86.gpio", }, 1802 {}, 1803 }; 1804 1805 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table); 1806 1807 static struct auxiliary_driver ti_sn_gpio_driver = { 1808 .name = "gpio", 1809 .probe = ti_sn_gpio_probe, 1810 .id_table = ti_sn_gpio_id_table, 1811 }; 1812 1813 static int __init ti_sn_gpio_register(void) 1814 { 1815 return auxiliary_driver_register(&ti_sn_gpio_driver); 1816 } 1817 1818 static void ti_sn_gpio_unregister(void) 1819 { 1820 auxiliary_driver_unregister(&ti_sn_gpio_driver); 1821 } 1822 1823 #else 1824 1825 static inline int ti_sn_gpio_register(void) { return 0; } 1826 static inline void ti_sn_gpio_unregister(void) {} 1827 1828 #endif 1829 1830 /* ----------------------------------------------------------------------------- 1831 * Probe & Remove 1832 */ 1833 1834 static void ti_sn65dsi86_runtime_disable(void *data) 1835 { 1836 pm_runtime_dont_use_autosuspend(data); 1837 pm_runtime_disable(data); 1838 } 1839 1840 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata) 1841 { 1842 unsigned int i; 1843 const char * const ti_sn_bridge_supply_names[] = { 1844 "vcca", "vcc", "vccio", "vpll", 1845 }; 1846 1847 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++) 1848 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i]; 1849 1850 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM, 1851 pdata->supplies); 1852 } 1853 1854 static int ti_sn65dsi86_probe(struct i2c_client *client) 1855 { 1856 struct device *dev = &client->dev; 1857 struct ti_sn65dsi86 *pdata; 1858 u8 id_buf[8]; 1859 int ret; 1860 1861 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1862 DRM_ERROR("device doesn't support I2C\n"); 1863 return -ENODEV; 1864 } 1865 1866 pdata = devm_drm_bridge_alloc(dev, struct ti_sn65dsi86, bridge, &ti_sn_bridge_funcs); 1867 if (IS_ERR(pdata)) 1868 return PTR_ERR(pdata); 1869 dev_set_drvdata(dev, pdata); 1870 pdata->dev = dev; 1871 1872 mutex_init(&pdata->comms_mutex); 1873 1874 pdata->regmap = devm_regmap_init_i2c(client, 1875 &ti_sn65dsi86_regmap_config); 1876 if (IS_ERR(pdata->regmap)) 1877 return dev_err_probe(dev, PTR_ERR(pdata->regmap), 1878 "regmap i2c init failed\n"); 1879 1880 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable", 1881 GPIOD_OUT_LOW); 1882 if (IS_ERR(pdata->enable_gpio)) 1883 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio), 1884 "failed to get enable gpio from DT\n"); 1885 1886 ret = ti_sn65dsi86_parse_regulators(pdata); 1887 if (ret) 1888 return dev_err_probe(dev, ret, "failed to parse regulators\n"); 1889 1890 pdata->refclk = devm_clk_get_optional(dev, "refclk"); 1891 if (IS_ERR(pdata->refclk)) 1892 return dev_err_probe(dev, PTR_ERR(pdata->refclk), 1893 "failed to get reference clock\n"); 1894 1895 pm_runtime_enable(dev); 1896 pm_runtime_set_autosuspend_delay(pdata->dev, 500); 1897 pm_runtime_use_autosuspend(pdata->dev); 1898 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev); 1899 if (ret) 1900 return ret; 1901 1902 pm_runtime_get_sync(dev); 1903 ret = regmap_bulk_read(pdata->regmap, SN_DEVICE_ID_REGS, id_buf, ARRAY_SIZE(id_buf)); 1904 pm_runtime_put_autosuspend(dev); 1905 if (ret) 1906 return dev_err_probe(dev, ret, "failed to read device id\n"); 1907 1908 /* The ID string is stored backwards */ 1909 if (strncmp(id_buf, "68ISD ", ARRAY_SIZE(id_buf))) 1910 return dev_err_probe(dev, -EOPNOTSUPP, "unsupported device id\n"); 1911 1912 /* 1913 * Break ourselves up into a collection of aux devices. The only real 1914 * motiviation here is to solve the chicken-and-egg problem of probe 1915 * ordering. The bridge wants the panel to be there when it probes. 1916 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards) 1917 * when it probes. The panel and maybe backlight might want the DDC 1918 * bus or the pwm_chip. Having sub-devices allows the some sub devices 1919 * to finish probing even if others return -EPROBE_DEFER and gets us 1920 * around the problems. 1921 */ 1922 1923 if (IS_ENABLED(CONFIG_OF_GPIO)) { 1924 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio"); 1925 if (ret) 1926 return ret; 1927 } 1928 1929 if (IS_REACHABLE(CONFIG_PWM)) { 1930 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm"); 1931 if (ret) 1932 return ret; 1933 } 1934 1935 /* 1936 * NOTE: At the end of the AUX channel probe we'll add the aux device 1937 * for the bridge. This is because the bridge can't be used until the 1938 * AUX channel is there and this is a very simple solution to the 1939 * dependency problem. 1940 */ 1941 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux"); 1942 } 1943 1944 static const struct i2c_device_id ti_sn65dsi86_id[] = { 1945 { "ti,sn65dsi86" }, 1946 {} 1947 }; 1948 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id); 1949 1950 static const struct of_device_id ti_sn65dsi86_match_table[] = { 1951 {.compatible = "ti,sn65dsi86"}, 1952 {}, 1953 }; 1954 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table); 1955 1956 static struct i2c_driver ti_sn65dsi86_driver = { 1957 .driver = { 1958 .name = "ti_sn65dsi86", 1959 .of_match_table = ti_sn65dsi86_match_table, 1960 .pm = &ti_sn65dsi86_pm_ops, 1961 }, 1962 .probe = ti_sn65dsi86_probe, 1963 .id_table = ti_sn65dsi86_id, 1964 }; 1965 1966 static int __init ti_sn65dsi86_init(void) 1967 { 1968 int ret; 1969 1970 ret = i2c_add_driver(&ti_sn65dsi86_driver); 1971 if (ret) 1972 return ret; 1973 1974 ret = ti_sn_gpio_register(); 1975 if (ret) 1976 goto err_main_was_registered; 1977 1978 ret = ti_sn_pwm_register(); 1979 if (ret) 1980 goto err_gpio_was_registered; 1981 1982 ret = auxiliary_driver_register(&ti_sn_aux_driver); 1983 if (ret) 1984 goto err_pwm_was_registered; 1985 1986 ret = auxiliary_driver_register(&ti_sn_bridge_driver); 1987 if (ret) 1988 goto err_aux_was_registered; 1989 1990 return 0; 1991 1992 err_aux_was_registered: 1993 auxiliary_driver_unregister(&ti_sn_aux_driver); 1994 err_pwm_was_registered: 1995 ti_sn_pwm_unregister(); 1996 err_gpio_was_registered: 1997 ti_sn_gpio_unregister(); 1998 err_main_was_registered: 1999 i2c_del_driver(&ti_sn65dsi86_driver); 2000 2001 return ret; 2002 } 2003 module_init(ti_sn65dsi86_init); 2004 2005 static void __exit ti_sn65dsi86_exit(void) 2006 { 2007 auxiliary_driver_unregister(&ti_sn_bridge_driver); 2008 auxiliary_driver_unregister(&ti_sn_aux_driver); 2009 ti_sn_pwm_unregister(); 2010 ti_sn_gpio_unregister(); 2011 i2c_del_driver(&ti_sn65dsi86_driver); 2012 } 2013 module_exit(ti_sn65dsi86_exit); 2014 2015 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>"); 2016 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver"); 2017 MODULE_LICENSE("GPL v2"); 2018