1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf 5 */ 6 7 #include <linux/atomic.h> 8 #include <linux/auxiliary_bus.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/debugfs.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/i2c.h> 16 #include <linux/iopoll.h> 17 #include <linux/module.h> 18 #include <linux/of_graph.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/pwm.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 24 #include <linux/unaligned.h> 25 26 #include <drm/display/drm_dp_aux_bus.h> 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_bridge.h> 31 #include <drm/drm_bridge_connector.h> 32 #include <drm/drm_edid.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_of.h> 35 #include <drm/drm_print.h> 36 #include <drm/drm_probe_helper.h> 37 38 #define SN_DEVICE_ID_REGS 0x00 /* up to 0x07 */ 39 #define SN_DEVICE_REV_REG 0x08 40 #define SN_DPPLL_SRC_REG 0x0A 41 #define DPPLL_CLK_SRC_DSICLK BIT(0) 42 #define REFCLK_FREQ_MASK GENMASK(3, 1) 43 #define REFCLK_FREQ(x) ((x) << 1) 44 #define DPPLL_SRC_DP_PLL_LOCK BIT(7) 45 #define SN_PLL_ENABLE_REG 0x0D 46 #define SN_DSI_LANES_REG 0x10 47 #define CHA_DSI_LANES_MASK GENMASK(4, 3) 48 #define CHA_DSI_LANES(x) ((x) << 3) 49 #define SN_DSIA_CLK_FREQ_REG 0x12 50 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20 51 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24 52 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C 53 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D 54 #define CHA_HSYNC_POLARITY BIT(7) 55 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30 56 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31 57 #define CHA_VSYNC_POLARITY BIT(7) 58 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34 59 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36 60 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38 61 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A 62 #define SN_LN_ASSIGN_REG 0x59 63 #define LN_ASSIGN_WIDTH 2 64 #define SN_ENH_FRAME_REG 0x5A 65 #define VSTREAM_ENABLE BIT(3) 66 #define LN_POLRS_OFFSET 4 67 #define LN_POLRS_MASK 0xf0 68 #define SN_DATA_FORMAT_REG 0x5B 69 #define BPP_18_RGB BIT(0) 70 #define SN_HPD_DISABLE_REG 0x5C 71 #define HPD_DISABLE BIT(0) 72 #define HPD_DEBOUNCED_STATE BIT(4) 73 #define SN_GPIO_IO_REG 0x5E 74 #define SN_GPIO_INPUT_SHIFT 4 75 #define SN_GPIO_OUTPUT_SHIFT 0 76 #define SN_GPIO_CTRL_REG 0x5F 77 #define SN_GPIO_MUX_INPUT 0 78 #define SN_GPIO_MUX_OUTPUT 1 79 #define SN_GPIO_MUX_SPECIAL 2 80 #define SN_GPIO_MUX_MASK 0x3 81 #define SN_AUX_WDATA_REG(x) (0x64 + (x)) 82 #define SN_AUX_ADDR_19_16_REG 0x74 83 #define SN_AUX_ADDR_15_8_REG 0x75 84 #define SN_AUX_ADDR_7_0_REG 0x76 85 #define SN_AUX_ADDR_MASK GENMASK(19, 0) 86 #define SN_AUX_LENGTH_REG 0x77 87 #define SN_AUX_CMD_REG 0x78 88 #define AUX_CMD_SEND BIT(0) 89 #define AUX_CMD_REQ(x) ((x) << 4) 90 #define SN_AUX_RDATA_REG(x) (0x79 + (x)) 91 #define SN_SSC_CONFIG_REG 0x93 92 #define DP_NUM_LANES_MASK GENMASK(5, 4) 93 #define DP_NUM_LANES(x) ((x) << 4) 94 #define SN_DATARATE_CONFIG_REG 0x94 95 #define DP_DATARATE_MASK GENMASK(7, 5) 96 #define DP_DATARATE(x) ((x) << 5) 97 #define SN_TRAINING_SETTING_REG 0x95 98 #define SCRAMBLE_DISABLE BIT(4) 99 #define SN_ML_TX_MODE_REG 0x96 100 #define ML_TX_MAIN_LINK_OFF 0 101 #define ML_TX_NORMAL_MODE BIT(0) 102 #define SN_PWM_PRE_DIV_REG 0xA0 103 #define SN_BACKLIGHT_SCALE_REG 0xA1 104 #define BACKLIGHT_SCALE_MAX 0xFFFF 105 #define SN_BACKLIGHT_REG 0xA3 106 #define SN_PWM_EN_INV_REG 0xA5 107 #define SN_PWM_INV_MASK BIT(0) 108 #define SN_PWM_EN_MASK BIT(1) 109 #define SN_AUX_CMD_STATUS_REG 0xF4 110 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3) 111 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5) 112 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6) 113 114 #define MIN_DSI_CLK_FREQ_MHZ 40 115 116 /* fudge factor required to account for 8b/10b encoding */ 117 #define DP_CLK_FUDGE_NUM 10 118 #define DP_CLK_FUDGE_DEN 8 119 120 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */ 121 #define SN_AUX_MAX_PAYLOAD_BYTES 16 122 123 #define SN_REGULATOR_SUPPLY_NUM 4 124 125 #define SN_MAX_DP_LANES 4 126 #define SN_NUM_GPIOS 4 127 #define SN_GPIO_PHYSICAL_OFFSET 1 128 129 #define SN_LINK_TRAINING_TRIES 10 130 131 #define SN_PWM_GPIO_IDX 3 /* 4th GPIO */ 132 133 /** 134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver. 135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality. 136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality. 137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality. 138 * @pwm_aux: AUX-bus sub device for PWM controller functionality. 139 * 140 * @dev: Pointer to the top level (i2c) device. 141 * @regmap: Regmap for accessing i2c. 142 * @aux: Our aux channel. 143 * @bridge: Our bridge. 144 * @connector: Our connector. 145 * @host_node: Remote DSI node. 146 * @dsi: Our MIPI DSI source. 147 * @refclk: Our reference clock. 148 * @next_bridge: The bridge on the eDP side. 149 * @enable_gpio: The GPIO we toggle to enable the bridge. 150 * @supplies: Data for bulk enabling/disabling our regulators. 151 * @dp_lanes: Count of dp_lanes we're using. 152 * @ln_assign: Value to program to the LN_ASSIGN register. 153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG. 154 * @comms_enabled: If true then communication over the aux channel is enabled. 155 * @comms_mutex: Protects modification of comms_enabled. 156 * 157 * @gchip: If we expose our GPIOs, this is used. 158 * @gchip_output: A cache of whether we've set GPIOs to output. This 159 * serves double-duty of keeping track of the direction and 160 * also keeping track of whether we've incremented the 161 * pm_runtime reference count for this pin, which we do 162 * whenever a pin is configured as an output. This is a 163 * bitmap so we can do atomic ops on it without an extra 164 * lock so concurrent users of our 4 GPIOs don't stomp on 165 * each other's read-modify-write. 166 * 167 * @pchip: pwm_chip if the PWM is exposed. 168 * @pwm_enabled: Used to track if the PWM signal is currently enabled. 169 * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM. 170 * @pwm_refclk_freq: Cache for the reference clock input to the PWM. 171 */ 172 struct ti_sn65dsi86 { 173 struct auxiliary_device *bridge_aux; 174 struct auxiliary_device *gpio_aux; 175 struct auxiliary_device *aux_aux; 176 struct auxiliary_device *pwm_aux; 177 178 struct device *dev; 179 struct regmap *regmap; 180 struct drm_dp_aux aux; 181 struct drm_bridge bridge; 182 struct drm_connector *connector; 183 struct device_node *host_node; 184 struct mipi_dsi_device *dsi; 185 struct clk *refclk; 186 struct drm_bridge *next_bridge; 187 struct gpio_desc *enable_gpio; 188 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM]; 189 int dp_lanes; 190 u8 ln_assign; 191 u8 ln_polrs; 192 bool comms_enabled; 193 struct mutex comms_mutex; 194 195 #if defined(CONFIG_OF_GPIO) 196 struct gpio_chip gchip; 197 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS); 198 #endif 199 #if IS_REACHABLE(CONFIG_PWM) 200 struct pwm_chip *pchip; 201 bool pwm_enabled; 202 atomic_t pwm_pin_busy; 203 #endif 204 unsigned int pwm_refclk_freq; 205 }; 206 207 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = { 208 { .range_min = 0, .range_max = 0xFF }, 209 }; 210 211 static const struct regmap_access_table ti_sn_bridge_volatile_table = { 212 .yes_ranges = ti_sn65dsi86_volatile_ranges, 213 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges), 214 }; 215 216 static const struct regmap_config ti_sn65dsi86_regmap_config = { 217 .reg_bits = 8, 218 .val_bits = 8, 219 .volatile_table = &ti_sn_bridge_volatile_table, 220 .cache_type = REGCACHE_NONE, 221 .max_register = 0xFF, 222 }; 223 224 static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata, 225 unsigned int reg, u16 *val) 226 { 227 u8 buf[2]; 228 int ret; 229 230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 231 if (ret) 232 return ret; 233 234 *val = buf[0] | (buf[1] << 8); 235 236 return 0; 237 } 238 239 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata, 240 unsigned int reg, u16 val) 241 { 242 u8 buf[2] = { val & 0xff, val >> 8 }; 243 244 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 245 } 246 247 static struct drm_display_mode * 248 get_new_adjusted_display_mode(struct drm_bridge *bridge, 249 struct drm_atomic_state *state) 250 { 251 struct drm_connector *connector = 252 drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 253 struct drm_connector_state *conn_state = 254 drm_atomic_get_new_connector_state(state, connector); 255 struct drm_crtc_state *crtc_state = 256 drm_atomic_get_new_crtc_state(state, conn_state->crtc); 257 258 return &crtc_state->adjusted_mode; 259 } 260 261 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata, 262 struct drm_atomic_state *state) 263 { 264 u32 bit_rate_khz, clk_freq_khz; 265 struct drm_display_mode *mode = 266 get_new_adjusted_display_mode(&pdata->bridge, state); 267 268 bit_rate_khz = mode->clock * 269 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 270 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2); 271 272 return clk_freq_khz; 273 } 274 275 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */ 276 static const u32 ti_sn_bridge_refclk_lut[] = { 277 12000000, 278 19200000, 279 26000000, 280 27000000, 281 38400000, 282 }; 283 284 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */ 285 static const u32 ti_sn_bridge_dsiclk_lut[] = { 286 468000000, 287 384000000, 288 416000000, 289 486000000, 290 460800000, 291 }; 292 293 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata, 294 struct drm_atomic_state *state) 295 { 296 int i; 297 u32 refclk_rate; 298 const u32 *refclk_lut; 299 size_t refclk_lut_size; 300 301 if (pdata->refclk) { 302 refclk_rate = clk_get_rate(pdata->refclk); 303 refclk_lut = ti_sn_bridge_refclk_lut; 304 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut); 305 clk_prepare_enable(pdata->refclk); 306 } else { 307 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata, state) * 1000; 308 refclk_lut = ti_sn_bridge_dsiclk_lut; 309 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut); 310 } 311 312 /* for i equals to refclk_lut_size means default frequency */ 313 for (i = 0; i < refclk_lut_size; i++) 314 if (refclk_lut[i] == refclk_rate) 315 break; 316 317 /* avoid buffer overflow and "1" is the default rate in the datasheet. */ 318 if (i >= refclk_lut_size) 319 i = 1; 320 321 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK, 322 REFCLK_FREQ(i)); 323 324 /* 325 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG, 326 * regardless of its actual sourcing. 327 */ 328 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i]; 329 } 330 331 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata, 332 struct drm_atomic_state *state) 333 { 334 mutex_lock(&pdata->comms_mutex); 335 336 /* configure bridge ref_clk */ 337 ti_sn_bridge_set_refclk_freq(pdata, state); 338 339 /* 340 * HPD on this bridge chip is a bit useless. This is an eDP bridge 341 * so the HPD is an internal signal that's only there to signal that 342 * the panel is done powering up. ...but the bridge chip debounces 343 * this signal by between 100 ms and 400 ms (depending on process, 344 * voltage, and temperate--I measured it at about 200 ms). One 345 * particular panel asserted HPD 84 ms after it was powered on meaning 346 * that we saw HPD 284 ms after power on. ...but the same panel said 347 * that instead of looking at HPD you could just hardcode a delay of 348 * 200 ms. We'll assume that the panel driver will have the hardcoded 349 * delay in its prepare and always disable HPD. 350 * 351 * For DisplayPort bridge type, we need HPD. So we use the bridge type 352 * to conditionally disable HPD. 353 * NOTE: The bridge type is set in ti_sn_bridge_probe() but enable_comms() 354 * can be called before. So for DisplayPort, HPD will be enabled once 355 * bridge type is set. We are using bridge type instead of "no-hpd" 356 * property because it is not used properly in devicetree description 357 * and hence is unreliable. 358 */ 359 360 if (pdata->bridge.type != DRM_MODE_CONNECTOR_DisplayPort) 361 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE, 362 HPD_DISABLE); 363 364 pdata->comms_enabled = true; 365 366 mutex_unlock(&pdata->comms_mutex); 367 } 368 369 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata) 370 { 371 mutex_lock(&pdata->comms_mutex); 372 373 pdata->comms_enabled = false; 374 clk_disable_unprepare(pdata->refclk); 375 376 mutex_unlock(&pdata->comms_mutex); 377 } 378 379 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev) 380 { 381 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 382 int ret; 383 384 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 385 if (ret) { 386 DRM_ERROR("failed to enable supplies %d\n", ret); 387 return ret; 388 } 389 390 /* td2: min 100 us after regulators before enabling the GPIO */ 391 usleep_range(100, 110); 392 393 gpiod_set_value_cansleep(pdata->enable_gpio, 1); 394 395 /* 396 * After EN is deasserted and an external clock is detected, the bridge 397 * will sample GPIO3:1 to determine its frequency. The driver will 398 * overwrite this setting in ti_sn_bridge_set_refclk_freq(). But this is 399 * racy. Thus we have to wait a couple of us. According to the datasheet 400 * the GPIO lines has to be stable at least 5 us (td5) but it seems that 401 * is not enough and the refclk frequency value is still lost or 402 * overwritten by the bridge itself. Waiting for 20us seems to work. 403 */ 404 usleep_range(20, 30); 405 406 /* 407 * If we have a reference clock we can enable communication w/ the 408 * panel (including the aux channel) w/out any need for an input clock 409 * so we can do it in resume which lets us read the EDID before 410 * pre_enable(). Without a reference clock we need the MIPI reference 411 * clock so reading early doesn't work. 412 */ 413 if (pdata->refclk) 414 ti_sn65dsi86_enable_comms(pdata, NULL); 415 416 return ret; 417 } 418 419 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev) 420 { 421 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 422 int ret; 423 424 if (pdata->refclk) 425 ti_sn65dsi86_disable_comms(pdata); 426 427 gpiod_set_value_cansleep(pdata->enable_gpio, 0); 428 429 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 430 if (ret) 431 DRM_ERROR("failed to disable supplies %d\n", ret); 432 433 return ret; 434 } 435 436 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = { 437 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL) 438 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 439 pm_runtime_force_resume) 440 }; 441 442 static int status_show(struct seq_file *s, void *data) 443 { 444 struct ti_sn65dsi86 *pdata = s->private; 445 unsigned int reg, val; 446 447 seq_puts(s, "STATUS REGISTERS:\n"); 448 449 pm_runtime_get_sync(pdata->dev); 450 451 /* IRQ Status Registers, see Table 31 in datasheet */ 452 for (reg = 0xf0; reg <= 0xf8; reg++) { 453 regmap_read(pdata->regmap, reg, &val); 454 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val); 455 } 456 457 pm_runtime_put_autosuspend(pdata->dev); 458 459 return 0; 460 } 461 DEFINE_SHOW_ATTRIBUTE(status); 462 463 /* ----------------------------------------------------------------------------- 464 * Auxiliary Devices (*not* AUX) 465 */ 466 467 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata, 468 struct auxiliary_device **aux_out, 469 const char *name) 470 { 471 struct device *dev = pdata->dev; 472 const struct i2c_client *client = to_i2c_client(dev); 473 struct auxiliary_device *aux; 474 int id; 475 476 id = (client->adapter->nr << 10) | client->addr; 477 aux = __devm_auxiliary_device_create(dev, KBUILD_MODNAME, name, 478 NULL, id); 479 if (!aux) 480 return -ENODEV; 481 482 *aux_out = aux; 483 return 0; 484 } 485 486 /* ----------------------------------------------------------------------------- 487 * AUX Adapter 488 */ 489 490 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux) 491 { 492 return container_of(aux, struct ti_sn65dsi86, aux); 493 } 494 495 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux, 496 struct drm_dp_aux_msg *msg) 497 { 498 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux); 499 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); 500 u32 request_val = AUX_CMD_REQ(msg->request); 501 u8 *buf = msg->buffer; 502 unsigned int len = msg->size; 503 unsigned int short_len; 504 unsigned int val; 505 int ret; 506 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG]; 507 508 if (len > SN_AUX_MAX_PAYLOAD_BYTES) 509 return -EINVAL; 510 511 pm_runtime_get_sync(pdata->dev); 512 mutex_lock(&pdata->comms_mutex); 513 514 /* 515 * If someone tries to do a DDC over AUX transaction before pre_enable() 516 * on a device without a dedicated reference clock then we just can't 517 * do it. Fail right away. This prevents non-refclk users from reading 518 * the EDID before enabling the panel but such is life. 519 */ 520 if (!pdata->comms_enabled) { 521 ret = -EIO; 522 goto exit; 523 } 524 525 switch (request) { 526 case DP_AUX_NATIVE_WRITE: 527 case DP_AUX_I2C_WRITE: 528 case DP_AUX_NATIVE_READ: 529 case DP_AUX_I2C_READ: 530 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val); 531 /* Assume it's good */ 532 msg->reply = 0; 533 break; 534 default: 535 ret = -EINVAL; 536 goto exit; 537 } 538 539 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32)); 540 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len, 541 addr_len); 542 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len, 543 ARRAY_SIZE(addr_len)); 544 545 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) 546 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len); 547 548 /* Clear old status bits before start so we don't get confused */ 549 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG, 550 AUX_IRQ_STATUS_NAT_I2C_FAIL | 551 AUX_IRQ_STATUS_AUX_RPLY_TOUT | 552 AUX_IRQ_STATUS_AUX_SHORT); 553 554 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND); 555 556 /* Zero delay loop because i2c transactions are slow already */ 557 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val, 558 !(val & AUX_CMD_SEND), 0, 50 * 1000); 559 if (ret) 560 goto exit; 561 562 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val); 563 if (ret) 564 goto exit; 565 566 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) { 567 /* 568 * The hardware tried the message seven times per the DP spec 569 * but it hit a timeout. We ignore defers here because they're 570 * handled in hardware. 571 */ 572 ret = -ETIMEDOUT; 573 goto exit; 574 } 575 576 if (val & AUX_IRQ_STATUS_AUX_SHORT) { 577 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &short_len); 578 len = min(len, short_len); 579 if (ret) 580 goto exit; 581 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) { 582 switch (request) { 583 case DP_AUX_I2C_WRITE: 584 case DP_AUX_I2C_READ: 585 msg->reply |= DP_AUX_I2C_REPLY_NACK; 586 break; 587 case DP_AUX_NATIVE_READ: 588 case DP_AUX_NATIVE_WRITE: 589 msg->reply |= DP_AUX_NATIVE_REPLY_NACK; 590 break; 591 } 592 len = 0; 593 goto exit; 594 } 595 596 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0) 597 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len); 598 599 exit: 600 mutex_unlock(&pdata->comms_mutex); 601 pm_runtime_mark_last_busy(pdata->dev); 602 pm_runtime_put_autosuspend(pdata->dev); 603 604 if (ret) 605 return ret; 606 return len; 607 } 608 609 static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us) 610 { 611 /* 612 * The HPD in this chip is a bit useless (See comment in 613 * ti_sn65dsi86_enable_comms) so if our driver is expected to wait 614 * for HPD, we just assume it's asserted after the wait_us delay. 615 * 616 * In case we are asked to wait forever (wait_us=0) take conservative 617 * 500ms delay. 618 */ 619 if (wait_us == 0) 620 wait_us = 500000; 621 622 usleep_range(wait_us, wait_us + 1000); 623 624 return 0; 625 } 626 627 static int ti_sn_aux_probe(struct auxiliary_device *adev, 628 const struct auxiliary_device_id *id) 629 { 630 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 631 int ret; 632 633 pdata->aux.name = "ti-sn65dsi86-aux"; 634 pdata->aux.dev = &adev->dev; 635 pdata->aux.transfer = ti_sn_aux_transfer; 636 pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted; 637 drm_dp_aux_init(&pdata->aux); 638 639 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux); 640 if (ret) 641 return ret; 642 643 /* 644 * The eDP to MIPI bridge parts don't work until the AUX channel is 645 * setup so we don't add it in the main driver probe, we add it now. 646 */ 647 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge"); 648 } 649 650 static const struct auxiliary_device_id ti_sn_aux_id_table[] = { 651 { .name = "ti_sn65dsi86.aux", }, 652 {}, 653 }; 654 655 static struct auxiliary_driver ti_sn_aux_driver = { 656 .name = "aux", 657 .probe = ti_sn_aux_probe, 658 .id_table = ti_sn_aux_id_table, 659 }; 660 661 /*------------------------------------------------------------------------------ 662 * DRM Bridge 663 */ 664 665 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge) 666 { 667 return container_of(bridge, struct ti_sn65dsi86, bridge); 668 } 669 670 static int ti_sn_attach_host(struct auxiliary_device *adev, struct ti_sn65dsi86 *pdata) 671 { 672 int val; 673 struct mipi_dsi_host *host; 674 struct mipi_dsi_device *dsi; 675 struct device *dev = pdata->dev; 676 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge", 677 .channel = 0, 678 .node = NULL, 679 }; 680 681 host = of_find_mipi_dsi_host_by_node(pdata->host_node); 682 if (!host) 683 return -EPROBE_DEFER; 684 685 dsi = devm_mipi_dsi_device_register_full(&adev->dev, host, &info); 686 if (IS_ERR(dsi)) 687 return PTR_ERR(dsi); 688 689 /* TODO: setting to 4 MIPI lanes always for now */ 690 dsi->lanes = 4; 691 dsi->format = MIPI_DSI_FMT_RGB888; 692 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; 693 694 /* check if continuous dsi clock is required or not */ 695 pm_runtime_get_sync(dev); 696 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val); 697 pm_runtime_put_autosuspend(dev); 698 if (!(val & DPPLL_CLK_SRC_DSICLK)) 699 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; 700 701 pdata->dsi = dsi; 702 703 return devm_mipi_dsi_attach(&adev->dev, dsi); 704 } 705 706 static int ti_sn_bridge_attach(struct drm_bridge *bridge, 707 struct drm_encoder *encoder, 708 enum drm_bridge_attach_flags flags) 709 { 710 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 711 int ret; 712 713 pdata->aux.drm_dev = bridge->dev; 714 ret = drm_dp_aux_register(&pdata->aux); 715 if (ret < 0) { 716 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret); 717 return ret; 718 } 719 720 /* 721 * Attach the next bridge. 722 * We never want the next bridge to *also* create a connector. 723 */ 724 ret = drm_bridge_attach(encoder, pdata->next_bridge, 725 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); 726 if (ret < 0) 727 goto err_initted_aux; 728 729 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 730 return 0; 731 732 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev, 733 pdata->bridge.encoder); 734 if (IS_ERR(pdata->connector)) { 735 ret = PTR_ERR(pdata->connector); 736 goto err_initted_aux; 737 } 738 739 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder); 740 741 return 0; 742 743 err_initted_aux: 744 drm_dp_aux_unregister(&pdata->aux); 745 return ret; 746 } 747 748 static void ti_sn_bridge_detach(struct drm_bridge *bridge) 749 { 750 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux); 751 } 752 753 static enum drm_mode_status 754 ti_sn_bridge_mode_valid(struct drm_bridge *bridge, 755 const struct drm_display_info *info, 756 const struct drm_display_mode *mode) 757 { 758 /* maximum supported resolution is 4K at 60 fps */ 759 if (mode->clock > 594000) 760 return MODE_CLOCK_HIGH; 761 762 /* 763 * The front and back porch registers are 8 bits, and pulse width 764 * registers are 15 bits, so reject any modes with larger periods. 765 */ 766 767 if ((mode->hsync_start - mode->hdisplay) > 0xff) 768 return MODE_HBLANK_WIDE; 769 770 if ((mode->vsync_start - mode->vdisplay) > 0xff) 771 return MODE_VBLANK_WIDE; 772 773 if ((mode->hsync_end - mode->hsync_start) > 0x7fff) 774 return MODE_HSYNC_WIDE; 775 776 if ((mode->vsync_end - mode->vsync_start) > 0x7fff) 777 return MODE_VSYNC_WIDE; 778 779 if ((mode->htotal - mode->hsync_end) > 0xff) 780 return MODE_HBLANK_WIDE; 781 782 if ((mode->vtotal - mode->vsync_end) > 0xff) 783 return MODE_VBLANK_WIDE; 784 785 return MODE_OK; 786 } 787 788 static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge, 789 struct drm_atomic_state *state) 790 { 791 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 792 793 /* disable video stream */ 794 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0); 795 } 796 797 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata, 798 struct drm_atomic_state *state) 799 { 800 unsigned int bit_rate_mhz, clk_freq_mhz; 801 unsigned int val; 802 struct drm_display_mode *mode = 803 get_new_adjusted_display_mode(&pdata->bridge, state); 804 805 /* set DSIA clk frequency */ 806 bit_rate_mhz = (mode->clock / 1000) * 807 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 808 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); 809 810 /* for each increment in val, frequency increases by 5MHz */ 811 val = (MIN_DSI_CLK_FREQ_MHZ / 5) + 812 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); 813 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); 814 } 815 816 static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector) 817 { 818 if (connector->display_info.bpc <= 6) 819 return 18; 820 else 821 return 24; 822 } 823 824 /* 825 * LUT index corresponds to register value and 826 * LUT values corresponds to dp data rate supported 827 * by the bridge in Mbps unit. 828 */ 829 static const unsigned int ti_sn_bridge_dp_rate_lut[] = { 830 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 831 }; 832 833 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata, 834 struct drm_atomic_state *state, 835 unsigned int bpp) 836 { 837 unsigned int bit_rate_khz, dp_rate_mhz; 838 unsigned int i; 839 struct drm_display_mode *mode = 840 get_new_adjusted_display_mode(&pdata->bridge, state); 841 842 /* Calculate minimum bit rate based on our pixel clock. */ 843 bit_rate_khz = mode->clock * bpp; 844 845 /* Calculate minimum DP data rate, taking 80% as per DP spec */ 846 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM, 847 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN); 848 849 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) 850 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz) 851 break; 852 853 return i; 854 } 855 856 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata) 857 { 858 unsigned int valid_rates = 0; 859 unsigned int rate_per_200khz; 860 unsigned int rate_mhz; 861 u8 dpcd_val; 862 int ret; 863 int i, j; 864 865 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val); 866 if (ret != 1) { 867 DRM_DEV_ERROR(pdata->dev, 868 "Can't read eDP rev (%d), assuming 1.1\n", ret); 869 dpcd_val = DP_EDP_11; 870 } 871 872 if (dpcd_val >= DP_EDP_14) { 873 /* eDP 1.4 devices must provide a custom table */ 874 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 875 876 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES, 877 sink_rates, sizeof(sink_rates)); 878 879 if (ret != sizeof(sink_rates)) { 880 DRM_DEV_ERROR(pdata->dev, 881 "Can't read supported rate table (%d)\n", ret); 882 883 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */ 884 memset(sink_rates, 0, sizeof(sink_rates)); 885 } 886 887 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 888 rate_per_200khz = le16_to_cpu(sink_rates[i]); 889 890 if (!rate_per_200khz) 891 break; 892 893 rate_mhz = rate_per_200khz * 200 / 1000; 894 for (j = 0; 895 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 896 j++) { 897 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz) 898 valid_rates |= BIT(j); 899 } 900 } 901 902 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) { 903 if (valid_rates & BIT(i)) 904 return valid_rates; 905 } 906 DRM_DEV_ERROR(pdata->dev, 907 "No matching eDP rates in table; falling back\n"); 908 } 909 910 /* On older versions best we can do is use DP_MAX_LINK_RATE */ 911 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val); 912 if (ret != 1) { 913 DRM_DEV_ERROR(pdata->dev, 914 "Can't read max rate (%d); assuming 5.4 GHz\n", 915 ret); 916 dpcd_val = DP_LINK_BW_5_4; 917 } 918 919 switch (dpcd_val) { 920 default: 921 DRM_DEV_ERROR(pdata->dev, 922 "Unexpected max rate (%#x); assuming 5.4 GHz\n", 923 (int)dpcd_val); 924 fallthrough; 925 case DP_LINK_BW_5_4: 926 valid_rates |= BIT(7); 927 fallthrough; 928 case DP_LINK_BW_2_7: 929 valid_rates |= BIT(4); 930 fallthrough; 931 case DP_LINK_BW_1_62: 932 valid_rates |= BIT(1); 933 break; 934 } 935 936 return valid_rates; 937 } 938 939 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata, 940 struct drm_atomic_state *state) 941 { 942 struct drm_display_mode *mode = 943 get_new_adjusted_display_mode(&pdata->bridge, state); 944 u8 hsync_polarity = 0, vsync_polarity = 0; 945 946 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 947 hsync_polarity = CHA_HSYNC_POLARITY; 948 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 949 vsync_polarity = CHA_VSYNC_POLARITY; 950 951 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG, 952 mode->hdisplay); 953 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG, 954 mode->vdisplay); 955 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, 956 (mode->hsync_end - mode->hsync_start) & 0xFF); 957 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, 958 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) | 959 hsync_polarity); 960 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, 961 (mode->vsync_end - mode->vsync_start) & 0xFF); 962 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, 963 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) | 964 vsync_polarity); 965 966 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG, 967 (mode->htotal - mode->hsync_end) & 0xFF); 968 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG, 969 (mode->vtotal - mode->vsync_end) & 0xFF); 970 971 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, 972 (mode->hsync_start - mode->hdisplay) & 0xFF); 973 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG, 974 (mode->vsync_start - mode->vdisplay) & 0xFF); 975 976 usleep_range(10000, 10500); /* 10ms delay recommended by spec */ 977 } 978 979 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata) 980 { 981 u8 data; 982 int ret; 983 984 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); 985 if (ret != 1) { 986 DRM_DEV_ERROR(pdata->dev, 987 "Can't read lane count (%d); assuming 4\n", ret); 988 return 4; 989 } 990 991 return data & DP_LANE_COUNT_MASK; 992 } 993 994 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx, 995 const char **last_err_str) 996 { 997 unsigned int val; 998 int ret; 999 int i; 1000 1001 /* set dp clk frequency value */ 1002 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, 1003 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx)); 1004 1005 /* enable DP PLL */ 1006 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); 1007 1008 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, 1009 val & DPPLL_SRC_DP_PLL_LOCK, 1000, 1010 50 * 1000); 1011 if (ret) { 1012 *last_err_str = "DP_PLL_LOCK polling failed"; 1013 goto exit; 1014 } 1015 1016 /* 1017 * We'll try to link train several times. As part of link training 1018 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If 1019 * the panel isn't ready quite it might respond NAK here which means 1020 * we need to try again. 1021 */ 1022 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) { 1023 /* Semi auto link training mode */ 1024 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); 1025 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, 1026 val == ML_TX_MAIN_LINK_OFF || 1027 val == ML_TX_NORMAL_MODE, 1000, 1028 500 * 1000); 1029 if (ret) { 1030 *last_err_str = "Training complete polling failed"; 1031 } else if (val == ML_TX_MAIN_LINK_OFF) { 1032 *last_err_str = "Link training failed, link is off"; 1033 ret = -EIO; 1034 continue; 1035 } 1036 1037 break; 1038 } 1039 1040 /* If we saw quite a few retries, add a note about it */ 1041 if (!ret && i > SN_LINK_TRAINING_TRIES / 2) 1042 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i); 1043 1044 exit: 1045 /* Disable the PLL if we failed */ 1046 if (ret) 1047 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1048 1049 return ret; 1050 } 1051 1052 static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge, 1053 struct drm_atomic_state *state) 1054 { 1055 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1056 struct drm_connector *connector; 1057 const char *last_err_str = "No supported DP rate"; 1058 unsigned int valid_rates; 1059 int dp_rate_idx; 1060 unsigned int val; 1061 int ret = -EINVAL; 1062 int max_dp_lanes; 1063 unsigned int bpp; 1064 1065 connector = drm_atomic_get_new_connector_for_encoder(state, 1066 bridge->encoder); 1067 if (!connector) { 1068 dev_err_ratelimited(pdata->dev, "Could not get the connector\n"); 1069 return; 1070 } 1071 1072 max_dp_lanes = ti_sn_get_max_lanes(pdata); 1073 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes); 1074 1075 /* DSI_A lane config */ 1076 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes); 1077 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, 1078 CHA_DSI_LANES_MASK, val); 1079 1080 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign); 1081 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK, 1082 pdata->ln_polrs << LN_POLRS_OFFSET); 1083 1084 /* set dsi clk frequency value */ 1085 ti_sn_bridge_set_dsi_rate(pdata, state); 1086 1087 /* 1088 * The SN65DSI86 only supports ASSR Display Authentication method and 1089 * this method is enabled for eDP panels. An eDP panel must support this 1090 * authentication method. We need to enable this method in the eDP panel 1091 * at DisplayPort address 0x0010A prior to link training. 1092 * 1093 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays 1094 * we need to disable the scrambler. 1095 */ 1096 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) { 1097 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, 1098 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); 1099 1100 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1101 SCRAMBLE_DISABLE, 0); 1102 } else { 1103 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1104 SCRAMBLE_DISABLE, SCRAMBLE_DISABLE); 1105 } 1106 1107 bpp = ti_sn_bridge_get_bpp(connector); 1108 /* Set the DP output format (18 bpp or 24 bpp) */ 1109 val = bpp == 18 ? BPP_18_RGB : 0; 1110 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); 1111 1112 /* DP lane config */ 1113 val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); 1114 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 1115 val); 1116 1117 valid_rates = ti_sn_bridge_read_valid_rates(pdata); 1118 1119 /* Train until we run out of rates */ 1120 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, state, bpp); 1121 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 1122 dp_rate_idx++) { 1123 if (!(valid_rates & BIT(dp_rate_idx))) 1124 continue; 1125 1126 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str); 1127 if (!ret) 1128 break; 1129 } 1130 if (ret) { 1131 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret); 1132 return; 1133 } 1134 1135 /* config video parameters */ 1136 ti_sn_bridge_set_video_timings(pdata, state); 1137 1138 /* enable video stream */ 1139 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 1140 VSTREAM_ENABLE); 1141 } 1142 1143 static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge, 1144 struct drm_atomic_state *state) 1145 { 1146 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1147 1148 pm_runtime_get_sync(pdata->dev); 1149 1150 if (!pdata->refclk) 1151 ti_sn65dsi86_enable_comms(pdata, state); 1152 1153 /* td7: min 100 us after enable before DSI data */ 1154 usleep_range(100, 110); 1155 } 1156 1157 static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge, 1158 struct drm_atomic_state *state) 1159 { 1160 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1161 1162 /* semi auto link training mode OFF */ 1163 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); 1164 /* Num lanes to 0 as per power sequencing in data sheet */ 1165 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0); 1166 /* disable DP PLL */ 1167 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1168 1169 if (!pdata->refclk) 1170 ti_sn65dsi86_disable_comms(pdata); 1171 1172 pm_runtime_put_sync(pdata->dev); 1173 } 1174 1175 static enum drm_connector_status 1176 ti_sn_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 1177 { 1178 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1179 int val = 0; 1180 1181 /* 1182 * Runtime reference is grabbed in ti_sn_bridge_hpd_enable() 1183 * as the chip won't report HPD just after being powered on. 1184 * HPD_DEBOUNCED_STATE reflects correct state only after the 1185 * debounce time (~100-400 ms). 1186 */ 1187 1188 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val); 1189 1190 return val & HPD_DEBOUNCED_STATE ? connector_status_connected 1191 : connector_status_disconnected; 1192 } 1193 1194 static const struct drm_edid *ti_sn_bridge_edid_read(struct drm_bridge *bridge, 1195 struct drm_connector *connector) 1196 { 1197 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1198 1199 return drm_edid_read_ddc(connector, &pdata->aux.ddc); 1200 } 1201 1202 static void ti_sn65dsi86_debugfs_init(struct drm_bridge *bridge, struct dentry *root) 1203 { 1204 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1205 struct dentry *debugfs; 1206 1207 debugfs = debugfs_create_dir(dev_name(pdata->dev), root); 1208 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops); 1209 } 1210 1211 static void ti_sn_bridge_hpd_enable(struct drm_bridge *bridge) 1212 { 1213 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1214 1215 /* 1216 * Device needs to be powered on before reading the HPD state 1217 * for reliable hpd detection in ti_sn_bridge_detect() due to 1218 * the high debounce time. 1219 */ 1220 1221 pm_runtime_get_sync(pdata->dev); 1222 } 1223 1224 static void ti_sn_bridge_hpd_disable(struct drm_bridge *bridge) 1225 { 1226 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1227 1228 pm_runtime_put_autosuspend(pdata->dev); 1229 } 1230 1231 static const struct drm_bridge_funcs ti_sn_bridge_funcs = { 1232 .attach = ti_sn_bridge_attach, 1233 .detach = ti_sn_bridge_detach, 1234 .mode_valid = ti_sn_bridge_mode_valid, 1235 .edid_read = ti_sn_bridge_edid_read, 1236 .detect = ti_sn_bridge_detect, 1237 .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable, 1238 .atomic_enable = ti_sn_bridge_atomic_enable, 1239 .atomic_disable = ti_sn_bridge_atomic_disable, 1240 .atomic_post_disable = ti_sn_bridge_atomic_post_disable, 1241 .atomic_reset = drm_atomic_helper_bridge_reset, 1242 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1243 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1244 .debugfs_init = ti_sn65dsi86_debugfs_init, 1245 .hpd_enable = ti_sn_bridge_hpd_enable, 1246 .hpd_disable = ti_sn_bridge_hpd_disable, 1247 }; 1248 1249 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata, 1250 struct device_node *np) 1251 { 1252 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 }; 1253 u32 lane_polarities[SN_MAX_DP_LANES] = { }; 1254 struct device_node *endpoint; 1255 u8 ln_assign = 0; 1256 u8 ln_polrs = 0; 1257 int dp_lanes; 1258 int i; 1259 1260 /* 1261 * Read config from the device tree about lane remapping and lane 1262 * polarities. These are optional and we assume identity map and 1263 * normal polarity if nothing is specified. It's OK to specify just 1264 * data-lanes but not lane-polarities but not vice versa. 1265 * 1266 * Error checking is light (we just make sure we don't crash or 1267 * buffer overrun) and we assume dts is well formed and specifying 1268 * mappings that the hardware supports. 1269 */ 1270 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1271 dp_lanes = drm_of_get_data_lanes_count(endpoint, 1, SN_MAX_DP_LANES); 1272 if (dp_lanes > 0) { 1273 of_property_read_u32_array(endpoint, "data-lanes", 1274 lane_assignments, dp_lanes); 1275 of_property_read_u32_array(endpoint, "lane-polarities", 1276 lane_polarities, dp_lanes); 1277 } else { 1278 dp_lanes = SN_MAX_DP_LANES; 1279 } 1280 of_node_put(endpoint); 1281 1282 /* 1283 * Convert into register format. Loop over all lanes even if 1284 * data-lanes had fewer elements so that we nicely initialize 1285 * the LN_ASSIGN register. 1286 */ 1287 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) { 1288 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i]; 1289 ln_polrs = ln_polrs << 1 | lane_polarities[i]; 1290 } 1291 1292 /* Stash in our struct for when we power on */ 1293 pdata->dp_lanes = dp_lanes; 1294 pdata->ln_assign = ln_assign; 1295 pdata->ln_polrs = ln_polrs; 1296 } 1297 1298 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata) 1299 { 1300 struct device_node *np = pdata->dev->of_node; 1301 1302 pdata->host_node = of_graph_get_remote_node(np, 0, 0); 1303 1304 if (!pdata->host_node) { 1305 DRM_ERROR("remote dsi host node not found\n"); 1306 return -ENODEV; 1307 } 1308 1309 return 0; 1310 } 1311 1312 static int ti_sn_bridge_probe(struct auxiliary_device *adev, 1313 const struct auxiliary_device_id *id) 1314 { 1315 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1316 struct device_node *np = pdata->dev->of_node; 1317 int ret; 1318 1319 pdata->next_bridge = devm_drm_of_get_bridge(&adev->dev, np, 1, 0); 1320 if (IS_ERR(pdata->next_bridge)) 1321 return dev_err_probe(&adev->dev, PTR_ERR(pdata->next_bridge), 1322 "failed to create panel bridge\n"); 1323 1324 ti_sn_bridge_parse_lanes(pdata, np); 1325 1326 ret = ti_sn_bridge_parse_dsi_host(pdata); 1327 if (ret) 1328 return ret; 1329 1330 pdata->bridge.of_node = np; 1331 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort 1332 ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP; 1333 1334 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) { 1335 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT | 1336 DRM_BRIDGE_OP_HPD; 1337 /* 1338 * If comms were already enabled they would have been enabled 1339 * with the wrong value of HPD_DISABLE. Update it now. Comms 1340 * could be enabled if anyone is holding a pm_runtime reference 1341 * (like if a GPIO is in use). Note that in most cases nobody 1342 * is doing AUX channel xfers before the bridge is added so 1343 * HPD doesn't _really_ matter then. The only exception is in 1344 * the eDP case where the panel wants to read the EDID before 1345 * the bridge is added. We always consistently have HPD disabled 1346 * for eDP. 1347 */ 1348 mutex_lock(&pdata->comms_mutex); 1349 if (pdata->comms_enabled) 1350 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, 1351 HPD_DISABLE, 0); 1352 mutex_unlock(&pdata->comms_mutex); 1353 } 1354 1355 drm_bridge_add(&pdata->bridge); 1356 1357 ret = ti_sn_attach_host(adev, pdata); 1358 if (ret) { 1359 dev_err_probe(&adev->dev, ret, "failed to attach dsi host\n"); 1360 goto err_remove_bridge; 1361 } 1362 1363 return 0; 1364 1365 err_remove_bridge: 1366 drm_bridge_remove(&pdata->bridge); 1367 return ret; 1368 } 1369 1370 static void ti_sn_bridge_remove(struct auxiliary_device *adev) 1371 { 1372 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1373 1374 if (!pdata) 1375 return; 1376 1377 drm_bridge_remove(&pdata->bridge); 1378 1379 of_node_put(pdata->host_node); 1380 } 1381 1382 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = { 1383 { .name = "ti_sn65dsi86.bridge", }, 1384 {}, 1385 }; 1386 1387 static struct auxiliary_driver ti_sn_bridge_driver = { 1388 .name = "bridge", 1389 .probe = ti_sn_bridge_probe, 1390 .remove = ti_sn_bridge_remove, 1391 .id_table = ti_sn_bridge_id_table, 1392 }; 1393 1394 /* ----------------------------------------------------------------------------- 1395 * PWM Controller 1396 */ 1397 #if IS_REACHABLE(CONFIG_PWM) 1398 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) 1399 { 1400 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0; 1401 } 1402 1403 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) 1404 { 1405 atomic_set(&pdata->pwm_pin_busy, 0); 1406 } 1407 1408 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip) 1409 { 1410 return pwmchip_get_drvdata(chip); 1411 } 1412 1413 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 1414 { 1415 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1416 1417 return ti_sn_pwm_pin_request(pdata); 1418 } 1419 1420 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 1421 { 1422 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1423 1424 ti_sn_pwm_pin_release(pdata); 1425 } 1426 1427 /* 1428 * Limitations: 1429 * - The PWM signal is not driven when the chip is powered down, or in its 1430 * reset state and the driver does not implement the "suspend state" 1431 * described in the documentation. In order to save power, state->enabled is 1432 * interpreted as denoting if the signal is expected to be valid, and is used 1433 * to determine if the chip needs to be kept powered. 1434 * - Changing both period and duty_cycle is not done atomically, neither is the 1435 * multi-byte register updates, so the output might briefly be undefined 1436 * during update. 1437 */ 1438 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 1439 const struct pwm_state *state) 1440 { 1441 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1442 unsigned int pwm_en_inv; 1443 unsigned int backlight; 1444 unsigned int pre_div; 1445 unsigned int scale; 1446 u64 period_max; 1447 u64 period; 1448 int ret; 1449 1450 if (!pdata->pwm_enabled) { 1451 ret = pm_runtime_resume_and_get(pwmchip_parent(chip)); 1452 if (ret < 0) 1453 return ret; 1454 } 1455 1456 if (state->enabled) { 1457 if (!pdata->pwm_enabled) { 1458 /* 1459 * The chip might have been powered down while we 1460 * didn't hold a PM runtime reference, so mux in the 1461 * PWM function on the GPIO pin again. 1462 */ 1463 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1464 SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX), 1465 SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX)); 1466 if (ret) { 1467 dev_err(pwmchip_parent(chip), "failed to mux in PWM function\n"); 1468 goto out; 1469 } 1470 } 1471 1472 /* 1473 * Per the datasheet the PWM frequency is given by: 1474 * 1475 * REFCLK_FREQ 1476 * PWM_FREQ = ----------------------------------- 1477 * PWM_PRE_DIV * BACKLIGHT_SCALE + 1 1478 * 1479 * However, after careful review the author is convinced that 1480 * the documentation has lost some parenthesis around 1481 * "BACKLIGHT_SCALE + 1". 1482 * 1483 * With the period T_pwm = 1/PWM_FREQ this can be written: 1484 * 1485 * T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1) 1486 * 1487 * In order to keep BACKLIGHT_SCALE within its 16 bits, 1488 * PWM_PRE_DIV must be: 1489 * 1490 * T_pwm * REFCLK_FREQ 1491 * PWM_PRE_DIV >= ------------------------- 1492 * BACKLIGHT_SCALE_MAX + 1 1493 * 1494 * To simplify the search and to favour higher resolution of 1495 * the duty cycle over accuracy of the period, the lowest 1496 * possible PWM_PRE_DIV is used. Finally the scale is 1497 * calculated as: 1498 * 1499 * T_pwm * REFCLK_FREQ 1500 * BACKLIGHT_SCALE = ---------------------- - 1 1501 * PWM_PRE_DIV 1502 * 1503 * Here T_pwm is represented in seconds, so appropriate scaling 1504 * to nanoseconds is necessary. 1505 */ 1506 1507 /* Minimum T_pwm is 1 / REFCLK_FREQ */ 1508 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) { 1509 ret = -EINVAL; 1510 goto out; 1511 } 1512 1513 /* 1514 * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ 1515 * Limit period to this to avoid overflows 1516 */ 1517 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1), 1518 pdata->pwm_refclk_freq); 1519 period = min(state->period, period_max); 1520 1521 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq, 1522 (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1)); 1523 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1; 1524 1525 /* 1526 * The documentation has the duty ratio given as: 1527 * 1528 * duty BACKLIGHT 1529 * ------- = --------------------- 1530 * period BACKLIGHT_SCALE + 1 1531 * 1532 * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according 1533 * to definition above and adjusting for nanosecond 1534 * representation of duty cycle gives us: 1535 */ 1536 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq, 1537 (u64)NSEC_PER_SEC * pre_div); 1538 if (backlight > scale) 1539 backlight = scale; 1540 1541 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div); 1542 if (ret) { 1543 dev_err(pwmchip_parent(chip), "failed to update PWM_PRE_DIV\n"); 1544 goto out; 1545 } 1546 1547 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale); 1548 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight); 1549 } 1550 1551 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) | 1552 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED); 1553 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv); 1554 if (ret) { 1555 dev_err(pwmchip_parent(chip), "failed to update PWM_EN/PWM_INV\n"); 1556 goto out; 1557 } 1558 1559 pdata->pwm_enabled = state->enabled; 1560 out: 1561 1562 if (!pdata->pwm_enabled) 1563 pm_runtime_put_sync(pwmchip_parent(chip)); 1564 1565 return ret; 1566 } 1567 1568 static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 1569 struct pwm_state *state) 1570 { 1571 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1572 unsigned int pwm_en_inv; 1573 unsigned int pre_div; 1574 u16 backlight; 1575 u16 scale; 1576 int ret; 1577 1578 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv); 1579 if (ret) 1580 return ret; 1581 1582 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale); 1583 if (ret) 1584 return ret; 1585 1586 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight); 1587 if (ret) 1588 return ret; 1589 1590 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div); 1591 if (ret) 1592 return ret; 1593 1594 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv); 1595 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv)) 1596 state->polarity = PWM_POLARITY_INVERSED; 1597 else 1598 state->polarity = PWM_POLARITY_NORMAL; 1599 1600 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1), 1601 pdata->pwm_refclk_freq); 1602 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight, 1603 pdata->pwm_refclk_freq); 1604 1605 if (state->duty_cycle > state->period) 1606 state->duty_cycle = state->period; 1607 1608 return 0; 1609 } 1610 1611 static const struct pwm_ops ti_sn_pwm_ops = { 1612 .request = ti_sn_pwm_request, 1613 .free = ti_sn_pwm_free, 1614 .apply = ti_sn_pwm_apply, 1615 .get_state = ti_sn_pwm_get_state, 1616 }; 1617 1618 static int ti_sn_pwm_probe(struct auxiliary_device *adev, 1619 const struct auxiliary_device_id *id) 1620 { 1621 struct pwm_chip *chip; 1622 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1623 1624 pdata->pchip = chip = devm_pwmchip_alloc(&adev->dev, 1, 0); 1625 if (IS_ERR(chip)) 1626 return PTR_ERR(chip); 1627 1628 pwmchip_set_drvdata(chip, pdata); 1629 1630 chip->ops = &ti_sn_pwm_ops; 1631 chip->of_xlate = of_pwm_single_xlate; 1632 1633 devm_pm_runtime_enable(&adev->dev); 1634 1635 return pwmchip_add(chip); 1636 } 1637 1638 static void ti_sn_pwm_remove(struct auxiliary_device *adev) 1639 { 1640 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1641 1642 pwmchip_remove(pdata->pchip); 1643 1644 if (pdata->pwm_enabled) 1645 pm_runtime_put_sync(&adev->dev); 1646 } 1647 1648 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = { 1649 { .name = "ti_sn65dsi86.pwm", }, 1650 {}, 1651 }; 1652 1653 static struct auxiliary_driver ti_sn_pwm_driver = { 1654 .name = "pwm", 1655 .probe = ti_sn_pwm_probe, 1656 .remove = ti_sn_pwm_remove, 1657 .id_table = ti_sn_pwm_id_table, 1658 }; 1659 1660 static int __init ti_sn_pwm_register(void) 1661 { 1662 return auxiliary_driver_register(&ti_sn_pwm_driver); 1663 } 1664 1665 static void ti_sn_pwm_unregister(void) 1666 { 1667 auxiliary_driver_unregister(&ti_sn_pwm_driver); 1668 } 1669 1670 #else 1671 static inline int __maybe_unused ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; } 1672 static inline void __maybe_unused ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {} 1673 1674 static inline int ti_sn_pwm_register(void) { return 0; } 1675 static inline void ti_sn_pwm_unregister(void) {} 1676 #endif 1677 1678 /* ----------------------------------------------------------------------------- 1679 * GPIO Controller 1680 */ 1681 #if defined(CONFIG_OF_GPIO) 1682 1683 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip, 1684 const struct of_phandle_args *gpiospec, 1685 u32 *flags) 1686 { 1687 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells)) 1688 return -EINVAL; 1689 1690 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1) 1691 return -EINVAL; 1692 1693 if (flags) 1694 *flags = gpiospec->args[1]; 1695 1696 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET; 1697 } 1698 1699 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip, 1700 unsigned int offset) 1701 { 1702 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1703 1704 /* 1705 * We already have to keep track of the direction because we use 1706 * that to figure out whether we've powered the device. We can 1707 * just return that rather than (maybe) powering up the device 1708 * to ask its direction. 1709 */ 1710 return test_bit(offset, pdata->gchip_output) ? 1711 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1712 } 1713 1714 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset) 1715 { 1716 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1717 unsigned int val; 1718 int ret; 1719 1720 /* 1721 * When the pin is an input we don't forcibly keep the bridge 1722 * powered--we just power it on to read the pin. NOTE: part of 1723 * the reason this works is that the bridge defaults (when 1724 * powered back on) to all 4 GPIOs being configured as GPIO input. 1725 * Also note that if something else is keeping the chip powered the 1726 * pm_runtime functions are lightweight increments of a refcount. 1727 */ 1728 pm_runtime_get_sync(pdata->dev); 1729 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val); 1730 pm_runtime_put_autosuspend(pdata->dev); 1731 1732 if (ret) 1733 return ret; 1734 1735 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset)); 1736 } 1737 1738 static int ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, 1739 int val) 1740 { 1741 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1742 1743 val &= 1; 1744 return regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, 1745 BIT(SN_GPIO_OUTPUT_SHIFT + offset), 1746 val << (SN_GPIO_OUTPUT_SHIFT + offset)); 1747 } 1748 1749 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip, 1750 unsigned int offset) 1751 { 1752 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1753 int shift = offset * 2; 1754 int ret; 1755 1756 if (!test_and_clear_bit(offset, pdata->gchip_output)) 1757 return 0; 1758 1759 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1760 SN_GPIO_MUX_MASK << shift, 1761 SN_GPIO_MUX_INPUT << shift); 1762 if (ret) { 1763 set_bit(offset, pdata->gchip_output); 1764 return ret; 1765 } 1766 1767 /* 1768 * NOTE: if nobody else is powering the device this may fully power 1769 * it off and when it comes back it will have lost all state, but 1770 * that's OK because the default is input and we're now an input. 1771 */ 1772 pm_runtime_put_autosuspend(pdata->dev); 1773 1774 return 0; 1775 } 1776 1777 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, 1778 unsigned int offset, int val) 1779 { 1780 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1781 int shift = offset * 2; 1782 int ret; 1783 1784 if (test_and_set_bit(offset, pdata->gchip_output)) 1785 return 0; 1786 1787 pm_runtime_get_sync(pdata->dev); 1788 1789 /* Set value first to avoid glitching */ 1790 ti_sn_bridge_gpio_set(chip, offset, val); 1791 1792 /* Set direction */ 1793 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1794 SN_GPIO_MUX_MASK << shift, 1795 SN_GPIO_MUX_OUTPUT << shift); 1796 if (ret) { 1797 clear_bit(offset, pdata->gchip_output); 1798 pm_runtime_put_autosuspend(pdata->dev); 1799 } 1800 1801 return ret; 1802 } 1803 1804 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset) 1805 { 1806 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1807 1808 if (offset == SN_PWM_GPIO_IDX) 1809 return ti_sn_pwm_pin_request(pdata); 1810 1811 return 0; 1812 } 1813 1814 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset) 1815 { 1816 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1817 1818 /* We won't keep pm_runtime if we're input, so switch there on free */ 1819 ti_sn_bridge_gpio_direction_input(chip, offset); 1820 1821 if (offset == SN_PWM_GPIO_IDX) 1822 ti_sn_pwm_pin_release(pdata); 1823 } 1824 1825 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = { 1826 "GPIO1", "GPIO2", "GPIO3", "GPIO4" 1827 }; 1828 1829 static int ti_sn_gpio_probe(struct auxiliary_device *adev, 1830 const struct auxiliary_device_id *id) 1831 { 1832 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1833 int ret; 1834 1835 /* Only init if someone is going to use us as a GPIO controller */ 1836 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller")) 1837 return 0; 1838 1839 pdata->gchip.label = dev_name(pdata->dev); 1840 pdata->gchip.parent = pdata->dev; 1841 pdata->gchip.owner = THIS_MODULE; 1842 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate; 1843 pdata->gchip.of_gpio_n_cells = 2; 1844 pdata->gchip.request = ti_sn_bridge_gpio_request; 1845 pdata->gchip.free = ti_sn_bridge_gpio_free; 1846 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction; 1847 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input; 1848 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output; 1849 pdata->gchip.get = ti_sn_bridge_gpio_get; 1850 pdata->gchip.set = ti_sn_bridge_gpio_set; 1851 pdata->gchip.can_sleep = true; 1852 pdata->gchip.names = ti_sn_bridge_gpio_names; 1853 pdata->gchip.ngpio = SN_NUM_GPIOS; 1854 pdata->gchip.base = -1; 1855 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata); 1856 if (ret) 1857 dev_err(pdata->dev, "can't add gpio chip\n"); 1858 1859 return ret; 1860 } 1861 1862 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = { 1863 { .name = "ti_sn65dsi86.gpio", }, 1864 {}, 1865 }; 1866 1867 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table); 1868 1869 static struct auxiliary_driver ti_sn_gpio_driver = { 1870 .name = "gpio", 1871 .probe = ti_sn_gpio_probe, 1872 .id_table = ti_sn_gpio_id_table, 1873 }; 1874 1875 static int __init ti_sn_gpio_register(void) 1876 { 1877 return auxiliary_driver_register(&ti_sn_gpio_driver); 1878 } 1879 1880 static void ti_sn_gpio_unregister(void) 1881 { 1882 auxiliary_driver_unregister(&ti_sn_gpio_driver); 1883 } 1884 1885 #else 1886 1887 static inline int ti_sn_gpio_register(void) { return 0; } 1888 static inline void ti_sn_gpio_unregister(void) {} 1889 1890 #endif 1891 1892 /* ----------------------------------------------------------------------------- 1893 * Probe & Remove 1894 */ 1895 1896 static void ti_sn65dsi86_runtime_disable(void *data) 1897 { 1898 pm_runtime_dont_use_autosuspend(data); 1899 pm_runtime_disable(data); 1900 } 1901 1902 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata) 1903 { 1904 unsigned int i; 1905 const char * const ti_sn_bridge_supply_names[] = { 1906 "vcca", "vcc", "vccio", "vpll", 1907 }; 1908 1909 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++) 1910 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i]; 1911 1912 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM, 1913 pdata->supplies); 1914 } 1915 1916 static int ti_sn65dsi86_probe(struct i2c_client *client) 1917 { 1918 struct device *dev = &client->dev; 1919 struct ti_sn65dsi86 *pdata; 1920 u8 id_buf[8]; 1921 int ret; 1922 1923 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1924 DRM_ERROR("device doesn't support I2C\n"); 1925 return -ENODEV; 1926 } 1927 1928 pdata = devm_drm_bridge_alloc(dev, struct ti_sn65dsi86, bridge, &ti_sn_bridge_funcs); 1929 if (IS_ERR(pdata)) 1930 return PTR_ERR(pdata); 1931 dev_set_drvdata(dev, pdata); 1932 pdata->dev = dev; 1933 1934 mutex_init(&pdata->comms_mutex); 1935 1936 pdata->regmap = devm_regmap_init_i2c(client, 1937 &ti_sn65dsi86_regmap_config); 1938 if (IS_ERR(pdata->regmap)) 1939 return dev_err_probe(dev, PTR_ERR(pdata->regmap), 1940 "regmap i2c init failed\n"); 1941 1942 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable", 1943 GPIOD_OUT_LOW); 1944 if (IS_ERR(pdata->enable_gpio)) 1945 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio), 1946 "failed to get enable gpio from DT\n"); 1947 1948 ret = ti_sn65dsi86_parse_regulators(pdata); 1949 if (ret) 1950 return dev_err_probe(dev, ret, "failed to parse regulators\n"); 1951 1952 pdata->refclk = devm_clk_get_optional(dev, "refclk"); 1953 if (IS_ERR(pdata->refclk)) 1954 return dev_err_probe(dev, PTR_ERR(pdata->refclk), 1955 "failed to get reference clock\n"); 1956 1957 pm_runtime_enable(dev); 1958 pm_runtime_set_autosuspend_delay(pdata->dev, 500); 1959 pm_runtime_use_autosuspend(pdata->dev); 1960 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev); 1961 if (ret) 1962 return ret; 1963 1964 pm_runtime_get_sync(dev); 1965 ret = regmap_bulk_read(pdata->regmap, SN_DEVICE_ID_REGS, id_buf, ARRAY_SIZE(id_buf)); 1966 pm_runtime_put_autosuspend(dev); 1967 if (ret) 1968 return dev_err_probe(dev, ret, "failed to read device id\n"); 1969 1970 /* The ID string is stored backwards */ 1971 if (strncmp(id_buf, "68ISD ", ARRAY_SIZE(id_buf))) 1972 return dev_err_probe(dev, -EOPNOTSUPP, "unsupported device id\n"); 1973 1974 /* 1975 * Break ourselves up into a collection of aux devices. The only real 1976 * motiviation here is to solve the chicken-and-egg problem of probe 1977 * ordering. The bridge wants the panel to be there when it probes. 1978 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards) 1979 * when it probes. The panel and maybe backlight might want the DDC 1980 * bus or the pwm_chip. Having sub-devices allows the some sub devices 1981 * to finish probing even if others return -EPROBE_DEFER and gets us 1982 * around the problems. 1983 */ 1984 1985 if (IS_ENABLED(CONFIG_OF_GPIO)) { 1986 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio"); 1987 if (ret) 1988 return ret; 1989 } 1990 1991 if (IS_REACHABLE(CONFIG_PWM)) { 1992 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm"); 1993 if (ret) 1994 return ret; 1995 } 1996 1997 /* 1998 * NOTE: At the end of the AUX channel probe we'll add the aux device 1999 * for the bridge. This is because the bridge can't be used until the 2000 * AUX channel is there and this is a very simple solution to the 2001 * dependency problem. 2002 */ 2003 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux"); 2004 } 2005 2006 static const struct i2c_device_id ti_sn65dsi86_id[] = { 2007 { "ti,sn65dsi86" }, 2008 {} 2009 }; 2010 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id); 2011 2012 static const struct of_device_id ti_sn65dsi86_match_table[] = { 2013 {.compatible = "ti,sn65dsi86"}, 2014 {}, 2015 }; 2016 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table); 2017 2018 static struct i2c_driver ti_sn65dsi86_driver = { 2019 .driver = { 2020 .name = "ti_sn65dsi86", 2021 .of_match_table = ti_sn65dsi86_match_table, 2022 .pm = &ti_sn65dsi86_pm_ops, 2023 }, 2024 .probe = ti_sn65dsi86_probe, 2025 .id_table = ti_sn65dsi86_id, 2026 }; 2027 2028 static int __init ti_sn65dsi86_init(void) 2029 { 2030 int ret; 2031 2032 ret = i2c_add_driver(&ti_sn65dsi86_driver); 2033 if (ret) 2034 return ret; 2035 2036 ret = ti_sn_gpio_register(); 2037 if (ret) 2038 goto err_main_was_registered; 2039 2040 ret = ti_sn_pwm_register(); 2041 if (ret) 2042 goto err_gpio_was_registered; 2043 2044 ret = auxiliary_driver_register(&ti_sn_aux_driver); 2045 if (ret) 2046 goto err_pwm_was_registered; 2047 2048 ret = auxiliary_driver_register(&ti_sn_bridge_driver); 2049 if (ret) 2050 goto err_aux_was_registered; 2051 2052 return 0; 2053 2054 err_aux_was_registered: 2055 auxiliary_driver_unregister(&ti_sn_aux_driver); 2056 err_pwm_was_registered: 2057 ti_sn_pwm_unregister(); 2058 err_gpio_was_registered: 2059 ti_sn_gpio_unregister(); 2060 err_main_was_registered: 2061 i2c_del_driver(&ti_sn65dsi86_driver); 2062 2063 return ret; 2064 } 2065 module_init(ti_sn65dsi86_init); 2066 2067 static void __exit ti_sn65dsi86_exit(void) 2068 { 2069 auxiliary_driver_unregister(&ti_sn_bridge_driver); 2070 auxiliary_driver_unregister(&ti_sn_aux_driver); 2071 ti_sn_pwm_unregister(); 2072 ti_sn_gpio_unregister(); 2073 i2c_del_driver(&ti_sn65dsi86_driver); 2074 } 2075 module_exit(ti_sn65dsi86_exit); 2076 2077 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>"); 2078 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver"); 2079 MODULE_LICENSE("GPL v2"); 2080