1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018, The Linux Foundation. All rights reserved. 4 * datasheet: https://www.ti.com/lit/ds/symlink/sn65dsi86.pdf 5 */ 6 7 #include <linux/atomic.h> 8 #include <linux/auxiliary_bus.h> 9 #include <linux/bitfield.h> 10 #include <linux/bits.h> 11 #include <linux/clk.h> 12 #include <linux/debugfs.h> 13 #include <linux/gpio/consumer.h> 14 #include <linux/gpio/driver.h> 15 #include <linux/i2c.h> 16 #include <linux/iopoll.h> 17 #include <linux/module.h> 18 #include <linux/of_graph.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/pwm.h> 21 #include <linux/regmap.h> 22 #include <linux/regulator/consumer.h> 23 24 #include <linux/unaligned.h> 25 26 #include <drm/display/drm_dp_aux_bus.h> 27 #include <drm/display/drm_dp_helper.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_bridge.h> 31 #include <drm/drm_bridge_connector.h> 32 #include <drm/drm_edid.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_of.h> 35 #include <drm/drm_print.h> 36 #include <drm/drm_probe_helper.h> 37 38 #define SN_DEVICE_ID_REGS 0x00 /* up to 0x07 */ 39 #define SN_DEVICE_REV_REG 0x08 40 #define SN_DPPLL_SRC_REG 0x0A 41 #define DPPLL_CLK_SRC_DSICLK BIT(0) 42 #define REFCLK_FREQ_MASK GENMASK(3, 1) 43 #define REFCLK_FREQ(x) ((x) << 1) 44 #define DPPLL_SRC_DP_PLL_LOCK BIT(7) 45 #define SN_PLL_ENABLE_REG 0x0D 46 #define SN_DSI_LANES_REG 0x10 47 #define CHA_DSI_LANES_MASK GENMASK(4, 3) 48 #define CHA_DSI_LANES(x) ((x) << 3) 49 #define SN_DSIA_CLK_FREQ_REG 0x12 50 #define SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG 0x20 51 #define SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG 0x24 52 #define SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG 0x2C 53 #define SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG 0x2D 54 #define CHA_HSYNC_POLARITY BIT(7) 55 #define SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG 0x30 56 #define SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG 0x31 57 #define CHA_VSYNC_POLARITY BIT(7) 58 #define SN_CHA_HORIZONTAL_BACK_PORCH_REG 0x34 59 #define SN_CHA_VERTICAL_BACK_PORCH_REG 0x36 60 #define SN_CHA_HORIZONTAL_FRONT_PORCH_REG 0x38 61 #define SN_CHA_VERTICAL_FRONT_PORCH_REG 0x3A 62 #define SN_LN_ASSIGN_REG 0x59 63 #define LN_ASSIGN_WIDTH 2 64 #define SN_ENH_FRAME_REG 0x5A 65 #define VSTREAM_ENABLE BIT(3) 66 #define LN_POLRS_OFFSET 4 67 #define LN_POLRS_MASK 0xf0 68 #define SN_DATA_FORMAT_REG 0x5B 69 #define BPP_18_RGB BIT(0) 70 #define SN_HPD_DISABLE_REG 0x5C 71 #define HPD_DISABLE BIT(0) 72 #define HPD_DEBOUNCED_STATE BIT(4) 73 #define SN_GPIO_IO_REG 0x5E 74 #define SN_GPIO_INPUT_SHIFT 4 75 #define SN_GPIO_OUTPUT_SHIFT 0 76 #define SN_GPIO_CTRL_REG 0x5F 77 #define SN_GPIO_MUX_INPUT 0 78 #define SN_GPIO_MUX_OUTPUT 1 79 #define SN_GPIO_MUX_SPECIAL 2 80 #define SN_GPIO_MUX_MASK 0x3 81 #define SN_AUX_WDATA_REG(x) (0x64 + (x)) 82 #define SN_AUX_ADDR_19_16_REG 0x74 83 #define SN_AUX_ADDR_15_8_REG 0x75 84 #define SN_AUX_ADDR_7_0_REG 0x76 85 #define SN_AUX_ADDR_MASK GENMASK(19, 0) 86 #define SN_AUX_LENGTH_REG 0x77 87 #define SN_AUX_CMD_REG 0x78 88 #define AUX_CMD_SEND BIT(0) 89 #define AUX_CMD_REQ(x) ((x) << 4) 90 #define SN_AUX_RDATA_REG(x) (0x79 + (x)) 91 #define SN_SSC_CONFIG_REG 0x93 92 #define DP_NUM_LANES_MASK GENMASK(5, 4) 93 #define DP_NUM_LANES(x) ((x) << 4) 94 #define SN_DATARATE_CONFIG_REG 0x94 95 #define DP_DATARATE_MASK GENMASK(7, 5) 96 #define DP_DATARATE(x) ((x) << 5) 97 #define SN_TRAINING_SETTING_REG 0x95 98 #define SCRAMBLE_DISABLE BIT(4) 99 #define SN_ML_TX_MODE_REG 0x96 100 #define ML_TX_MAIN_LINK_OFF 0 101 #define ML_TX_NORMAL_MODE BIT(0) 102 #define SN_PWM_PRE_DIV_REG 0xA0 103 #define SN_BACKLIGHT_SCALE_REG 0xA1 104 #define BACKLIGHT_SCALE_MAX 0xFFFF 105 #define SN_BACKLIGHT_REG 0xA3 106 #define SN_PWM_EN_INV_REG 0xA5 107 #define SN_PWM_INV_MASK BIT(0) 108 #define SN_PWM_EN_MASK BIT(1) 109 #define SN_AUX_CMD_STATUS_REG 0xF4 110 #define AUX_IRQ_STATUS_AUX_RPLY_TOUT BIT(3) 111 #define AUX_IRQ_STATUS_AUX_SHORT BIT(5) 112 #define AUX_IRQ_STATUS_NAT_I2C_FAIL BIT(6) 113 114 #define MIN_DSI_CLK_FREQ_MHZ 40 115 116 /* fudge factor required to account for 8b/10b encoding */ 117 #define DP_CLK_FUDGE_NUM 10 118 #define DP_CLK_FUDGE_DEN 8 119 120 /* Matches DP_AUX_MAX_PAYLOAD_BYTES (for now) */ 121 #define SN_AUX_MAX_PAYLOAD_BYTES 16 122 123 #define SN_REGULATOR_SUPPLY_NUM 4 124 125 #define SN_MAX_DP_LANES 4 126 #define SN_NUM_GPIOS 4 127 #define SN_GPIO_PHYSICAL_OFFSET 1 128 129 #define SN_LINK_TRAINING_TRIES 10 130 131 #define SN_PWM_GPIO_IDX 3 /* 4th GPIO */ 132 133 /** 134 * struct ti_sn65dsi86 - Platform data for ti-sn65dsi86 driver. 135 * @bridge_aux: AUX-bus sub device for MIPI-to-eDP bridge functionality. 136 * @gpio_aux: AUX-bus sub device for GPIO controller functionality. 137 * @aux_aux: AUX-bus sub device for eDP AUX channel functionality. 138 * @pwm_aux: AUX-bus sub device for PWM controller functionality. 139 * 140 * @dev: Pointer to the top level (i2c) device. 141 * @regmap: Regmap for accessing i2c. 142 * @aux: Our aux channel. 143 * @bridge: Our bridge. 144 * @connector: Our connector. 145 * @host_node: Remote DSI node. 146 * @dsi: Our MIPI DSI source. 147 * @refclk: Our reference clock. 148 * @next_bridge: The bridge on the eDP side. 149 * @enable_gpio: The GPIO we toggle to enable the bridge. 150 * @supplies: Data for bulk enabling/disabling our regulators. 151 * @dp_lanes: Count of dp_lanes we're using. 152 * @ln_assign: Value to program to the LN_ASSIGN register. 153 * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG. 154 * @comms_enabled: If true then communication over the aux channel is enabled. 155 * @comms_mutex: Protects modification of comms_enabled. 156 * 157 * @gchip: If we expose our GPIOs, this is used. 158 * @gchip_output: A cache of whether we've set GPIOs to output. This 159 * serves double-duty of keeping track of the direction and 160 * also keeping track of whether we've incremented the 161 * pm_runtime reference count for this pin, which we do 162 * whenever a pin is configured as an output. This is a 163 * bitmap so we can do atomic ops on it without an extra 164 * lock so concurrent users of our 4 GPIOs don't stomp on 165 * each other's read-modify-write. 166 * 167 * @pchip: pwm_chip if the PWM is exposed. 168 * @pwm_enabled: Used to track if the PWM signal is currently enabled. 169 * @pwm_pin_busy: Track if GPIO4 is currently requested for GPIO or PWM. 170 * @pwm_refclk_freq: Cache for the reference clock input to the PWM. 171 */ 172 struct ti_sn65dsi86 { 173 struct auxiliary_device *bridge_aux; 174 struct auxiliary_device *gpio_aux; 175 struct auxiliary_device *aux_aux; 176 struct auxiliary_device *pwm_aux; 177 178 struct device *dev; 179 struct regmap *regmap; 180 struct drm_dp_aux aux; 181 struct drm_bridge bridge; 182 struct drm_connector *connector; 183 struct device_node *host_node; 184 struct mipi_dsi_device *dsi; 185 struct clk *refclk; 186 struct drm_bridge *next_bridge; 187 struct gpio_desc *enable_gpio; 188 struct regulator_bulk_data supplies[SN_REGULATOR_SUPPLY_NUM]; 189 int dp_lanes; 190 u8 ln_assign; 191 u8 ln_polrs; 192 bool comms_enabled; 193 struct mutex comms_mutex; 194 195 #if defined(CONFIG_OF_GPIO) 196 struct gpio_chip gchip; 197 DECLARE_BITMAP(gchip_output, SN_NUM_GPIOS); 198 #endif 199 #if IS_REACHABLE(CONFIG_PWM) 200 struct pwm_chip *pchip; 201 bool pwm_enabled; 202 atomic_t pwm_pin_busy; 203 #endif 204 unsigned int pwm_refclk_freq; 205 }; 206 207 static const struct regmap_range ti_sn65dsi86_volatile_ranges[] = { 208 { .range_min = 0, .range_max = 0xFF }, 209 }; 210 211 static const struct regmap_access_table ti_sn_bridge_volatile_table = { 212 .yes_ranges = ti_sn65dsi86_volatile_ranges, 213 .n_yes_ranges = ARRAY_SIZE(ti_sn65dsi86_volatile_ranges), 214 }; 215 216 static const struct regmap_config ti_sn65dsi86_regmap_config = { 217 .reg_bits = 8, 218 .val_bits = 8, 219 .volatile_table = &ti_sn_bridge_volatile_table, 220 .cache_type = REGCACHE_NONE, 221 .max_register = 0xFF, 222 }; 223 224 static int __maybe_unused ti_sn65dsi86_read_u16(struct ti_sn65dsi86 *pdata, 225 unsigned int reg, u16 *val) 226 { 227 u8 buf[2]; 228 int ret; 229 230 ret = regmap_bulk_read(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 231 if (ret) 232 return ret; 233 234 *val = buf[0] | (buf[1] << 8); 235 236 return 0; 237 } 238 239 static void ti_sn65dsi86_write_u16(struct ti_sn65dsi86 *pdata, 240 unsigned int reg, u16 val) 241 { 242 u8 buf[2] = { val & 0xff, val >> 8 }; 243 244 regmap_bulk_write(pdata->regmap, reg, buf, ARRAY_SIZE(buf)); 245 } 246 247 static struct drm_display_mode * 248 get_new_adjusted_display_mode(struct drm_bridge *bridge, 249 struct drm_atomic_state *state) 250 { 251 struct drm_connector *connector = 252 drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 253 struct drm_connector_state *conn_state = 254 drm_atomic_get_new_connector_state(state, connector); 255 struct drm_crtc_state *crtc_state = 256 drm_atomic_get_new_crtc_state(state, conn_state->crtc); 257 258 return &crtc_state->adjusted_mode; 259 } 260 261 static u32 ti_sn_bridge_get_dsi_freq(struct ti_sn65dsi86 *pdata, 262 struct drm_atomic_state *state) 263 { 264 u32 bit_rate_khz, clk_freq_khz; 265 struct drm_display_mode *mode = 266 get_new_adjusted_display_mode(&pdata->bridge, state); 267 268 bit_rate_khz = mode->clock * 269 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 270 clk_freq_khz = bit_rate_khz / (pdata->dsi->lanes * 2); 271 272 return clk_freq_khz; 273 } 274 275 /* clk frequencies supported by bridge in Hz in case derived from REFCLK pin */ 276 static const u32 ti_sn_bridge_refclk_lut[] = { 277 12000000, 278 19200000, 279 26000000, 280 27000000, 281 38400000, 282 }; 283 284 /* clk frequencies supported by bridge in Hz in case derived from DACP/N pin */ 285 static const u32 ti_sn_bridge_dsiclk_lut[] = { 286 468000000, 287 384000000, 288 416000000, 289 486000000, 290 460800000, 291 }; 292 293 static void ti_sn_bridge_set_refclk_freq(struct ti_sn65dsi86 *pdata, 294 struct drm_atomic_state *state) 295 { 296 int i; 297 u32 refclk_rate; 298 const u32 *refclk_lut; 299 size_t refclk_lut_size; 300 301 if (pdata->refclk) { 302 refclk_rate = clk_get_rate(pdata->refclk); 303 refclk_lut = ti_sn_bridge_refclk_lut; 304 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_refclk_lut); 305 clk_prepare_enable(pdata->refclk); 306 } else { 307 refclk_rate = ti_sn_bridge_get_dsi_freq(pdata, state) * 1000; 308 refclk_lut = ti_sn_bridge_dsiclk_lut; 309 refclk_lut_size = ARRAY_SIZE(ti_sn_bridge_dsiclk_lut); 310 } 311 312 /* for i equals to refclk_lut_size means default frequency */ 313 for (i = 0; i < refclk_lut_size; i++) 314 if (refclk_lut[i] == refclk_rate) 315 break; 316 317 /* avoid buffer overflow and "1" is the default rate in the datasheet. */ 318 if (i >= refclk_lut_size) 319 i = 1; 320 321 regmap_update_bits(pdata->regmap, SN_DPPLL_SRC_REG, REFCLK_FREQ_MASK, 322 REFCLK_FREQ(i)); 323 324 /* 325 * The PWM refclk is based on the value written to SN_DPPLL_SRC_REG, 326 * regardless of its actual sourcing. 327 */ 328 pdata->pwm_refclk_freq = ti_sn_bridge_refclk_lut[i]; 329 } 330 331 static void ti_sn65dsi86_enable_comms(struct ti_sn65dsi86 *pdata, 332 struct drm_atomic_state *state) 333 { 334 mutex_lock(&pdata->comms_mutex); 335 336 /* configure bridge ref_clk */ 337 ti_sn_bridge_set_refclk_freq(pdata, state); 338 339 /* 340 * HPD on this bridge chip is a bit useless. This is an eDP bridge 341 * so the HPD is an internal signal that's only there to signal that 342 * the panel is done powering up. ...but the bridge chip debounces 343 * this signal by between 100 ms and 400 ms (depending on process, 344 * voltage, and temperate--I measured it at about 200 ms). One 345 * particular panel asserted HPD 84 ms after it was powered on meaning 346 * that we saw HPD 284 ms after power on. ...but the same panel said 347 * that instead of looking at HPD you could just hardcode a delay of 348 * 200 ms. We'll assume that the panel driver will have the hardcoded 349 * delay in its prepare and always disable HPD. 350 * 351 * For DisplayPort bridge type, we need HPD. So we use the bridge type 352 * to conditionally disable HPD. 353 * NOTE: The bridge type is set in ti_sn_bridge_probe() but enable_comms() 354 * can be called before. So for DisplayPort, HPD will be enabled once 355 * bridge type is set. We are using bridge type instead of "no-hpd" 356 * property because it is not used properly in devicetree description 357 * and hence is unreliable. 358 */ 359 360 if (pdata->bridge.type != DRM_MODE_CONNECTOR_DisplayPort) 361 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, HPD_DISABLE, 362 HPD_DISABLE); 363 364 pdata->comms_enabled = true; 365 366 mutex_unlock(&pdata->comms_mutex); 367 } 368 369 static void ti_sn65dsi86_disable_comms(struct ti_sn65dsi86 *pdata) 370 { 371 mutex_lock(&pdata->comms_mutex); 372 373 pdata->comms_enabled = false; 374 clk_disable_unprepare(pdata->refclk); 375 376 mutex_unlock(&pdata->comms_mutex); 377 } 378 379 static int __maybe_unused ti_sn65dsi86_resume(struct device *dev) 380 { 381 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 382 int ret; 383 384 ret = regulator_bulk_enable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 385 if (ret) { 386 DRM_ERROR("failed to enable supplies %d\n", ret); 387 return ret; 388 } 389 390 /* td2: min 100 us after regulators before enabling the GPIO */ 391 usleep_range(100, 110); 392 393 gpiod_set_value_cansleep(pdata->enable_gpio, 1); 394 395 /* 396 * If we have a reference clock we can enable communication w/ the 397 * panel (including the aux channel) w/out any need for an input clock 398 * so we can do it in resume which lets us read the EDID before 399 * pre_enable(). Without a reference clock we need the MIPI reference 400 * clock so reading early doesn't work. 401 */ 402 if (pdata->refclk) 403 ti_sn65dsi86_enable_comms(pdata, NULL); 404 405 return ret; 406 } 407 408 static int __maybe_unused ti_sn65dsi86_suspend(struct device *dev) 409 { 410 struct ti_sn65dsi86 *pdata = dev_get_drvdata(dev); 411 int ret; 412 413 if (pdata->refclk) 414 ti_sn65dsi86_disable_comms(pdata); 415 416 gpiod_set_value_cansleep(pdata->enable_gpio, 0); 417 418 ret = regulator_bulk_disable(SN_REGULATOR_SUPPLY_NUM, pdata->supplies); 419 if (ret) 420 DRM_ERROR("failed to disable supplies %d\n", ret); 421 422 return ret; 423 } 424 425 static const struct dev_pm_ops ti_sn65dsi86_pm_ops = { 426 SET_RUNTIME_PM_OPS(ti_sn65dsi86_suspend, ti_sn65dsi86_resume, NULL) 427 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 428 pm_runtime_force_resume) 429 }; 430 431 static int status_show(struct seq_file *s, void *data) 432 { 433 struct ti_sn65dsi86 *pdata = s->private; 434 unsigned int reg, val; 435 436 seq_puts(s, "STATUS REGISTERS:\n"); 437 438 pm_runtime_get_sync(pdata->dev); 439 440 /* IRQ Status Registers, see Table 31 in datasheet */ 441 for (reg = 0xf0; reg <= 0xf8; reg++) { 442 regmap_read(pdata->regmap, reg, &val); 443 seq_printf(s, "[0x%02x] = 0x%08x\n", reg, val); 444 } 445 446 pm_runtime_put_autosuspend(pdata->dev); 447 448 return 0; 449 } 450 DEFINE_SHOW_ATTRIBUTE(status); 451 452 /* ----------------------------------------------------------------------------- 453 * Auxiliary Devices (*not* AUX) 454 */ 455 456 static int ti_sn65dsi86_add_aux_device(struct ti_sn65dsi86 *pdata, 457 struct auxiliary_device **aux_out, 458 const char *name) 459 { 460 struct device *dev = pdata->dev; 461 const struct i2c_client *client = to_i2c_client(dev); 462 struct auxiliary_device *aux; 463 int id; 464 465 id = (client->adapter->nr << 10) | client->addr; 466 aux = __devm_auxiliary_device_create(dev, KBUILD_MODNAME, name, 467 NULL, id); 468 if (!aux) 469 return -ENODEV; 470 471 *aux_out = aux; 472 return 0; 473 } 474 475 /* ----------------------------------------------------------------------------- 476 * AUX Adapter 477 */ 478 479 static struct ti_sn65dsi86 *aux_to_ti_sn65dsi86(struct drm_dp_aux *aux) 480 { 481 return container_of(aux, struct ti_sn65dsi86, aux); 482 } 483 484 static ssize_t ti_sn_aux_transfer(struct drm_dp_aux *aux, 485 struct drm_dp_aux_msg *msg) 486 { 487 struct ti_sn65dsi86 *pdata = aux_to_ti_sn65dsi86(aux); 488 u32 request = msg->request & ~(DP_AUX_I2C_MOT | DP_AUX_I2C_WRITE_STATUS_UPDATE); 489 u32 request_val = AUX_CMD_REQ(msg->request); 490 u8 *buf = msg->buffer; 491 unsigned int len = msg->size; 492 unsigned int short_len; 493 unsigned int val; 494 int ret; 495 u8 addr_len[SN_AUX_LENGTH_REG + 1 - SN_AUX_ADDR_19_16_REG]; 496 497 if (len > SN_AUX_MAX_PAYLOAD_BYTES) 498 return -EINVAL; 499 500 pm_runtime_get_sync(pdata->dev); 501 mutex_lock(&pdata->comms_mutex); 502 503 /* 504 * If someone tries to do a DDC over AUX transaction before pre_enable() 505 * on a device without a dedicated reference clock then we just can't 506 * do it. Fail right away. This prevents non-refclk users from reading 507 * the EDID before enabling the panel but such is life. 508 */ 509 if (!pdata->comms_enabled) { 510 ret = -EIO; 511 goto exit; 512 } 513 514 switch (request) { 515 case DP_AUX_NATIVE_WRITE: 516 case DP_AUX_I2C_WRITE: 517 case DP_AUX_NATIVE_READ: 518 case DP_AUX_I2C_READ: 519 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val); 520 /* Assume it's good */ 521 msg->reply = 0; 522 break; 523 default: 524 ret = -EINVAL; 525 goto exit; 526 } 527 528 BUILD_BUG_ON(sizeof(addr_len) != sizeof(__be32)); 529 put_unaligned_be32((msg->address & SN_AUX_ADDR_MASK) << 8 | len, 530 addr_len); 531 regmap_bulk_write(pdata->regmap, SN_AUX_ADDR_19_16_REG, addr_len, 532 ARRAY_SIZE(addr_len)); 533 534 if (request == DP_AUX_NATIVE_WRITE || request == DP_AUX_I2C_WRITE) 535 regmap_bulk_write(pdata->regmap, SN_AUX_WDATA_REG(0), buf, len); 536 537 /* Clear old status bits before start so we don't get confused */ 538 regmap_write(pdata->regmap, SN_AUX_CMD_STATUS_REG, 539 AUX_IRQ_STATUS_NAT_I2C_FAIL | 540 AUX_IRQ_STATUS_AUX_RPLY_TOUT | 541 AUX_IRQ_STATUS_AUX_SHORT); 542 543 regmap_write(pdata->regmap, SN_AUX_CMD_REG, request_val | AUX_CMD_SEND); 544 545 /* Zero delay loop because i2c transactions are slow already */ 546 ret = regmap_read_poll_timeout(pdata->regmap, SN_AUX_CMD_REG, val, 547 !(val & AUX_CMD_SEND), 0, 50 * 1000); 548 if (ret) 549 goto exit; 550 551 ret = regmap_read(pdata->regmap, SN_AUX_CMD_STATUS_REG, &val); 552 if (ret) 553 goto exit; 554 555 if (val & AUX_IRQ_STATUS_AUX_RPLY_TOUT) { 556 /* 557 * The hardware tried the message seven times per the DP spec 558 * but it hit a timeout. We ignore defers here because they're 559 * handled in hardware. 560 */ 561 ret = -ETIMEDOUT; 562 goto exit; 563 } 564 565 if (val & AUX_IRQ_STATUS_AUX_SHORT) { 566 ret = regmap_read(pdata->regmap, SN_AUX_LENGTH_REG, &short_len); 567 len = min(len, short_len); 568 if (ret) 569 goto exit; 570 } else if (val & AUX_IRQ_STATUS_NAT_I2C_FAIL) { 571 switch (request) { 572 case DP_AUX_I2C_WRITE: 573 case DP_AUX_I2C_READ: 574 msg->reply |= DP_AUX_I2C_REPLY_NACK; 575 break; 576 case DP_AUX_NATIVE_READ: 577 case DP_AUX_NATIVE_WRITE: 578 msg->reply |= DP_AUX_NATIVE_REPLY_NACK; 579 break; 580 } 581 len = 0; 582 goto exit; 583 } 584 585 if (request != DP_AUX_NATIVE_WRITE && request != DP_AUX_I2C_WRITE && len != 0) 586 ret = regmap_bulk_read(pdata->regmap, SN_AUX_RDATA_REG(0), buf, len); 587 588 exit: 589 mutex_unlock(&pdata->comms_mutex); 590 pm_runtime_mark_last_busy(pdata->dev); 591 pm_runtime_put_autosuspend(pdata->dev); 592 593 if (ret) 594 return ret; 595 return len; 596 } 597 598 static int ti_sn_aux_wait_hpd_asserted(struct drm_dp_aux *aux, unsigned long wait_us) 599 { 600 /* 601 * The HPD in this chip is a bit useless (See comment in 602 * ti_sn65dsi86_enable_comms) so if our driver is expected to wait 603 * for HPD, we just assume it's asserted after the wait_us delay. 604 * 605 * In case we are asked to wait forever (wait_us=0) take conservative 606 * 500ms delay. 607 */ 608 if (wait_us == 0) 609 wait_us = 500000; 610 611 usleep_range(wait_us, wait_us + 1000); 612 613 return 0; 614 } 615 616 static int ti_sn_aux_probe(struct auxiliary_device *adev, 617 const struct auxiliary_device_id *id) 618 { 619 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 620 int ret; 621 622 pdata->aux.name = "ti-sn65dsi86-aux"; 623 pdata->aux.dev = &adev->dev; 624 pdata->aux.transfer = ti_sn_aux_transfer; 625 pdata->aux.wait_hpd_asserted = ti_sn_aux_wait_hpd_asserted; 626 drm_dp_aux_init(&pdata->aux); 627 628 ret = devm_of_dp_aux_populate_ep_devices(&pdata->aux); 629 if (ret) 630 return ret; 631 632 /* 633 * The eDP to MIPI bridge parts don't work until the AUX channel is 634 * setup so we don't add it in the main driver probe, we add it now. 635 */ 636 return ti_sn65dsi86_add_aux_device(pdata, &pdata->bridge_aux, "bridge"); 637 } 638 639 static const struct auxiliary_device_id ti_sn_aux_id_table[] = { 640 { .name = "ti_sn65dsi86.aux", }, 641 {}, 642 }; 643 644 static struct auxiliary_driver ti_sn_aux_driver = { 645 .name = "aux", 646 .probe = ti_sn_aux_probe, 647 .id_table = ti_sn_aux_id_table, 648 }; 649 650 /*------------------------------------------------------------------------------ 651 * DRM Bridge 652 */ 653 654 static struct ti_sn65dsi86 *bridge_to_ti_sn65dsi86(struct drm_bridge *bridge) 655 { 656 return container_of(bridge, struct ti_sn65dsi86, bridge); 657 } 658 659 static int ti_sn_attach_host(struct auxiliary_device *adev, struct ti_sn65dsi86 *pdata) 660 { 661 int val; 662 struct mipi_dsi_host *host; 663 struct mipi_dsi_device *dsi; 664 struct device *dev = pdata->dev; 665 const struct mipi_dsi_device_info info = { .type = "ti_sn_bridge", 666 .channel = 0, 667 .node = NULL, 668 }; 669 670 host = of_find_mipi_dsi_host_by_node(pdata->host_node); 671 if (!host) 672 return -EPROBE_DEFER; 673 674 dsi = devm_mipi_dsi_device_register_full(&adev->dev, host, &info); 675 if (IS_ERR(dsi)) 676 return PTR_ERR(dsi); 677 678 /* TODO: setting to 4 MIPI lanes always for now */ 679 dsi->lanes = 4; 680 dsi->format = MIPI_DSI_FMT_RGB888; 681 dsi->mode_flags = MIPI_DSI_MODE_VIDEO; 682 683 /* check if continuous dsi clock is required or not */ 684 pm_runtime_get_sync(dev); 685 regmap_read(pdata->regmap, SN_DPPLL_SRC_REG, &val); 686 pm_runtime_put_autosuspend(dev); 687 if (!(val & DPPLL_CLK_SRC_DSICLK)) 688 dsi->mode_flags |= MIPI_DSI_CLOCK_NON_CONTINUOUS; 689 690 pdata->dsi = dsi; 691 692 return devm_mipi_dsi_attach(&adev->dev, dsi); 693 } 694 695 static int ti_sn_bridge_attach(struct drm_bridge *bridge, 696 struct drm_encoder *encoder, 697 enum drm_bridge_attach_flags flags) 698 { 699 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 700 int ret; 701 702 pdata->aux.drm_dev = bridge->dev; 703 ret = drm_dp_aux_register(&pdata->aux); 704 if (ret < 0) { 705 drm_err(bridge->dev, "Failed to register DP AUX channel: %d\n", ret); 706 return ret; 707 } 708 709 /* 710 * Attach the next bridge. 711 * We never want the next bridge to *also* create a connector. 712 */ 713 ret = drm_bridge_attach(encoder, pdata->next_bridge, 714 &pdata->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); 715 if (ret < 0) 716 goto err_initted_aux; 717 718 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 719 return 0; 720 721 pdata->connector = drm_bridge_connector_init(pdata->bridge.dev, 722 pdata->bridge.encoder); 723 if (IS_ERR(pdata->connector)) { 724 ret = PTR_ERR(pdata->connector); 725 goto err_initted_aux; 726 } 727 728 drm_connector_attach_encoder(pdata->connector, pdata->bridge.encoder); 729 730 return 0; 731 732 err_initted_aux: 733 drm_dp_aux_unregister(&pdata->aux); 734 return ret; 735 } 736 737 static void ti_sn_bridge_detach(struct drm_bridge *bridge) 738 { 739 drm_dp_aux_unregister(&bridge_to_ti_sn65dsi86(bridge)->aux); 740 } 741 742 static enum drm_mode_status 743 ti_sn_bridge_mode_valid(struct drm_bridge *bridge, 744 const struct drm_display_info *info, 745 const struct drm_display_mode *mode) 746 { 747 /* maximum supported resolution is 4K at 60 fps */ 748 if (mode->clock > 594000) 749 return MODE_CLOCK_HIGH; 750 751 /* 752 * The front and back porch registers are 8 bits, and pulse width 753 * registers are 15 bits, so reject any modes with larger periods. 754 */ 755 756 if ((mode->hsync_start - mode->hdisplay) > 0xff) 757 return MODE_HBLANK_WIDE; 758 759 if ((mode->vsync_start - mode->vdisplay) > 0xff) 760 return MODE_VBLANK_WIDE; 761 762 if ((mode->hsync_end - mode->hsync_start) > 0x7fff) 763 return MODE_HSYNC_WIDE; 764 765 if ((mode->vsync_end - mode->vsync_start) > 0x7fff) 766 return MODE_VSYNC_WIDE; 767 768 if ((mode->htotal - mode->hsync_end) > 0xff) 769 return MODE_HBLANK_WIDE; 770 771 if ((mode->vtotal - mode->vsync_end) > 0xff) 772 return MODE_VBLANK_WIDE; 773 774 return MODE_OK; 775 } 776 777 static void ti_sn_bridge_atomic_disable(struct drm_bridge *bridge, 778 struct drm_atomic_state *state) 779 { 780 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 781 782 /* disable video stream */ 783 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 0); 784 } 785 786 static void ti_sn_bridge_set_dsi_rate(struct ti_sn65dsi86 *pdata, 787 struct drm_atomic_state *state) 788 { 789 unsigned int bit_rate_mhz, clk_freq_mhz; 790 unsigned int val; 791 struct drm_display_mode *mode = 792 get_new_adjusted_display_mode(&pdata->bridge, state); 793 794 /* set DSIA clk frequency */ 795 bit_rate_mhz = (mode->clock / 1000) * 796 mipi_dsi_pixel_format_to_bpp(pdata->dsi->format); 797 clk_freq_mhz = bit_rate_mhz / (pdata->dsi->lanes * 2); 798 799 /* for each increment in val, frequency increases by 5MHz */ 800 val = (MIN_DSI_CLK_FREQ_MHZ / 5) + 801 (((clk_freq_mhz - MIN_DSI_CLK_FREQ_MHZ) / 5) & 0xFF); 802 regmap_write(pdata->regmap, SN_DSIA_CLK_FREQ_REG, val); 803 } 804 805 static unsigned int ti_sn_bridge_get_bpp(struct drm_connector *connector) 806 { 807 if (connector->display_info.bpc <= 6) 808 return 18; 809 else 810 return 24; 811 } 812 813 /* 814 * LUT index corresponds to register value and 815 * LUT values corresponds to dp data rate supported 816 * by the bridge in Mbps unit. 817 */ 818 static const unsigned int ti_sn_bridge_dp_rate_lut[] = { 819 0, 1620, 2160, 2430, 2700, 3240, 4320, 5400 820 }; 821 822 static int ti_sn_bridge_calc_min_dp_rate_idx(struct ti_sn65dsi86 *pdata, 823 struct drm_atomic_state *state, 824 unsigned int bpp) 825 { 826 unsigned int bit_rate_khz, dp_rate_mhz; 827 unsigned int i; 828 struct drm_display_mode *mode = 829 get_new_adjusted_display_mode(&pdata->bridge, state); 830 831 /* Calculate minimum bit rate based on our pixel clock. */ 832 bit_rate_khz = mode->clock * bpp; 833 834 /* Calculate minimum DP data rate, taking 80% as per DP spec */ 835 dp_rate_mhz = DIV_ROUND_UP(bit_rate_khz * DP_CLK_FUDGE_NUM, 836 1000 * pdata->dp_lanes * DP_CLK_FUDGE_DEN); 837 838 for (i = 1; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut) - 1; i++) 839 if (ti_sn_bridge_dp_rate_lut[i] >= dp_rate_mhz) 840 break; 841 842 return i; 843 } 844 845 static unsigned int ti_sn_bridge_read_valid_rates(struct ti_sn65dsi86 *pdata) 846 { 847 unsigned int valid_rates = 0; 848 unsigned int rate_per_200khz; 849 unsigned int rate_mhz; 850 u8 dpcd_val; 851 int ret; 852 int i, j; 853 854 ret = drm_dp_dpcd_readb(&pdata->aux, DP_EDP_DPCD_REV, &dpcd_val); 855 if (ret != 1) { 856 DRM_DEV_ERROR(pdata->dev, 857 "Can't read eDP rev (%d), assuming 1.1\n", ret); 858 dpcd_val = DP_EDP_11; 859 } 860 861 if (dpcd_val >= DP_EDP_14) { 862 /* eDP 1.4 devices must provide a custom table */ 863 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 864 865 ret = drm_dp_dpcd_read(&pdata->aux, DP_SUPPORTED_LINK_RATES, 866 sink_rates, sizeof(sink_rates)); 867 868 if (ret != sizeof(sink_rates)) { 869 DRM_DEV_ERROR(pdata->dev, 870 "Can't read supported rate table (%d)\n", ret); 871 872 /* By zeroing we'll fall back to DP_MAX_LINK_RATE. */ 873 memset(sink_rates, 0, sizeof(sink_rates)); 874 } 875 876 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 877 rate_per_200khz = le16_to_cpu(sink_rates[i]); 878 879 if (!rate_per_200khz) 880 break; 881 882 rate_mhz = rate_per_200khz * 200 / 1000; 883 for (j = 0; 884 j < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 885 j++) { 886 if (ti_sn_bridge_dp_rate_lut[j] == rate_mhz) 887 valid_rates |= BIT(j); 888 } 889 } 890 891 for (i = 0; i < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); i++) { 892 if (valid_rates & BIT(i)) 893 return valid_rates; 894 } 895 DRM_DEV_ERROR(pdata->dev, 896 "No matching eDP rates in table; falling back\n"); 897 } 898 899 /* On older versions best we can do is use DP_MAX_LINK_RATE */ 900 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LINK_RATE, &dpcd_val); 901 if (ret != 1) { 902 DRM_DEV_ERROR(pdata->dev, 903 "Can't read max rate (%d); assuming 5.4 GHz\n", 904 ret); 905 dpcd_val = DP_LINK_BW_5_4; 906 } 907 908 switch (dpcd_val) { 909 default: 910 DRM_DEV_ERROR(pdata->dev, 911 "Unexpected max rate (%#x); assuming 5.4 GHz\n", 912 (int)dpcd_val); 913 fallthrough; 914 case DP_LINK_BW_5_4: 915 valid_rates |= BIT(7); 916 fallthrough; 917 case DP_LINK_BW_2_7: 918 valid_rates |= BIT(4); 919 fallthrough; 920 case DP_LINK_BW_1_62: 921 valid_rates |= BIT(1); 922 break; 923 } 924 925 return valid_rates; 926 } 927 928 static void ti_sn_bridge_set_video_timings(struct ti_sn65dsi86 *pdata, 929 struct drm_atomic_state *state) 930 { 931 struct drm_display_mode *mode = 932 get_new_adjusted_display_mode(&pdata->bridge, state); 933 u8 hsync_polarity = 0, vsync_polarity = 0; 934 935 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 936 hsync_polarity = CHA_HSYNC_POLARITY; 937 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 938 vsync_polarity = CHA_VSYNC_POLARITY; 939 940 ti_sn65dsi86_write_u16(pdata, SN_CHA_ACTIVE_LINE_LENGTH_LOW_REG, 941 mode->hdisplay); 942 ti_sn65dsi86_write_u16(pdata, SN_CHA_VERTICAL_DISPLAY_SIZE_LOW_REG, 943 mode->vdisplay); 944 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_LOW_REG, 945 (mode->hsync_end - mode->hsync_start) & 0xFF); 946 regmap_write(pdata->regmap, SN_CHA_HSYNC_PULSE_WIDTH_HIGH_REG, 947 (((mode->hsync_end - mode->hsync_start) >> 8) & 0x7F) | 948 hsync_polarity); 949 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_LOW_REG, 950 (mode->vsync_end - mode->vsync_start) & 0xFF); 951 regmap_write(pdata->regmap, SN_CHA_VSYNC_PULSE_WIDTH_HIGH_REG, 952 (((mode->vsync_end - mode->vsync_start) >> 8) & 0x7F) | 953 vsync_polarity); 954 955 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_BACK_PORCH_REG, 956 (mode->htotal - mode->hsync_end) & 0xFF); 957 regmap_write(pdata->regmap, SN_CHA_VERTICAL_BACK_PORCH_REG, 958 (mode->vtotal - mode->vsync_end) & 0xFF); 959 960 regmap_write(pdata->regmap, SN_CHA_HORIZONTAL_FRONT_PORCH_REG, 961 (mode->hsync_start - mode->hdisplay) & 0xFF); 962 regmap_write(pdata->regmap, SN_CHA_VERTICAL_FRONT_PORCH_REG, 963 (mode->vsync_start - mode->vdisplay) & 0xFF); 964 965 usleep_range(10000, 10500); /* 10ms delay recommended by spec */ 966 } 967 968 static unsigned int ti_sn_get_max_lanes(struct ti_sn65dsi86 *pdata) 969 { 970 u8 data; 971 int ret; 972 973 ret = drm_dp_dpcd_readb(&pdata->aux, DP_MAX_LANE_COUNT, &data); 974 if (ret != 1) { 975 DRM_DEV_ERROR(pdata->dev, 976 "Can't read lane count (%d); assuming 4\n", ret); 977 return 4; 978 } 979 980 return data & DP_LANE_COUNT_MASK; 981 } 982 983 static int ti_sn_link_training(struct ti_sn65dsi86 *pdata, int dp_rate_idx, 984 const char **last_err_str) 985 { 986 unsigned int val; 987 int ret; 988 int i; 989 990 /* set dp clk frequency value */ 991 regmap_update_bits(pdata->regmap, SN_DATARATE_CONFIG_REG, 992 DP_DATARATE_MASK, DP_DATARATE(dp_rate_idx)); 993 994 /* enable DP PLL */ 995 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 1); 996 997 ret = regmap_read_poll_timeout(pdata->regmap, SN_DPPLL_SRC_REG, val, 998 val & DPPLL_SRC_DP_PLL_LOCK, 1000, 999 50 * 1000); 1000 if (ret) { 1001 *last_err_str = "DP_PLL_LOCK polling failed"; 1002 goto exit; 1003 } 1004 1005 /* 1006 * We'll try to link train several times. As part of link training 1007 * the bridge chip will write DP_SET_POWER_D0 to DP_SET_POWER. If 1008 * the panel isn't ready quite it might respond NAK here which means 1009 * we need to try again. 1010 */ 1011 for (i = 0; i < SN_LINK_TRAINING_TRIES; i++) { 1012 /* Semi auto link training mode */ 1013 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0x0A); 1014 ret = regmap_read_poll_timeout(pdata->regmap, SN_ML_TX_MODE_REG, val, 1015 val == ML_TX_MAIN_LINK_OFF || 1016 val == ML_TX_NORMAL_MODE, 1000, 1017 500 * 1000); 1018 if (ret) { 1019 *last_err_str = "Training complete polling failed"; 1020 } else if (val == ML_TX_MAIN_LINK_OFF) { 1021 *last_err_str = "Link training failed, link is off"; 1022 ret = -EIO; 1023 continue; 1024 } 1025 1026 break; 1027 } 1028 1029 /* If we saw quite a few retries, add a note about it */ 1030 if (!ret && i > SN_LINK_TRAINING_TRIES / 2) 1031 DRM_DEV_INFO(pdata->dev, "Link training needed %d retries\n", i); 1032 1033 exit: 1034 /* Disable the PLL if we failed */ 1035 if (ret) 1036 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1037 1038 return ret; 1039 } 1040 1041 static void ti_sn_bridge_atomic_enable(struct drm_bridge *bridge, 1042 struct drm_atomic_state *state) 1043 { 1044 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1045 struct drm_connector *connector; 1046 const char *last_err_str = "No supported DP rate"; 1047 unsigned int valid_rates; 1048 int dp_rate_idx; 1049 unsigned int val; 1050 int ret = -EINVAL; 1051 int max_dp_lanes; 1052 unsigned int bpp; 1053 1054 connector = drm_atomic_get_new_connector_for_encoder(state, 1055 bridge->encoder); 1056 if (!connector) { 1057 dev_err_ratelimited(pdata->dev, "Could not get the connector\n"); 1058 return; 1059 } 1060 1061 max_dp_lanes = ti_sn_get_max_lanes(pdata); 1062 pdata->dp_lanes = min(pdata->dp_lanes, max_dp_lanes); 1063 1064 /* DSI_A lane config */ 1065 val = CHA_DSI_LANES(SN_MAX_DP_LANES - pdata->dsi->lanes); 1066 regmap_update_bits(pdata->regmap, SN_DSI_LANES_REG, 1067 CHA_DSI_LANES_MASK, val); 1068 1069 regmap_write(pdata->regmap, SN_LN_ASSIGN_REG, pdata->ln_assign); 1070 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, LN_POLRS_MASK, 1071 pdata->ln_polrs << LN_POLRS_OFFSET); 1072 1073 /* set dsi clk frequency value */ 1074 ti_sn_bridge_set_dsi_rate(pdata, state); 1075 1076 /* 1077 * The SN65DSI86 only supports ASSR Display Authentication method and 1078 * this method is enabled for eDP panels. An eDP panel must support this 1079 * authentication method. We need to enable this method in the eDP panel 1080 * at DisplayPort address 0x0010A prior to link training. 1081 * 1082 * As only ASSR is supported by SN65DSI86, for full DisplayPort displays 1083 * we need to disable the scrambler. 1084 */ 1085 if (pdata->bridge.type == DRM_MODE_CONNECTOR_eDP) { 1086 drm_dp_dpcd_writeb(&pdata->aux, DP_EDP_CONFIGURATION_SET, 1087 DP_ALTERNATE_SCRAMBLER_RESET_ENABLE); 1088 1089 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1090 SCRAMBLE_DISABLE, 0); 1091 } else { 1092 regmap_update_bits(pdata->regmap, SN_TRAINING_SETTING_REG, 1093 SCRAMBLE_DISABLE, SCRAMBLE_DISABLE); 1094 } 1095 1096 bpp = ti_sn_bridge_get_bpp(connector); 1097 /* Set the DP output format (18 bpp or 24 bpp) */ 1098 val = bpp == 18 ? BPP_18_RGB : 0; 1099 regmap_update_bits(pdata->regmap, SN_DATA_FORMAT_REG, BPP_18_RGB, val); 1100 1101 /* DP lane config */ 1102 val = DP_NUM_LANES(min(pdata->dp_lanes, 3)); 1103 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 1104 val); 1105 1106 valid_rates = ti_sn_bridge_read_valid_rates(pdata); 1107 1108 /* Train until we run out of rates */ 1109 for (dp_rate_idx = ti_sn_bridge_calc_min_dp_rate_idx(pdata, state, bpp); 1110 dp_rate_idx < ARRAY_SIZE(ti_sn_bridge_dp_rate_lut); 1111 dp_rate_idx++) { 1112 if (!(valid_rates & BIT(dp_rate_idx))) 1113 continue; 1114 1115 ret = ti_sn_link_training(pdata, dp_rate_idx, &last_err_str); 1116 if (!ret) 1117 break; 1118 } 1119 if (ret) { 1120 DRM_DEV_ERROR(pdata->dev, "%s (%d)\n", last_err_str, ret); 1121 return; 1122 } 1123 1124 /* config video parameters */ 1125 ti_sn_bridge_set_video_timings(pdata, state); 1126 1127 /* enable video stream */ 1128 regmap_update_bits(pdata->regmap, SN_ENH_FRAME_REG, VSTREAM_ENABLE, 1129 VSTREAM_ENABLE); 1130 } 1131 1132 static void ti_sn_bridge_atomic_pre_enable(struct drm_bridge *bridge, 1133 struct drm_atomic_state *state) 1134 { 1135 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1136 1137 pm_runtime_get_sync(pdata->dev); 1138 1139 if (!pdata->refclk) 1140 ti_sn65dsi86_enable_comms(pdata, state); 1141 1142 /* td7: min 100 us after enable before DSI data */ 1143 usleep_range(100, 110); 1144 } 1145 1146 static void ti_sn_bridge_atomic_post_disable(struct drm_bridge *bridge, 1147 struct drm_atomic_state *state) 1148 { 1149 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1150 1151 /* semi auto link training mode OFF */ 1152 regmap_write(pdata->regmap, SN_ML_TX_MODE_REG, 0); 1153 /* Num lanes to 0 as per power sequencing in data sheet */ 1154 regmap_update_bits(pdata->regmap, SN_SSC_CONFIG_REG, DP_NUM_LANES_MASK, 0); 1155 /* disable DP PLL */ 1156 regmap_write(pdata->regmap, SN_PLL_ENABLE_REG, 0); 1157 1158 if (!pdata->refclk) 1159 ti_sn65dsi86_disable_comms(pdata); 1160 1161 pm_runtime_put_sync(pdata->dev); 1162 } 1163 1164 static enum drm_connector_status 1165 ti_sn_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 1166 { 1167 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1168 int val = 0; 1169 1170 /* 1171 * Runtime reference is grabbed in ti_sn_bridge_hpd_enable() 1172 * as the chip won't report HPD just after being powered on. 1173 * HPD_DEBOUNCED_STATE reflects correct state only after the 1174 * debounce time (~100-400 ms). 1175 */ 1176 1177 regmap_read(pdata->regmap, SN_HPD_DISABLE_REG, &val); 1178 1179 return val & HPD_DEBOUNCED_STATE ? connector_status_connected 1180 : connector_status_disconnected; 1181 } 1182 1183 static const struct drm_edid *ti_sn_bridge_edid_read(struct drm_bridge *bridge, 1184 struct drm_connector *connector) 1185 { 1186 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1187 1188 return drm_edid_read_ddc(connector, &pdata->aux.ddc); 1189 } 1190 1191 static void ti_sn65dsi86_debugfs_init(struct drm_bridge *bridge, struct dentry *root) 1192 { 1193 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1194 struct dentry *debugfs; 1195 1196 debugfs = debugfs_create_dir(dev_name(pdata->dev), root); 1197 debugfs_create_file("status", 0600, debugfs, pdata, &status_fops); 1198 } 1199 1200 static void ti_sn_bridge_hpd_enable(struct drm_bridge *bridge) 1201 { 1202 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1203 1204 /* 1205 * Device needs to be powered on before reading the HPD state 1206 * for reliable hpd detection in ti_sn_bridge_detect() due to 1207 * the high debounce time. 1208 */ 1209 1210 pm_runtime_get_sync(pdata->dev); 1211 } 1212 1213 static void ti_sn_bridge_hpd_disable(struct drm_bridge *bridge) 1214 { 1215 struct ti_sn65dsi86 *pdata = bridge_to_ti_sn65dsi86(bridge); 1216 1217 pm_runtime_put_autosuspend(pdata->dev); 1218 } 1219 1220 static const struct drm_bridge_funcs ti_sn_bridge_funcs = { 1221 .attach = ti_sn_bridge_attach, 1222 .detach = ti_sn_bridge_detach, 1223 .mode_valid = ti_sn_bridge_mode_valid, 1224 .edid_read = ti_sn_bridge_edid_read, 1225 .detect = ti_sn_bridge_detect, 1226 .atomic_pre_enable = ti_sn_bridge_atomic_pre_enable, 1227 .atomic_enable = ti_sn_bridge_atomic_enable, 1228 .atomic_disable = ti_sn_bridge_atomic_disable, 1229 .atomic_post_disable = ti_sn_bridge_atomic_post_disable, 1230 .atomic_reset = drm_atomic_helper_bridge_reset, 1231 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1232 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1233 .debugfs_init = ti_sn65dsi86_debugfs_init, 1234 .hpd_enable = ti_sn_bridge_hpd_enable, 1235 .hpd_disable = ti_sn_bridge_hpd_disable, 1236 }; 1237 1238 static void ti_sn_bridge_parse_lanes(struct ti_sn65dsi86 *pdata, 1239 struct device_node *np) 1240 { 1241 u32 lane_assignments[SN_MAX_DP_LANES] = { 0, 1, 2, 3 }; 1242 u32 lane_polarities[SN_MAX_DP_LANES] = { }; 1243 struct device_node *endpoint; 1244 u8 ln_assign = 0; 1245 u8 ln_polrs = 0; 1246 int dp_lanes; 1247 int i; 1248 1249 /* 1250 * Read config from the device tree about lane remapping and lane 1251 * polarities. These are optional and we assume identity map and 1252 * normal polarity if nothing is specified. It's OK to specify just 1253 * data-lanes but not lane-polarities but not vice versa. 1254 * 1255 * Error checking is light (we just make sure we don't crash or 1256 * buffer overrun) and we assume dts is well formed and specifying 1257 * mappings that the hardware supports. 1258 */ 1259 endpoint = of_graph_get_endpoint_by_regs(np, 1, -1); 1260 dp_lanes = drm_of_get_data_lanes_count(endpoint, 1, SN_MAX_DP_LANES); 1261 if (dp_lanes > 0) { 1262 of_property_read_u32_array(endpoint, "data-lanes", 1263 lane_assignments, dp_lanes); 1264 of_property_read_u32_array(endpoint, "lane-polarities", 1265 lane_polarities, dp_lanes); 1266 } else { 1267 dp_lanes = SN_MAX_DP_LANES; 1268 } 1269 of_node_put(endpoint); 1270 1271 /* 1272 * Convert into register format. Loop over all lanes even if 1273 * data-lanes had fewer elements so that we nicely initialize 1274 * the LN_ASSIGN register. 1275 */ 1276 for (i = SN_MAX_DP_LANES - 1; i >= 0; i--) { 1277 ln_assign = ln_assign << LN_ASSIGN_WIDTH | lane_assignments[i]; 1278 ln_polrs = ln_polrs << 1 | lane_polarities[i]; 1279 } 1280 1281 /* Stash in our struct for when we power on */ 1282 pdata->dp_lanes = dp_lanes; 1283 pdata->ln_assign = ln_assign; 1284 pdata->ln_polrs = ln_polrs; 1285 } 1286 1287 static int ti_sn_bridge_parse_dsi_host(struct ti_sn65dsi86 *pdata) 1288 { 1289 struct device_node *np = pdata->dev->of_node; 1290 1291 pdata->host_node = of_graph_get_remote_node(np, 0, 0); 1292 1293 if (!pdata->host_node) { 1294 DRM_ERROR("remote dsi host node not found\n"); 1295 return -ENODEV; 1296 } 1297 1298 return 0; 1299 } 1300 1301 static int ti_sn_bridge_probe(struct auxiliary_device *adev, 1302 const struct auxiliary_device_id *id) 1303 { 1304 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1305 struct device_node *np = pdata->dev->of_node; 1306 int ret; 1307 1308 pdata->next_bridge = devm_drm_of_get_bridge(&adev->dev, np, 1, 0); 1309 if (IS_ERR(pdata->next_bridge)) 1310 return dev_err_probe(&adev->dev, PTR_ERR(pdata->next_bridge), 1311 "failed to create panel bridge\n"); 1312 1313 ti_sn_bridge_parse_lanes(pdata, np); 1314 1315 ret = ti_sn_bridge_parse_dsi_host(pdata); 1316 if (ret) 1317 return ret; 1318 1319 pdata->bridge.of_node = np; 1320 pdata->bridge.type = pdata->next_bridge->type == DRM_MODE_CONNECTOR_DisplayPort 1321 ? DRM_MODE_CONNECTOR_DisplayPort : DRM_MODE_CONNECTOR_eDP; 1322 1323 if (pdata->bridge.type == DRM_MODE_CONNECTOR_DisplayPort) { 1324 pdata->bridge.ops = DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT | 1325 DRM_BRIDGE_OP_HPD; 1326 /* 1327 * If comms were already enabled they would have been enabled 1328 * with the wrong value of HPD_DISABLE. Update it now. Comms 1329 * could be enabled if anyone is holding a pm_runtime reference 1330 * (like if a GPIO is in use). Note that in most cases nobody 1331 * is doing AUX channel xfers before the bridge is added so 1332 * HPD doesn't _really_ matter then. The only exception is in 1333 * the eDP case where the panel wants to read the EDID before 1334 * the bridge is added. We always consistently have HPD disabled 1335 * for eDP. 1336 */ 1337 mutex_lock(&pdata->comms_mutex); 1338 if (pdata->comms_enabled) 1339 regmap_update_bits(pdata->regmap, SN_HPD_DISABLE_REG, 1340 HPD_DISABLE, 0); 1341 mutex_unlock(&pdata->comms_mutex); 1342 } 1343 1344 drm_bridge_add(&pdata->bridge); 1345 1346 ret = ti_sn_attach_host(adev, pdata); 1347 if (ret) { 1348 dev_err_probe(&adev->dev, ret, "failed to attach dsi host\n"); 1349 goto err_remove_bridge; 1350 } 1351 1352 return 0; 1353 1354 err_remove_bridge: 1355 drm_bridge_remove(&pdata->bridge); 1356 return ret; 1357 } 1358 1359 static void ti_sn_bridge_remove(struct auxiliary_device *adev) 1360 { 1361 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1362 1363 if (!pdata) 1364 return; 1365 1366 drm_bridge_remove(&pdata->bridge); 1367 1368 of_node_put(pdata->host_node); 1369 } 1370 1371 static const struct auxiliary_device_id ti_sn_bridge_id_table[] = { 1372 { .name = "ti_sn65dsi86.bridge", }, 1373 {}, 1374 }; 1375 1376 static struct auxiliary_driver ti_sn_bridge_driver = { 1377 .name = "bridge", 1378 .probe = ti_sn_bridge_probe, 1379 .remove = ti_sn_bridge_remove, 1380 .id_table = ti_sn_bridge_id_table, 1381 }; 1382 1383 /* ----------------------------------------------------------------------------- 1384 * PWM Controller 1385 */ 1386 #if IS_REACHABLE(CONFIG_PWM) 1387 static int ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) 1388 { 1389 return atomic_xchg(&pdata->pwm_pin_busy, 1) ? -EBUSY : 0; 1390 } 1391 1392 static void ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) 1393 { 1394 atomic_set(&pdata->pwm_pin_busy, 0); 1395 } 1396 1397 static struct ti_sn65dsi86 *pwm_chip_to_ti_sn_bridge(struct pwm_chip *chip) 1398 { 1399 return pwmchip_get_drvdata(chip); 1400 } 1401 1402 static int ti_sn_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) 1403 { 1404 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1405 1406 return ti_sn_pwm_pin_request(pdata); 1407 } 1408 1409 static void ti_sn_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) 1410 { 1411 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1412 1413 ti_sn_pwm_pin_release(pdata); 1414 } 1415 1416 /* 1417 * Limitations: 1418 * - The PWM signal is not driven when the chip is powered down, or in its 1419 * reset state and the driver does not implement the "suspend state" 1420 * described in the documentation. In order to save power, state->enabled is 1421 * interpreted as denoting if the signal is expected to be valid, and is used 1422 * to determine if the chip needs to be kept powered. 1423 * - Changing both period and duty_cycle is not done atomically, neither is the 1424 * multi-byte register updates, so the output might briefly be undefined 1425 * during update. 1426 */ 1427 static int ti_sn_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, 1428 const struct pwm_state *state) 1429 { 1430 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1431 unsigned int pwm_en_inv; 1432 unsigned int backlight; 1433 unsigned int pre_div; 1434 unsigned int scale; 1435 u64 period_max; 1436 u64 period; 1437 int ret; 1438 1439 if (!pdata->pwm_enabled) { 1440 ret = pm_runtime_resume_and_get(pwmchip_parent(chip)); 1441 if (ret < 0) 1442 return ret; 1443 } 1444 1445 if (state->enabled) { 1446 if (!pdata->pwm_enabled) { 1447 /* 1448 * The chip might have been powered down while we 1449 * didn't hold a PM runtime reference, so mux in the 1450 * PWM function on the GPIO pin again. 1451 */ 1452 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1453 SN_GPIO_MUX_MASK << (2 * SN_PWM_GPIO_IDX), 1454 SN_GPIO_MUX_SPECIAL << (2 * SN_PWM_GPIO_IDX)); 1455 if (ret) { 1456 dev_err(pwmchip_parent(chip), "failed to mux in PWM function\n"); 1457 goto out; 1458 } 1459 } 1460 1461 /* 1462 * Per the datasheet the PWM frequency is given by: 1463 * 1464 * REFCLK_FREQ 1465 * PWM_FREQ = ----------------------------------- 1466 * PWM_PRE_DIV * BACKLIGHT_SCALE + 1 1467 * 1468 * However, after careful review the author is convinced that 1469 * the documentation has lost some parenthesis around 1470 * "BACKLIGHT_SCALE + 1". 1471 * 1472 * With the period T_pwm = 1/PWM_FREQ this can be written: 1473 * 1474 * T_pwm * REFCLK_FREQ = PWM_PRE_DIV * (BACKLIGHT_SCALE + 1) 1475 * 1476 * In order to keep BACKLIGHT_SCALE within its 16 bits, 1477 * PWM_PRE_DIV must be: 1478 * 1479 * T_pwm * REFCLK_FREQ 1480 * PWM_PRE_DIV >= ------------------------- 1481 * BACKLIGHT_SCALE_MAX + 1 1482 * 1483 * To simplify the search and to favour higher resolution of 1484 * the duty cycle over accuracy of the period, the lowest 1485 * possible PWM_PRE_DIV is used. Finally the scale is 1486 * calculated as: 1487 * 1488 * T_pwm * REFCLK_FREQ 1489 * BACKLIGHT_SCALE = ---------------------- - 1 1490 * PWM_PRE_DIV 1491 * 1492 * Here T_pwm is represented in seconds, so appropriate scaling 1493 * to nanoseconds is necessary. 1494 */ 1495 1496 /* Minimum T_pwm is 1 / REFCLK_FREQ */ 1497 if (state->period <= NSEC_PER_SEC / pdata->pwm_refclk_freq) { 1498 ret = -EINVAL; 1499 goto out; 1500 } 1501 1502 /* 1503 * Maximum T_pwm is 255 * (65535 + 1) / REFCLK_FREQ 1504 * Limit period to this to avoid overflows 1505 */ 1506 period_max = div_u64((u64)NSEC_PER_SEC * 255 * (65535 + 1), 1507 pdata->pwm_refclk_freq); 1508 period = min(state->period, period_max); 1509 1510 pre_div = DIV64_U64_ROUND_UP(period * pdata->pwm_refclk_freq, 1511 (u64)NSEC_PER_SEC * (BACKLIGHT_SCALE_MAX + 1)); 1512 scale = div64_u64(period * pdata->pwm_refclk_freq, (u64)NSEC_PER_SEC * pre_div) - 1; 1513 1514 /* 1515 * The documentation has the duty ratio given as: 1516 * 1517 * duty BACKLIGHT 1518 * ------- = --------------------- 1519 * period BACKLIGHT_SCALE + 1 1520 * 1521 * Solve for BACKLIGHT, substituting BACKLIGHT_SCALE according 1522 * to definition above and adjusting for nanosecond 1523 * representation of duty cycle gives us: 1524 */ 1525 backlight = div64_u64(state->duty_cycle * pdata->pwm_refclk_freq, 1526 (u64)NSEC_PER_SEC * pre_div); 1527 if (backlight > scale) 1528 backlight = scale; 1529 1530 ret = regmap_write(pdata->regmap, SN_PWM_PRE_DIV_REG, pre_div); 1531 if (ret) { 1532 dev_err(pwmchip_parent(chip), "failed to update PWM_PRE_DIV\n"); 1533 goto out; 1534 } 1535 1536 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_SCALE_REG, scale); 1537 ti_sn65dsi86_write_u16(pdata, SN_BACKLIGHT_REG, backlight); 1538 } 1539 1540 pwm_en_inv = FIELD_PREP(SN_PWM_EN_MASK, state->enabled) | 1541 FIELD_PREP(SN_PWM_INV_MASK, state->polarity == PWM_POLARITY_INVERSED); 1542 ret = regmap_write(pdata->regmap, SN_PWM_EN_INV_REG, pwm_en_inv); 1543 if (ret) { 1544 dev_err(pwmchip_parent(chip), "failed to update PWM_EN/PWM_INV\n"); 1545 goto out; 1546 } 1547 1548 pdata->pwm_enabled = state->enabled; 1549 out: 1550 1551 if (!pdata->pwm_enabled) 1552 pm_runtime_put_sync(pwmchip_parent(chip)); 1553 1554 return ret; 1555 } 1556 1557 static int ti_sn_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, 1558 struct pwm_state *state) 1559 { 1560 struct ti_sn65dsi86 *pdata = pwm_chip_to_ti_sn_bridge(chip); 1561 unsigned int pwm_en_inv; 1562 unsigned int pre_div; 1563 u16 backlight; 1564 u16 scale; 1565 int ret; 1566 1567 ret = regmap_read(pdata->regmap, SN_PWM_EN_INV_REG, &pwm_en_inv); 1568 if (ret) 1569 return ret; 1570 1571 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_SCALE_REG, &scale); 1572 if (ret) 1573 return ret; 1574 1575 ret = ti_sn65dsi86_read_u16(pdata, SN_BACKLIGHT_REG, &backlight); 1576 if (ret) 1577 return ret; 1578 1579 ret = regmap_read(pdata->regmap, SN_PWM_PRE_DIV_REG, &pre_div); 1580 if (ret) 1581 return ret; 1582 1583 state->enabled = FIELD_GET(SN_PWM_EN_MASK, pwm_en_inv); 1584 if (FIELD_GET(SN_PWM_INV_MASK, pwm_en_inv)) 1585 state->polarity = PWM_POLARITY_INVERSED; 1586 else 1587 state->polarity = PWM_POLARITY_NORMAL; 1588 1589 state->period = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * (scale + 1), 1590 pdata->pwm_refclk_freq); 1591 state->duty_cycle = DIV_ROUND_UP_ULL((u64)NSEC_PER_SEC * pre_div * backlight, 1592 pdata->pwm_refclk_freq); 1593 1594 if (state->duty_cycle > state->period) 1595 state->duty_cycle = state->period; 1596 1597 return 0; 1598 } 1599 1600 static const struct pwm_ops ti_sn_pwm_ops = { 1601 .request = ti_sn_pwm_request, 1602 .free = ti_sn_pwm_free, 1603 .apply = ti_sn_pwm_apply, 1604 .get_state = ti_sn_pwm_get_state, 1605 }; 1606 1607 static int ti_sn_pwm_probe(struct auxiliary_device *adev, 1608 const struct auxiliary_device_id *id) 1609 { 1610 struct pwm_chip *chip; 1611 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1612 1613 pdata->pchip = chip = devm_pwmchip_alloc(&adev->dev, 1, 0); 1614 if (IS_ERR(chip)) 1615 return PTR_ERR(chip); 1616 1617 pwmchip_set_drvdata(chip, pdata); 1618 1619 chip->ops = &ti_sn_pwm_ops; 1620 chip->of_xlate = of_pwm_single_xlate; 1621 1622 devm_pm_runtime_enable(&adev->dev); 1623 1624 return pwmchip_add(chip); 1625 } 1626 1627 static void ti_sn_pwm_remove(struct auxiliary_device *adev) 1628 { 1629 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1630 1631 pwmchip_remove(pdata->pchip); 1632 1633 if (pdata->pwm_enabled) 1634 pm_runtime_put_sync(&adev->dev); 1635 } 1636 1637 static const struct auxiliary_device_id ti_sn_pwm_id_table[] = { 1638 { .name = "ti_sn65dsi86.pwm", }, 1639 {}, 1640 }; 1641 1642 static struct auxiliary_driver ti_sn_pwm_driver = { 1643 .name = "pwm", 1644 .probe = ti_sn_pwm_probe, 1645 .remove = ti_sn_pwm_remove, 1646 .id_table = ti_sn_pwm_id_table, 1647 }; 1648 1649 static int __init ti_sn_pwm_register(void) 1650 { 1651 return auxiliary_driver_register(&ti_sn_pwm_driver); 1652 } 1653 1654 static void ti_sn_pwm_unregister(void) 1655 { 1656 auxiliary_driver_unregister(&ti_sn_pwm_driver); 1657 } 1658 1659 #else 1660 static inline int __maybe_unused ti_sn_pwm_pin_request(struct ti_sn65dsi86 *pdata) { return 0; } 1661 static inline void __maybe_unused ti_sn_pwm_pin_release(struct ti_sn65dsi86 *pdata) {} 1662 1663 static inline int ti_sn_pwm_register(void) { return 0; } 1664 static inline void ti_sn_pwm_unregister(void) {} 1665 #endif 1666 1667 /* ----------------------------------------------------------------------------- 1668 * GPIO Controller 1669 */ 1670 #if defined(CONFIG_OF_GPIO) 1671 1672 static int tn_sn_bridge_of_xlate(struct gpio_chip *chip, 1673 const struct of_phandle_args *gpiospec, 1674 u32 *flags) 1675 { 1676 if (WARN_ON(gpiospec->args_count < chip->of_gpio_n_cells)) 1677 return -EINVAL; 1678 1679 if (gpiospec->args[0] > chip->ngpio || gpiospec->args[0] < 1) 1680 return -EINVAL; 1681 1682 if (flags) 1683 *flags = gpiospec->args[1]; 1684 1685 return gpiospec->args[0] - SN_GPIO_PHYSICAL_OFFSET; 1686 } 1687 1688 static int ti_sn_bridge_gpio_get_direction(struct gpio_chip *chip, 1689 unsigned int offset) 1690 { 1691 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1692 1693 /* 1694 * We already have to keep track of the direction because we use 1695 * that to figure out whether we've powered the device. We can 1696 * just return that rather than (maybe) powering up the device 1697 * to ask its direction. 1698 */ 1699 return test_bit(offset, pdata->gchip_output) ? 1700 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1701 } 1702 1703 static int ti_sn_bridge_gpio_get(struct gpio_chip *chip, unsigned int offset) 1704 { 1705 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1706 unsigned int val; 1707 int ret; 1708 1709 /* 1710 * When the pin is an input we don't forcibly keep the bridge 1711 * powered--we just power it on to read the pin. NOTE: part of 1712 * the reason this works is that the bridge defaults (when 1713 * powered back on) to all 4 GPIOs being configured as GPIO input. 1714 * Also note that if something else is keeping the chip powered the 1715 * pm_runtime functions are lightweight increments of a refcount. 1716 */ 1717 pm_runtime_get_sync(pdata->dev); 1718 ret = regmap_read(pdata->regmap, SN_GPIO_IO_REG, &val); 1719 pm_runtime_put_autosuspend(pdata->dev); 1720 1721 if (ret) 1722 return ret; 1723 1724 return !!(val & BIT(SN_GPIO_INPUT_SHIFT + offset)); 1725 } 1726 1727 static int ti_sn_bridge_gpio_set(struct gpio_chip *chip, unsigned int offset, 1728 int val) 1729 { 1730 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1731 1732 val &= 1; 1733 return regmap_update_bits(pdata->regmap, SN_GPIO_IO_REG, 1734 BIT(SN_GPIO_OUTPUT_SHIFT + offset), 1735 val << (SN_GPIO_OUTPUT_SHIFT + offset)); 1736 } 1737 1738 static int ti_sn_bridge_gpio_direction_input(struct gpio_chip *chip, 1739 unsigned int offset) 1740 { 1741 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1742 int shift = offset * 2; 1743 int ret; 1744 1745 if (!test_and_clear_bit(offset, pdata->gchip_output)) 1746 return 0; 1747 1748 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1749 SN_GPIO_MUX_MASK << shift, 1750 SN_GPIO_MUX_INPUT << shift); 1751 if (ret) { 1752 set_bit(offset, pdata->gchip_output); 1753 return ret; 1754 } 1755 1756 /* 1757 * NOTE: if nobody else is powering the device this may fully power 1758 * it off and when it comes back it will have lost all state, but 1759 * that's OK because the default is input and we're now an input. 1760 */ 1761 pm_runtime_put_autosuspend(pdata->dev); 1762 1763 return 0; 1764 } 1765 1766 static int ti_sn_bridge_gpio_direction_output(struct gpio_chip *chip, 1767 unsigned int offset, int val) 1768 { 1769 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1770 int shift = offset * 2; 1771 int ret; 1772 1773 if (test_and_set_bit(offset, pdata->gchip_output)) 1774 return 0; 1775 1776 pm_runtime_get_sync(pdata->dev); 1777 1778 /* Set value first to avoid glitching */ 1779 ti_sn_bridge_gpio_set(chip, offset, val); 1780 1781 /* Set direction */ 1782 ret = regmap_update_bits(pdata->regmap, SN_GPIO_CTRL_REG, 1783 SN_GPIO_MUX_MASK << shift, 1784 SN_GPIO_MUX_OUTPUT << shift); 1785 if (ret) { 1786 clear_bit(offset, pdata->gchip_output); 1787 pm_runtime_put_autosuspend(pdata->dev); 1788 } 1789 1790 return ret; 1791 } 1792 1793 static int ti_sn_bridge_gpio_request(struct gpio_chip *chip, unsigned int offset) 1794 { 1795 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1796 1797 if (offset == SN_PWM_GPIO_IDX) 1798 return ti_sn_pwm_pin_request(pdata); 1799 1800 return 0; 1801 } 1802 1803 static void ti_sn_bridge_gpio_free(struct gpio_chip *chip, unsigned int offset) 1804 { 1805 struct ti_sn65dsi86 *pdata = gpiochip_get_data(chip); 1806 1807 /* We won't keep pm_runtime if we're input, so switch there on free */ 1808 ti_sn_bridge_gpio_direction_input(chip, offset); 1809 1810 if (offset == SN_PWM_GPIO_IDX) 1811 ti_sn_pwm_pin_release(pdata); 1812 } 1813 1814 static const char * const ti_sn_bridge_gpio_names[SN_NUM_GPIOS] = { 1815 "GPIO1", "GPIO2", "GPIO3", "GPIO4" 1816 }; 1817 1818 static int ti_sn_gpio_probe(struct auxiliary_device *adev, 1819 const struct auxiliary_device_id *id) 1820 { 1821 struct ti_sn65dsi86 *pdata = dev_get_drvdata(adev->dev.parent); 1822 int ret; 1823 1824 /* Only init if someone is going to use us as a GPIO controller */ 1825 if (!of_property_read_bool(pdata->dev->of_node, "gpio-controller")) 1826 return 0; 1827 1828 pdata->gchip.label = dev_name(pdata->dev); 1829 pdata->gchip.parent = pdata->dev; 1830 pdata->gchip.owner = THIS_MODULE; 1831 pdata->gchip.of_xlate = tn_sn_bridge_of_xlate; 1832 pdata->gchip.of_gpio_n_cells = 2; 1833 pdata->gchip.request = ti_sn_bridge_gpio_request; 1834 pdata->gchip.free = ti_sn_bridge_gpio_free; 1835 pdata->gchip.get_direction = ti_sn_bridge_gpio_get_direction; 1836 pdata->gchip.direction_input = ti_sn_bridge_gpio_direction_input; 1837 pdata->gchip.direction_output = ti_sn_bridge_gpio_direction_output; 1838 pdata->gchip.get = ti_sn_bridge_gpio_get; 1839 pdata->gchip.set = ti_sn_bridge_gpio_set; 1840 pdata->gchip.can_sleep = true; 1841 pdata->gchip.names = ti_sn_bridge_gpio_names; 1842 pdata->gchip.ngpio = SN_NUM_GPIOS; 1843 pdata->gchip.base = -1; 1844 ret = devm_gpiochip_add_data(&adev->dev, &pdata->gchip, pdata); 1845 if (ret) 1846 dev_err(pdata->dev, "can't add gpio chip\n"); 1847 1848 return ret; 1849 } 1850 1851 static const struct auxiliary_device_id ti_sn_gpio_id_table[] = { 1852 { .name = "ti_sn65dsi86.gpio", }, 1853 {}, 1854 }; 1855 1856 MODULE_DEVICE_TABLE(auxiliary, ti_sn_gpio_id_table); 1857 1858 static struct auxiliary_driver ti_sn_gpio_driver = { 1859 .name = "gpio", 1860 .probe = ti_sn_gpio_probe, 1861 .id_table = ti_sn_gpio_id_table, 1862 }; 1863 1864 static int __init ti_sn_gpio_register(void) 1865 { 1866 return auxiliary_driver_register(&ti_sn_gpio_driver); 1867 } 1868 1869 static void ti_sn_gpio_unregister(void) 1870 { 1871 auxiliary_driver_unregister(&ti_sn_gpio_driver); 1872 } 1873 1874 #else 1875 1876 static inline int ti_sn_gpio_register(void) { return 0; } 1877 static inline void ti_sn_gpio_unregister(void) {} 1878 1879 #endif 1880 1881 /* ----------------------------------------------------------------------------- 1882 * Probe & Remove 1883 */ 1884 1885 static void ti_sn65dsi86_runtime_disable(void *data) 1886 { 1887 pm_runtime_dont_use_autosuspend(data); 1888 pm_runtime_disable(data); 1889 } 1890 1891 static int ti_sn65dsi86_parse_regulators(struct ti_sn65dsi86 *pdata) 1892 { 1893 unsigned int i; 1894 const char * const ti_sn_bridge_supply_names[] = { 1895 "vcca", "vcc", "vccio", "vpll", 1896 }; 1897 1898 for (i = 0; i < SN_REGULATOR_SUPPLY_NUM; i++) 1899 pdata->supplies[i].supply = ti_sn_bridge_supply_names[i]; 1900 1901 return devm_regulator_bulk_get(pdata->dev, SN_REGULATOR_SUPPLY_NUM, 1902 pdata->supplies); 1903 } 1904 1905 static int ti_sn65dsi86_probe(struct i2c_client *client) 1906 { 1907 struct device *dev = &client->dev; 1908 struct ti_sn65dsi86 *pdata; 1909 u8 id_buf[8]; 1910 int ret; 1911 1912 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1913 DRM_ERROR("device doesn't support I2C\n"); 1914 return -ENODEV; 1915 } 1916 1917 pdata = devm_drm_bridge_alloc(dev, struct ti_sn65dsi86, bridge, &ti_sn_bridge_funcs); 1918 if (IS_ERR(pdata)) 1919 return PTR_ERR(pdata); 1920 dev_set_drvdata(dev, pdata); 1921 pdata->dev = dev; 1922 1923 mutex_init(&pdata->comms_mutex); 1924 1925 pdata->regmap = devm_regmap_init_i2c(client, 1926 &ti_sn65dsi86_regmap_config); 1927 if (IS_ERR(pdata->regmap)) 1928 return dev_err_probe(dev, PTR_ERR(pdata->regmap), 1929 "regmap i2c init failed\n"); 1930 1931 pdata->enable_gpio = devm_gpiod_get_optional(dev, "enable", 1932 GPIOD_OUT_LOW); 1933 if (IS_ERR(pdata->enable_gpio)) 1934 return dev_err_probe(dev, PTR_ERR(pdata->enable_gpio), 1935 "failed to get enable gpio from DT\n"); 1936 1937 ret = ti_sn65dsi86_parse_regulators(pdata); 1938 if (ret) 1939 return dev_err_probe(dev, ret, "failed to parse regulators\n"); 1940 1941 pdata->refclk = devm_clk_get_optional(dev, "refclk"); 1942 if (IS_ERR(pdata->refclk)) 1943 return dev_err_probe(dev, PTR_ERR(pdata->refclk), 1944 "failed to get reference clock\n"); 1945 1946 pm_runtime_enable(dev); 1947 pm_runtime_set_autosuspend_delay(pdata->dev, 500); 1948 pm_runtime_use_autosuspend(pdata->dev); 1949 ret = devm_add_action_or_reset(dev, ti_sn65dsi86_runtime_disable, dev); 1950 if (ret) 1951 return ret; 1952 1953 pm_runtime_get_sync(dev); 1954 ret = regmap_bulk_read(pdata->regmap, SN_DEVICE_ID_REGS, id_buf, ARRAY_SIZE(id_buf)); 1955 pm_runtime_put_autosuspend(dev); 1956 if (ret) 1957 return dev_err_probe(dev, ret, "failed to read device id\n"); 1958 1959 /* The ID string is stored backwards */ 1960 if (strncmp(id_buf, "68ISD ", ARRAY_SIZE(id_buf))) 1961 return dev_err_probe(dev, -EOPNOTSUPP, "unsupported device id\n"); 1962 1963 /* 1964 * Break ourselves up into a collection of aux devices. The only real 1965 * motiviation here is to solve the chicken-and-egg problem of probe 1966 * ordering. The bridge wants the panel to be there when it probes. 1967 * The panel wants its HPD GPIO (provided by sn65dsi86 on some boards) 1968 * when it probes. The panel and maybe backlight might want the DDC 1969 * bus or the pwm_chip. Having sub-devices allows the some sub devices 1970 * to finish probing even if others return -EPROBE_DEFER and gets us 1971 * around the problems. 1972 */ 1973 1974 if (IS_ENABLED(CONFIG_OF_GPIO)) { 1975 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->gpio_aux, "gpio"); 1976 if (ret) 1977 return ret; 1978 } 1979 1980 if (IS_REACHABLE(CONFIG_PWM)) { 1981 ret = ti_sn65dsi86_add_aux_device(pdata, &pdata->pwm_aux, "pwm"); 1982 if (ret) 1983 return ret; 1984 } 1985 1986 /* 1987 * NOTE: At the end of the AUX channel probe we'll add the aux device 1988 * for the bridge. This is because the bridge can't be used until the 1989 * AUX channel is there and this is a very simple solution to the 1990 * dependency problem. 1991 */ 1992 return ti_sn65dsi86_add_aux_device(pdata, &pdata->aux_aux, "aux"); 1993 } 1994 1995 static const struct i2c_device_id ti_sn65dsi86_id[] = { 1996 { "ti,sn65dsi86" }, 1997 {} 1998 }; 1999 MODULE_DEVICE_TABLE(i2c, ti_sn65dsi86_id); 2000 2001 static const struct of_device_id ti_sn65dsi86_match_table[] = { 2002 {.compatible = "ti,sn65dsi86"}, 2003 {}, 2004 }; 2005 MODULE_DEVICE_TABLE(of, ti_sn65dsi86_match_table); 2006 2007 static struct i2c_driver ti_sn65dsi86_driver = { 2008 .driver = { 2009 .name = "ti_sn65dsi86", 2010 .of_match_table = ti_sn65dsi86_match_table, 2011 .pm = &ti_sn65dsi86_pm_ops, 2012 }, 2013 .probe = ti_sn65dsi86_probe, 2014 .id_table = ti_sn65dsi86_id, 2015 }; 2016 2017 static int __init ti_sn65dsi86_init(void) 2018 { 2019 int ret; 2020 2021 ret = i2c_add_driver(&ti_sn65dsi86_driver); 2022 if (ret) 2023 return ret; 2024 2025 ret = ti_sn_gpio_register(); 2026 if (ret) 2027 goto err_main_was_registered; 2028 2029 ret = ti_sn_pwm_register(); 2030 if (ret) 2031 goto err_gpio_was_registered; 2032 2033 ret = auxiliary_driver_register(&ti_sn_aux_driver); 2034 if (ret) 2035 goto err_pwm_was_registered; 2036 2037 ret = auxiliary_driver_register(&ti_sn_bridge_driver); 2038 if (ret) 2039 goto err_aux_was_registered; 2040 2041 return 0; 2042 2043 err_aux_was_registered: 2044 auxiliary_driver_unregister(&ti_sn_aux_driver); 2045 err_pwm_was_registered: 2046 ti_sn_pwm_unregister(); 2047 err_gpio_was_registered: 2048 ti_sn_gpio_unregister(); 2049 err_main_was_registered: 2050 i2c_del_driver(&ti_sn65dsi86_driver); 2051 2052 return ret; 2053 } 2054 module_init(ti_sn65dsi86_init); 2055 2056 static void __exit ti_sn65dsi86_exit(void) 2057 { 2058 auxiliary_driver_unregister(&ti_sn_bridge_driver); 2059 auxiliary_driver_unregister(&ti_sn_aux_driver); 2060 ti_sn_pwm_unregister(); 2061 ti_sn_gpio_unregister(); 2062 i2c_del_driver(&ti_sn65dsi86_driver); 2063 } 2064 module_exit(ti_sn65dsi86_exit); 2065 2066 MODULE_AUTHOR("Sandeep Panda <spanda@codeaurora.org>"); 2067 MODULE_DESCRIPTION("sn65dsi86 DSI to eDP bridge driver"); 2068 MODULE_LICENSE("GPL v2"); 2069