1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * TI SN65DSI83,84,85 driver 4 * 5 * Currently supported: 6 * - SN65DSI83 7 * = 1x Single-link DSI ~ 1x Single-link LVDS 8 * - Supported 9 * - Single-link LVDS mode tested 10 * - SN65DSI84 11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS 12 * - Supported 13 * - Dual-link LVDS mode tested 14 * - 2x Single-link LVDS mode unsupported 15 * (should be easy to add by someone who has the HW) 16 * - SN65DSI85 17 * = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS 18 * - Unsupported 19 * (should be easy to add by someone who has the HW) 20 * 21 * Copyright (C) 2021 Marek Vasut <marex@denx.de> 22 * 23 * Based on previous work of: 24 * Valentin Raevsky <valentin@compulab.co.il> 25 * Philippe Schenker <philippe.schenker@toradex.com> 26 */ 27 28 #include <linux/bits.h> 29 #include <linux/clk.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/i2c.h> 32 #include <linux/media-bus-format.h> 33 #include <linux/module.h> 34 #include <linux/of.h> 35 #include <linux/of_graph.h> 36 #include <linux/regmap.h> 37 #include <linux/regulator/consumer.h> 38 39 #include <drm/drm_atomic_helper.h> 40 #include <drm/drm_bridge.h> 41 #include <drm/drm_mipi_dsi.h> 42 #include <drm/drm_of.h> 43 #include <drm/drm_panel.h> 44 #include <drm/drm_print.h> 45 #include <drm/drm_probe_helper.h> 46 47 /* ID registers */ 48 #define REG_ID(n) (0x00 + (n)) 49 /* Reset and clock registers */ 50 #define REG_RC_RESET 0x09 51 #define REG_RC_RESET_SOFT_RESET BIT(0) 52 #define REG_RC_LVDS_PLL 0x0a 53 #define REG_RC_LVDS_PLL_PLL_EN_STAT BIT(7) 54 #define REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n) (((n) & 0x7) << 1) 55 #define REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY BIT(0) 56 #define REG_RC_DSI_CLK 0x0b 57 #define REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n) (((n) & 0x1f) << 3) 58 #define REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n) ((n) & 0x3) 59 #define REG_RC_PLL_EN 0x0d 60 #define REG_RC_PLL_EN_PLL_EN BIT(0) 61 /* DSI registers */ 62 #define REG_DSI_LANE 0x10 63 #define REG_DSI_LANE_LEFT_RIGHT_PIXELS BIT(7) /* DSI85-only */ 64 #define REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0 /* DSI85-only */ 65 #define REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE BIT(6) /* DSI85-only */ 66 #define REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE BIT(5) 67 #define REG_DSI_LANE_CHA_DSI_LANES(n) (((n) & 0x3) << 3) 68 #define REG_DSI_LANE_CHB_DSI_LANES(n) (((n) & 0x3) << 1) 69 #define REG_DSI_LANE_SOT_ERR_TOL_DIS BIT(0) 70 #define REG_DSI_EQ 0x11 71 #define REG_DSI_EQ_CHA_DSI_DATA_EQ(n) (((n) & 0x3) << 6) 72 #define REG_DSI_EQ_CHA_DSI_CLK_EQ(n) (((n) & 0x3) << 2) 73 #define REG_DSI_CLK 0x12 74 #define REG_DSI_CLK_CHA_DSI_CLK_RANGE(n) ((n) & 0xff) 75 /* LVDS registers */ 76 #define REG_LVDS_FMT 0x18 77 #define REG_LVDS_FMT_DE_NEG_POLARITY BIT(7) 78 #define REG_LVDS_FMT_HS_NEG_POLARITY BIT(6) 79 #define REG_LVDS_FMT_VS_NEG_POLARITY BIT(5) 80 #define REG_LVDS_FMT_LVDS_LINK_CFG BIT(4) /* 0:AB 1:A-only */ 81 #define REG_LVDS_FMT_CHA_24BPP_MODE BIT(3) 82 #define REG_LVDS_FMT_CHB_24BPP_MODE BIT(2) 83 #define REG_LVDS_FMT_CHA_24BPP_FORMAT1 BIT(1) 84 #define REG_LVDS_FMT_CHB_24BPP_FORMAT1 BIT(0) 85 #define REG_LVDS_VCOM 0x19 86 #define REG_LVDS_VCOM_CHA_LVDS_VOCM BIT(6) 87 #define REG_LVDS_VCOM_CHB_LVDS_VOCM BIT(4) 88 #define REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n) (((n) & 0x3) << 2) 89 #define REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n) ((n) & 0x3) 90 #define REG_LVDS_LANE 0x1a 91 #define REG_LVDS_LANE_EVEN_ODD_SWAP BIT(6) 92 #define REG_LVDS_LANE_CHA_REVERSE_LVDS BIT(5) 93 #define REG_LVDS_LANE_CHB_REVERSE_LVDS BIT(4) 94 #define REG_LVDS_LANE_CHA_LVDS_TERM BIT(1) 95 #define REG_LVDS_LANE_CHB_LVDS_TERM BIT(0) 96 #define REG_LVDS_CM 0x1b 97 #define REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n) (((n) & 0x3) << 4) 98 #define REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n) ((n) & 0x3) 99 /* Video registers */ 100 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW 0x20 101 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21 102 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW 0x24 103 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x25 104 #define REG_VID_CHA_SYNC_DELAY_LOW 0x28 105 #define REG_VID_CHA_SYNC_DELAY_HIGH 0x29 106 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW 0x2c 107 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2d 108 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30 109 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31 110 #define REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34 111 #define REG_VID_CHA_VERTICAL_BACK_PORCH 0x36 112 #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38 113 #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a 114 #define REG_VID_CHA_TEST_PATTERN 0x3c 115 /* IRQ registers */ 116 #define REG_IRQ_GLOBAL 0xe0 117 #define REG_IRQ_GLOBAL_IRQ_EN BIT(0) 118 #define REG_IRQ_EN 0xe1 119 #define REG_IRQ_EN_CHA_SYNCH_ERR_EN BIT(7) 120 #define REG_IRQ_EN_CHA_CRC_ERR_EN BIT(6) 121 #define REG_IRQ_EN_CHA_UNC_ECC_ERR_EN BIT(5) 122 #define REG_IRQ_EN_CHA_COR_ECC_ERR_EN BIT(4) 123 #define REG_IRQ_EN_CHA_LLP_ERR_EN BIT(3) 124 #define REG_IRQ_EN_CHA_SOT_BIT_ERR_EN BIT(2) 125 #define REG_IRQ_EN_CHA_PLL_UNLOCK_EN BIT(0) 126 #define REG_IRQ_STAT 0xe5 127 #define REG_IRQ_STAT_CHA_SYNCH_ERR BIT(7) 128 #define REG_IRQ_STAT_CHA_CRC_ERR BIT(6) 129 #define REG_IRQ_STAT_CHA_UNC_ECC_ERR BIT(5) 130 #define REG_IRQ_STAT_CHA_COR_ECC_ERR BIT(4) 131 #define REG_IRQ_STAT_CHA_LLP_ERR BIT(3) 132 #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2) 133 #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0) 134 135 enum sn65dsi83_channel { 136 CHANNEL_A, 137 CHANNEL_B 138 }; 139 140 enum sn65dsi83_lvds_term { 141 OHM_100, 142 OHM_200 143 }; 144 145 enum sn65dsi83_model { 146 MODEL_SN65DSI83, 147 MODEL_SN65DSI84, 148 }; 149 150 struct sn65dsi83 { 151 struct drm_bridge bridge; 152 struct device *dev; 153 struct regmap *regmap; 154 struct mipi_dsi_device *dsi; 155 struct drm_bridge *panel_bridge; 156 struct gpio_desc *enable_gpio; 157 struct regulator *vcc; 158 bool lvds_dual_link; 159 bool lvds_dual_link_even_odd_swap; 160 int lvds_vod_swing_conf[2]; 161 int lvds_term_conf[2]; 162 }; 163 164 static const struct regmap_range sn65dsi83_readable_ranges[] = { 165 regmap_reg_range(REG_ID(0), REG_ID(8)), 166 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK), 167 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 168 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 169 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 170 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 171 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 172 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 173 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 174 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 175 REG_VID_CHA_SYNC_DELAY_HIGH), 176 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 177 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 178 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 179 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 180 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 181 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 182 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 183 REG_VID_CHA_VERTICAL_BACK_PORCH), 184 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 185 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 186 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 187 REG_VID_CHA_VERTICAL_FRONT_PORCH), 188 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 189 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 190 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 191 }; 192 193 static const struct regmap_access_table sn65dsi83_readable_table = { 194 .yes_ranges = sn65dsi83_readable_ranges, 195 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges), 196 }; 197 198 static const struct regmap_range sn65dsi83_writeable_ranges[] = { 199 regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK), 200 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 201 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 202 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 203 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 204 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 205 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 206 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 207 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 208 REG_VID_CHA_SYNC_DELAY_HIGH), 209 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 210 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 211 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 212 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 213 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 214 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 215 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 216 REG_VID_CHA_VERTICAL_BACK_PORCH), 217 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 218 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 219 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 220 REG_VID_CHA_VERTICAL_FRONT_PORCH), 221 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 222 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 223 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 224 }; 225 226 static const struct regmap_access_table sn65dsi83_writeable_table = { 227 .yes_ranges = sn65dsi83_writeable_ranges, 228 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges), 229 }; 230 231 static const struct regmap_range sn65dsi83_volatile_ranges[] = { 232 regmap_reg_range(REG_RC_RESET, REG_RC_RESET), 233 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL), 234 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 235 }; 236 237 static const struct regmap_access_table sn65dsi83_volatile_table = { 238 .yes_ranges = sn65dsi83_volatile_ranges, 239 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges), 240 }; 241 242 static const struct regmap_config sn65dsi83_regmap_config = { 243 .reg_bits = 8, 244 .val_bits = 8, 245 .rd_table = &sn65dsi83_readable_table, 246 .wr_table = &sn65dsi83_writeable_table, 247 .volatile_table = &sn65dsi83_volatile_table, 248 .cache_type = REGCACHE_MAPLE, 249 .max_register = REG_IRQ_STAT, 250 }; 251 252 static const int lvds_vod_swing_data_table[2][4][2] = { 253 { /* 100 Ohm */ 254 { 180000, 313000 }, 255 { 215000, 372000 }, 256 { 250000, 430000 }, 257 { 290000, 488000 }, 258 }, 259 { /* 200 Ohm */ 260 { 150000, 261000 }, 261 { 200000, 346000 }, 262 { 250000, 428000 }, 263 { 300000, 511000 }, 264 }, 265 }; 266 267 static const int lvds_vod_swing_clock_table[2][4][2] = { 268 { /* 100 Ohm */ 269 { 140000, 244000 }, 270 { 168000, 290000 }, 271 { 195000, 335000 }, 272 { 226000, 381000 }, 273 }, 274 { /* 200 Ohm */ 275 { 117000, 204000 }, 276 { 156000, 270000 }, 277 { 195000, 334000 }, 278 { 234000, 399000 }, 279 }, 280 }; 281 282 static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge) 283 { 284 return container_of(bridge, struct sn65dsi83, bridge); 285 } 286 287 static int sn65dsi83_attach(struct drm_bridge *bridge, 288 enum drm_bridge_attach_flags flags) 289 { 290 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 291 292 return drm_bridge_attach(bridge->encoder, ctx->panel_bridge, 293 &ctx->bridge, flags); 294 } 295 296 static void sn65dsi83_detach(struct drm_bridge *bridge) 297 { 298 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 299 300 if (!ctx->dsi) 301 return; 302 303 ctx->dsi = NULL; 304 } 305 306 static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx, 307 const struct drm_display_mode *mode) 308 { 309 /* 310 * The encoding of the LVDS_CLK_RANGE is as follows: 311 * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz 312 * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz 313 * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz 314 * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz 315 * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz 316 * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz 317 * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that 318 * the ends of the ranges are clamped to the supported range. Since 319 * sn65dsi83_mode_valid() already filters the valid modes and limits 320 * the clock to 25..154 MHz, the range calculation can be simplified 321 * as follows: 322 */ 323 int mode_clock = mode->clock; 324 325 if (ctx->lvds_dual_link) 326 mode_clock /= 2; 327 328 return (mode_clock - 12500) / 25000; 329 } 330 331 static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx, 332 const struct drm_display_mode *mode) 333 { 334 /* 335 * The encoding of the CHA_DSI_CLK_RANGE is as follows: 336 * 0x00 through 0x07 - Reserved 337 * 0x08 - 40 <= DSI_CLK < 45 MHz 338 * 0x09 - 45 <= DSI_CLK < 50 MHz 339 * ... 340 * 0x63 - 495 <= DSI_CLK < 500 MHz 341 * 0x64 - 500 MHz 342 * 0x65 through 0xFF - Reserved 343 * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz. 344 * The DSI clock are calculated as: 345 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2 346 * the 2 is there because the bus is DDR. 347 */ 348 return DIV_ROUND_UP(clamp((unsigned int)mode->clock * 349 mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) / 350 ctx->dsi->lanes / 2, 40000U, 500000U), 5000U); 351 } 352 353 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx) 354 { 355 /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */ 356 unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format); 357 358 dsi_div /= ctx->dsi->lanes; 359 360 if (!ctx->lvds_dual_link) 361 dsi_div /= 2; 362 363 return dsi_div - 1; 364 } 365 366 static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, 367 struct drm_bridge_state *old_bridge_state) 368 { 369 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 370 struct drm_atomic_state *state = old_bridge_state->base.state; 371 const struct drm_bridge_state *bridge_state; 372 const struct drm_crtc_state *crtc_state; 373 const struct drm_display_mode *mode; 374 struct drm_connector *connector; 375 struct drm_crtc *crtc; 376 bool lvds_format_24bpp; 377 bool lvds_format_jeida; 378 unsigned int pval; 379 __le16 le16val; 380 u16 val; 381 int ret; 382 383 ret = regulator_enable(ctx->vcc); 384 if (ret) { 385 dev_err(ctx->dev, "Failed to enable vcc: %d\n", ret); 386 return; 387 } 388 389 /* Deassert reset */ 390 gpiod_set_value_cansleep(ctx->enable_gpio, 1); 391 usleep_range(10000, 11000); 392 393 /* Get the LVDS format from the bridge state. */ 394 bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 395 396 switch (bridge_state->output_bus_cfg.format) { 397 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 398 lvds_format_24bpp = false; 399 lvds_format_jeida = true; 400 break; 401 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 402 lvds_format_24bpp = true; 403 lvds_format_jeida = true; 404 break; 405 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 406 lvds_format_24bpp = true; 407 lvds_format_jeida = false; 408 break; 409 default: 410 /* 411 * Some bridges still don't set the correct 412 * LVDS bus pixel format, use SPWG24 default 413 * format until those are fixed. 414 */ 415 lvds_format_24bpp = true; 416 lvds_format_jeida = false; 417 dev_warn(ctx->dev, 418 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", 419 bridge_state->output_bus_cfg.format); 420 break; 421 } 422 423 /* 424 * Retrieve the CRTC adjusted mode. This requires a little dance to go 425 * from the bridge to the encoder, to the connector and to the CRTC. 426 */ 427 connector = drm_atomic_get_new_connector_for_encoder(state, 428 bridge->encoder); 429 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 430 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 431 mode = &crtc_state->adjusted_mode; 432 433 /* Clear reset, disable PLL */ 434 regmap_write(ctx->regmap, REG_RC_RESET, 0x00); 435 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 436 437 /* Reference clock derived from DSI link clock. */ 438 regmap_write(ctx->regmap, REG_RC_LVDS_PLL, 439 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) | 440 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY); 441 regmap_write(ctx->regmap, REG_DSI_CLK, 442 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx, mode))); 443 regmap_write(ctx->regmap, REG_RC_DSI_CLK, 444 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx))); 445 446 /* Set number of DSI lanes and LVDS link config. */ 447 regmap_write(ctx->regmap, REG_DSI_LANE, 448 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE | 449 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi->lanes - 1)) | 450 /* CHB is DSI85-only, set to default on DSI83/DSI84 */ 451 REG_DSI_LANE_CHB_DSI_LANES(3)); 452 /* No equalization. */ 453 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00); 454 455 /* Set up sync signal polarity. */ 456 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 457 REG_LVDS_FMT_HS_NEG_POLARITY : 0) | 458 (mode->flags & DRM_MODE_FLAG_NVSYNC ? 459 REG_LVDS_FMT_VS_NEG_POLARITY : 0); 460 461 /* Set up bits-per-pixel, 18bpp or 24bpp. */ 462 if (lvds_format_24bpp) { 463 val |= REG_LVDS_FMT_CHA_24BPP_MODE; 464 if (ctx->lvds_dual_link) 465 val |= REG_LVDS_FMT_CHB_24BPP_MODE; 466 } 467 468 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */ 469 if (lvds_format_jeida) { 470 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1; 471 if (ctx->lvds_dual_link) 472 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1; 473 } 474 475 /* Set up LVDS output config (DSI84,DSI85) */ 476 if (!ctx->lvds_dual_link) 477 val |= REG_LVDS_FMT_LVDS_LINK_CFG; 478 479 regmap_write(ctx->regmap, REG_LVDS_FMT, val); 480 regmap_write(ctx->regmap, REG_LVDS_VCOM, 481 REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_A]) | 482 REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_B])); 483 regmap_write(ctx->regmap, REG_LVDS_LANE, 484 (ctx->lvds_dual_link_even_odd_swap ? 485 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) | 486 (ctx->lvds_term_conf[CHANNEL_A] ? 487 REG_LVDS_LANE_CHA_LVDS_TERM : 0) | 488 (ctx->lvds_term_conf[CHANNEL_B] ? 489 REG_LVDS_LANE_CHB_LVDS_TERM : 0)); 490 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); 491 492 le16val = cpu_to_le16(mode->hdisplay); 493 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 494 &le16val, 2); 495 le16val = cpu_to_le16(mode->vdisplay); 496 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 497 &le16val, 2); 498 /* 32 + 1 pixel clock to ensure proper operation */ 499 le16val = cpu_to_le16(32 + 1); 500 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2); 501 le16val = cpu_to_le16(mode->hsync_end - mode->hsync_start); 502 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 503 &le16val, 2); 504 le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start); 505 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 506 &le16val, 2); 507 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH, 508 mode->htotal - mode->hsync_end); 509 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH, 510 mode->vtotal - mode->vsync_end); 511 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 512 mode->hsync_start - mode->hdisplay); 513 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, 514 mode->vsync_start - mode->vdisplay); 515 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); 516 517 /* Enable PLL */ 518 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); 519 usleep_range(3000, 4000); 520 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval, 521 pval & REG_RC_LVDS_PLL_PLL_EN_STAT, 522 1000, 100000); 523 if (ret) { 524 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret); 525 /* On failure, disable PLL again and exit. */ 526 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 527 return; 528 } 529 530 /* Trigger reset after CSR register update. */ 531 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET); 532 533 /* Wait for 10ms after soft reset as specified in datasheet */ 534 usleep_range(10000, 12000); 535 } 536 537 static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, 538 struct drm_bridge_state *old_bridge_state) 539 { 540 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 541 unsigned int pval; 542 543 /* Clear all errors that got asserted during initialization. */ 544 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); 545 regmap_write(ctx->regmap, REG_IRQ_STAT, pval); 546 547 /* Wait for 1ms and check for errors in status register */ 548 usleep_range(1000, 1100); 549 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); 550 if (pval) 551 dev_err(ctx->dev, "Unexpected link status 0x%02x\n", pval); 552 } 553 554 static void sn65dsi83_atomic_disable(struct drm_bridge *bridge, 555 struct drm_bridge_state *old_bridge_state) 556 { 557 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 558 int ret; 559 560 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ 561 gpiod_set_value_cansleep(ctx->enable_gpio, 0); 562 usleep_range(10000, 11000); 563 564 ret = regulator_disable(ctx->vcc); 565 if (ret) 566 dev_err(ctx->dev, "Failed to disable vcc: %d\n", ret); 567 568 regcache_mark_dirty(ctx->regmap); 569 } 570 571 static enum drm_mode_status 572 sn65dsi83_mode_valid(struct drm_bridge *bridge, 573 const struct drm_display_info *info, 574 const struct drm_display_mode *mode) 575 { 576 /* LVDS output clock range 25..154 MHz */ 577 if (mode->clock < 25000) 578 return MODE_CLOCK_LOW; 579 if (mode->clock > 154000) 580 return MODE_CLOCK_HIGH; 581 582 return MODE_OK; 583 } 584 585 #define MAX_INPUT_SEL_FORMATS 1 586 587 static u32 * 588 sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 589 struct drm_bridge_state *bridge_state, 590 struct drm_crtc_state *crtc_state, 591 struct drm_connector_state *conn_state, 592 u32 output_fmt, 593 unsigned int *num_input_fmts) 594 { 595 u32 *input_fmts; 596 597 *num_input_fmts = 0; 598 599 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 600 GFP_KERNEL); 601 if (!input_fmts) 602 return NULL; 603 604 /* This is the DSI-end bus format */ 605 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 606 *num_input_fmts = 1; 607 608 return input_fmts; 609 } 610 611 static const struct drm_bridge_funcs sn65dsi83_funcs = { 612 .attach = sn65dsi83_attach, 613 .detach = sn65dsi83_detach, 614 .atomic_enable = sn65dsi83_atomic_enable, 615 .atomic_pre_enable = sn65dsi83_atomic_pre_enable, 616 .atomic_disable = sn65dsi83_atomic_disable, 617 .mode_valid = sn65dsi83_mode_valid, 618 619 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 620 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 621 .atomic_reset = drm_atomic_helper_bridge_reset, 622 .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts, 623 }; 624 625 static int sn65dsi83_select_lvds_vod_swing(struct device *dev, 626 u32 lvds_vod_swing_data[2], u32 lvds_vod_swing_clk[2], u8 lvds_term) 627 { 628 int i; 629 630 for (i = 0; i <= 3; i++) { 631 if (lvds_vod_swing_data_table[lvds_term][i][0] >= lvds_vod_swing_data[0] && 632 lvds_vod_swing_data_table[lvds_term][i][1] <= lvds_vod_swing_data[1] && 633 lvds_vod_swing_clock_table[lvds_term][i][0] >= lvds_vod_swing_clk[0] && 634 lvds_vod_swing_clock_table[lvds_term][i][1] <= lvds_vod_swing_clk[1]) 635 return i; 636 } 637 638 dev_err(dev, "failed to find appropriate LVDS_VOD_SWING configuration\n"); 639 return -EINVAL; 640 } 641 642 static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel) 643 { 644 struct device *dev = ctx->dev; 645 struct device_node *endpoint; 646 int endpoint_reg; 647 /* Set so the property can be freely selected if not defined */ 648 u32 lvds_vod_swing_data[2] = { 0, 1000000 }; 649 u32 lvds_vod_swing_clk[2] = { 0, 1000000 }; 650 /* Set default near end terminataion to 200 Ohm */ 651 u32 lvds_term = 200; 652 int lvds_vod_swing_conf; 653 int ret = 0; 654 int ret_data; 655 int ret_clock; 656 657 if (channel == CHANNEL_A) 658 endpoint_reg = 2; 659 else 660 endpoint_reg = 3; 661 662 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, endpoint_reg, -1); 663 664 of_property_read_u32(endpoint, "ti,lvds-termination-ohms", &lvds_term); 665 if (lvds_term == 100) 666 ctx->lvds_term_conf[channel] = OHM_100; 667 else if (lvds_term == 200) 668 ctx->lvds_term_conf[channel] = OHM_200; 669 else { 670 ret = -EINVAL; 671 goto exit; 672 } 673 674 ret_data = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-data-microvolt", 675 lvds_vod_swing_data, ARRAY_SIZE(lvds_vod_swing_data)); 676 if (ret_data != 0 && ret_data != -EINVAL) { 677 ret = ret_data; 678 goto exit; 679 } 680 681 ret_clock = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-clock-microvolt", 682 lvds_vod_swing_clk, ARRAY_SIZE(lvds_vod_swing_clk)); 683 if (ret_clock != 0 && ret_clock != -EINVAL) { 684 ret = ret_clock; 685 goto exit; 686 } 687 688 /* Use default value if both properties are NOT defined. */ 689 if (ret_data == -EINVAL && ret_clock == -EINVAL) 690 lvds_vod_swing_conf = 0x1; 691 692 /* Use lookup table if any of the two properties is defined. */ 693 if (!ret_data || !ret_clock) { 694 lvds_vod_swing_conf = sn65dsi83_select_lvds_vod_swing(dev, lvds_vod_swing_data, 695 lvds_vod_swing_clk, ctx->lvds_term_conf[channel]); 696 if (lvds_vod_swing_conf < 0) { 697 ret = lvds_vod_swing_conf; 698 goto exit; 699 } 700 } 701 702 ctx->lvds_vod_swing_conf[channel] = lvds_vod_swing_conf; 703 ret = 0; 704 exit: 705 of_node_put(endpoint); 706 return ret; 707 } 708 709 static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model) 710 { 711 struct drm_bridge *panel_bridge; 712 struct device *dev = ctx->dev; 713 int ret; 714 715 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_A); 716 if (ret < 0) 717 return ret; 718 719 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_B); 720 if (ret < 0) 721 return ret; 722 723 ctx->lvds_dual_link = false; 724 ctx->lvds_dual_link_even_odd_swap = false; 725 if (model != MODEL_SN65DSI83) { 726 struct device_node *port2, *port3; 727 int dual_link; 728 729 port2 = of_graph_get_port_by_id(dev->of_node, 2); 730 port3 = of_graph_get_port_by_id(dev->of_node, 3); 731 dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3); 732 of_node_put(port2); 733 of_node_put(port3); 734 735 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) { 736 ctx->lvds_dual_link = true; 737 /* Odd pixels to LVDS Channel A, even pixels to B */ 738 ctx->lvds_dual_link_even_odd_swap = false; 739 } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { 740 ctx->lvds_dual_link = true; 741 /* Even pixels to LVDS Channel A, odd pixels to B */ 742 ctx->lvds_dual_link_even_odd_swap = true; 743 } 744 } 745 746 panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0); 747 if (IS_ERR(panel_bridge)) 748 return dev_err_probe(dev, PTR_ERR(panel_bridge), "Failed to get panel bridge\n"); 749 750 ctx->panel_bridge = panel_bridge; 751 752 ctx->vcc = devm_regulator_get(dev, "vcc"); 753 if (IS_ERR(ctx->vcc)) 754 return dev_err_probe(dev, PTR_ERR(ctx->vcc), 755 "Failed to get supply 'vcc'\n"); 756 757 return 0; 758 } 759 760 static int sn65dsi83_host_attach(struct sn65dsi83 *ctx) 761 { 762 struct device *dev = ctx->dev; 763 struct device_node *host_node; 764 struct device_node *endpoint; 765 struct mipi_dsi_device *dsi; 766 struct mipi_dsi_host *host; 767 const struct mipi_dsi_device_info info = { 768 .type = "sn65dsi83", 769 .channel = 0, 770 .node = NULL, 771 }; 772 int dsi_lanes, ret; 773 774 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); 775 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4); 776 host_node = of_graph_get_remote_port_parent(endpoint); 777 host = of_find_mipi_dsi_host_by_node(host_node); 778 of_node_put(host_node); 779 of_node_put(endpoint); 780 781 if (!host) 782 return -EPROBE_DEFER; 783 784 if (dsi_lanes < 0) 785 return dsi_lanes; 786 787 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 788 if (IS_ERR(dsi)) 789 return dev_err_probe(dev, PTR_ERR(dsi), 790 "failed to create dsi device\n"); 791 792 ctx->dsi = dsi; 793 794 dsi->lanes = dsi_lanes; 795 dsi->format = MIPI_DSI_FMT_RGB888; 796 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 797 MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP | 798 MIPI_DSI_MODE_VIDEO_NO_HSA | MIPI_DSI_MODE_NO_EOT_PACKET; 799 800 ret = devm_mipi_dsi_attach(dev, dsi); 801 if (ret < 0) { 802 dev_err(dev, "failed to attach dsi to host: %d\n", ret); 803 return ret; 804 } 805 806 return 0; 807 } 808 809 static int sn65dsi83_probe(struct i2c_client *client) 810 { 811 const struct i2c_device_id *id = i2c_client_get_device_id(client); 812 struct device *dev = &client->dev; 813 enum sn65dsi83_model model; 814 struct sn65dsi83 *ctx; 815 int ret; 816 817 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 818 if (!ctx) 819 return -ENOMEM; 820 821 ctx->dev = dev; 822 823 if (dev->of_node) { 824 model = (enum sn65dsi83_model)(uintptr_t) 825 of_device_get_match_data(dev); 826 } else { 827 model = id->driver_data; 828 } 829 830 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ 831 ctx->enable_gpio = devm_gpiod_get_optional(ctx->dev, "enable", 832 GPIOD_OUT_LOW); 833 if (IS_ERR(ctx->enable_gpio)) 834 return dev_err_probe(dev, PTR_ERR(ctx->enable_gpio), "failed to get enable GPIO\n"); 835 836 usleep_range(10000, 11000); 837 838 ret = sn65dsi83_parse_dt(ctx, model); 839 if (ret) 840 return ret; 841 842 ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config); 843 if (IS_ERR(ctx->regmap)) 844 return dev_err_probe(dev, PTR_ERR(ctx->regmap), "failed to get regmap\n"); 845 846 dev_set_drvdata(dev, ctx); 847 i2c_set_clientdata(client, ctx); 848 849 ctx->bridge.funcs = &sn65dsi83_funcs; 850 ctx->bridge.of_node = dev->of_node; 851 ctx->bridge.pre_enable_prev_first = true; 852 drm_bridge_add(&ctx->bridge); 853 854 ret = sn65dsi83_host_attach(ctx); 855 if (ret) { 856 dev_err_probe(dev, ret, "failed to attach DSI host\n"); 857 goto err_remove_bridge; 858 } 859 860 return 0; 861 862 err_remove_bridge: 863 drm_bridge_remove(&ctx->bridge); 864 return ret; 865 } 866 867 static void sn65dsi83_remove(struct i2c_client *client) 868 { 869 struct sn65dsi83 *ctx = i2c_get_clientdata(client); 870 871 drm_bridge_remove(&ctx->bridge); 872 } 873 874 static const struct i2c_device_id sn65dsi83_id[] = { 875 { "ti,sn65dsi83", MODEL_SN65DSI83 }, 876 { "ti,sn65dsi84", MODEL_SN65DSI84 }, 877 {}, 878 }; 879 MODULE_DEVICE_TABLE(i2c, sn65dsi83_id); 880 881 static const struct of_device_id sn65dsi83_match_table[] = { 882 { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 }, 883 { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 }, 884 {}, 885 }; 886 MODULE_DEVICE_TABLE(of, sn65dsi83_match_table); 887 888 static struct i2c_driver sn65dsi83_driver = { 889 .probe = sn65dsi83_probe, 890 .remove = sn65dsi83_remove, 891 .id_table = sn65dsi83_id, 892 .driver = { 893 .name = "sn65dsi83", 894 .of_match_table = sn65dsi83_match_table, 895 }, 896 }; 897 module_i2c_driver(sn65dsi83_driver); 898 899 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 900 MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver"); 901 MODULE_LICENSE("GPL v2"); 902