1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * TI SN65DSI83,84,85 driver 4 * 5 * Currently supported: 6 * - SN65DSI83 7 * = 1x Single-link DSI ~ 1x Single-link LVDS 8 * - Supported 9 * - Single-link LVDS mode tested 10 * - SN65DSI84 11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS 12 * - Supported 13 * - Dual-link LVDS mode tested 14 * - 2x Single-link LVDS mode unsupported 15 * (should be easy to add by someone who has the HW) 16 * - SN65DSI85 17 * = 2x Single-link or 1x Dual-link DSI ~ 2x Single-link or 1x Dual-link LVDS 18 * - Unsupported 19 * (should be easy to add by someone who has the HW) 20 * 21 * Copyright (C) 2021 Marek Vasut <marex@denx.de> 22 * 23 * Based on previous work of: 24 * Valentin Raevsky <valentin@compulab.co.il> 25 * Philippe Schenker <philippe.schenker@toradex.com> 26 */ 27 28 #include <linux/bits.h> 29 #include <linux/clk.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/i2c.h> 32 #include <linux/media-bus-format.h> 33 #include <linux/module.h> 34 #include <linux/of.h> 35 #include <linux/of_graph.h> 36 #include <linux/regmap.h> 37 #include <linux/regulator/consumer.h> 38 #include <linux/timer.h> 39 #include <linux/workqueue.h> 40 41 #include <drm/drm_atomic_helper.h> 42 #include <drm/drm_bridge.h> 43 #include <drm/drm_bridge_helper.h> 44 #include <drm/drm_mipi_dsi.h> 45 #include <drm/drm_of.h> 46 #include <drm/drm_print.h> 47 #include <drm/drm_probe_helper.h> 48 49 /* ID registers */ 50 #define REG_ID(n) (0x00 + (n)) 51 /* Reset and clock registers */ 52 #define REG_RC_RESET 0x09 53 #define REG_RC_RESET_SOFT_RESET BIT(0) 54 #define REG_RC_LVDS_PLL 0x0a 55 #define REG_RC_LVDS_PLL_PLL_EN_STAT BIT(7) 56 #define REG_RC_LVDS_PLL_LVDS_CLK_RANGE(n) (((n) & 0x7) << 1) 57 #define REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY BIT(0) 58 #define REG_RC_DSI_CLK 0x0b 59 #define REG_RC_DSI_CLK_DSI_CLK_DIVIDER(n) (((n) & 0x1f) << 3) 60 #define REG_RC_DSI_CLK_REFCLK_MULTIPLIER(n) ((n) & 0x3) 61 #define REG_RC_PLL_EN 0x0d 62 #define REG_RC_PLL_EN_PLL_EN BIT(0) 63 /* DSI registers */ 64 #define REG_DSI_LANE 0x10 65 #define REG_DSI_LANE_LEFT_RIGHT_PIXELS BIT(7) /* DSI85-only */ 66 #define REG_DSI_LANE_DSI_CHANNEL_MODE_DUAL 0 /* DSI85-only */ 67 #define REG_DSI_LANE_DSI_CHANNEL_MODE_2SINGLE BIT(6) /* DSI85-only */ 68 #define REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE BIT(5) 69 #define REG_DSI_LANE_CHA_DSI_LANES(n) (((n) & 0x3) << 3) 70 #define REG_DSI_LANE_CHB_DSI_LANES(n) (((n) & 0x3) << 1) 71 #define REG_DSI_LANE_SOT_ERR_TOL_DIS BIT(0) 72 #define REG_DSI_EQ 0x11 73 #define REG_DSI_EQ_CHA_DSI_DATA_EQ(n) (((n) & 0x3) << 6) 74 #define REG_DSI_EQ_CHA_DSI_CLK_EQ(n) (((n) & 0x3) << 2) 75 #define REG_DSI_CLK 0x12 76 #define REG_DSI_CLK_CHA_DSI_CLK_RANGE(n) ((n) & 0xff) 77 /* LVDS registers */ 78 #define REG_LVDS_FMT 0x18 79 #define REG_LVDS_FMT_DE_NEG_POLARITY BIT(7) 80 #define REG_LVDS_FMT_HS_NEG_POLARITY BIT(6) 81 #define REG_LVDS_FMT_VS_NEG_POLARITY BIT(5) 82 #define REG_LVDS_FMT_LVDS_LINK_CFG BIT(4) /* 0:AB 1:A-only */ 83 #define REG_LVDS_FMT_CHA_24BPP_MODE BIT(3) 84 #define REG_LVDS_FMT_CHB_24BPP_MODE BIT(2) 85 #define REG_LVDS_FMT_CHA_24BPP_FORMAT1 BIT(1) 86 #define REG_LVDS_FMT_CHB_24BPP_FORMAT1 BIT(0) 87 #define REG_LVDS_VCOM 0x19 88 #define REG_LVDS_VCOM_CHA_LVDS_VOCM BIT(6) 89 #define REG_LVDS_VCOM_CHB_LVDS_VOCM BIT(4) 90 #define REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(n) (((n) & 0x3) << 2) 91 #define REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(n) ((n) & 0x3) 92 #define REG_LVDS_LANE 0x1a 93 #define REG_LVDS_LANE_EVEN_ODD_SWAP BIT(6) 94 #define REG_LVDS_LANE_CHA_REVERSE_LVDS BIT(5) 95 #define REG_LVDS_LANE_CHB_REVERSE_LVDS BIT(4) 96 #define REG_LVDS_LANE_CHA_LVDS_TERM BIT(1) 97 #define REG_LVDS_LANE_CHB_LVDS_TERM BIT(0) 98 #define REG_LVDS_CM 0x1b 99 #define REG_LVDS_CM_CHA_LVDS_CM_ADJUST(n) (((n) & 0x3) << 4) 100 #define REG_LVDS_CM_CHB_LVDS_CM_ADJUST(n) ((n) & 0x3) 101 /* Video registers */ 102 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW 0x20 103 #define REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH 0x21 104 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW 0x24 105 #define REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH 0x25 106 #define REG_VID_CHA_SYNC_DELAY_LOW 0x28 107 #define REG_VID_CHA_SYNC_DELAY_HIGH 0x29 108 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW 0x2c 109 #define REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH 0x2d 110 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW 0x30 111 #define REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH 0x31 112 #define REG_VID_CHA_HORIZONTAL_BACK_PORCH 0x34 113 #define REG_VID_CHA_VERTICAL_BACK_PORCH 0x36 114 #define REG_VID_CHA_HORIZONTAL_FRONT_PORCH 0x38 115 #define REG_VID_CHA_VERTICAL_FRONT_PORCH 0x3a 116 #define REG_VID_CHA_TEST_PATTERN 0x3c 117 /* IRQ registers */ 118 #define REG_IRQ_GLOBAL 0xe0 119 #define REG_IRQ_GLOBAL_IRQ_EN BIT(0) 120 #define REG_IRQ_EN 0xe1 121 #define REG_IRQ_EN_CHA_SYNCH_ERR_EN BIT(7) 122 #define REG_IRQ_EN_CHA_CRC_ERR_EN BIT(6) 123 #define REG_IRQ_EN_CHA_UNC_ECC_ERR_EN BIT(5) 124 #define REG_IRQ_EN_CHA_COR_ECC_ERR_EN BIT(4) 125 #define REG_IRQ_EN_CHA_LLP_ERR_EN BIT(3) 126 #define REG_IRQ_EN_CHA_SOT_BIT_ERR_EN BIT(2) 127 #define REG_IRQ_EN_CHA_PLL_UNLOCK_EN BIT(0) 128 #define REG_IRQ_STAT 0xe5 129 #define REG_IRQ_STAT_CHA_SYNCH_ERR BIT(7) 130 #define REG_IRQ_STAT_CHA_CRC_ERR BIT(6) 131 #define REG_IRQ_STAT_CHA_UNC_ECC_ERR BIT(5) 132 #define REG_IRQ_STAT_CHA_COR_ECC_ERR BIT(4) 133 #define REG_IRQ_STAT_CHA_LLP_ERR BIT(3) 134 #define REG_IRQ_STAT_CHA_SOT_BIT_ERR BIT(2) 135 #define REG_IRQ_STAT_CHA_PLL_UNLOCK BIT(0) 136 137 enum sn65dsi83_channel { 138 CHANNEL_A, 139 CHANNEL_B 140 }; 141 142 enum sn65dsi83_lvds_term { 143 OHM_100, 144 OHM_200 145 }; 146 147 enum sn65dsi83_model { 148 MODEL_SN65DSI83, 149 MODEL_SN65DSI84, 150 }; 151 152 struct sn65dsi83 { 153 struct drm_bridge bridge; 154 struct device *dev; 155 struct regmap *regmap; 156 struct mipi_dsi_device *dsi; 157 struct drm_bridge *panel_bridge; 158 struct gpio_desc *enable_gpio; 159 struct regulator *vcc; 160 bool lvds_dual_link; 161 bool lvds_dual_link_even_odd_swap; 162 int lvds_vod_swing_conf[2]; 163 int lvds_term_conf[2]; 164 int irq; 165 struct delayed_work monitor_work; 166 struct work_struct reset_work; 167 }; 168 169 static const struct regmap_range sn65dsi83_readable_ranges[] = { 170 regmap_reg_range(REG_ID(0), REG_ID(8)), 171 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_DSI_CLK), 172 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 173 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 174 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 175 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 176 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 177 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 178 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 179 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 180 REG_VID_CHA_SYNC_DELAY_HIGH), 181 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 182 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 183 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 184 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 185 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 186 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 187 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 188 REG_VID_CHA_VERTICAL_BACK_PORCH), 189 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 190 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 191 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 192 REG_VID_CHA_VERTICAL_FRONT_PORCH), 193 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 194 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 195 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 196 }; 197 198 static const struct regmap_access_table sn65dsi83_readable_table = { 199 .yes_ranges = sn65dsi83_readable_ranges, 200 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_readable_ranges), 201 }; 202 203 static const struct regmap_range sn65dsi83_writeable_ranges[] = { 204 regmap_reg_range(REG_RC_RESET, REG_RC_DSI_CLK), 205 regmap_reg_range(REG_RC_PLL_EN, REG_RC_PLL_EN), 206 regmap_reg_range(REG_DSI_LANE, REG_DSI_CLK), 207 regmap_reg_range(REG_LVDS_FMT, REG_LVDS_CM), 208 regmap_reg_range(REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 209 REG_VID_CHA_ACTIVE_LINE_LENGTH_HIGH), 210 regmap_reg_range(REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 211 REG_VID_CHA_VERTICAL_DISPLAY_SIZE_HIGH), 212 regmap_reg_range(REG_VID_CHA_SYNC_DELAY_LOW, 213 REG_VID_CHA_SYNC_DELAY_HIGH), 214 regmap_reg_range(REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 215 REG_VID_CHA_HSYNC_PULSE_WIDTH_HIGH), 216 regmap_reg_range(REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 217 REG_VID_CHA_VSYNC_PULSE_WIDTH_HIGH), 218 regmap_reg_range(REG_VID_CHA_HORIZONTAL_BACK_PORCH, 219 REG_VID_CHA_HORIZONTAL_BACK_PORCH), 220 regmap_reg_range(REG_VID_CHA_VERTICAL_BACK_PORCH, 221 REG_VID_CHA_VERTICAL_BACK_PORCH), 222 regmap_reg_range(REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 223 REG_VID_CHA_HORIZONTAL_FRONT_PORCH), 224 regmap_reg_range(REG_VID_CHA_VERTICAL_FRONT_PORCH, 225 REG_VID_CHA_VERTICAL_FRONT_PORCH), 226 regmap_reg_range(REG_VID_CHA_TEST_PATTERN, REG_VID_CHA_TEST_PATTERN), 227 regmap_reg_range(REG_IRQ_GLOBAL, REG_IRQ_EN), 228 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 229 }; 230 231 static const struct regmap_access_table sn65dsi83_writeable_table = { 232 .yes_ranges = sn65dsi83_writeable_ranges, 233 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_writeable_ranges), 234 }; 235 236 static const struct regmap_range sn65dsi83_volatile_ranges[] = { 237 regmap_reg_range(REG_RC_RESET, REG_RC_RESET), 238 regmap_reg_range(REG_RC_LVDS_PLL, REG_RC_LVDS_PLL), 239 regmap_reg_range(REG_IRQ_STAT, REG_IRQ_STAT), 240 }; 241 242 static const struct regmap_access_table sn65dsi83_volatile_table = { 243 .yes_ranges = sn65dsi83_volatile_ranges, 244 .n_yes_ranges = ARRAY_SIZE(sn65dsi83_volatile_ranges), 245 }; 246 247 static const struct regmap_config sn65dsi83_regmap_config = { 248 .reg_bits = 8, 249 .val_bits = 8, 250 .rd_table = &sn65dsi83_readable_table, 251 .wr_table = &sn65dsi83_writeable_table, 252 .volatile_table = &sn65dsi83_volatile_table, 253 .cache_type = REGCACHE_MAPLE, 254 .max_register = REG_IRQ_STAT, 255 }; 256 257 static const int lvds_vod_swing_data_table[2][4][2] = { 258 { /* 100 Ohm */ 259 { 180000, 313000 }, 260 { 215000, 372000 }, 261 { 250000, 430000 }, 262 { 290000, 488000 }, 263 }, 264 { /* 200 Ohm */ 265 { 150000, 261000 }, 266 { 200000, 346000 }, 267 { 250000, 428000 }, 268 { 300000, 511000 }, 269 }, 270 }; 271 272 static const int lvds_vod_swing_clock_table[2][4][2] = { 273 { /* 100 Ohm */ 274 { 140000, 244000 }, 275 { 168000, 290000 }, 276 { 195000, 335000 }, 277 { 226000, 381000 }, 278 }, 279 { /* 200 Ohm */ 280 { 117000, 204000 }, 281 { 156000, 270000 }, 282 { 195000, 334000 }, 283 { 234000, 399000 }, 284 }, 285 }; 286 287 static struct sn65dsi83 *bridge_to_sn65dsi83(struct drm_bridge *bridge) 288 { 289 return container_of(bridge, struct sn65dsi83, bridge); 290 } 291 292 static int sn65dsi83_attach(struct drm_bridge *bridge, 293 struct drm_encoder *encoder, 294 enum drm_bridge_attach_flags flags) 295 { 296 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 297 298 return drm_bridge_attach(encoder, ctx->panel_bridge, 299 &ctx->bridge, flags); 300 } 301 302 static void sn65dsi83_detach(struct drm_bridge *bridge) 303 { 304 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 305 306 if (!ctx->dsi) 307 return; 308 309 ctx->dsi = NULL; 310 } 311 312 static u8 sn65dsi83_get_lvds_range(struct sn65dsi83 *ctx, 313 const struct drm_display_mode *mode) 314 { 315 /* 316 * The encoding of the LVDS_CLK_RANGE is as follows: 317 * 000 - 25 MHz <= LVDS_CLK < 37.5 MHz 318 * 001 - 37.5 MHz <= LVDS_CLK < 62.5 MHz 319 * 010 - 62.5 MHz <= LVDS_CLK < 87.5 MHz 320 * 011 - 87.5 MHz <= LVDS_CLK < 112.5 MHz 321 * 100 - 112.5 MHz <= LVDS_CLK < 137.5 MHz 322 * 101 - 137.5 MHz <= LVDS_CLK <= 154 MHz 323 * which is a range of 12.5MHz..162.5MHz in 50MHz steps, except that 324 * the ends of the ranges are clamped to the supported range. Since 325 * sn65dsi83_mode_valid() already filters the valid modes and limits 326 * the clock to 25..154 MHz, the range calculation can be simplified 327 * as follows: 328 */ 329 int mode_clock = mode->clock; 330 331 if (ctx->lvds_dual_link) 332 mode_clock /= 2; 333 334 return (mode_clock - 12500) / 25000; 335 } 336 337 static u8 sn65dsi83_get_dsi_range(struct sn65dsi83 *ctx, 338 const struct drm_display_mode *mode) 339 { 340 /* 341 * The encoding of the CHA_DSI_CLK_RANGE is as follows: 342 * 0x00 through 0x07 - Reserved 343 * 0x08 - 40 <= DSI_CLK < 45 MHz 344 * 0x09 - 45 <= DSI_CLK < 50 MHz 345 * ... 346 * 0x63 - 495 <= DSI_CLK < 500 MHz 347 * 0x64 - 500 MHz 348 * 0x65 through 0xFF - Reserved 349 * which is DSI clock in 5 MHz steps, clamped to 40..500 MHz. 350 * The DSI clock are calculated as: 351 * DSI_CLK = mode clock * bpp / dsi_data_lanes / 2 352 * the 2 is there because the bus is DDR. 353 */ 354 return DIV_ROUND_UP(clamp((unsigned int)mode->clock * 355 mipi_dsi_pixel_format_to_bpp(ctx->dsi->format) / 356 ctx->dsi->lanes / 2, 40000U, 500000U), 5000U); 357 } 358 359 static u8 sn65dsi83_get_dsi_div(struct sn65dsi83 *ctx) 360 { 361 /* The divider is (DSI_CLK / LVDS_CLK) - 1, which really is: */ 362 unsigned int dsi_div = mipi_dsi_pixel_format_to_bpp(ctx->dsi->format); 363 364 dsi_div /= ctx->dsi->lanes; 365 366 if (!ctx->lvds_dual_link) 367 dsi_div /= 2; 368 369 return dsi_div - 1; 370 } 371 372 static int sn65dsi83_reset_pipe(struct sn65dsi83 *sn65dsi83) 373 { 374 struct drm_modeset_acquire_ctx ctx; 375 int err; 376 377 /* 378 * Reset active outputs of the related CRTC. 379 * 380 * This way, drm core will reconfigure each components in the CRTC 381 * outputs path. In our case, this will force the previous component to 382 * go back in LP11 mode and so allow the reconfiguration of SN65DSI83 383 * bridge. 384 * 385 * Keep the lock during the whole operation to be atomic. 386 */ 387 388 drm_modeset_acquire_init(&ctx, 0); 389 390 dev_warn(sn65dsi83->dev, "reset the pipe\n"); 391 392 retry: 393 err = drm_bridge_helper_reset_crtc(&sn65dsi83->bridge, &ctx); 394 if (err == -EDEADLK) { 395 drm_modeset_backoff(&ctx); 396 goto retry; 397 } 398 399 drm_modeset_drop_locks(&ctx); 400 drm_modeset_acquire_fini(&ctx); 401 402 return 0; 403 } 404 405 static void sn65dsi83_reset_work(struct work_struct *ws) 406 { 407 struct sn65dsi83 *ctx = container_of(ws, struct sn65dsi83, reset_work); 408 int ret; 409 410 /* Reset the pipe */ 411 ret = sn65dsi83_reset_pipe(ctx); 412 if (ret) { 413 dev_err(ctx->dev, "reset pipe failed %pe\n", ERR_PTR(ret)); 414 return; 415 } 416 if (ctx->irq) 417 enable_irq(ctx->irq); 418 } 419 420 static void sn65dsi83_handle_errors(struct sn65dsi83 *ctx) 421 { 422 unsigned int irq_stat; 423 int ret; 424 425 /* 426 * Schedule a reset in case of: 427 * - the bridge doesn't answer 428 * - the bridge signals an error 429 */ 430 431 ret = regmap_read(ctx->regmap, REG_IRQ_STAT, &irq_stat); 432 433 /* 434 * Some hardware (Toradex Verdin AM62) is known to report the 435 * PLL_UNLOCK error interrupt while working without visible 436 * problems. In lack of a reliable way to discriminate such cases 437 * from user-visible PLL_UNLOCK cases, ignore that bit entirely. 438 */ 439 if (ret || irq_stat & ~REG_IRQ_STAT_CHA_PLL_UNLOCK) { 440 /* 441 * IRQ acknowledged is not always possible (the bridge can be in 442 * a state where it doesn't answer anymore). To prevent an 443 * interrupt storm, disable interrupt. The interrupt will be 444 * after the reset. 445 */ 446 if (ctx->irq) 447 disable_irq_nosync(ctx->irq); 448 449 schedule_work(&ctx->reset_work); 450 } 451 } 452 453 static void sn65dsi83_monitor_work(struct work_struct *work) 454 { 455 struct sn65dsi83 *ctx = container_of(to_delayed_work(work), 456 struct sn65dsi83, monitor_work); 457 458 sn65dsi83_handle_errors(ctx); 459 460 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000)); 461 } 462 463 static void sn65dsi83_monitor_start(struct sn65dsi83 *ctx) 464 { 465 schedule_delayed_work(&ctx->monitor_work, msecs_to_jiffies(1000)); 466 } 467 468 static void sn65dsi83_monitor_stop(struct sn65dsi83 *ctx) 469 { 470 cancel_delayed_work_sync(&ctx->monitor_work); 471 } 472 473 static void sn65dsi83_atomic_pre_enable(struct drm_bridge *bridge, 474 struct drm_atomic_state *state) 475 { 476 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 477 const struct drm_bridge_state *bridge_state; 478 const struct drm_crtc_state *crtc_state; 479 const struct drm_display_mode *mode; 480 struct drm_connector *connector; 481 struct drm_crtc *crtc; 482 bool lvds_format_24bpp; 483 bool lvds_format_jeida; 484 unsigned int pval; 485 __le16 le16val; 486 u16 val; 487 int ret; 488 489 ret = regulator_enable(ctx->vcc); 490 if (ret) { 491 dev_err(ctx->dev, "Failed to enable vcc: %d\n", ret); 492 return; 493 } 494 495 /* Deassert reset */ 496 gpiod_set_value_cansleep(ctx->enable_gpio, 1); 497 usleep_range(10000, 11000); 498 499 /* Get the LVDS format from the bridge state. */ 500 bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 501 502 switch (bridge_state->output_bus_cfg.format) { 503 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 504 lvds_format_24bpp = false; 505 lvds_format_jeida = true; 506 break; 507 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 508 lvds_format_24bpp = true; 509 lvds_format_jeida = true; 510 break; 511 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 512 lvds_format_24bpp = true; 513 lvds_format_jeida = false; 514 break; 515 default: 516 /* 517 * Some bridges still don't set the correct 518 * LVDS bus pixel format, use SPWG24 default 519 * format until those are fixed. 520 */ 521 lvds_format_24bpp = true; 522 lvds_format_jeida = false; 523 dev_warn(ctx->dev, 524 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", 525 bridge_state->output_bus_cfg.format); 526 break; 527 } 528 529 /* 530 * Retrieve the CRTC adjusted mode. This requires a little dance to go 531 * from the bridge to the encoder, to the connector and to the CRTC. 532 */ 533 connector = drm_atomic_get_new_connector_for_encoder(state, 534 bridge->encoder); 535 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 536 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 537 mode = &crtc_state->adjusted_mode; 538 539 /* Clear reset, disable PLL */ 540 regmap_write(ctx->regmap, REG_RC_RESET, 0x00); 541 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 542 543 /* Reference clock derived from DSI link clock. */ 544 regmap_write(ctx->regmap, REG_RC_LVDS_PLL, 545 REG_RC_LVDS_PLL_LVDS_CLK_RANGE(sn65dsi83_get_lvds_range(ctx, mode)) | 546 REG_RC_LVDS_PLL_HS_CLK_SRC_DPHY); 547 regmap_write(ctx->regmap, REG_DSI_CLK, 548 REG_DSI_CLK_CHA_DSI_CLK_RANGE(sn65dsi83_get_dsi_range(ctx, mode))); 549 regmap_write(ctx->regmap, REG_RC_DSI_CLK, 550 REG_RC_DSI_CLK_DSI_CLK_DIVIDER(sn65dsi83_get_dsi_div(ctx))); 551 552 /* Set number of DSI lanes and LVDS link config. */ 553 regmap_write(ctx->regmap, REG_DSI_LANE, 554 REG_DSI_LANE_DSI_CHANNEL_MODE_SINGLE | 555 REG_DSI_LANE_CHA_DSI_LANES(~(ctx->dsi->lanes - 1)) | 556 /* CHB is DSI85-only, set to default on DSI83/DSI84 */ 557 REG_DSI_LANE_CHB_DSI_LANES(3)); 558 /* No equalization. */ 559 regmap_write(ctx->regmap, REG_DSI_EQ, 0x00); 560 561 /* Set up sync signal polarity. */ 562 val = (mode->flags & DRM_MODE_FLAG_NHSYNC ? 563 REG_LVDS_FMT_HS_NEG_POLARITY : 0) | 564 (mode->flags & DRM_MODE_FLAG_NVSYNC ? 565 REG_LVDS_FMT_VS_NEG_POLARITY : 0); 566 val |= bridge_state->output_bus_cfg.flags & DRM_BUS_FLAG_DE_LOW ? 567 REG_LVDS_FMT_DE_NEG_POLARITY : 0; 568 569 /* Set up bits-per-pixel, 18bpp or 24bpp. */ 570 if (lvds_format_24bpp) { 571 val |= REG_LVDS_FMT_CHA_24BPP_MODE; 572 if (ctx->lvds_dual_link) 573 val |= REG_LVDS_FMT_CHB_24BPP_MODE; 574 } 575 576 /* Set up LVDS format, JEIDA/Format 1 or SPWG/Format 2 */ 577 if (lvds_format_jeida) { 578 val |= REG_LVDS_FMT_CHA_24BPP_FORMAT1; 579 if (ctx->lvds_dual_link) 580 val |= REG_LVDS_FMT_CHB_24BPP_FORMAT1; 581 } 582 583 /* Set up LVDS output config (DSI84,DSI85) */ 584 if (!ctx->lvds_dual_link) 585 val |= REG_LVDS_FMT_LVDS_LINK_CFG; 586 587 regmap_write(ctx->regmap, REG_LVDS_FMT, val); 588 regmap_write(ctx->regmap, REG_LVDS_VCOM, 589 REG_LVDS_VCOM_CHA_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_A]) | 590 REG_LVDS_VCOM_CHB_LVDS_VOD_SWING(ctx->lvds_vod_swing_conf[CHANNEL_B])); 591 regmap_write(ctx->regmap, REG_LVDS_LANE, 592 (ctx->lvds_dual_link_even_odd_swap ? 593 REG_LVDS_LANE_EVEN_ODD_SWAP : 0) | 594 (ctx->lvds_term_conf[CHANNEL_A] ? 595 REG_LVDS_LANE_CHA_LVDS_TERM : 0) | 596 (ctx->lvds_term_conf[CHANNEL_B] ? 597 REG_LVDS_LANE_CHB_LVDS_TERM : 0)); 598 regmap_write(ctx->regmap, REG_LVDS_CM, 0x00); 599 600 le16val = cpu_to_le16(mode->hdisplay); 601 regmap_bulk_write(ctx->regmap, REG_VID_CHA_ACTIVE_LINE_LENGTH_LOW, 602 &le16val, 2); 603 le16val = cpu_to_le16(mode->vdisplay); 604 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VERTICAL_DISPLAY_SIZE_LOW, 605 &le16val, 2); 606 /* 32 + 1 pixel clock to ensure proper operation */ 607 le16val = cpu_to_le16(32 + 1); 608 regmap_bulk_write(ctx->regmap, REG_VID_CHA_SYNC_DELAY_LOW, &le16val, 2); 609 le16val = cpu_to_le16(mode->hsync_end - mode->hsync_start); 610 regmap_bulk_write(ctx->regmap, REG_VID_CHA_HSYNC_PULSE_WIDTH_LOW, 611 &le16val, 2); 612 le16val = cpu_to_le16(mode->vsync_end - mode->vsync_start); 613 regmap_bulk_write(ctx->regmap, REG_VID_CHA_VSYNC_PULSE_WIDTH_LOW, 614 &le16val, 2); 615 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_BACK_PORCH, 616 mode->htotal - mode->hsync_end); 617 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_BACK_PORCH, 618 mode->vtotal - mode->vsync_end); 619 regmap_write(ctx->regmap, REG_VID_CHA_HORIZONTAL_FRONT_PORCH, 620 mode->hsync_start - mode->hdisplay); 621 regmap_write(ctx->regmap, REG_VID_CHA_VERTICAL_FRONT_PORCH, 622 mode->vsync_start - mode->vdisplay); 623 regmap_write(ctx->regmap, REG_VID_CHA_TEST_PATTERN, 0x00); 624 625 /* Enable PLL */ 626 regmap_write(ctx->regmap, REG_RC_PLL_EN, REG_RC_PLL_EN_PLL_EN); 627 usleep_range(3000, 4000); 628 ret = regmap_read_poll_timeout(ctx->regmap, REG_RC_LVDS_PLL, pval, 629 pval & REG_RC_LVDS_PLL_PLL_EN_STAT, 630 1000, 100000); 631 if (ret) { 632 dev_err(ctx->dev, "failed to lock PLL, ret=%i\n", ret); 633 /* On failure, disable PLL again and exit. */ 634 regmap_write(ctx->regmap, REG_RC_PLL_EN, 0x00); 635 return; 636 } 637 638 /* Trigger reset after CSR register update. */ 639 regmap_write(ctx->regmap, REG_RC_RESET, REG_RC_RESET_SOFT_RESET); 640 641 /* Wait for 10ms after soft reset as specified in datasheet */ 642 usleep_range(10000, 12000); 643 } 644 645 static void sn65dsi83_atomic_enable(struct drm_bridge *bridge, 646 struct drm_atomic_state *state) 647 { 648 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 649 unsigned int pval; 650 651 /* Clear all errors that got asserted during initialization. */ 652 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); 653 regmap_write(ctx->regmap, REG_IRQ_STAT, pval); 654 655 /* Wait for 1ms and check for errors in status register */ 656 usleep_range(1000, 1100); 657 regmap_read(ctx->regmap, REG_IRQ_STAT, &pval); 658 if (pval) 659 dev_err(ctx->dev, "Unexpected link status 0x%02x\n", pval); 660 661 if (ctx->irq) { 662 /* Enable irq to detect errors */ 663 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, REG_IRQ_GLOBAL_IRQ_EN); 664 regmap_write(ctx->regmap, REG_IRQ_EN, 0xff & ~REG_IRQ_EN_CHA_PLL_UNLOCK_EN); 665 } else { 666 /* Use the polling task */ 667 sn65dsi83_monitor_start(ctx); 668 } 669 } 670 671 static void sn65dsi83_atomic_disable(struct drm_bridge *bridge, 672 struct drm_atomic_state *state) 673 { 674 struct sn65dsi83 *ctx = bridge_to_sn65dsi83(bridge); 675 int ret; 676 677 if (ctx->irq) { 678 /* Disable irq */ 679 regmap_write(ctx->regmap, REG_IRQ_EN, 0x0); 680 regmap_write(ctx->regmap, REG_IRQ_GLOBAL, 0x0); 681 } else { 682 /* Stop the polling task */ 683 sn65dsi83_monitor_stop(ctx); 684 } 685 686 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ 687 gpiod_set_value_cansleep(ctx->enable_gpio, 0); 688 usleep_range(10000, 11000); 689 690 ret = regulator_disable(ctx->vcc); 691 if (ret) 692 dev_err(ctx->dev, "Failed to disable vcc: %d\n", ret); 693 694 regcache_mark_dirty(ctx->regmap); 695 } 696 697 static enum drm_mode_status 698 sn65dsi83_mode_valid(struct drm_bridge *bridge, 699 const struct drm_display_info *info, 700 const struct drm_display_mode *mode) 701 { 702 /* LVDS output clock range 25..154 MHz */ 703 if (mode->clock < 25000) 704 return MODE_CLOCK_LOW; 705 if (mode->clock > 154000) 706 return MODE_CLOCK_HIGH; 707 708 return MODE_OK; 709 } 710 711 #define MAX_INPUT_SEL_FORMATS 1 712 713 static u32 * 714 sn65dsi83_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 715 struct drm_bridge_state *bridge_state, 716 struct drm_crtc_state *crtc_state, 717 struct drm_connector_state *conn_state, 718 u32 output_fmt, 719 unsigned int *num_input_fmts) 720 { 721 u32 *input_fmts; 722 723 *num_input_fmts = 0; 724 725 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 726 GFP_KERNEL); 727 if (!input_fmts) 728 return NULL; 729 730 /* This is the DSI-end bus format */ 731 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 732 *num_input_fmts = 1; 733 734 return input_fmts; 735 } 736 737 static const struct drm_bridge_funcs sn65dsi83_funcs = { 738 .attach = sn65dsi83_attach, 739 .detach = sn65dsi83_detach, 740 .atomic_enable = sn65dsi83_atomic_enable, 741 .atomic_pre_enable = sn65dsi83_atomic_pre_enable, 742 .atomic_disable = sn65dsi83_atomic_disable, 743 .mode_valid = sn65dsi83_mode_valid, 744 745 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 746 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 747 .atomic_reset = drm_atomic_helper_bridge_reset, 748 .atomic_get_input_bus_fmts = sn65dsi83_atomic_get_input_bus_fmts, 749 }; 750 751 static int sn65dsi83_select_lvds_vod_swing(struct device *dev, 752 u32 lvds_vod_swing_data[2], u32 lvds_vod_swing_clk[2], u8 lvds_term) 753 { 754 int i; 755 756 for (i = 0; i <= 3; i++) { 757 if (lvds_vod_swing_data_table[lvds_term][i][0] >= lvds_vod_swing_data[0] && 758 lvds_vod_swing_data_table[lvds_term][i][1] <= lvds_vod_swing_data[1] && 759 lvds_vod_swing_clock_table[lvds_term][i][0] >= lvds_vod_swing_clk[0] && 760 lvds_vod_swing_clock_table[lvds_term][i][1] <= lvds_vod_swing_clk[1]) 761 return i; 762 } 763 764 dev_err(dev, "failed to find appropriate LVDS_VOD_SWING configuration\n"); 765 return -EINVAL; 766 } 767 768 static int sn65dsi83_parse_lvds_endpoint(struct sn65dsi83 *ctx, int channel) 769 { 770 struct device *dev = ctx->dev; 771 struct device_node *endpoint; 772 int endpoint_reg; 773 /* Set so the property can be freely selected if not defined */ 774 u32 lvds_vod_swing_data[2] = { 0, 1000000 }; 775 u32 lvds_vod_swing_clk[2] = { 0, 1000000 }; 776 /* Set default near end terminataion to 200 Ohm */ 777 u32 lvds_term = 200; 778 int lvds_vod_swing_conf; 779 int ret = 0; 780 int ret_data; 781 int ret_clock; 782 783 if (channel == CHANNEL_A) 784 endpoint_reg = 2; 785 else 786 endpoint_reg = 3; 787 788 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, endpoint_reg, -1); 789 790 of_property_read_u32(endpoint, "ti,lvds-termination-ohms", &lvds_term); 791 if (lvds_term == 100) 792 ctx->lvds_term_conf[channel] = OHM_100; 793 else if (lvds_term == 200) 794 ctx->lvds_term_conf[channel] = OHM_200; 795 else { 796 ret = -EINVAL; 797 goto exit; 798 } 799 800 ret_data = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-data-microvolt", 801 lvds_vod_swing_data, ARRAY_SIZE(lvds_vod_swing_data)); 802 if (ret_data != 0 && ret_data != -EINVAL) { 803 ret = ret_data; 804 goto exit; 805 } 806 807 ret_clock = of_property_read_u32_array(endpoint, "ti,lvds-vod-swing-clock-microvolt", 808 lvds_vod_swing_clk, ARRAY_SIZE(lvds_vod_swing_clk)); 809 if (ret_clock != 0 && ret_clock != -EINVAL) { 810 ret = ret_clock; 811 goto exit; 812 } 813 814 /* Use default value if both properties are NOT defined. */ 815 if (ret_data == -EINVAL && ret_clock == -EINVAL) 816 lvds_vod_swing_conf = 0x1; 817 818 /* Use lookup table if any of the two properties is defined. */ 819 if (!ret_data || !ret_clock) { 820 lvds_vod_swing_conf = sn65dsi83_select_lvds_vod_swing(dev, lvds_vod_swing_data, 821 lvds_vod_swing_clk, ctx->lvds_term_conf[channel]); 822 if (lvds_vod_swing_conf < 0) { 823 ret = lvds_vod_swing_conf; 824 goto exit; 825 } 826 } 827 828 ctx->lvds_vod_swing_conf[channel] = lvds_vod_swing_conf; 829 ret = 0; 830 exit: 831 of_node_put(endpoint); 832 return ret; 833 } 834 835 static int sn65dsi83_parse_dt(struct sn65dsi83 *ctx, enum sn65dsi83_model model) 836 { 837 struct drm_bridge *panel_bridge; 838 struct device *dev = ctx->dev; 839 int ret; 840 841 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_A); 842 if (ret < 0) 843 return ret; 844 845 ret = sn65dsi83_parse_lvds_endpoint(ctx, CHANNEL_B); 846 if (ret < 0) 847 return ret; 848 849 ctx->lvds_dual_link = false; 850 ctx->lvds_dual_link_even_odd_swap = false; 851 if (model != MODEL_SN65DSI83) { 852 struct device_node *port2, *port3; 853 int dual_link; 854 855 port2 = of_graph_get_port_by_id(dev->of_node, 2); 856 port3 = of_graph_get_port_by_id(dev->of_node, 3); 857 dual_link = drm_of_lvds_get_dual_link_pixel_order(port2, port3); 858 of_node_put(port2); 859 of_node_put(port3); 860 861 if (dual_link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS) { 862 ctx->lvds_dual_link = true; 863 /* Odd pixels to LVDS Channel A, even pixels to B */ 864 ctx->lvds_dual_link_even_odd_swap = false; 865 } else if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { 866 ctx->lvds_dual_link = true; 867 /* Even pixels to LVDS Channel A, odd pixels to B */ 868 ctx->lvds_dual_link_even_odd_swap = true; 869 } 870 } 871 872 panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0); 873 if (IS_ERR(panel_bridge)) 874 return dev_err_probe(dev, PTR_ERR(panel_bridge), "Failed to get panel bridge\n"); 875 876 ctx->panel_bridge = panel_bridge; 877 878 ctx->vcc = devm_regulator_get(dev, "vcc"); 879 if (IS_ERR(ctx->vcc)) 880 return dev_err_probe(dev, PTR_ERR(ctx->vcc), 881 "Failed to get supply 'vcc'\n"); 882 883 return 0; 884 } 885 886 static int sn65dsi83_host_attach(struct sn65dsi83 *ctx) 887 { 888 struct device *dev = ctx->dev; 889 struct device_node *host_node; 890 struct device_node *endpoint; 891 struct mipi_dsi_device *dsi; 892 struct mipi_dsi_host *host; 893 const struct mipi_dsi_device_info info = { 894 .type = "sn65dsi83", 895 .channel = 0, 896 .node = NULL, 897 }; 898 int dsi_lanes, ret; 899 900 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); 901 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4); 902 host_node = of_graph_get_remote_port_parent(endpoint); 903 host = of_find_mipi_dsi_host_by_node(host_node); 904 of_node_put(host_node); 905 of_node_put(endpoint); 906 907 if (!host) 908 return -EPROBE_DEFER; 909 910 if (dsi_lanes < 0) 911 return dsi_lanes; 912 913 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 914 if (IS_ERR(dsi)) 915 return dev_err_probe(dev, PTR_ERR(dsi), 916 "failed to create dsi device\n"); 917 918 ctx->dsi = dsi; 919 920 dsi->lanes = dsi_lanes; 921 dsi->format = MIPI_DSI_FMT_RGB888; 922 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 923 MIPI_DSI_MODE_VIDEO_NO_HFP | MIPI_DSI_MODE_VIDEO_NO_HBP | 924 MIPI_DSI_MODE_VIDEO_NO_HSA | MIPI_DSI_MODE_NO_EOT_PACKET; 925 926 ret = devm_mipi_dsi_attach(dev, dsi); 927 if (ret < 0) { 928 dev_err(dev, "failed to attach dsi to host: %d\n", ret); 929 return ret; 930 } 931 932 return 0; 933 } 934 935 static irqreturn_t sn65dsi83_irq(int irq, void *data) 936 { 937 struct sn65dsi83 *ctx = data; 938 939 sn65dsi83_handle_errors(ctx); 940 return IRQ_HANDLED; 941 } 942 943 static int sn65dsi83_probe(struct i2c_client *client) 944 { 945 const struct i2c_device_id *id = i2c_client_get_device_id(client); 946 struct device *dev = &client->dev; 947 enum sn65dsi83_model model; 948 struct sn65dsi83 *ctx; 949 int ret; 950 951 ctx = devm_drm_bridge_alloc(dev, struct sn65dsi83, bridge, &sn65dsi83_funcs); 952 if (IS_ERR(ctx)) 953 return PTR_ERR(ctx); 954 955 ctx->dev = dev; 956 INIT_WORK(&ctx->reset_work, sn65dsi83_reset_work); 957 INIT_DELAYED_WORK(&ctx->monitor_work, sn65dsi83_monitor_work); 958 959 if (dev->of_node) { 960 model = (enum sn65dsi83_model)(uintptr_t) 961 of_device_get_match_data(dev); 962 } else { 963 model = id->driver_data; 964 } 965 966 /* Put the chip in reset, pull EN line low, and assure 10ms reset low timing. */ 967 ctx->enable_gpio = devm_gpiod_get_optional(ctx->dev, "enable", 968 GPIOD_OUT_LOW); 969 if (IS_ERR(ctx->enable_gpio)) 970 return dev_err_probe(dev, PTR_ERR(ctx->enable_gpio), "failed to get enable GPIO\n"); 971 972 usleep_range(10000, 11000); 973 974 ret = sn65dsi83_parse_dt(ctx, model); 975 if (ret) 976 return ret; 977 978 ctx->regmap = devm_regmap_init_i2c(client, &sn65dsi83_regmap_config); 979 if (IS_ERR(ctx->regmap)) 980 return dev_err_probe(dev, PTR_ERR(ctx->regmap), "failed to get regmap\n"); 981 982 if (client->irq) { 983 ctx->irq = client->irq; 984 ret = devm_request_threaded_irq(ctx->dev, ctx->irq, NULL, sn65dsi83_irq, 985 IRQF_ONESHOT, dev_name(ctx->dev), ctx); 986 if (ret) 987 return dev_err_probe(dev, ret, "failed to request irq\n"); 988 } 989 990 dev_set_drvdata(dev, ctx); 991 i2c_set_clientdata(client, ctx); 992 993 ctx->bridge.of_node = dev->of_node; 994 ctx->bridge.pre_enable_prev_first = true; 995 ctx->bridge.type = DRM_MODE_CONNECTOR_LVDS; 996 drm_bridge_add(&ctx->bridge); 997 998 ret = sn65dsi83_host_attach(ctx); 999 if (ret) { 1000 dev_err_probe(dev, ret, "failed to attach DSI host\n"); 1001 goto err_remove_bridge; 1002 } 1003 1004 return 0; 1005 1006 err_remove_bridge: 1007 drm_bridge_remove(&ctx->bridge); 1008 return ret; 1009 } 1010 1011 static void sn65dsi83_remove(struct i2c_client *client) 1012 { 1013 struct sn65dsi83 *ctx = i2c_get_clientdata(client); 1014 1015 drm_bridge_remove(&ctx->bridge); 1016 } 1017 1018 static const struct i2c_device_id sn65dsi83_id[] = { 1019 { "ti,sn65dsi83", MODEL_SN65DSI83 }, 1020 { "ti,sn65dsi84", MODEL_SN65DSI84 }, 1021 {}, 1022 }; 1023 MODULE_DEVICE_TABLE(i2c, sn65dsi83_id); 1024 1025 static const struct of_device_id sn65dsi83_match_table[] = { 1026 { .compatible = "ti,sn65dsi83", .data = (void *)MODEL_SN65DSI83 }, 1027 { .compatible = "ti,sn65dsi84", .data = (void *)MODEL_SN65DSI84 }, 1028 {}, 1029 }; 1030 MODULE_DEVICE_TABLE(of, sn65dsi83_match_table); 1031 1032 static struct i2c_driver sn65dsi83_driver = { 1033 .probe = sn65dsi83_probe, 1034 .remove = sn65dsi83_remove, 1035 .id_table = sn65dsi83_id, 1036 .driver = { 1037 .name = "sn65dsi83", 1038 .of_match_table = sn65dsi83_match_table, 1039 }, 1040 }; 1041 module_i2c_driver(sn65dsi83_driver); 1042 1043 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 1044 MODULE_DESCRIPTION("TI SN65DSI83 DSI to LVDS bridge driver"); 1045 MODULE_LICENSE("GPL v2"); 1046