1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2025 Icenowy Zheng <uwu@icenowy.me> 4 * 5 * Based on rcar_dw_hdmi.c, which is: 6 * Copyright (C) 2016 Renesas Electronics Corporation 7 * Based on imx8mp-hdmi-tx.c, which is: 8 * Copyright (C) 2022 Pengutronix, Lucas Stach <kernel@pengutronix.de> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/module.h> 13 #include <linux/platform_device.h> 14 #include <linux/reset.h> 15 16 #include <drm/bridge/dw_hdmi.h> 17 #include <drm/drm_modes.h> 18 19 #define TH1520_HDMI_PHY_OPMODE_PLLCFG 0x06 /* Mode of operation and PLL dividers */ 20 #define TH1520_HDMI_PHY_CKSYMTXCTRL 0x09 /* Clock Symbol and Transmitter Control Register */ 21 #define TH1520_HDMI_PHY_VLEVCTRL 0x0e /* Voltage Level Control Register */ 22 #define TH1520_HDMI_PHY_PLLCURRGMPCTRL 0x10 /* PLL current and Gmp (conductance) */ 23 #define TH1520_HDMI_PHY_PLLDIVCTRL 0x11 /* PLL dividers */ 24 #define TH1520_HDMI_PHY_TXTERM 0x19 /* Transmission Termination Register */ 25 26 struct th1520_hdmi_phy_params { 27 unsigned long mpixelclock; 28 u16 opmode_pllcfg; 29 u16 pllcurrgmpctrl; 30 u16 plldivctrl; 31 u16 cksymtxctrl; 32 u16 vlevctrl; 33 u16 txterm; 34 }; 35 36 static const struct th1520_hdmi_phy_params th1520_hdmi_phy_params[] = { 37 { 35500000, 0x0003, 0x0283, 0x0628, 0x8088, 0x01a0, 0x0007 }, 38 { 44900000, 0x0003, 0x0285, 0x0228, 0x8088, 0x01a0, 0x0007 }, 39 { 71000000, 0x0002, 0x1183, 0x0614, 0x8088, 0x01a0, 0x0007 }, 40 { 90000000, 0x0002, 0x1142, 0x0214, 0x8088, 0x01a0, 0x0007 }, 41 { 121750000, 0x0001, 0x20c0, 0x060a, 0x8088, 0x01a0, 0x0007 }, 42 { 165000000, 0x0001, 0x2080, 0x020a, 0x8088, 0x01a0, 0x0007 }, 43 { 198000000, 0x0000, 0x3040, 0x0605, 0x83c8, 0x0120, 0x0004 }, 44 { 297000000, 0x0000, 0x3041, 0x0205, 0x81dc, 0x0200, 0x0005 }, 45 { 371250000, 0x0640, 0x3041, 0x0205, 0x80f6, 0x0140, 0x0000 }, 46 { 495000000, 0x0640, 0x3080, 0x0005, 0x80f6, 0x0140, 0x0000 }, 47 { 594000000, 0x0640, 0x3080, 0x0005, 0x80fa, 0x01e0, 0x0004 }, 48 }; 49 50 struct th1520_hdmi { 51 struct dw_hdmi_plat_data plat_data; 52 struct dw_hdmi *dw_hdmi; 53 struct clk *pixclk; 54 struct reset_control *mainrst, *prst; 55 }; 56 57 static enum drm_mode_status 58 th1520_hdmi_mode_valid(struct dw_hdmi *hdmi, void *data, 59 const struct drm_display_info *info, 60 const struct drm_display_mode *mode) 61 { 62 /* 63 * The maximum supported clock frequency is 594 MHz, as shown in the PHY 64 * parameters table. 65 */ 66 if (mode->clock > 594000) 67 return MODE_CLOCK_HIGH; 68 69 return MODE_OK; 70 } 71 72 static void th1520_hdmi_phy_set_params(struct dw_hdmi *hdmi, 73 const struct th1520_hdmi_phy_params *params) 74 { 75 dw_hdmi_phy_i2c_write(hdmi, params->opmode_pllcfg, 76 TH1520_HDMI_PHY_OPMODE_PLLCFG); 77 dw_hdmi_phy_i2c_write(hdmi, params->pllcurrgmpctrl, 78 TH1520_HDMI_PHY_PLLCURRGMPCTRL); 79 dw_hdmi_phy_i2c_write(hdmi, params->plldivctrl, 80 TH1520_HDMI_PHY_PLLDIVCTRL); 81 dw_hdmi_phy_i2c_write(hdmi, params->vlevctrl, 82 TH1520_HDMI_PHY_VLEVCTRL); 83 dw_hdmi_phy_i2c_write(hdmi, params->cksymtxctrl, 84 TH1520_HDMI_PHY_CKSYMTXCTRL); 85 dw_hdmi_phy_i2c_write(hdmi, params->txterm, 86 TH1520_HDMI_PHY_TXTERM); 87 } 88 89 static int th1520_hdmi_phy_configure(struct dw_hdmi *hdmi, void *data, 90 unsigned long mpixelclock) 91 { 92 unsigned int i; 93 94 for (i = 0; i < ARRAY_SIZE(th1520_hdmi_phy_params); i++) { 95 if (mpixelclock <= th1520_hdmi_phy_params[i].mpixelclock) { 96 th1520_hdmi_phy_set_params(hdmi, 97 &th1520_hdmi_phy_params[i]); 98 return 0; 99 } 100 } 101 102 return -EINVAL; 103 } 104 105 static int th1520_dw_hdmi_probe(struct platform_device *pdev) 106 { 107 struct th1520_hdmi *hdmi; 108 struct dw_hdmi_plat_data *plat_data; 109 struct device *dev = &pdev->dev; 110 111 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 112 if (!hdmi) 113 return -ENOMEM; 114 115 plat_data = &hdmi->plat_data; 116 117 hdmi->pixclk = devm_clk_get_enabled(dev, "pix"); 118 if (IS_ERR(hdmi->pixclk)) 119 return dev_err_probe(dev, PTR_ERR(hdmi->pixclk), 120 "Unable to get pixel clock\n"); 121 122 hdmi->mainrst = devm_reset_control_get_exclusive_deasserted(dev, "main"); 123 if (IS_ERR(hdmi->mainrst)) 124 return dev_err_probe(dev, PTR_ERR(hdmi->mainrst), 125 "Unable to get main reset\n"); 126 127 hdmi->prst = devm_reset_control_get_exclusive_deasserted(dev, "apb"); 128 if (IS_ERR(hdmi->prst)) 129 return dev_err_probe(dev, PTR_ERR(hdmi->prst), 130 "Unable to get apb reset\n"); 131 132 plat_data->output_port = 1; 133 plat_data->mode_valid = th1520_hdmi_mode_valid; 134 plat_data->configure_phy = th1520_hdmi_phy_configure; 135 plat_data->priv_data = hdmi; 136 137 hdmi->dw_hdmi = dw_hdmi_probe(pdev, plat_data); 138 if (IS_ERR(hdmi)) 139 return PTR_ERR(hdmi); 140 141 platform_set_drvdata(pdev, hdmi); 142 143 return 0; 144 } 145 146 static void th1520_dw_hdmi_remove(struct platform_device *pdev) 147 { 148 struct dw_hdmi *hdmi = platform_get_drvdata(pdev); 149 150 dw_hdmi_remove(hdmi); 151 } 152 153 static const struct of_device_id th1520_dw_hdmi_of_table[] = { 154 { .compatible = "thead,th1520-dw-hdmi" }, 155 { /* Sentinel */ }, 156 }; 157 MODULE_DEVICE_TABLE(of, th1520_dw_hdmi_of_table); 158 159 static struct platform_driver th1520_dw_hdmi_platform_driver = { 160 .probe = th1520_dw_hdmi_probe, 161 .remove = th1520_dw_hdmi_remove, 162 .driver = { 163 .name = "th1520-dw-hdmi", 164 .of_match_table = th1520_dw_hdmi_of_table, 165 }, 166 }; 167 168 module_platform_driver(th1520_dw_hdmi_platform_driver); 169 170 MODULE_AUTHOR("Icenowy Zheng <uwu@icenowy.me>"); 171 MODULE_DESCRIPTION("T-Head TH1520 HDMI Encoder Driver"); 172 MODULE_LICENSE("GPL"); 173