1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Texas Instruments 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/gpio/consumer.h> 9 #include <linux/hdmi.h> 10 #include <linux/i2c.h> 11 #include <linux/module.h> 12 #include <linux/platform_data/tda9950.h> 13 #include <linux/irq.h> 14 #include <sound/asoundef.h> 15 #include <sound/hdmi-codec.h> 16 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_bridge.h> 19 #include <drm/drm_edid.h> 20 #include <drm/drm_of.h> 21 #include <drm/drm_print.h> 22 #include <drm/drm_probe_helper.h> 23 #include <drm/drm_simple_kms_helper.h> 24 25 #include <media/cec-notifier.h> 26 27 #include <dt-bindings/display/tda998x.h> 28 29 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 30 31 enum { 32 AUDIO_ROUTE_I2S, 33 AUDIO_ROUTE_SPDIF, 34 AUDIO_ROUTE_NUM 35 }; 36 37 struct tda998x_audio_route { 38 u8 ena_aclk; 39 u8 mux_ap; 40 u8 aip_clksel; 41 }; 42 43 struct tda998x_audio_settings { 44 const struct tda998x_audio_route *route; 45 struct hdmi_audio_infoframe cea; 46 unsigned int sample_rate; 47 u8 status[5]; 48 u8 ena_ap; 49 u8 i2s_format; 50 u8 cts_n; 51 }; 52 53 struct tda998x_priv { 54 struct i2c_client *cec; 55 struct i2c_client *hdmi; 56 struct mutex mutex; 57 u16 rev; 58 u8 cec_addr; 59 u8 current_page; 60 bool is_on; 61 bool supports_infoframes; 62 bool sink_has_audio; 63 enum hdmi_quantization_range rgb_quant_range; 64 u8 vip_cntrl_0; 65 u8 vip_cntrl_1; 66 u8 vip_cntrl_2; 67 unsigned long tmds_clock; 68 struct tda998x_audio_settings audio; 69 70 struct platform_device *audio_pdev; 71 struct mutex audio_mutex; 72 73 struct mutex edid_mutex; 74 wait_queue_head_t wq_edid; 75 volatile int wq_edid_wait; 76 77 struct work_struct detect_work; 78 struct timer_list edid_delay_timer; 79 wait_queue_head_t edid_delay_waitq; 80 bool edid_delay_active; 81 82 struct drm_encoder encoder; 83 struct drm_bridge bridge; 84 struct drm_connector connector; 85 86 u8 audio_port_enable[AUDIO_ROUTE_NUM]; 87 struct tda9950_glue cec_glue; 88 struct gpio_desc *calib; 89 struct cec_notifier *cec_notify; 90 }; 91 92 #define conn_to_tda998x_priv(x) \ 93 container_of(x, struct tda998x_priv, connector) 94 #define enc_to_tda998x_priv(x) \ 95 container_of(x, struct tda998x_priv, encoder) 96 #define bridge_to_tda998x_priv(x) \ 97 container_of(x, struct tda998x_priv, bridge) 98 99 /* The TDA9988 series of devices use a paged register scheme.. to simplify 100 * things we encode the page # in upper bits of the register #. To read/ 101 * write a given register, we need to make sure CURPAGE register is set 102 * appropriately. Which implies reads/writes are not atomic. Fun! 103 */ 104 105 #define REG(page, addr) (((page) << 8) | (addr)) 106 #define REG2ADDR(reg) ((reg) & 0xff) 107 #define REG2PAGE(reg) (((reg) >> 8) & 0xff) 108 109 #define REG_CURPAGE 0xff /* write */ 110 111 112 /* Page 00h: General Control */ 113 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ 114 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ 115 # define MAIN_CNTRL0_SR (1 << 0) 116 # define MAIN_CNTRL0_DECS (1 << 1) 117 # define MAIN_CNTRL0_DEHS (1 << 2) 118 # define MAIN_CNTRL0_CECS (1 << 3) 119 # define MAIN_CNTRL0_CEHS (1 << 4) 120 # define MAIN_CNTRL0_SCALER (1 << 7) 121 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ 122 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ 123 # define SOFTRESET_AUDIO (1 << 0) 124 # define SOFTRESET_I2C_MASTER (1 << 1) 125 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ 126 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ 127 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ 128 # define I2C_MASTER_DIS_MM (1 << 0) 129 # define I2C_MASTER_DIS_FILT (1 << 1) 130 # define I2C_MASTER_APP_STRT_LAT (1 << 2) 131 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ 132 # define FEAT_POWERDOWN_PREFILT BIT(0) 133 # define FEAT_POWERDOWN_CSC BIT(1) 134 # define FEAT_POWERDOWN_SPDIF (1 << 3) 135 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ 136 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ 137 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ 138 # define INT_FLAGS_2_EDID_BLK_RD (1 << 1) 139 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ 140 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ 141 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ 142 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ 143 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ 144 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ 145 # define VIP_CNTRL_0_MIRR_A (1 << 7) 146 # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) 147 # define VIP_CNTRL_0_MIRR_B (1 << 3) 148 # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) 149 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ 150 # define VIP_CNTRL_1_MIRR_C (1 << 7) 151 # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) 152 # define VIP_CNTRL_1_MIRR_D (1 << 3) 153 # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) 154 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ 155 # define VIP_CNTRL_2_MIRR_E (1 << 7) 156 # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) 157 # define VIP_CNTRL_2_MIRR_F (1 << 3) 158 # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) 159 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ 160 # define VIP_CNTRL_3_X_TGL (1 << 0) 161 # define VIP_CNTRL_3_H_TGL (1 << 1) 162 # define VIP_CNTRL_3_V_TGL (1 << 2) 163 # define VIP_CNTRL_3_EMB (1 << 3) 164 # define VIP_CNTRL_3_SYNC_DE (1 << 4) 165 # define VIP_CNTRL_3_SYNC_HS (1 << 5) 166 # define VIP_CNTRL_3_DE_INT (1 << 6) 167 # define VIP_CNTRL_3_EDGE (1 << 7) 168 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ 169 # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) 170 # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) 171 # define VIP_CNTRL_4_CCIR656 (1 << 4) 172 # define VIP_CNTRL_4_656_ALT (1 << 5) 173 # define VIP_CNTRL_4_TST_656 (1 << 6) 174 # define VIP_CNTRL_4_TST_PAT (1 << 7) 175 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ 176 # define VIP_CNTRL_5_CKCASE (1 << 0) 177 # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) 178 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */ 179 # define MUX_AP_SELECT_I2S 0x64 180 # define MUX_AP_SELECT_SPDIF 0x40 181 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ 182 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ 183 # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) 184 # define MAT_CONTRL_MAT_BP (1 << 2) 185 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ 186 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ 187 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ 188 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ 189 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ 190 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ 191 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ 192 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ 193 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ 194 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ 195 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ 196 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ 197 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ 198 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ 199 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ 200 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ 201 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ 202 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ 203 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ 204 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ 205 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ 206 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ 207 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ 208 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ 209 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ 210 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ 211 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ 212 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ 213 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ 214 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ 215 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ 216 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ 217 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ 218 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ 219 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ 220 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ 221 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ 222 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ 223 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ 224 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ 225 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ 226 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ 227 # define TBG_CNTRL_0_TOP_TGL (1 << 0) 228 # define TBG_CNTRL_0_TOP_SEL (1 << 1) 229 # define TBG_CNTRL_0_DE_EXT (1 << 2) 230 # define TBG_CNTRL_0_TOP_EXT (1 << 3) 231 # define TBG_CNTRL_0_FRAME_DIS (1 << 5) 232 # define TBG_CNTRL_0_SYNC_MTHD (1 << 6) 233 # define TBG_CNTRL_0_SYNC_ONCE (1 << 7) 234 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ 235 # define TBG_CNTRL_1_H_TGL (1 << 0) 236 # define TBG_CNTRL_1_V_TGL (1 << 1) 237 # define TBG_CNTRL_1_TGL_EN (1 << 2) 238 # define TBG_CNTRL_1_X_EXT (1 << 3) 239 # define TBG_CNTRL_1_H_EXT (1 << 4) 240 # define TBG_CNTRL_1_V_EXT (1 << 5) 241 # define TBG_CNTRL_1_DWIN_DIS (1 << 6) 242 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ 243 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ 244 # define HVF_CNTRL_0_SM (1 << 7) 245 # define HVF_CNTRL_0_RWB (1 << 6) 246 # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) 247 # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) 248 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ 249 # define HVF_CNTRL_1_FOR (1 << 0) 250 # define HVF_CNTRL_1_YUVBLK (1 << 1) 251 # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 252 # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) 253 # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) 254 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ 255 # define RPT_CNTRL_REPEAT(x) ((x) & 15) 256 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ 257 # define I2S_FORMAT_PHILIPS (0 << 0) 258 # define I2S_FORMAT_LEFT_J (2 << 0) 259 # define I2S_FORMAT_RIGHT_J (3 << 0) 260 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ 261 # define AIP_CLKSEL_AIP_SPDIF (0 << 3) 262 # define AIP_CLKSEL_AIP_I2S (1 << 3) 263 # define AIP_CLKSEL_FS_ACLK (0 << 0) 264 # define AIP_CLKSEL_FS_MCLK (1 << 0) 265 # define AIP_CLKSEL_FS_FS64SPDIF (2 << 0) 266 267 /* Page 02h: PLL settings */ 268 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ 269 # define PLL_SERIAL_1_SRL_FDN (1 << 0) 270 # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) 271 # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) 272 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ 273 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0) 274 # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 275 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ 276 # define PLL_SERIAL_3_SRL_CCIR (1 << 0) 277 # define PLL_SERIAL_3_SRL_DE (1 << 2) 278 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) 279 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ 280 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ 281 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ 282 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ 283 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ 284 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ 285 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ 286 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ 287 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ 288 # define AUDIO_DIV_SERCLK_1 0 289 # define AUDIO_DIV_SERCLK_2 1 290 # define AUDIO_DIV_SERCLK_4 2 291 # define AUDIO_DIV_SERCLK_8 3 292 # define AUDIO_DIV_SERCLK_16 4 293 # define AUDIO_DIV_SERCLK_32 5 294 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ 295 # define SEL_CLK_SEL_CLK1 (1 << 0) 296 # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 297 # define SEL_CLK_ENA_SC_CLK (1 << 3) 298 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ 299 300 301 /* Page 09h: EDID Control */ 302 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ 303 /* next 127 successive registers are the EDID block */ 304 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ 305 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ 306 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ 307 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ 308 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ 309 310 311 /* Page 10h: information frames and packets */ 312 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ 313 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ 314 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ 315 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ 316 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ 317 318 319 /* Page 11h: audio settings and content info packets */ 320 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ 321 # define AIP_CNTRL_0_RST_FIFO (1 << 0) 322 # define AIP_CNTRL_0_SWAP (1 << 1) 323 # define AIP_CNTRL_0_LAYOUT (1 << 2) 324 # define AIP_CNTRL_0_ACR_MAN (1 << 5) 325 # define AIP_CNTRL_0_RST_CTS (1 << 6) 326 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */ 327 # define CA_I2S_CA_I2S(x) (((x) & 31) << 0) 328 # define CA_I2S_HBR_CHSTAT (1 << 6) 329 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ 330 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ 331 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ 332 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ 333 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ 334 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ 335 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ 336 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */ 337 # define CTS_N_K(x) (((x) & 7) << 0) 338 # define CTS_N_M(x) (((x) & 3) << 4) 339 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ 340 # define ENC_CNTRL_RST_ENC (1 << 0) 341 # define ENC_CNTRL_RST_SEL (1 << 1) 342 # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) 343 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ 344 # define DIP_FLAGS_ACR (1 << 0) 345 # define DIP_FLAGS_GC (1 << 1) 346 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ 347 # define DIP_IF_FLAGS_IF1 (1 << 1) 348 # define DIP_IF_FLAGS_IF2 (1 << 2) 349 # define DIP_IF_FLAGS_IF3 (1 << 3) 350 # define DIP_IF_FLAGS_IF4 (1 << 4) 351 # define DIP_IF_FLAGS_IF5 (1 << 5) 352 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ 353 354 355 /* Page 12h: HDCP and OTP */ 356 #define REG_TX3 REG(0x12, 0x9a) /* read/write */ 357 #define REG_TX4 REG(0x12, 0x9b) /* read/write */ 358 # define TX4_PD_RAM (1 << 1) 359 #define REG_TX33 REG(0x12, 0xb8) /* read/write */ 360 # define TX33_HDMI (1 << 1) 361 362 363 /* Page 13h: Gamut related metadata packets */ 364 365 366 367 /* CEC registers: (not paged) 368 */ 369 #define REG_CEC_INTSTATUS 0xee /* read */ 370 # define CEC_INTSTATUS_CEC (1 << 0) 371 # define CEC_INTSTATUS_HDMI (1 << 1) 372 #define REG_CEC_CAL_XOSC_CTRL1 0xf2 373 # define CEC_CAL_XOSC_CTRL1_ENA_CAL BIT(0) 374 #define REG_CEC_DES_FREQ2 0xf5 375 # define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7) 376 #define REG_CEC_CLK 0xf6 377 # define CEC_CLK_FRO 0x11 378 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ 379 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) 380 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) 381 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) 382 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) 383 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */ 384 #define REG_CEC_RXSHPDINT 0xfd /* read */ 385 # define CEC_RXSHPDINT_RXSENS BIT(0) 386 # define CEC_RXSHPDINT_HPD BIT(1) 387 #define REG_CEC_RXSHPDLEV 0xfe /* read */ 388 # define CEC_RXSHPDLEV_RXSENS (1 << 0) 389 # define CEC_RXSHPDLEV_HPD (1 << 1) 390 391 #define REG_CEC_ENAMODS 0xff /* read/write */ 392 # define CEC_ENAMODS_EN_CEC_CLK (1 << 7) 393 # define CEC_ENAMODS_DIS_FRO (1 << 6) 394 # define CEC_ENAMODS_DIS_CCLK (1 << 5) 395 # define CEC_ENAMODS_EN_RXSENS (1 << 2) 396 # define CEC_ENAMODS_EN_HDMI (1 << 1) 397 # define CEC_ENAMODS_EN_CEC (1 << 0) 398 399 400 /* Device versions: */ 401 #define TDA9989N2 0x0101 402 #define TDA19989 0x0201 403 #define TDA19989N2 0x0202 404 #define TDA19988 0x0301 405 406 static void 407 cec_write(struct tda998x_priv *priv, u16 addr, u8 val) 408 { 409 u8 buf[] = {addr, val}; 410 struct i2c_msg msg = { 411 .addr = priv->cec_addr, 412 .len = 2, 413 .buf = buf, 414 }; 415 int ret; 416 417 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1); 418 if (ret < 0) 419 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n", 420 ret, addr); 421 } 422 423 static u8 424 cec_read(struct tda998x_priv *priv, u8 addr) 425 { 426 u8 val; 427 struct i2c_msg msg[2] = { 428 { 429 .addr = priv->cec_addr, 430 .len = 1, 431 .buf = &addr, 432 }, { 433 .addr = priv->cec_addr, 434 .flags = I2C_M_RD, 435 .len = 1, 436 .buf = &val, 437 }, 438 }; 439 int ret; 440 441 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg)); 442 if (ret < 0) { 443 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n", 444 ret, addr); 445 val = 0; 446 } 447 448 return val; 449 } 450 451 static void cec_enamods(struct tda998x_priv *priv, u8 mods, bool enable) 452 { 453 int val = cec_read(priv, REG_CEC_ENAMODS); 454 455 if (val < 0) 456 return; 457 458 if (enable) 459 val |= mods; 460 else 461 val &= ~mods; 462 463 cec_write(priv, REG_CEC_ENAMODS, val); 464 } 465 466 static void tda998x_cec_set_calibration(struct tda998x_priv *priv, bool enable) 467 { 468 if (enable) { 469 u8 val; 470 471 cec_write(priv, 0xf3, 0xc0); 472 cec_write(priv, 0xf4, 0xd4); 473 474 /* Enable automatic calibration mode */ 475 val = cec_read(priv, REG_CEC_DES_FREQ2); 476 val &= ~CEC_DES_FREQ2_DIS_AUTOCAL; 477 cec_write(priv, REG_CEC_DES_FREQ2, val); 478 479 /* Enable free running oscillator */ 480 cec_write(priv, REG_CEC_CLK, CEC_CLK_FRO); 481 cec_enamods(priv, CEC_ENAMODS_DIS_FRO, false); 482 483 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 484 CEC_CAL_XOSC_CTRL1_ENA_CAL); 485 } else { 486 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0); 487 } 488 } 489 490 /* 491 * Calibration for the internal oscillator: we need to set calibration mode, 492 * and then pulse the IRQ line low for a 10ms ± 1% period. 493 */ 494 static void tda998x_cec_calibration(struct tda998x_priv *priv) 495 { 496 struct gpio_desc *calib = priv->calib; 497 498 mutex_lock(&priv->edid_mutex); 499 if (priv->hdmi->irq > 0) 500 disable_irq(priv->hdmi->irq); 501 gpiod_direction_output(calib, 1); 502 tda998x_cec_set_calibration(priv, true); 503 504 local_irq_disable(); 505 gpiod_set_value(calib, 0); 506 mdelay(10); 507 gpiod_set_value(calib, 1); 508 local_irq_enable(); 509 510 tda998x_cec_set_calibration(priv, false); 511 gpiod_direction_input(calib); 512 if (priv->hdmi->irq > 0) 513 enable_irq(priv->hdmi->irq); 514 mutex_unlock(&priv->edid_mutex); 515 } 516 517 static int tda998x_cec_hook_init(void *data) 518 { 519 struct tda998x_priv *priv = data; 520 struct gpio_desc *calib; 521 522 calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS); 523 if (IS_ERR(calib)) { 524 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n", 525 PTR_ERR(calib)); 526 return PTR_ERR(calib); 527 } 528 529 priv->calib = calib; 530 531 return 0; 532 } 533 534 static void tda998x_cec_hook_exit(void *data) 535 { 536 struct tda998x_priv *priv = data; 537 538 gpiod_put(priv->calib); 539 priv->calib = NULL; 540 } 541 542 static int tda998x_cec_hook_open(void *data) 543 { 544 struct tda998x_priv *priv = data; 545 546 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, true); 547 tda998x_cec_calibration(priv); 548 549 return 0; 550 } 551 552 static void tda998x_cec_hook_release(void *data) 553 { 554 struct tda998x_priv *priv = data; 555 556 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, false); 557 } 558 559 static int 560 set_page(struct tda998x_priv *priv, u16 reg) 561 { 562 if (REG2PAGE(reg) != priv->current_page) { 563 struct i2c_client *client = priv->hdmi; 564 u8 buf[] = { 565 REG_CURPAGE, REG2PAGE(reg) 566 }; 567 int ret = i2c_master_send(client, buf, sizeof(buf)); 568 if (ret < 0) { 569 dev_err(&client->dev, "%s %04x err %d\n", __func__, 570 reg, ret); 571 return ret; 572 } 573 574 priv->current_page = REG2PAGE(reg); 575 } 576 return 0; 577 } 578 579 static int 580 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt) 581 { 582 struct i2c_client *client = priv->hdmi; 583 u8 addr = REG2ADDR(reg); 584 int ret; 585 586 mutex_lock(&priv->mutex); 587 ret = set_page(priv, reg); 588 if (ret < 0) 589 goto out; 590 591 ret = i2c_master_send(client, &addr, sizeof(addr)); 592 if (ret < 0) 593 goto fail; 594 595 ret = i2c_master_recv(client, buf, cnt); 596 if (ret < 0) 597 goto fail; 598 599 goto out; 600 601 fail: 602 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); 603 out: 604 mutex_unlock(&priv->mutex); 605 return ret; 606 } 607 608 #define MAX_WRITE_RANGE_BUF 32 609 610 static void 611 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt) 612 { 613 struct i2c_client *client = priv->hdmi; 614 /* This is the maximum size of the buffer passed in */ 615 u8 buf[MAX_WRITE_RANGE_BUF + 1]; 616 int ret; 617 618 if (cnt > MAX_WRITE_RANGE_BUF) { 619 dev_err(&client->dev, "Fixed write buffer too small (%d)\n", 620 MAX_WRITE_RANGE_BUF); 621 return; 622 } 623 624 buf[0] = REG2ADDR(reg); 625 memcpy(&buf[1], p, cnt); 626 627 mutex_lock(&priv->mutex); 628 ret = set_page(priv, reg); 629 if (ret < 0) 630 goto out; 631 632 ret = i2c_master_send(client, buf, cnt + 1); 633 if (ret < 0) 634 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 635 out: 636 mutex_unlock(&priv->mutex); 637 } 638 639 static int 640 reg_read(struct tda998x_priv *priv, u16 reg) 641 { 642 u8 val = 0; 643 int ret; 644 645 ret = reg_read_range(priv, reg, &val, sizeof(val)); 646 if (ret < 0) 647 return ret; 648 return val; 649 } 650 651 static void 652 reg_write(struct tda998x_priv *priv, u16 reg, u8 val) 653 { 654 struct i2c_client *client = priv->hdmi; 655 u8 buf[] = {REG2ADDR(reg), val}; 656 int ret; 657 658 mutex_lock(&priv->mutex); 659 ret = set_page(priv, reg); 660 if (ret < 0) 661 goto out; 662 663 ret = i2c_master_send(client, buf, sizeof(buf)); 664 if (ret < 0) 665 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 666 out: 667 mutex_unlock(&priv->mutex); 668 } 669 670 static void 671 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val) 672 { 673 struct i2c_client *client = priv->hdmi; 674 u8 buf[] = {REG2ADDR(reg), val >> 8, val}; 675 int ret; 676 677 mutex_lock(&priv->mutex); 678 ret = set_page(priv, reg); 679 if (ret < 0) 680 goto out; 681 682 ret = i2c_master_send(client, buf, sizeof(buf)); 683 if (ret < 0) 684 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 685 out: 686 mutex_unlock(&priv->mutex); 687 } 688 689 static void 690 reg_set(struct tda998x_priv *priv, u16 reg, u8 val) 691 { 692 int old_val; 693 694 old_val = reg_read(priv, reg); 695 if (old_val >= 0) 696 reg_write(priv, reg, old_val | val); 697 } 698 699 static void 700 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val) 701 { 702 int old_val; 703 704 old_val = reg_read(priv, reg); 705 if (old_val >= 0) 706 reg_write(priv, reg, old_val & ~val); 707 } 708 709 static void 710 tda998x_reset(struct tda998x_priv *priv) 711 { 712 /* reset audio and i2c master: */ 713 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 714 msleep(50); 715 reg_write(priv, REG_SOFTRESET, 0); 716 msleep(50); 717 718 /* reset transmitter: */ 719 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 720 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 721 722 /* PLL registers common configuration */ 723 reg_write(priv, REG_PLL_SERIAL_1, 0x00); 724 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 725 reg_write(priv, REG_PLL_SERIAL_3, 0x00); 726 reg_write(priv, REG_SERIALIZER, 0x00); 727 reg_write(priv, REG_BUFFER_OUT, 0x00); 728 reg_write(priv, REG_PLL_SCG1, 0x00); 729 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); 730 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 731 reg_write(priv, REG_PLL_SCGN1, 0xfa); 732 reg_write(priv, REG_PLL_SCGN2, 0x00); 733 reg_write(priv, REG_PLL_SCGR1, 0x5b); 734 reg_write(priv, REG_PLL_SCGR2, 0x00); 735 reg_write(priv, REG_PLL_SCG2, 0x10); 736 737 /* Write the default value MUX register */ 738 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24); 739 } 740 741 /* 742 * The TDA998x has a problem when trying to read the EDID close to a 743 * HPD assertion: it needs a delay of 100ms to avoid timing out while 744 * trying to read EDID data. 745 * 746 * However, tda998x_connector_get_modes() may be called at any moment 747 * after tda998x_connector_detect() indicates that we are connected, so 748 * we need to delay probing modes in tda998x_connector_get_modes() after 749 * we have seen a HPD inactive->active transition. This code implements 750 * that delay. 751 */ 752 static void tda998x_edid_delay_done(struct timer_list *t) 753 { 754 struct tda998x_priv *priv = from_timer(priv, t, edid_delay_timer); 755 756 priv->edid_delay_active = false; 757 wake_up(&priv->edid_delay_waitq); 758 schedule_work(&priv->detect_work); 759 } 760 761 static void tda998x_edid_delay_start(struct tda998x_priv *priv) 762 { 763 priv->edid_delay_active = true; 764 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10); 765 } 766 767 static int tda998x_edid_delay_wait(struct tda998x_priv *priv) 768 { 769 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active); 770 } 771 772 /* 773 * We need to run the KMS hotplug event helper outside of our threaded 774 * interrupt routine as this can call back into our get_modes method, 775 * which will want to make use of interrupts. 776 */ 777 static void tda998x_detect_work(struct work_struct *work) 778 { 779 struct tda998x_priv *priv = 780 container_of(work, struct tda998x_priv, detect_work); 781 struct drm_device *dev = priv->connector.dev; 782 783 if (dev) 784 drm_kms_helper_hotplug_event(dev); 785 } 786 787 /* 788 * only 2 interrupts may occur: screen plug/unplug and EDID read 789 */ 790 static irqreturn_t tda998x_irq_thread(int irq, void *data) 791 { 792 struct tda998x_priv *priv = data; 793 u8 sta, cec, lvl, flag0, flag1, flag2; 794 bool handled = false; 795 796 sta = cec_read(priv, REG_CEC_INTSTATUS); 797 if (sta & CEC_INTSTATUS_HDMI) { 798 cec = cec_read(priv, REG_CEC_RXSHPDINT); 799 lvl = cec_read(priv, REG_CEC_RXSHPDLEV); 800 flag0 = reg_read(priv, REG_INT_FLAGS_0); 801 flag1 = reg_read(priv, REG_INT_FLAGS_1); 802 flag2 = reg_read(priv, REG_INT_FLAGS_2); 803 DRM_DEBUG_DRIVER( 804 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n", 805 sta, cec, lvl, flag0, flag1, flag2); 806 807 if (cec & CEC_RXSHPDINT_HPD) { 808 if (lvl & CEC_RXSHPDLEV_HPD) { 809 tda998x_edid_delay_start(priv); 810 } else { 811 schedule_work(&priv->detect_work); 812 cec_notifier_phys_addr_invalidate( 813 priv->cec_notify); 814 } 815 816 handled = true; 817 } 818 819 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) { 820 priv->wq_edid_wait = 0; 821 wake_up(&priv->wq_edid); 822 handled = true; 823 } 824 } 825 826 return IRQ_RETVAL(handled); 827 } 828 829 static void 830 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr, 831 union hdmi_infoframe *frame) 832 { 833 u8 buf[MAX_WRITE_RANGE_BUF]; 834 ssize_t len; 835 836 len = hdmi_infoframe_pack(frame, buf, sizeof(buf)); 837 if (len < 0) { 838 dev_err(&priv->hdmi->dev, 839 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n", 840 frame->any.type, len); 841 return; 842 } 843 844 reg_clear(priv, REG_DIP_IF_FLAGS, bit); 845 reg_write_range(priv, addr, buf, len); 846 reg_set(priv, REG_DIP_IF_FLAGS, bit); 847 } 848 849 static void tda998x_write_aif(struct tda998x_priv *priv, 850 const struct hdmi_audio_infoframe *cea) 851 { 852 union hdmi_infoframe frame; 853 854 frame.audio = *cea; 855 856 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame); 857 } 858 859 static void 860 tda998x_write_avi(struct tda998x_priv *priv, const struct drm_display_mode *mode) 861 { 862 union hdmi_infoframe frame; 863 864 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 865 &priv->connector, mode); 866 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL; 867 drm_hdmi_avi_infoframe_quant_range(&frame.avi, &priv->connector, mode, 868 priv->rgb_quant_range); 869 870 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame); 871 } 872 873 static void tda998x_write_vsi(struct tda998x_priv *priv, 874 const struct drm_display_mode *mode) 875 { 876 union hdmi_infoframe frame; 877 878 if (drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, 879 &priv->connector, 880 mode)) 881 reg_clear(priv, REG_DIP_IF_FLAGS, DIP_IF_FLAGS_IF1); 882 else 883 tda998x_write_if(priv, DIP_IF_FLAGS_IF1, REG_IF1_HB0, &frame); 884 } 885 886 /* Audio support */ 887 888 static const struct tda998x_audio_route tda998x_audio_route[AUDIO_ROUTE_NUM] = { 889 [AUDIO_ROUTE_I2S] = { 890 .ena_aclk = 1, 891 .mux_ap = MUX_AP_SELECT_I2S, 892 .aip_clksel = AIP_CLKSEL_AIP_I2S | AIP_CLKSEL_FS_ACLK, 893 }, 894 [AUDIO_ROUTE_SPDIF] = { 895 .ena_aclk = 0, 896 .mux_ap = MUX_AP_SELECT_SPDIF, 897 .aip_clksel = AIP_CLKSEL_AIP_SPDIF | AIP_CLKSEL_FS_FS64SPDIF, 898 }, 899 }; 900 901 /* Configure the TDA998x audio data and clock routing. */ 902 static int tda998x_derive_routing(struct tda998x_priv *priv, 903 struct tda998x_audio_settings *s, 904 unsigned int route) 905 { 906 s->route = &tda998x_audio_route[route]; 907 s->ena_ap = priv->audio_port_enable[route]; 908 if (s->ena_ap == 0) { 909 dev_err(&priv->hdmi->dev, "no audio configuration found\n"); 910 return -EINVAL; 911 } 912 913 return 0; 914 } 915 916 /* 917 * The audio clock divisor register controls a divider producing Audio_Clk_Out 918 * from SERclk by dividing it by 2^n where 0 <= n <= 5. We don't know what 919 * Audio_Clk_Out or SERclk are. We guess SERclk is the same as TMDS clock. 920 * 921 * It seems that Audio_Clk_Out must be the smallest value that is greater 922 * than 128*fs, otherwise audio does not function. There is some suggestion 923 * that 126*fs is a better value. 924 */ 925 static u8 tda998x_get_adiv(struct tda998x_priv *priv, unsigned int fs) 926 { 927 unsigned long min_audio_clk = fs * 128; 928 unsigned long ser_clk = priv->tmds_clock * 1000; 929 u8 adiv; 930 931 for (adiv = AUDIO_DIV_SERCLK_32; adiv != AUDIO_DIV_SERCLK_1; adiv--) 932 if (ser_clk > min_audio_clk << adiv) 933 break; 934 935 dev_dbg(&priv->hdmi->dev, 936 "ser_clk=%luHz fs=%uHz min_aclk=%luHz adiv=%d\n", 937 ser_clk, fs, min_audio_clk, adiv); 938 939 return adiv; 940 } 941 942 /* 943 * In auto-CTS mode, the TDA998x uses a "measured time stamp" counter to 944 * generate the CTS value. It appears that the "measured time stamp" is 945 * the number of TDMS clock cycles within a number of audio input clock 946 * cycles defined by the k and N parameters defined below, in a similar 947 * way to that which is set out in the CTS generation in the HDMI spec. 948 * 949 * tmdsclk ----> mts -> /m ---> CTS 950 * ^ 951 * sclk -> /k -> /N 952 * 953 * CTS = mts / m, where m is 2^M. 954 * /k is a divider based on the K value below, K+1 for K < 4, or 8 for K >= 4 955 * /N is a divider based on the HDMI specified N value. 956 * 957 * This produces the following equation: 958 * CTS = tmds_clock * k * N / (sclk * m) 959 * 960 * When combined with the sink-side equation, and realising that sclk is 961 * bclk_ratio * fs, we end up with: 962 * k = m * bclk_ratio / 128. 963 * 964 * Note: S/PDIF always uses a bclk_ratio of 64. 965 */ 966 static int tda998x_derive_cts_n(struct tda998x_priv *priv, 967 struct tda998x_audio_settings *settings, 968 unsigned int ratio) 969 { 970 switch (ratio) { 971 case 16: 972 settings->cts_n = CTS_N_M(3) | CTS_N_K(0); 973 break; 974 case 32: 975 settings->cts_n = CTS_N_M(3) | CTS_N_K(1); 976 break; 977 case 48: 978 settings->cts_n = CTS_N_M(3) | CTS_N_K(2); 979 break; 980 case 64: 981 settings->cts_n = CTS_N_M(3) | CTS_N_K(3); 982 break; 983 case 128: 984 settings->cts_n = CTS_N_M(0) | CTS_N_K(0); 985 break; 986 default: 987 dev_err(&priv->hdmi->dev, "unsupported bclk ratio %ufs\n", 988 ratio); 989 return -EINVAL; 990 } 991 return 0; 992 } 993 994 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on) 995 { 996 if (on) { 997 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO); 998 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO); 999 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 1000 } else { 1001 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 1002 } 1003 } 1004 1005 static void tda998x_configure_audio(struct tda998x_priv *priv) 1006 { 1007 const struct tda998x_audio_settings *settings = &priv->audio; 1008 u8 buf[6], adiv; 1009 u32 n; 1010 1011 /* If audio is not configured, there is nothing to do. */ 1012 if (settings->ena_ap == 0) 1013 return; 1014 1015 adiv = tda998x_get_adiv(priv, settings->sample_rate); 1016 1017 /* Enable audio ports */ 1018 reg_write(priv, REG_ENA_AP, settings->ena_ap); 1019 reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk); 1020 reg_write(priv, REG_MUX_AP, settings->route->mux_ap); 1021 reg_write(priv, REG_I2S_FORMAT, settings->i2s_format); 1022 reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel); 1023 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT | 1024 AIP_CNTRL_0_ACR_MAN); /* auto CTS */ 1025 reg_write(priv, REG_CTS_N, settings->cts_n); 1026 reg_write(priv, REG_AUDIO_DIV, adiv); 1027 1028 /* 1029 * This is the approximate value of N, which happens to be 1030 * the recommended values for non-coherent clocks. 1031 */ 1032 n = 128 * settings->sample_rate / 1000; 1033 1034 /* Write the CTS and N values */ 1035 buf[0] = 0x44; 1036 buf[1] = 0x42; 1037 buf[2] = 0x01; 1038 buf[3] = n; 1039 buf[4] = n >> 8; 1040 buf[5] = n >> 16; 1041 reg_write_range(priv, REG_ACR_CTS_0, buf, 6); 1042 1043 /* Reset CTS generator */ 1044 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 1045 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 1046 1047 /* Write the channel status 1048 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because 1049 * there is a separate register for each I2S wire. 1050 */ 1051 buf[0] = settings->status[0]; 1052 buf[1] = settings->status[1]; 1053 buf[2] = settings->status[3]; 1054 buf[3] = settings->status[4]; 1055 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4); 1056 1057 tda998x_audio_mute(priv, true); 1058 msleep(20); 1059 tda998x_audio_mute(priv, false); 1060 1061 tda998x_write_aif(priv, &settings->cea); 1062 } 1063 1064 static int tda998x_audio_hw_params(struct device *dev, void *data, 1065 struct hdmi_codec_daifmt *daifmt, 1066 struct hdmi_codec_params *params) 1067 { 1068 struct tda998x_priv *priv = dev_get_drvdata(dev); 1069 unsigned int bclk_ratio; 1070 bool spdif = daifmt->fmt == HDMI_SPDIF; 1071 int ret; 1072 struct tda998x_audio_settings audio = { 1073 .sample_rate = params->sample_rate, 1074 .cea = params->cea, 1075 }; 1076 1077 memcpy(audio.status, params->iec.status, 1078 min(sizeof(audio.status), sizeof(params->iec.status))); 1079 1080 switch (daifmt->fmt) { 1081 case HDMI_I2S: 1082 audio.i2s_format = I2S_FORMAT_PHILIPS; 1083 break; 1084 case HDMI_LEFT_J: 1085 audio.i2s_format = I2S_FORMAT_LEFT_J; 1086 break; 1087 case HDMI_RIGHT_J: 1088 audio.i2s_format = I2S_FORMAT_RIGHT_J; 1089 break; 1090 case HDMI_SPDIF: 1091 audio.i2s_format = 0; 1092 break; 1093 default: 1094 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt); 1095 return -EINVAL; 1096 } 1097 1098 if (!spdif && 1099 (daifmt->bit_clk_inv || daifmt->frame_clk_inv || 1100 daifmt->bit_clk_provider || daifmt->frame_clk_provider)) { 1101 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, 1102 daifmt->bit_clk_inv, daifmt->frame_clk_inv, 1103 daifmt->bit_clk_provider, 1104 daifmt->frame_clk_provider); 1105 return -EINVAL; 1106 } 1107 1108 ret = tda998x_derive_routing(priv, &audio, AUDIO_ROUTE_I2S + spdif); 1109 if (ret < 0) 1110 return ret; 1111 1112 bclk_ratio = spdif ? 64 : params->sample_width * 2; 1113 ret = tda998x_derive_cts_n(priv, &audio, bclk_ratio); 1114 if (ret < 0) 1115 return ret; 1116 1117 mutex_lock(&priv->audio_mutex); 1118 priv->audio = audio; 1119 if (priv->supports_infoframes && priv->sink_has_audio) 1120 tda998x_configure_audio(priv); 1121 mutex_unlock(&priv->audio_mutex); 1122 1123 return 0; 1124 } 1125 1126 static void tda998x_audio_shutdown(struct device *dev, void *data) 1127 { 1128 struct tda998x_priv *priv = dev_get_drvdata(dev); 1129 1130 mutex_lock(&priv->audio_mutex); 1131 1132 reg_write(priv, REG_ENA_AP, 0); 1133 priv->audio.ena_ap = 0; 1134 1135 mutex_unlock(&priv->audio_mutex); 1136 } 1137 1138 static int tda998x_audio_mute_stream(struct device *dev, void *data, 1139 bool enable, int direction) 1140 { 1141 struct tda998x_priv *priv = dev_get_drvdata(dev); 1142 1143 mutex_lock(&priv->audio_mutex); 1144 1145 tda998x_audio_mute(priv, enable); 1146 1147 mutex_unlock(&priv->audio_mutex); 1148 return 0; 1149 } 1150 1151 static int tda998x_audio_get_eld(struct device *dev, void *data, 1152 uint8_t *buf, size_t len) 1153 { 1154 struct tda998x_priv *priv = dev_get_drvdata(dev); 1155 1156 mutex_lock(&priv->audio_mutex); 1157 memcpy(buf, priv->connector.eld, 1158 min(sizeof(priv->connector.eld), len)); 1159 mutex_unlock(&priv->audio_mutex); 1160 1161 return 0; 1162 } 1163 1164 static const struct hdmi_codec_ops audio_codec_ops = { 1165 .hw_params = tda998x_audio_hw_params, 1166 .audio_shutdown = tda998x_audio_shutdown, 1167 .mute_stream = tda998x_audio_mute_stream, 1168 .get_eld = tda998x_audio_get_eld, 1169 }; 1170 1171 static int tda998x_audio_codec_init(struct tda998x_priv *priv, 1172 struct device *dev) 1173 { 1174 struct hdmi_codec_pdata codec_data = { 1175 .ops = &audio_codec_ops, 1176 .max_i2s_channels = 2, 1177 .no_i2s_capture = 1, 1178 .no_spdif_capture = 1, 1179 .no_capture_mute = 1, 1180 }; 1181 1182 if (priv->audio_port_enable[AUDIO_ROUTE_I2S]) 1183 codec_data.i2s = 1; 1184 if (priv->audio_port_enable[AUDIO_ROUTE_SPDIF]) 1185 codec_data.spdif = 1; 1186 1187 priv->audio_pdev = platform_device_register_data( 1188 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, 1189 &codec_data, sizeof(codec_data)); 1190 1191 return PTR_ERR_OR_ZERO(priv->audio_pdev); 1192 } 1193 1194 /* DRM connector functions */ 1195 1196 static enum drm_connector_status 1197 tda998x_connector_detect(struct drm_connector *connector, bool force) 1198 { 1199 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1200 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV); 1201 1202 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : 1203 connector_status_disconnected; 1204 } 1205 1206 static void tda998x_connector_destroy(struct drm_connector *connector) 1207 { 1208 drm_connector_cleanup(connector); 1209 } 1210 1211 static const struct drm_connector_funcs tda998x_connector_funcs = { 1212 .reset = drm_atomic_helper_connector_reset, 1213 .fill_modes = drm_helper_probe_single_connector_modes, 1214 .detect = tda998x_connector_detect, 1215 .destroy = tda998x_connector_destroy, 1216 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1217 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1218 }; 1219 1220 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length) 1221 { 1222 struct tda998x_priv *priv = data; 1223 u8 offset, segptr; 1224 int ret, i; 1225 1226 offset = (blk & 1) ? 128 : 0; 1227 segptr = blk / 2; 1228 1229 mutex_lock(&priv->edid_mutex); 1230 1231 reg_write(priv, REG_DDC_ADDR, 0xa0); 1232 reg_write(priv, REG_DDC_OFFS, offset); 1233 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60); 1234 reg_write(priv, REG_DDC_SEGM, segptr); 1235 1236 /* enable reading EDID: */ 1237 priv->wq_edid_wait = 1; 1238 reg_write(priv, REG_EDID_CTRL, 0x1); 1239 1240 /* flag must be cleared by sw: */ 1241 reg_write(priv, REG_EDID_CTRL, 0x0); 1242 1243 /* wait for block read to complete: */ 1244 if (priv->hdmi->irq) { 1245 i = wait_event_timeout(priv->wq_edid, 1246 !priv->wq_edid_wait, 1247 msecs_to_jiffies(100)); 1248 if (i < 0) { 1249 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i); 1250 ret = i; 1251 goto failed; 1252 } 1253 } else { 1254 for (i = 100; i > 0; i--) { 1255 msleep(1); 1256 ret = reg_read(priv, REG_INT_FLAGS_2); 1257 if (ret < 0) 1258 goto failed; 1259 if (ret & INT_FLAGS_2_EDID_BLK_RD) 1260 break; 1261 } 1262 } 1263 1264 if (i == 0) { 1265 dev_err(&priv->hdmi->dev, "read edid timeout\n"); 1266 ret = -ETIMEDOUT; 1267 goto failed; 1268 } 1269 1270 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length); 1271 if (ret != length) { 1272 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n", 1273 blk, ret); 1274 goto failed; 1275 } 1276 1277 ret = 0; 1278 1279 failed: 1280 mutex_unlock(&priv->edid_mutex); 1281 return ret; 1282 } 1283 1284 static int tda998x_connector_get_modes(struct drm_connector *connector) 1285 { 1286 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1287 const struct drm_edid *drm_edid; 1288 int n; 1289 1290 /* 1291 * If we get killed while waiting for the HPD timeout, return 1292 * no modes found: we are not in a restartable path, so we 1293 * can't handle signals gracefully. 1294 */ 1295 if (tda998x_edid_delay_wait(priv)) 1296 return 0; 1297 1298 if (priv->rev == TDA19988) 1299 reg_clear(priv, REG_TX4, TX4_PD_RAM); 1300 1301 drm_edid = drm_edid_read_custom(connector, read_edid_block, priv); 1302 1303 if (priv->rev == TDA19988) 1304 reg_set(priv, REG_TX4, TX4_PD_RAM); 1305 1306 drm_edid_connector_update(connector, drm_edid); 1307 cec_notifier_set_phys_addr(priv->cec_notify, 1308 connector->display_info.source_physical_address); 1309 1310 if (!drm_edid) { 1311 dev_warn(&priv->hdmi->dev, "failed to read EDID\n"); 1312 return 0; 1313 } 1314 1315 mutex_lock(&priv->audio_mutex); 1316 n = drm_edid_connector_add_modes(connector); 1317 priv->sink_has_audio = connector->display_info.has_audio; 1318 mutex_unlock(&priv->audio_mutex); 1319 1320 drm_edid_free(drm_edid); 1321 1322 return n; 1323 } 1324 1325 static struct drm_encoder * 1326 tda998x_connector_best_encoder(struct drm_connector *connector) 1327 { 1328 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1329 1330 return priv->bridge.encoder; 1331 } 1332 1333 static 1334 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = { 1335 .get_modes = tda998x_connector_get_modes, 1336 .best_encoder = tda998x_connector_best_encoder, 1337 }; 1338 1339 static int tda998x_connector_init(struct tda998x_priv *priv, 1340 struct drm_device *drm) 1341 { 1342 struct drm_connector *connector = &priv->connector; 1343 int ret; 1344 1345 connector->interlace_allowed = 1; 1346 1347 if (priv->hdmi->irq) 1348 connector->polled = DRM_CONNECTOR_POLL_HPD; 1349 else 1350 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1351 DRM_CONNECTOR_POLL_DISCONNECT; 1352 1353 drm_connector_helper_add(connector, &tda998x_connector_helper_funcs); 1354 ret = drm_connector_init(drm, connector, &tda998x_connector_funcs, 1355 DRM_MODE_CONNECTOR_HDMIA); 1356 if (ret) 1357 return ret; 1358 1359 drm_connector_attach_encoder(&priv->connector, 1360 priv->bridge.encoder); 1361 1362 return 0; 1363 } 1364 1365 /* DRM bridge functions */ 1366 1367 static int tda998x_bridge_attach(struct drm_bridge *bridge, 1368 struct drm_encoder *encoder, 1369 enum drm_bridge_attach_flags flags) 1370 { 1371 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1372 1373 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) { 1374 DRM_ERROR("Fix bridge driver to make connector optional!"); 1375 return -EINVAL; 1376 } 1377 1378 return tda998x_connector_init(priv, bridge->dev); 1379 } 1380 1381 static void tda998x_bridge_detach(struct drm_bridge *bridge) 1382 { 1383 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1384 1385 drm_connector_cleanup(&priv->connector); 1386 } 1387 1388 static enum drm_mode_status tda998x_bridge_mode_valid(struct drm_bridge *bridge, 1389 const struct drm_display_info *info, 1390 const struct drm_display_mode *mode) 1391 { 1392 /* TDA19988 dotclock can go up to 165MHz */ 1393 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1394 1395 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000)) 1396 return MODE_CLOCK_HIGH; 1397 if (mode->htotal >= BIT(13)) 1398 return MODE_BAD_HVALUE; 1399 if (mode->vtotal >= BIT(11)) 1400 return MODE_BAD_VVALUE; 1401 return MODE_OK; 1402 } 1403 1404 static void tda998x_bridge_enable(struct drm_bridge *bridge) 1405 { 1406 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1407 1408 if (!priv->is_on) { 1409 /* enable video ports, audio will be enabled later */ 1410 reg_write(priv, REG_ENA_VP_0, 0xff); 1411 reg_write(priv, REG_ENA_VP_1, 0xff); 1412 reg_write(priv, REG_ENA_VP_2, 0xff); 1413 /* set muxing after enabling ports: */ 1414 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0); 1415 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1); 1416 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2); 1417 1418 priv->is_on = true; 1419 } 1420 } 1421 1422 static void tda998x_bridge_disable(struct drm_bridge *bridge) 1423 { 1424 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1425 1426 if (priv->is_on) { 1427 /* disable video ports */ 1428 reg_write(priv, REG_ENA_VP_0, 0x00); 1429 reg_write(priv, REG_ENA_VP_1, 0x00); 1430 reg_write(priv, REG_ENA_VP_2, 0x00); 1431 1432 priv->is_on = false; 1433 } 1434 } 1435 1436 static void tda998x_bridge_mode_set(struct drm_bridge *bridge, 1437 const struct drm_display_mode *mode, 1438 const struct drm_display_mode *adjusted_mode) 1439 { 1440 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1441 unsigned long tmds_clock; 1442 u16 ref_pix, ref_line, n_pix, n_line; 1443 u16 hs_pix_s, hs_pix_e; 1444 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; 1445 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; 1446 u16 vwin1_line_s, vwin1_line_e; 1447 u16 vwin2_line_s, vwin2_line_e; 1448 u16 de_pix_s, de_pix_e; 1449 u8 reg, div, rep, sel_clk; 1450 1451 /* 1452 * Since we are "computer" like, our source invariably produces 1453 * full-range RGB. If the monitor supports full-range, then use 1454 * it, otherwise reduce to limited-range. 1455 */ 1456 priv->rgb_quant_range = 1457 priv->connector.display_info.rgb_quant_range_selectable ? 1458 HDMI_QUANTIZATION_RANGE_FULL : 1459 drm_default_rgb_quant_range(adjusted_mode); 1460 1461 /* 1462 * Internally TDA998x is using ITU-R BT.656 style sync but 1463 * we get VESA style sync. TDA998x is using a reference pixel 1464 * relative to ITU to sync to the input frame and for output 1465 * sync generation. Currently, we are using reference detection 1466 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point 1467 * which is position of rising VS with coincident rising HS. 1468 * 1469 * Now there is some issues to take care of: 1470 * - HDMI data islands require sync-before-active 1471 * - TDA998x register values must be > 0 to be enabled 1472 * - REFLINE needs an additional offset of +1 1473 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB 1474 * 1475 * So we add +1 to all horizontal and vertical register values, 1476 * plus an additional +3 for REFPIX as we are using RGB input only. 1477 */ 1478 n_pix = mode->htotal; 1479 n_line = mode->vtotal; 1480 1481 hs_pix_e = mode->hsync_end - mode->hdisplay; 1482 hs_pix_s = mode->hsync_start - mode->hdisplay; 1483 de_pix_e = mode->htotal; 1484 de_pix_s = mode->htotal - mode->hdisplay; 1485 ref_pix = 3 + hs_pix_s; 1486 1487 /* 1488 * Attached LCD controllers may generate broken sync. Allow 1489 * those to adjust the position of the rising VS edge by adding 1490 * HSKEW to ref_pix. 1491 */ 1492 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) 1493 ref_pix += adjusted_mode->hskew; 1494 1495 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { 1496 ref_line = 1 + mode->vsync_start - mode->vdisplay; 1497 vwin1_line_s = mode->vtotal - mode->vdisplay - 1; 1498 vwin1_line_e = vwin1_line_s + mode->vdisplay; 1499 vs1_pix_s = vs1_pix_e = hs_pix_s; 1500 vs1_line_s = mode->vsync_start - mode->vdisplay; 1501 vs1_line_e = vs1_line_s + 1502 mode->vsync_end - mode->vsync_start; 1503 vwin2_line_s = vwin2_line_e = 0; 1504 vs2_pix_s = vs2_pix_e = 0; 1505 vs2_line_s = vs2_line_e = 0; 1506 } else { 1507 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; 1508 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; 1509 vwin1_line_e = vwin1_line_s + mode->vdisplay/2; 1510 vs1_pix_s = vs1_pix_e = hs_pix_s; 1511 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; 1512 vs1_line_e = vs1_line_s + 1513 (mode->vsync_end - mode->vsync_start)/2; 1514 vwin2_line_s = vwin1_line_s + mode->vtotal/2; 1515 vwin2_line_e = vwin2_line_s + mode->vdisplay/2; 1516 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; 1517 vs2_line_s = vs1_line_s + mode->vtotal/2 ; 1518 vs2_line_e = vs2_line_s + 1519 (mode->vsync_end - mode->vsync_start)/2; 1520 } 1521 1522 /* 1523 * Select pixel repeat depending on the double-clock flag 1524 * (which means we have to repeat each pixel once.) 1525 */ 1526 rep = mode->flags & DRM_MODE_FLAG_DBLCLK ? 1 : 0; 1527 sel_clk = SEL_CLK_ENA_SC_CLK | SEL_CLK_SEL_CLK1 | 1528 SEL_CLK_SEL_VRF_CLK(rep ? 2 : 0); 1529 1530 /* the TMDS clock is scaled up by the pixel repeat */ 1531 tmds_clock = mode->clock * (1 + rep); 1532 1533 /* 1534 * The divisor is power-of-2. The TDA9983B datasheet gives 1535 * this as ranges of Msample/s, which is 10x the TMDS clock: 1536 * 0 - 800 to 1500 Msample/s 1537 * 1 - 400 to 800 Msample/s 1538 * 2 - 200 to 400 Msample/s 1539 * 3 - as 2 above 1540 */ 1541 for (div = 0; div < 3; div++) 1542 if (80000 >> div <= tmds_clock) 1543 break; 1544 1545 mutex_lock(&priv->audio_mutex); 1546 1547 priv->tmds_clock = tmds_clock; 1548 1549 /* mute the audio FIFO: */ 1550 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 1551 1552 /* set HDMI HDCP mode off: */ 1553 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 1554 reg_clear(priv, REG_TX33, TX33_HDMI); 1555 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); 1556 1557 /* no pre-filter or interpolator: */ 1558 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | 1559 HVF_CNTRL_0_INTPOL(0)); 1560 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT); 1561 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 1562 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | 1563 VIP_CNTRL_4_BLC(0)); 1564 1565 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); 1566 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR | 1567 PLL_SERIAL_3_SRL_DE); 1568 reg_write(priv, REG_SERIALIZER, 0); 1569 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); 1570 1571 reg_write(priv, REG_RPT_CNTRL, RPT_CNTRL_REPEAT(rep)); 1572 reg_write(priv, REG_SEL_CLK, sel_clk); 1573 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | 1574 PLL_SERIAL_2_SRL_PR(rep)); 1575 1576 /* set color matrix according to output rgb quant range */ 1577 if (priv->rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) { 1578 static u8 tda998x_full_to_limited_range[] = { 1579 MAT_CONTRL_MAT_SC(2), 1580 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1581 0x03, 0x6f, 0x00, 0x00, 0x00, 0x00, 1582 0x00, 0x00, 0x03, 0x6f, 0x00, 0x00, 1583 0x00, 0x00, 0x00, 0x00, 0x03, 0x6f, 1584 0x00, 0x40, 0x00, 0x40, 0x00, 0x40 1585 }; 1586 reg_clear(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC); 1587 reg_write_range(priv, REG_MAT_CONTRL, 1588 tda998x_full_to_limited_range, 1589 sizeof(tda998x_full_to_limited_range)); 1590 } else { 1591 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP | 1592 MAT_CONTRL_MAT_SC(1)); 1593 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC); 1594 } 1595 1596 /* set BIAS tmds value: */ 1597 reg_write(priv, REG_ANA_GENERAL, 0x09); 1598 1599 /* 1600 * Sync on rising HSYNC/VSYNC 1601 */ 1602 reg = VIP_CNTRL_3_SYNC_HS; 1603 1604 /* 1605 * TDA19988 requires high-active sync at input stage, 1606 * so invert low-active sync provided by master encoder here 1607 */ 1608 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1609 reg |= VIP_CNTRL_3_H_TGL; 1610 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1611 reg |= VIP_CNTRL_3_V_TGL; 1612 reg_write(priv, REG_VIP_CNTRL_3, reg); 1613 1614 reg_write(priv, REG_VIDFORMAT, 0x00); 1615 reg_write16(priv, REG_REFPIX_MSB, ref_pix); 1616 reg_write16(priv, REG_REFLINE_MSB, ref_line); 1617 reg_write16(priv, REG_NPIX_MSB, n_pix); 1618 reg_write16(priv, REG_NLINE_MSB, n_line); 1619 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s); 1620 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s); 1621 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e); 1622 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e); 1623 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s); 1624 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s); 1625 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e); 1626 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e); 1627 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s); 1628 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e); 1629 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s); 1630 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e); 1631 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s); 1632 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e); 1633 reg_write16(priv, REG_DE_START_MSB, de_pix_s); 1634 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e); 1635 1636 if (priv->rev == TDA19988) { 1637 /* let incoming pixels fill the active space (if any) */ 1638 reg_write(priv, REG_ENABLE_SPACE, 0x00); 1639 } 1640 1641 /* 1642 * Always generate sync polarity relative to input sync and 1643 * revert input stage toggled sync at output stage 1644 */ 1645 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN; 1646 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1647 reg |= TBG_CNTRL_1_H_TGL; 1648 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1649 reg |= TBG_CNTRL_1_V_TGL; 1650 reg_write(priv, REG_TBG_CNTRL_1, reg); 1651 1652 /* must be last register set: */ 1653 reg_write(priv, REG_TBG_CNTRL_0, 0); 1654 1655 /* CEA-861B section 6 says that: 1656 * CEA version 1 (CEA-861) has no support for infoframes. 1657 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes, 1658 * and optional basic audio. 1659 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes, 1660 * and optional digital audio, with audio infoframes. 1661 * 1662 * Since we only support generation of version 2 AVI infoframes, 1663 * ignore CEA version 2 and below (iow, behave as if we're a 1664 * CEA-861 source.) 1665 */ 1666 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3; 1667 1668 if (priv->supports_infoframes) { 1669 /* We need to turn HDMI HDCP stuff on to get audio through */ 1670 reg &= ~TBG_CNTRL_1_DWIN_DIS; 1671 reg_write(priv, REG_TBG_CNTRL_1, reg); 1672 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); 1673 reg_set(priv, REG_TX33, TX33_HDMI); 1674 1675 tda998x_write_avi(priv, adjusted_mode); 1676 tda998x_write_vsi(priv, adjusted_mode); 1677 1678 if (priv->sink_has_audio) 1679 tda998x_configure_audio(priv); 1680 } 1681 1682 mutex_unlock(&priv->audio_mutex); 1683 } 1684 1685 static const struct drm_bridge_funcs tda998x_bridge_funcs = { 1686 .attach = tda998x_bridge_attach, 1687 .detach = tda998x_bridge_detach, 1688 .mode_valid = tda998x_bridge_mode_valid, 1689 .disable = tda998x_bridge_disable, 1690 .mode_set = tda998x_bridge_mode_set, 1691 .enable = tda998x_bridge_enable, 1692 }; 1693 1694 /* I2C driver functions */ 1695 1696 static int tda998x_get_audio_ports(struct tda998x_priv *priv, 1697 struct device_node *np) 1698 { 1699 const u32 *port_data; 1700 u32 size; 1701 int i; 1702 1703 port_data = of_get_property(np, "audio-ports", &size); 1704 if (!port_data) 1705 return 0; 1706 1707 size /= sizeof(u32); 1708 if (size > 2 * ARRAY_SIZE(priv->audio_port_enable) || size % 2 != 0) { 1709 dev_err(&priv->hdmi->dev, 1710 "Bad number of elements in audio-ports dt-property\n"); 1711 return -EINVAL; 1712 } 1713 1714 size /= 2; 1715 1716 for (i = 0; i < size; i++) { 1717 unsigned int route; 1718 u8 afmt = be32_to_cpup(&port_data[2*i]); 1719 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]); 1720 1721 switch (afmt) { 1722 case TDA998x_I2S: 1723 route = AUDIO_ROUTE_I2S; 1724 break; 1725 case TDA998x_SPDIF: 1726 route = AUDIO_ROUTE_SPDIF; 1727 break; 1728 default: 1729 dev_err(&priv->hdmi->dev, 1730 "Bad audio format %u\n", afmt); 1731 return -EINVAL; 1732 } 1733 1734 if (!ena_ap) { 1735 dev_err(&priv->hdmi->dev, "invalid zero port config\n"); 1736 continue; 1737 } 1738 1739 if (priv->audio_port_enable[route]) { 1740 dev_err(&priv->hdmi->dev, 1741 "%s format already configured\n", 1742 route == AUDIO_ROUTE_SPDIF ? "SPDIF" : "I2S"); 1743 return -EINVAL; 1744 } 1745 1746 priv->audio_port_enable[route] = ena_ap; 1747 } 1748 return 0; 1749 } 1750 1751 static void tda998x_destroy(struct device *dev) 1752 { 1753 struct tda998x_priv *priv = dev_get_drvdata(dev); 1754 1755 drm_bridge_remove(&priv->bridge); 1756 1757 /* disable all IRQs and free the IRQ handler */ 1758 cec_write(priv, REG_CEC_RXSHPDINTENA, 0); 1759 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 1760 1761 if (priv->audio_pdev) 1762 platform_device_unregister(priv->audio_pdev); 1763 1764 if (priv->hdmi->irq) 1765 free_irq(priv->hdmi->irq, priv); 1766 1767 timer_delete_sync(&priv->edid_delay_timer); 1768 cancel_work_sync(&priv->detect_work); 1769 1770 i2c_unregister_device(priv->cec); 1771 1772 cec_notifier_conn_unregister(priv->cec_notify); 1773 } 1774 1775 static int tda998x_create(struct device *dev) 1776 { 1777 struct i2c_client *client = to_i2c_client(dev); 1778 struct device_node *np = client->dev.of_node; 1779 struct i2c_board_info cec_info; 1780 struct tda998x_priv *priv; 1781 u32 video; 1782 int rev_lo, rev_hi, ret; 1783 1784 priv = devm_drm_bridge_alloc(dev, struct tda998x_priv, bridge, &tda998x_bridge_funcs); 1785 if (IS_ERR(priv)) 1786 return PTR_ERR(priv); 1787 1788 dev_set_drvdata(dev, priv); 1789 1790 mutex_init(&priv->mutex); /* protect the page access */ 1791 mutex_init(&priv->audio_mutex); /* protect access from audio thread */ 1792 mutex_init(&priv->edid_mutex); 1793 INIT_LIST_HEAD(&priv->bridge.list); 1794 init_waitqueue_head(&priv->edid_delay_waitq); 1795 timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0); 1796 INIT_WORK(&priv->detect_work, tda998x_detect_work); 1797 1798 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); 1799 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); 1800 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); 1801 1802 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */ 1803 priv->cec_addr = 0x34 + (client->addr & 0x03); 1804 priv->current_page = 0xff; 1805 priv->hdmi = client; 1806 1807 /* wake up the device: */ 1808 cec_write(priv, REG_CEC_ENAMODS, 1809 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); 1810 1811 tda998x_reset(priv); 1812 1813 /* read version: */ 1814 rev_lo = reg_read(priv, REG_VERSION_LSB); 1815 if (rev_lo < 0) { 1816 dev_err(dev, "failed to read version: %d\n", rev_lo); 1817 return rev_lo; 1818 } 1819 1820 rev_hi = reg_read(priv, REG_VERSION_MSB); 1821 if (rev_hi < 0) { 1822 dev_err(dev, "failed to read version: %d\n", rev_hi); 1823 return rev_hi; 1824 } 1825 1826 priv->rev = rev_lo | rev_hi << 8; 1827 1828 /* mask off feature bits: */ 1829 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ 1830 1831 switch (priv->rev) { 1832 case TDA9989N2: 1833 dev_info(dev, "found TDA9989 n2"); 1834 break; 1835 case TDA19989: 1836 dev_info(dev, "found TDA19989"); 1837 break; 1838 case TDA19989N2: 1839 dev_info(dev, "found TDA19989 n2"); 1840 break; 1841 case TDA19988: 1842 dev_info(dev, "found TDA19988"); 1843 break; 1844 default: 1845 dev_err(dev, "found unsupported device: %04x\n", priv->rev); 1846 return -ENXIO; 1847 } 1848 1849 /* after reset, enable DDC: */ 1850 reg_write(priv, REG_DDC_DISABLE, 0x00); 1851 1852 /* set clock on DDC channel: */ 1853 reg_write(priv, REG_TX3, 39); 1854 1855 /* if necessary, disable multi-master: */ 1856 if (priv->rev == TDA19989) 1857 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM); 1858 1859 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL, 1860 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 1861 1862 /* ensure interrupts are disabled */ 1863 cec_write(priv, REG_CEC_RXSHPDINTENA, 0); 1864 1865 /* clear pending interrupts */ 1866 cec_read(priv, REG_CEC_RXSHPDINT); 1867 reg_read(priv, REG_INT_FLAGS_0); 1868 reg_read(priv, REG_INT_FLAGS_1); 1869 reg_read(priv, REG_INT_FLAGS_2); 1870 1871 /* initialize the optional IRQ */ 1872 if (client->irq) { 1873 unsigned long irq_flags; 1874 1875 /* init read EDID waitqueue and HDP work */ 1876 init_waitqueue_head(&priv->wq_edid); 1877 1878 irq_flags = 1879 irqd_get_trigger_type(irq_get_irq_data(client->irq)); 1880 1881 priv->cec_glue.irq_flags = irq_flags; 1882 1883 irq_flags |= IRQF_SHARED | IRQF_ONESHOT; 1884 ret = request_threaded_irq(client->irq, NULL, 1885 tda998x_irq_thread, irq_flags, 1886 "tda998x", priv); 1887 if (ret) { 1888 dev_err(dev, "failed to request IRQ#%u: %d\n", 1889 client->irq, ret); 1890 goto err_irq; 1891 } 1892 1893 /* enable HPD irq */ 1894 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD); 1895 } 1896 1897 priv->cec_notify = cec_notifier_conn_register(dev, NULL, NULL); 1898 if (!priv->cec_notify) { 1899 ret = -ENOMEM; 1900 goto fail; 1901 } 1902 1903 priv->cec_glue.parent = dev; 1904 priv->cec_glue.data = priv; 1905 priv->cec_glue.init = tda998x_cec_hook_init; 1906 priv->cec_glue.exit = tda998x_cec_hook_exit; 1907 priv->cec_glue.open = tda998x_cec_hook_open; 1908 priv->cec_glue.release = tda998x_cec_hook_release; 1909 1910 /* 1911 * Some TDA998x are actually two I2C devices merged onto one piece 1912 * of silicon: TDA9989 and TDA19989 combine the HDMI transmitter 1913 * with a slightly modified TDA9950 CEC device. The CEC device 1914 * is at the TDA9950 address, with the address pins strapped across 1915 * to the TDA998x address pins. Hence, it always has the same 1916 * offset. 1917 */ 1918 memset(&cec_info, 0, sizeof(cec_info)); 1919 strscpy(cec_info.type, "tda9950", sizeof(cec_info.type)); 1920 cec_info.addr = priv->cec_addr; 1921 cec_info.platform_data = &priv->cec_glue; 1922 cec_info.irq = client->irq; 1923 1924 priv->cec = i2c_new_client_device(client->adapter, &cec_info); 1925 if (IS_ERR(priv->cec)) { 1926 ret = PTR_ERR(priv->cec); 1927 goto fail; 1928 } 1929 1930 /* enable EDID read irq: */ 1931 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 1932 1933 if (np) { 1934 /* get the device tree parameters */ 1935 ret = of_property_read_u32(np, "video-ports", &video); 1936 if (ret == 0) { 1937 priv->vip_cntrl_0 = video >> 16; 1938 priv->vip_cntrl_1 = video >> 8; 1939 priv->vip_cntrl_2 = video; 1940 } 1941 1942 ret = tda998x_get_audio_ports(priv, np); 1943 if (ret) 1944 goto fail; 1945 1946 if (priv->audio_port_enable[AUDIO_ROUTE_I2S] || 1947 priv->audio_port_enable[AUDIO_ROUTE_SPDIF]) 1948 tda998x_audio_codec_init(priv, &client->dev); 1949 } 1950 1951 #ifdef CONFIG_OF 1952 priv->bridge.of_node = dev->of_node; 1953 #endif 1954 1955 drm_bridge_add(&priv->bridge); 1956 1957 return 0; 1958 1959 fail: 1960 tda998x_destroy(dev); 1961 err_irq: 1962 return ret; 1963 } 1964 1965 /* DRM encoder functions */ 1966 1967 static int tda998x_encoder_init(struct device *dev, struct drm_device *drm) 1968 { 1969 struct tda998x_priv *priv = dev_get_drvdata(dev); 1970 u32 crtcs = 0; 1971 int ret; 1972 1973 if (dev->of_node) 1974 crtcs = drm_of_find_possible_crtcs(drm, dev->of_node); 1975 1976 /* If no CRTCs were found, fall back to our old behaviour */ 1977 if (crtcs == 0) { 1978 dev_warn(dev, "Falling back to first CRTC\n"); 1979 crtcs = 1 << 0; 1980 } 1981 1982 priv->encoder.possible_crtcs = crtcs; 1983 1984 ret = drm_simple_encoder_init(drm, &priv->encoder, 1985 DRM_MODE_ENCODER_TMDS); 1986 if (ret) 1987 goto err_encoder; 1988 1989 ret = drm_bridge_attach(&priv->encoder, &priv->bridge, NULL, 0); 1990 if (ret) 1991 goto err_bridge; 1992 1993 return 0; 1994 1995 err_bridge: 1996 drm_encoder_cleanup(&priv->encoder); 1997 err_encoder: 1998 return ret; 1999 } 2000 2001 static int tda998x_bind(struct device *dev, struct device *master, void *data) 2002 { 2003 struct drm_device *drm = data; 2004 2005 return tda998x_encoder_init(dev, drm); 2006 } 2007 2008 static void tda998x_unbind(struct device *dev, struct device *master, 2009 void *data) 2010 { 2011 struct tda998x_priv *priv = dev_get_drvdata(dev); 2012 2013 drm_encoder_cleanup(&priv->encoder); 2014 } 2015 2016 static const struct component_ops tda998x_ops = { 2017 .bind = tda998x_bind, 2018 .unbind = tda998x_unbind, 2019 }; 2020 2021 static int 2022 tda998x_probe(struct i2c_client *client) 2023 { 2024 int ret; 2025 2026 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 2027 dev_warn(&client->dev, "adapter does not support I2C\n"); 2028 return -EIO; 2029 } 2030 2031 ret = tda998x_create(&client->dev); 2032 if (ret) 2033 return ret; 2034 2035 ret = component_add(&client->dev, &tda998x_ops); 2036 if (ret) 2037 tda998x_destroy(&client->dev); 2038 return ret; 2039 } 2040 2041 static void tda998x_remove(struct i2c_client *client) 2042 { 2043 component_del(&client->dev, &tda998x_ops); 2044 tda998x_destroy(&client->dev); 2045 } 2046 2047 #ifdef CONFIG_OF 2048 static const struct of_device_id tda998x_dt_ids[] = { 2049 { .compatible = "nxp,tda998x", }, 2050 { } 2051 }; 2052 MODULE_DEVICE_TABLE(of, tda998x_dt_ids); 2053 #endif 2054 2055 static const struct i2c_device_id tda998x_ids[] = { 2056 { "tda998x" }, 2057 { } 2058 }; 2059 MODULE_DEVICE_TABLE(i2c, tda998x_ids); 2060 2061 static struct i2c_driver tda998x_driver = { 2062 .probe = tda998x_probe, 2063 .remove = tda998x_remove, 2064 .driver = { 2065 .name = "tda998x", 2066 .of_match_table = of_match_ptr(tda998x_dt_ids), 2067 }, 2068 .id_table = tda998x_ids, 2069 }; 2070 2071 module_i2c_driver(tda998x_driver); 2072 2073 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 2074 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); 2075 MODULE_LICENSE("GPL"); 2076