1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Texas Instruments 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include <linux/gpio/consumer.h> 8 #include <linux/hdmi.h> 9 #include <linux/i2c.h> 10 #include <linux/module.h> 11 #include <linux/platform_data/tda9950.h> 12 #include <linux/irq.h> 13 #include <sound/asoundef.h> 14 #include <sound/hdmi-codec.h> 15 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_bridge.h> 18 #include <drm/drm_edid.h> 19 #include <drm/drm_of.h> 20 #include <drm/drm_print.h> 21 #include <drm/drm_probe_helper.h> 22 #include <drm/drm_simple_kms_helper.h> 23 24 #include <media/cec-notifier.h> 25 26 #include <dt-bindings/display/tda998x.h> 27 28 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__) 29 30 enum { 31 AUDIO_ROUTE_I2S, 32 AUDIO_ROUTE_SPDIF, 33 AUDIO_ROUTE_NUM 34 }; 35 36 struct tda998x_audio_route { 37 u8 ena_aclk; 38 u8 mux_ap; 39 u8 aip_clksel; 40 }; 41 42 struct tda998x_audio_settings { 43 const struct tda998x_audio_route *route; 44 struct hdmi_audio_infoframe cea; 45 unsigned int sample_rate; 46 u8 status[5]; 47 u8 ena_ap; 48 u8 i2s_format; 49 u8 cts_n; 50 }; 51 52 struct tda998x_priv { 53 struct i2c_client *cec; 54 struct i2c_client *hdmi; 55 struct mutex mutex; 56 u16 rev; 57 u8 cec_addr; 58 u8 current_page; 59 bool is_on; 60 bool supports_infoframes; 61 bool sink_has_audio; 62 enum hdmi_quantization_range rgb_quant_range; 63 u8 vip_cntrl_0; 64 u8 vip_cntrl_1; 65 u8 vip_cntrl_2; 66 unsigned long tmds_clock; 67 struct tda998x_audio_settings audio; 68 69 struct platform_device *audio_pdev; 70 struct mutex audio_mutex; 71 72 struct mutex edid_mutex; 73 wait_queue_head_t wq_edid; 74 volatile int wq_edid_wait; 75 76 struct work_struct detect_work; 77 struct timer_list edid_delay_timer; 78 wait_queue_head_t edid_delay_waitq; 79 bool edid_delay_active; 80 81 struct drm_encoder encoder; 82 struct drm_bridge bridge; 83 struct drm_connector connector; 84 85 u8 audio_port_enable[AUDIO_ROUTE_NUM]; 86 struct tda9950_glue cec_glue; 87 struct gpio_desc *calib; 88 struct cec_notifier *cec_notify; 89 }; 90 91 #define conn_to_tda998x_priv(x) \ 92 container_of(x, struct tda998x_priv, connector) 93 #define enc_to_tda998x_priv(x) \ 94 container_of(x, struct tda998x_priv, encoder) 95 #define bridge_to_tda998x_priv(x) \ 96 container_of(x, struct tda998x_priv, bridge) 97 98 /* The TDA9988 series of devices use a paged register scheme.. to simplify 99 * things we encode the page # in upper bits of the register #. To read/ 100 * write a given register, we need to make sure CURPAGE register is set 101 * appropriately. Which implies reads/writes are not atomic. Fun! 102 */ 103 104 #define REG(page, addr) (((page) << 8) | (addr)) 105 #define REG2ADDR(reg) ((reg) & 0xff) 106 #define REG2PAGE(reg) (((reg) >> 8) & 0xff) 107 108 #define REG_CURPAGE 0xff /* write */ 109 110 111 /* Page 00h: General Control */ 112 #define REG_VERSION_LSB REG(0x00, 0x00) /* read */ 113 #define REG_MAIN_CNTRL0 REG(0x00, 0x01) /* read/write */ 114 # define MAIN_CNTRL0_SR (1 << 0) 115 # define MAIN_CNTRL0_DECS (1 << 1) 116 # define MAIN_CNTRL0_DEHS (1 << 2) 117 # define MAIN_CNTRL0_CECS (1 << 3) 118 # define MAIN_CNTRL0_CEHS (1 << 4) 119 # define MAIN_CNTRL0_SCALER (1 << 7) 120 #define REG_VERSION_MSB REG(0x00, 0x02) /* read */ 121 #define REG_SOFTRESET REG(0x00, 0x0a) /* write */ 122 # define SOFTRESET_AUDIO (1 << 0) 123 # define SOFTRESET_I2C_MASTER (1 << 1) 124 #define REG_DDC_DISABLE REG(0x00, 0x0b) /* read/write */ 125 #define REG_CCLK_ON REG(0x00, 0x0c) /* read/write */ 126 #define REG_I2C_MASTER REG(0x00, 0x0d) /* read/write */ 127 # define I2C_MASTER_DIS_MM (1 << 0) 128 # define I2C_MASTER_DIS_FILT (1 << 1) 129 # define I2C_MASTER_APP_STRT_LAT (1 << 2) 130 #define REG_FEAT_POWERDOWN REG(0x00, 0x0e) /* read/write */ 131 # define FEAT_POWERDOWN_PREFILT BIT(0) 132 # define FEAT_POWERDOWN_CSC BIT(1) 133 # define FEAT_POWERDOWN_SPDIF (1 << 3) 134 #define REG_INT_FLAGS_0 REG(0x00, 0x0f) /* read/write */ 135 #define REG_INT_FLAGS_1 REG(0x00, 0x10) /* read/write */ 136 #define REG_INT_FLAGS_2 REG(0x00, 0x11) /* read/write */ 137 # define INT_FLAGS_2_EDID_BLK_RD (1 << 1) 138 #define REG_ENA_ACLK REG(0x00, 0x16) /* read/write */ 139 #define REG_ENA_VP_0 REG(0x00, 0x18) /* read/write */ 140 #define REG_ENA_VP_1 REG(0x00, 0x19) /* read/write */ 141 #define REG_ENA_VP_2 REG(0x00, 0x1a) /* read/write */ 142 #define REG_ENA_AP REG(0x00, 0x1e) /* read/write */ 143 #define REG_VIP_CNTRL_0 REG(0x00, 0x20) /* write */ 144 # define VIP_CNTRL_0_MIRR_A (1 << 7) 145 # define VIP_CNTRL_0_SWAP_A(x) (((x) & 7) << 4) 146 # define VIP_CNTRL_0_MIRR_B (1 << 3) 147 # define VIP_CNTRL_0_SWAP_B(x) (((x) & 7) << 0) 148 #define REG_VIP_CNTRL_1 REG(0x00, 0x21) /* write */ 149 # define VIP_CNTRL_1_MIRR_C (1 << 7) 150 # define VIP_CNTRL_1_SWAP_C(x) (((x) & 7) << 4) 151 # define VIP_CNTRL_1_MIRR_D (1 << 3) 152 # define VIP_CNTRL_1_SWAP_D(x) (((x) & 7) << 0) 153 #define REG_VIP_CNTRL_2 REG(0x00, 0x22) /* write */ 154 # define VIP_CNTRL_2_MIRR_E (1 << 7) 155 # define VIP_CNTRL_2_SWAP_E(x) (((x) & 7) << 4) 156 # define VIP_CNTRL_2_MIRR_F (1 << 3) 157 # define VIP_CNTRL_2_SWAP_F(x) (((x) & 7) << 0) 158 #define REG_VIP_CNTRL_3 REG(0x00, 0x23) /* write */ 159 # define VIP_CNTRL_3_X_TGL (1 << 0) 160 # define VIP_CNTRL_3_H_TGL (1 << 1) 161 # define VIP_CNTRL_3_V_TGL (1 << 2) 162 # define VIP_CNTRL_3_EMB (1 << 3) 163 # define VIP_CNTRL_3_SYNC_DE (1 << 4) 164 # define VIP_CNTRL_3_SYNC_HS (1 << 5) 165 # define VIP_CNTRL_3_DE_INT (1 << 6) 166 # define VIP_CNTRL_3_EDGE (1 << 7) 167 #define REG_VIP_CNTRL_4 REG(0x00, 0x24) /* write */ 168 # define VIP_CNTRL_4_BLC(x) (((x) & 3) << 0) 169 # define VIP_CNTRL_4_BLANKIT(x) (((x) & 3) << 2) 170 # define VIP_CNTRL_4_CCIR656 (1 << 4) 171 # define VIP_CNTRL_4_656_ALT (1 << 5) 172 # define VIP_CNTRL_4_TST_656 (1 << 6) 173 # define VIP_CNTRL_4_TST_PAT (1 << 7) 174 #define REG_VIP_CNTRL_5 REG(0x00, 0x25) /* write */ 175 # define VIP_CNTRL_5_CKCASE (1 << 0) 176 # define VIP_CNTRL_5_SP_CNT(x) (((x) & 3) << 1) 177 #define REG_MUX_AP REG(0x00, 0x26) /* read/write */ 178 # define MUX_AP_SELECT_I2S 0x64 179 # define MUX_AP_SELECT_SPDIF 0x40 180 #define REG_MUX_VP_VIP_OUT REG(0x00, 0x27) /* read/write */ 181 #define REG_MAT_CONTRL REG(0x00, 0x80) /* write */ 182 # define MAT_CONTRL_MAT_SC(x) (((x) & 3) << 0) 183 # define MAT_CONTRL_MAT_BP (1 << 2) 184 #define REG_VIDFORMAT REG(0x00, 0xa0) /* write */ 185 #define REG_REFPIX_MSB REG(0x00, 0xa1) /* write */ 186 #define REG_REFPIX_LSB REG(0x00, 0xa2) /* write */ 187 #define REG_REFLINE_MSB REG(0x00, 0xa3) /* write */ 188 #define REG_REFLINE_LSB REG(0x00, 0xa4) /* write */ 189 #define REG_NPIX_MSB REG(0x00, 0xa5) /* write */ 190 #define REG_NPIX_LSB REG(0x00, 0xa6) /* write */ 191 #define REG_NLINE_MSB REG(0x00, 0xa7) /* write */ 192 #define REG_NLINE_LSB REG(0x00, 0xa8) /* write */ 193 #define REG_VS_LINE_STRT_1_MSB REG(0x00, 0xa9) /* write */ 194 #define REG_VS_LINE_STRT_1_LSB REG(0x00, 0xaa) /* write */ 195 #define REG_VS_PIX_STRT_1_MSB REG(0x00, 0xab) /* write */ 196 #define REG_VS_PIX_STRT_1_LSB REG(0x00, 0xac) /* write */ 197 #define REG_VS_LINE_END_1_MSB REG(0x00, 0xad) /* write */ 198 #define REG_VS_LINE_END_1_LSB REG(0x00, 0xae) /* write */ 199 #define REG_VS_PIX_END_1_MSB REG(0x00, 0xaf) /* write */ 200 #define REG_VS_PIX_END_1_LSB REG(0x00, 0xb0) /* write */ 201 #define REG_VS_LINE_STRT_2_MSB REG(0x00, 0xb1) /* write */ 202 #define REG_VS_LINE_STRT_2_LSB REG(0x00, 0xb2) /* write */ 203 #define REG_VS_PIX_STRT_2_MSB REG(0x00, 0xb3) /* write */ 204 #define REG_VS_PIX_STRT_2_LSB REG(0x00, 0xb4) /* write */ 205 #define REG_VS_LINE_END_2_MSB REG(0x00, 0xb5) /* write */ 206 #define REG_VS_LINE_END_2_LSB REG(0x00, 0xb6) /* write */ 207 #define REG_VS_PIX_END_2_MSB REG(0x00, 0xb7) /* write */ 208 #define REG_VS_PIX_END_2_LSB REG(0x00, 0xb8) /* write */ 209 #define REG_HS_PIX_START_MSB REG(0x00, 0xb9) /* write */ 210 #define REG_HS_PIX_START_LSB REG(0x00, 0xba) /* write */ 211 #define REG_HS_PIX_STOP_MSB REG(0x00, 0xbb) /* write */ 212 #define REG_HS_PIX_STOP_LSB REG(0x00, 0xbc) /* write */ 213 #define REG_VWIN_START_1_MSB REG(0x00, 0xbd) /* write */ 214 #define REG_VWIN_START_1_LSB REG(0x00, 0xbe) /* write */ 215 #define REG_VWIN_END_1_MSB REG(0x00, 0xbf) /* write */ 216 #define REG_VWIN_END_1_LSB REG(0x00, 0xc0) /* write */ 217 #define REG_VWIN_START_2_MSB REG(0x00, 0xc1) /* write */ 218 #define REG_VWIN_START_2_LSB REG(0x00, 0xc2) /* write */ 219 #define REG_VWIN_END_2_MSB REG(0x00, 0xc3) /* write */ 220 #define REG_VWIN_END_2_LSB REG(0x00, 0xc4) /* write */ 221 #define REG_DE_START_MSB REG(0x00, 0xc5) /* write */ 222 #define REG_DE_START_LSB REG(0x00, 0xc6) /* write */ 223 #define REG_DE_STOP_MSB REG(0x00, 0xc7) /* write */ 224 #define REG_DE_STOP_LSB REG(0x00, 0xc8) /* write */ 225 #define REG_TBG_CNTRL_0 REG(0x00, 0xca) /* write */ 226 # define TBG_CNTRL_0_TOP_TGL (1 << 0) 227 # define TBG_CNTRL_0_TOP_SEL (1 << 1) 228 # define TBG_CNTRL_0_DE_EXT (1 << 2) 229 # define TBG_CNTRL_0_TOP_EXT (1 << 3) 230 # define TBG_CNTRL_0_FRAME_DIS (1 << 5) 231 # define TBG_CNTRL_0_SYNC_MTHD (1 << 6) 232 # define TBG_CNTRL_0_SYNC_ONCE (1 << 7) 233 #define REG_TBG_CNTRL_1 REG(0x00, 0xcb) /* write */ 234 # define TBG_CNTRL_1_H_TGL (1 << 0) 235 # define TBG_CNTRL_1_V_TGL (1 << 1) 236 # define TBG_CNTRL_1_TGL_EN (1 << 2) 237 # define TBG_CNTRL_1_X_EXT (1 << 3) 238 # define TBG_CNTRL_1_H_EXT (1 << 4) 239 # define TBG_CNTRL_1_V_EXT (1 << 5) 240 # define TBG_CNTRL_1_DWIN_DIS (1 << 6) 241 #define REG_ENABLE_SPACE REG(0x00, 0xd6) /* write */ 242 #define REG_HVF_CNTRL_0 REG(0x00, 0xe4) /* write */ 243 # define HVF_CNTRL_0_SM (1 << 7) 244 # define HVF_CNTRL_0_RWB (1 << 6) 245 # define HVF_CNTRL_0_PREFIL(x) (((x) & 3) << 2) 246 # define HVF_CNTRL_0_INTPOL(x) (((x) & 3) << 0) 247 #define REG_HVF_CNTRL_1 REG(0x00, 0xe5) /* write */ 248 # define HVF_CNTRL_1_FOR (1 << 0) 249 # define HVF_CNTRL_1_YUVBLK (1 << 1) 250 # define HVF_CNTRL_1_VQR(x) (((x) & 3) << 2) 251 # define HVF_CNTRL_1_PAD(x) (((x) & 3) << 4) 252 # define HVF_CNTRL_1_SEMI_PLANAR (1 << 6) 253 #define REG_RPT_CNTRL REG(0x00, 0xf0) /* write */ 254 # define RPT_CNTRL_REPEAT(x) ((x) & 15) 255 #define REG_I2S_FORMAT REG(0x00, 0xfc) /* read/write */ 256 # define I2S_FORMAT_PHILIPS (0 << 0) 257 # define I2S_FORMAT_LEFT_J (2 << 0) 258 # define I2S_FORMAT_RIGHT_J (3 << 0) 259 #define REG_AIP_CLKSEL REG(0x00, 0xfd) /* write */ 260 # define AIP_CLKSEL_AIP_SPDIF (0 << 3) 261 # define AIP_CLKSEL_AIP_I2S (1 << 3) 262 # define AIP_CLKSEL_FS_ACLK (0 << 0) 263 # define AIP_CLKSEL_FS_MCLK (1 << 0) 264 # define AIP_CLKSEL_FS_FS64SPDIF (2 << 0) 265 266 /* Page 02h: PLL settings */ 267 #define REG_PLL_SERIAL_1 REG(0x02, 0x00) /* read/write */ 268 # define PLL_SERIAL_1_SRL_FDN (1 << 0) 269 # define PLL_SERIAL_1_SRL_IZ(x) (((x) & 3) << 1) 270 # define PLL_SERIAL_1_SRL_MAN_IZ (1 << 6) 271 #define REG_PLL_SERIAL_2 REG(0x02, 0x01) /* read/write */ 272 # define PLL_SERIAL_2_SRL_NOSC(x) ((x) << 0) 273 # define PLL_SERIAL_2_SRL_PR(x) (((x) & 0xf) << 4) 274 #define REG_PLL_SERIAL_3 REG(0x02, 0x02) /* read/write */ 275 # define PLL_SERIAL_3_SRL_CCIR (1 << 0) 276 # define PLL_SERIAL_3_SRL_DE (1 << 2) 277 # define PLL_SERIAL_3_SRL_PXIN_SEL (1 << 4) 278 #define REG_SERIALIZER REG(0x02, 0x03) /* read/write */ 279 #define REG_BUFFER_OUT REG(0x02, 0x04) /* read/write */ 280 #define REG_PLL_SCG1 REG(0x02, 0x05) /* read/write */ 281 #define REG_PLL_SCG2 REG(0x02, 0x06) /* read/write */ 282 #define REG_PLL_SCGN1 REG(0x02, 0x07) /* read/write */ 283 #define REG_PLL_SCGN2 REG(0x02, 0x08) /* read/write */ 284 #define REG_PLL_SCGR1 REG(0x02, 0x09) /* read/write */ 285 #define REG_PLL_SCGR2 REG(0x02, 0x0a) /* read/write */ 286 #define REG_AUDIO_DIV REG(0x02, 0x0e) /* read/write */ 287 # define AUDIO_DIV_SERCLK_1 0 288 # define AUDIO_DIV_SERCLK_2 1 289 # define AUDIO_DIV_SERCLK_4 2 290 # define AUDIO_DIV_SERCLK_8 3 291 # define AUDIO_DIV_SERCLK_16 4 292 # define AUDIO_DIV_SERCLK_32 5 293 #define REG_SEL_CLK REG(0x02, 0x11) /* read/write */ 294 # define SEL_CLK_SEL_CLK1 (1 << 0) 295 # define SEL_CLK_SEL_VRF_CLK(x) (((x) & 3) << 1) 296 # define SEL_CLK_ENA_SC_CLK (1 << 3) 297 #define REG_ANA_GENERAL REG(0x02, 0x12) /* read/write */ 298 299 300 /* Page 09h: EDID Control */ 301 #define REG_EDID_DATA_0 REG(0x09, 0x00) /* read */ 302 /* next 127 successive registers are the EDID block */ 303 #define REG_EDID_CTRL REG(0x09, 0xfa) /* read/write */ 304 #define REG_DDC_ADDR REG(0x09, 0xfb) /* read/write */ 305 #define REG_DDC_OFFS REG(0x09, 0xfc) /* read/write */ 306 #define REG_DDC_SEGM_ADDR REG(0x09, 0xfd) /* read/write */ 307 #define REG_DDC_SEGM REG(0x09, 0xfe) /* read/write */ 308 309 310 /* Page 10h: information frames and packets */ 311 #define REG_IF1_HB0 REG(0x10, 0x20) /* read/write */ 312 #define REG_IF2_HB0 REG(0x10, 0x40) /* read/write */ 313 #define REG_IF3_HB0 REG(0x10, 0x60) /* read/write */ 314 #define REG_IF4_HB0 REG(0x10, 0x80) /* read/write */ 315 #define REG_IF5_HB0 REG(0x10, 0xa0) /* read/write */ 316 317 318 /* Page 11h: audio settings and content info packets */ 319 #define REG_AIP_CNTRL_0 REG(0x11, 0x00) /* read/write */ 320 # define AIP_CNTRL_0_RST_FIFO (1 << 0) 321 # define AIP_CNTRL_0_SWAP (1 << 1) 322 # define AIP_CNTRL_0_LAYOUT (1 << 2) 323 # define AIP_CNTRL_0_ACR_MAN (1 << 5) 324 # define AIP_CNTRL_0_RST_CTS (1 << 6) 325 #define REG_CA_I2S REG(0x11, 0x01) /* read/write */ 326 # define CA_I2S_CA_I2S(x) (((x) & 31) << 0) 327 # define CA_I2S_HBR_CHSTAT (1 << 6) 328 #define REG_LATENCY_RD REG(0x11, 0x04) /* read/write */ 329 #define REG_ACR_CTS_0 REG(0x11, 0x05) /* read/write */ 330 #define REG_ACR_CTS_1 REG(0x11, 0x06) /* read/write */ 331 #define REG_ACR_CTS_2 REG(0x11, 0x07) /* read/write */ 332 #define REG_ACR_N_0 REG(0x11, 0x08) /* read/write */ 333 #define REG_ACR_N_1 REG(0x11, 0x09) /* read/write */ 334 #define REG_ACR_N_2 REG(0x11, 0x0a) /* read/write */ 335 #define REG_CTS_N REG(0x11, 0x0c) /* read/write */ 336 # define CTS_N_K(x) (((x) & 7) << 0) 337 # define CTS_N_M(x) (((x) & 3) << 4) 338 #define REG_ENC_CNTRL REG(0x11, 0x0d) /* read/write */ 339 # define ENC_CNTRL_RST_ENC (1 << 0) 340 # define ENC_CNTRL_RST_SEL (1 << 1) 341 # define ENC_CNTRL_CTL_CODE(x) (((x) & 3) << 2) 342 #define REG_DIP_FLAGS REG(0x11, 0x0e) /* read/write */ 343 # define DIP_FLAGS_ACR (1 << 0) 344 # define DIP_FLAGS_GC (1 << 1) 345 #define REG_DIP_IF_FLAGS REG(0x11, 0x0f) /* read/write */ 346 # define DIP_IF_FLAGS_IF1 (1 << 1) 347 # define DIP_IF_FLAGS_IF2 (1 << 2) 348 # define DIP_IF_FLAGS_IF3 (1 << 3) 349 # define DIP_IF_FLAGS_IF4 (1 << 4) 350 # define DIP_IF_FLAGS_IF5 (1 << 5) 351 #define REG_CH_STAT_B(x) REG(0x11, 0x14 + (x)) /* read/write */ 352 353 354 /* Page 12h: HDCP and OTP */ 355 #define REG_TX3 REG(0x12, 0x9a) /* read/write */ 356 #define REG_TX4 REG(0x12, 0x9b) /* read/write */ 357 # define TX4_PD_RAM (1 << 1) 358 #define REG_TX33 REG(0x12, 0xb8) /* read/write */ 359 # define TX33_HDMI (1 << 1) 360 361 362 /* Page 13h: Gamut related metadata packets */ 363 364 365 366 /* CEC registers: (not paged) 367 */ 368 #define REG_CEC_INTSTATUS 0xee /* read */ 369 # define CEC_INTSTATUS_CEC (1 << 0) 370 # define CEC_INTSTATUS_HDMI (1 << 1) 371 #define REG_CEC_CAL_XOSC_CTRL1 0xf2 372 # define CEC_CAL_XOSC_CTRL1_ENA_CAL BIT(0) 373 #define REG_CEC_DES_FREQ2 0xf5 374 # define CEC_DES_FREQ2_DIS_AUTOCAL BIT(7) 375 #define REG_CEC_CLK 0xf6 376 # define CEC_CLK_FRO 0x11 377 #define REG_CEC_FRO_IM_CLK_CTRL 0xfb /* read/write */ 378 # define CEC_FRO_IM_CLK_CTRL_GHOST_DIS (1 << 7) 379 # define CEC_FRO_IM_CLK_CTRL_ENA_OTP (1 << 6) 380 # define CEC_FRO_IM_CLK_CTRL_IMCLK_SEL (1 << 1) 381 # define CEC_FRO_IM_CLK_CTRL_FRO_DIV (1 << 0) 382 #define REG_CEC_RXSHPDINTENA 0xfc /* read/write */ 383 #define REG_CEC_RXSHPDINT 0xfd /* read */ 384 # define CEC_RXSHPDINT_RXSENS BIT(0) 385 # define CEC_RXSHPDINT_HPD BIT(1) 386 #define REG_CEC_RXSHPDLEV 0xfe /* read */ 387 # define CEC_RXSHPDLEV_RXSENS (1 << 0) 388 # define CEC_RXSHPDLEV_HPD (1 << 1) 389 390 #define REG_CEC_ENAMODS 0xff /* read/write */ 391 # define CEC_ENAMODS_EN_CEC_CLK (1 << 7) 392 # define CEC_ENAMODS_DIS_FRO (1 << 6) 393 # define CEC_ENAMODS_DIS_CCLK (1 << 5) 394 # define CEC_ENAMODS_EN_RXSENS (1 << 2) 395 # define CEC_ENAMODS_EN_HDMI (1 << 1) 396 # define CEC_ENAMODS_EN_CEC (1 << 0) 397 398 399 /* Device versions: */ 400 #define TDA9989N2 0x0101 401 #define TDA19989 0x0201 402 #define TDA19989N2 0x0202 403 #define TDA19988 0x0301 404 405 static void 406 cec_write(struct tda998x_priv *priv, u16 addr, u8 val) 407 { 408 u8 buf[] = {addr, val}; 409 struct i2c_msg msg = { 410 .addr = priv->cec_addr, 411 .len = 2, 412 .buf = buf, 413 }; 414 int ret; 415 416 ret = i2c_transfer(priv->hdmi->adapter, &msg, 1); 417 if (ret < 0) 418 dev_err(&priv->hdmi->dev, "Error %d writing to cec:0x%x\n", 419 ret, addr); 420 } 421 422 static u8 423 cec_read(struct tda998x_priv *priv, u8 addr) 424 { 425 u8 val; 426 struct i2c_msg msg[2] = { 427 { 428 .addr = priv->cec_addr, 429 .len = 1, 430 .buf = &addr, 431 }, { 432 .addr = priv->cec_addr, 433 .flags = I2C_M_RD, 434 .len = 1, 435 .buf = &val, 436 }, 437 }; 438 int ret; 439 440 ret = i2c_transfer(priv->hdmi->adapter, msg, ARRAY_SIZE(msg)); 441 if (ret < 0) { 442 dev_err(&priv->hdmi->dev, "Error %d reading from cec:0x%x\n", 443 ret, addr); 444 val = 0; 445 } 446 447 return val; 448 } 449 450 static void cec_enamods(struct tda998x_priv *priv, u8 mods, bool enable) 451 { 452 int val = cec_read(priv, REG_CEC_ENAMODS); 453 454 if (val < 0) 455 return; 456 457 if (enable) 458 val |= mods; 459 else 460 val &= ~mods; 461 462 cec_write(priv, REG_CEC_ENAMODS, val); 463 } 464 465 static void tda998x_cec_set_calibration(struct tda998x_priv *priv, bool enable) 466 { 467 if (enable) { 468 u8 val; 469 470 cec_write(priv, 0xf3, 0xc0); 471 cec_write(priv, 0xf4, 0xd4); 472 473 /* Enable automatic calibration mode */ 474 val = cec_read(priv, REG_CEC_DES_FREQ2); 475 val &= ~CEC_DES_FREQ2_DIS_AUTOCAL; 476 cec_write(priv, REG_CEC_DES_FREQ2, val); 477 478 /* Enable free running oscillator */ 479 cec_write(priv, REG_CEC_CLK, CEC_CLK_FRO); 480 cec_enamods(priv, CEC_ENAMODS_DIS_FRO, false); 481 482 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 483 CEC_CAL_XOSC_CTRL1_ENA_CAL); 484 } else { 485 cec_write(priv, REG_CEC_CAL_XOSC_CTRL1, 0); 486 } 487 } 488 489 /* 490 * Calibration for the internal oscillator: we need to set calibration mode, 491 * and then pulse the IRQ line low for a 10ms ± 1% period. 492 */ 493 static void tda998x_cec_calibration(struct tda998x_priv *priv) 494 { 495 struct gpio_desc *calib = priv->calib; 496 497 mutex_lock(&priv->edid_mutex); 498 if (priv->hdmi->irq > 0) 499 disable_irq(priv->hdmi->irq); 500 gpiod_direction_output(calib, 1); 501 tda998x_cec_set_calibration(priv, true); 502 503 local_irq_disable(); 504 gpiod_set_value(calib, 0); 505 mdelay(10); 506 gpiod_set_value(calib, 1); 507 local_irq_enable(); 508 509 tda998x_cec_set_calibration(priv, false); 510 gpiod_direction_input(calib); 511 if (priv->hdmi->irq > 0) 512 enable_irq(priv->hdmi->irq); 513 mutex_unlock(&priv->edid_mutex); 514 } 515 516 static int tda998x_cec_hook_init(void *data) 517 { 518 struct tda998x_priv *priv = data; 519 struct gpio_desc *calib; 520 521 calib = gpiod_get(&priv->hdmi->dev, "nxp,calib", GPIOD_ASIS); 522 if (IS_ERR(calib)) { 523 dev_warn(&priv->hdmi->dev, "failed to get calibration gpio: %ld\n", 524 PTR_ERR(calib)); 525 return PTR_ERR(calib); 526 } 527 528 priv->calib = calib; 529 530 return 0; 531 } 532 533 static void tda998x_cec_hook_exit(void *data) 534 { 535 struct tda998x_priv *priv = data; 536 537 gpiod_put(priv->calib); 538 priv->calib = NULL; 539 } 540 541 static int tda998x_cec_hook_open(void *data) 542 { 543 struct tda998x_priv *priv = data; 544 545 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, true); 546 tda998x_cec_calibration(priv); 547 548 return 0; 549 } 550 551 static void tda998x_cec_hook_release(void *data) 552 { 553 struct tda998x_priv *priv = data; 554 555 cec_enamods(priv, CEC_ENAMODS_EN_CEC_CLK | CEC_ENAMODS_EN_CEC, false); 556 } 557 558 static int 559 set_page(struct tda998x_priv *priv, u16 reg) 560 { 561 if (REG2PAGE(reg) != priv->current_page) { 562 struct i2c_client *client = priv->hdmi; 563 u8 buf[] = { 564 REG_CURPAGE, REG2PAGE(reg) 565 }; 566 int ret = i2c_master_send(client, buf, sizeof(buf)); 567 if (ret < 0) { 568 dev_err(&client->dev, "%s %04x err %d\n", __func__, 569 reg, ret); 570 return ret; 571 } 572 573 priv->current_page = REG2PAGE(reg); 574 } 575 return 0; 576 } 577 578 static int 579 reg_read_range(struct tda998x_priv *priv, u16 reg, char *buf, int cnt) 580 { 581 struct i2c_client *client = priv->hdmi; 582 u8 addr = REG2ADDR(reg); 583 int ret; 584 585 mutex_lock(&priv->mutex); 586 ret = set_page(priv, reg); 587 if (ret < 0) 588 goto out; 589 590 ret = i2c_master_send(client, &addr, sizeof(addr)); 591 if (ret < 0) 592 goto fail; 593 594 ret = i2c_master_recv(client, buf, cnt); 595 if (ret < 0) 596 goto fail; 597 598 goto out; 599 600 fail: 601 dev_err(&client->dev, "Error %d reading from 0x%x\n", ret, reg); 602 out: 603 mutex_unlock(&priv->mutex); 604 return ret; 605 } 606 607 #define MAX_WRITE_RANGE_BUF 32 608 609 static void 610 reg_write_range(struct tda998x_priv *priv, u16 reg, u8 *p, int cnt) 611 { 612 struct i2c_client *client = priv->hdmi; 613 /* This is the maximum size of the buffer passed in */ 614 u8 buf[MAX_WRITE_RANGE_BUF + 1]; 615 int ret; 616 617 if (cnt > MAX_WRITE_RANGE_BUF) { 618 dev_err(&client->dev, "Fixed write buffer too small (%d)\n", 619 MAX_WRITE_RANGE_BUF); 620 return; 621 } 622 623 buf[0] = REG2ADDR(reg); 624 memcpy(&buf[1], p, cnt); 625 626 mutex_lock(&priv->mutex); 627 ret = set_page(priv, reg); 628 if (ret < 0) 629 goto out; 630 631 ret = i2c_master_send(client, buf, cnt + 1); 632 if (ret < 0) 633 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 634 out: 635 mutex_unlock(&priv->mutex); 636 } 637 638 static int 639 reg_read(struct tda998x_priv *priv, u16 reg) 640 { 641 u8 val = 0; 642 int ret; 643 644 ret = reg_read_range(priv, reg, &val, sizeof(val)); 645 if (ret < 0) 646 return ret; 647 return val; 648 } 649 650 static void 651 reg_write(struct tda998x_priv *priv, u16 reg, u8 val) 652 { 653 struct i2c_client *client = priv->hdmi; 654 u8 buf[] = {REG2ADDR(reg), val}; 655 int ret; 656 657 mutex_lock(&priv->mutex); 658 ret = set_page(priv, reg); 659 if (ret < 0) 660 goto out; 661 662 ret = i2c_master_send(client, buf, sizeof(buf)); 663 if (ret < 0) 664 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 665 out: 666 mutex_unlock(&priv->mutex); 667 } 668 669 static void 670 reg_write16(struct tda998x_priv *priv, u16 reg, u16 val) 671 { 672 struct i2c_client *client = priv->hdmi; 673 u8 buf[] = {REG2ADDR(reg), val >> 8, val}; 674 int ret; 675 676 mutex_lock(&priv->mutex); 677 ret = set_page(priv, reg); 678 if (ret < 0) 679 goto out; 680 681 ret = i2c_master_send(client, buf, sizeof(buf)); 682 if (ret < 0) 683 dev_err(&client->dev, "Error %d writing to 0x%x\n", ret, reg); 684 out: 685 mutex_unlock(&priv->mutex); 686 } 687 688 static void 689 reg_set(struct tda998x_priv *priv, u16 reg, u8 val) 690 { 691 int old_val; 692 693 old_val = reg_read(priv, reg); 694 if (old_val >= 0) 695 reg_write(priv, reg, old_val | val); 696 } 697 698 static void 699 reg_clear(struct tda998x_priv *priv, u16 reg, u8 val) 700 { 701 int old_val; 702 703 old_val = reg_read(priv, reg); 704 if (old_val >= 0) 705 reg_write(priv, reg, old_val & ~val); 706 } 707 708 static void 709 tda998x_reset(struct tda998x_priv *priv) 710 { 711 /* reset audio and i2c master: */ 712 reg_write(priv, REG_SOFTRESET, SOFTRESET_AUDIO | SOFTRESET_I2C_MASTER); 713 msleep(50); 714 reg_write(priv, REG_SOFTRESET, 0); 715 msleep(50); 716 717 /* reset transmitter: */ 718 reg_set(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 719 reg_clear(priv, REG_MAIN_CNTRL0, MAIN_CNTRL0_SR); 720 721 /* PLL registers common configuration */ 722 reg_write(priv, REG_PLL_SERIAL_1, 0x00); 723 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(1)); 724 reg_write(priv, REG_PLL_SERIAL_3, 0x00); 725 reg_write(priv, REG_SERIALIZER, 0x00); 726 reg_write(priv, REG_BUFFER_OUT, 0x00); 727 reg_write(priv, REG_PLL_SCG1, 0x00); 728 reg_write(priv, REG_AUDIO_DIV, AUDIO_DIV_SERCLK_8); 729 reg_write(priv, REG_SEL_CLK, SEL_CLK_SEL_CLK1 | SEL_CLK_ENA_SC_CLK); 730 reg_write(priv, REG_PLL_SCGN1, 0xfa); 731 reg_write(priv, REG_PLL_SCGN2, 0x00); 732 reg_write(priv, REG_PLL_SCGR1, 0x5b); 733 reg_write(priv, REG_PLL_SCGR2, 0x00); 734 reg_write(priv, REG_PLL_SCG2, 0x10); 735 736 /* Write the default value MUX register */ 737 reg_write(priv, REG_MUX_VP_VIP_OUT, 0x24); 738 } 739 740 /* 741 * The TDA998x has a problem when trying to read the EDID close to a 742 * HPD assertion: it needs a delay of 100ms to avoid timing out while 743 * trying to read EDID data. 744 * 745 * However, tda998x_connector_get_modes() may be called at any moment 746 * after tda998x_connector_detect() indicates that we are connected, so 747 * we need to delay probing modes in tda998x_connector_get_modes() after 748 * we have seen a HPD inactive->active transition. This code implements 749 * that delay. 750 */ 751 static void tda998x_edid_delay_done(struct timer_list *t) 752 { 753 struct tda998x_priv *priv = timer_container_of(priv, t, 754 edid_delay_timer); 755 756 priv->edid_delay_active = false; 757 wake_up(&priv->edid_delay_waitq); 758 schedule_work(&priv->detect_work); 759 } 760 761 static void tda998x_edid_delay_start(struct tda998x_priv *priv) 762 { 763 priv->edid_delay_active = true; 764 mod_timer(&priv->edid_delay_timer, jiffies + HZ/10); 765 } 766 767 static int tda998x_edid_delay_wait(struct tda998x_priv *priv) 768 { 769 return wait_event_killable(priv->edid_delay_waitq, !priv->edid_delay_active); 770 } 771 772 /* 773 * We need to run the KMS hotplug event helper outside of our threaded 774 * interrupt routine as this can call back into our get_modes method, 775 * which will want to make use of interrupts. 776 */ 777 static void tda998x_detect_work(struct work_struct *work) 778 { 779 struct tda998x_priv *priv = 780 container_of(work, struct tda998x_priv, detect_work); 781 struct drm_device *dev = priv->connector.dev; 782 783 if (dev) 784 drm_kms_helper_hotplug_event(dev); 785 } 786 787 /* 788 * only 2 interrupts may occur: screen plug/unplug and EDID read 789 */ 790 static irqreturn_t tda998x_irq_thread(int irq, void *data) 791 { 792 struct tda998x_priv *priv = data; 793 u8 sta, cec, lvl, flag0, flag1, flag2; 794 bool handled = false; 795 796 sta = cec_read(priv, REG_CEC_INTSTATUS); 797 if (sta & CEC_INTSTATUS_HDMI) { 798 cec = cec_read(priv, REG_CEC_RXSHPDINT); 799 lvl = cec_read(priv, REG_CEC_RXSHPDLEV); 800 flag0 = reg_read(priv, REG_INT_FLAGS_0); 801 flag1 = reg_read(priv, REG_INT_FLAGS_1); 802 flag2 = reg_read(priv, REG_INT_FLAGS_2); 803 DRM_DEBUG_DRIVER( 804 "tda irq sta %02x cec %02x lvl %02x f0 %02x f1 %02x f2 %02x\n", 805 sta, cec, lvl, flag0, flag1, flag2); 806 807 if (cec & CEC_RXSHPDINT_HPD) { 808 if (lvl & CEC_RXSHPDLEV_HPD) { 809 tda998x_edid_delay_start(priv); 810 } else { 811 schedule_work(&priv->detect_work); 812 cec_notifier_phys_addr_invalidate( 813 priv->cec_notify); 814 } 815 816 handled = true; 817 } 818 819 if ((flag2 & INT_FLAGS_2_EDID_BLK_RD) && priv->wq_edid_wait) { 820 priv->wq_edid_wait = 0; 821 wake_up(&priv->wq_edid); 822 handled = true; 823 } 824 } 825 826 return IRQ_RETVAL(handled); 827 } 828 829 static void 830 tda998x_write_if(struct tda998x_priv *priv, u8 bit, u16 addr, 831 union hdmi_infoframe *frame) 832 { 833 u8 buf[MAX_WRITE_RANGE_BUF]; 834 ssize_t len; 835 836 len = hdmi_infoframe_pack(frame, buf, sizeof(buf)); 837 if (len < 0) { 838 dev_err(&priv->hdmi->dev, 839 "hdmi_infoframe_pack() type=0x%02x failed: %zd\n", 840 frame->any.type, len); 841 return; 842 } 843 844 reg_clear(priv, REG_DIP_IF_FLAGS, bit); 845 reg_write_range(priv, addr, buf, len); 846 reg_set(priv, REG_DIP_IF_FLAGS, bit); 847 } 848 849 static void tda998x_write_aif(struct tda998x_priv *priv, 850 const struct hdmi_audio_infoframe *cea) 851 { 852 union hdmi_infoframe frame; 853 854 frame.audio = *cea; 855 856 tda998x_write_if(priv, DIP_IF_FLAGS_IF4, REG_IF4_HB0, &frame); 857 } 858 859 static void 860 tda998x_write_avi(struct tda998x_priv *priv, const struct drm_display_mode *mode) 861 { 862 union hdmi_infoframe frame; 863 864 drm_hdmi_avi_infoframe_from_display_mode(&frame.avi, 865 &priv->connector, mode); 866 frame.avi.quantization_range = HDMI_QUANTIZATION_RANGE_FULL; 867 drm_hdmi_avi_infoframe_quant_range(&frame.avi, &priv->connector, mode, 868 priv->rgb_quant_range); 869 870 tda998x_write_if(priv, DIP_IF_FLAGS_IF2, REG_IF2_HB0, &frame); 871 } 872 873 static void tda998x_write_vsi(struct tda998x_priv *priv, 874 const struct drm_display_mode *mode) 875 { 876 union hdmi_infoframe frame; 877 878 if (drm_hdmi_vendor_infoframe_from_display_mode(&frame.vendor.hdmi, 879 &priv->connector, 880 mode)) 881 reg_clear(priv, REG_DIP_IF_FLAGS, DIP_IF_FLAGS_IF1); 882 else 883 tda998x_write_if(priv, DIP_IF_FLAGS_IF1, REG_IF1_HB0, &frame); 884 } 885 886 /* Audio support */ 887 888 static const struct tda998x_audio_route tda998x_audio_route[AUDIO_ROUTE_NUM] = { 889 [AUDIO_ROUTE_I2S] = { 890 .ena_aclk = 1, 891 .mux_ap = MUX_AP_SELECT_I2S, 892 .aip_clksel = AIP_CLKSEL_AIP_I2S | AIP_CLKSEL_FS_ACLK, 893 }, 894 [AUDIO_ROUTE_SPDIF] = { 895 .ena_aclk = 0, 896 .mux_ap = MUX_AP_SELECT_SPDIF, 897 .aip_clksel = AIP_CLKSEL_AIP_SPDIF | AIP_CLKSEL_FS_FS64SPDIF, 898 }, 899 }; 900 901 /* Configure the TDA998x audio data and clock routing. */ 902 static int tda998x_derive_routing(struct tda998x_priv *priv, 903 struct tda998x_audio_settings *s, 904 unsigned int route) 905 { 906 s->route = &tda998x_audio_route[route]; 907 s->ena_ap = priv->audio_port_enable[route]; 908 if (s->ena_ap == 0) { 909 dev_err(&priv->hdmi->dev, "no audio configuration found\n"); 910 return -EINVAL; 911 } 912 913 return 0; 914 } 915 916 /* 917 * The audio clock divisor register controls a divider producing Audio_Clk_Out 918 * from SERclk by dividing it by 2^n where 0 <= n <= 5. We don't know what 919 * Audio_Clk_Out or SERclk are. We guess SERclk is the same as TMDS clock. 920 * 921 * It seems that Audio_Clk_Out must be the smallest value that is greater 922 * than 128*fs, otherwise audio does not function. There is some suggestion 923 * that 126*fs is a better value. 924 */ 925 static u8 tda998x_get_adiv(struct tda998x_priv *priv, unsigned int fs) 926 { 927 unsigned long min_audio_clk = fs * 128; 928 unsigned long ser_clk = priv->tmds_clock * 1000; 929 u8 adiv; 930 931 for (adiv = AUDIO_DIV_SERCLK_32; adiv != AUDIO_DIV_SERCLK_1; adiv--) 932 if (ser_clk > min_audio_clk << adiv) 933 break; 934 935 dev_dbg(&priv->hdmi->dev, 936 "ser_clk=%luHz fs=%uHz min_aclk=%luHz adiv=%d\n", 937 ser_clk, fs, min_audio_clk, adiv); 938 939 return adiv; 940 } 941 942 /* 943 * In auto-CTS mode, the TDA998x uses a "measured time stamp" counter to 944 * generate the CTS value. It appears that the "measured time stamp" is 945 * the number of TDMS clock cycles within a number of audio input clock 946 * cycles defined by the k and N parameters defined below, in a similar 947 * way to that which is set out in the CTS generation in the HDMI spec. 948 * 949 * tmdsclk ----> mts -> /m ---> CTS 950 * ^ 951 * sclk -> /k -> /N 952 * 953 * CTS = mts / m, where m is 2^M. 954 * /k is a divider based on the K value below, K+1 for K < 4, or 8 for K >= 4 955 * /N is a divider based on the HDMI specified N value. 956 * 957 * This produces the following equation: 958 * CTS = tmds_clock * k * N / (sclk * m) 959 * 960 * When combined with the sink-side equation, and realising that sclk is 961 * bclk_ratio * fs, we end up with: 962 * k = m * bclk_ratio / 128. 963 * 964 * Note: S/PDIF always uses a bclk_ratio of 64. 965 */ 966 static int tda998x_derive_cts_n(struct tda998x_priv *priv, 967 struct tda998x_audio_settings *settings, 968 unsigned int ratio) 969 { 970 switch (ratio) { 971 case 16: 972 settings->cts_n = CTS_N_M(3) | CTS_N_K(0); 973 break; 974 case 32: 975 settings->cts_n = CTS_N_M(3) | CTS_N_K(1); 976 break; 977 case 48: 978 settings->cts_n = CTS_N_M(3) | CTS_N_K(2); 979 break; 980 case 64: 981 settings->cts_n = CTS_N_M(3) | CTS_N_K(3); 982 break; 983 case 128: 984 settings->cts_n = CTS_N_M(0) | CTS_N_K(0); 985 break; 986 default: 987 dev_err(&priv->hdmi->dev, "unsupported bclk ratio %ufs\n", 988 ratio); 989 return -EINVAL; 990 } 991 return 0; 992 } 993 994 static void tda998x_audio_mute(struct tda998x_priv *priv, bool on) 995 { 996 if (on) { 997 reg_set(priv, REG_SOFTRESET, SOFTRESET_AUDIO); 998 reg_clear(priv, REG_SOFTRESET, SOFTRESET_AUDIO); 999 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 1000 } else { 1001 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 1002 } 1003 } 1004 1005 static void tda998x_configure_audio(struct tda998x_priv *priv) 1006 { 1007 const struct tda998x_audio_settings *settings = &priv->audio; 1008 u8 buf[6], adiv; 1009 u32 n; 1010 1011 /* If audio is not configured, there is nothing to do. */ 1012 if (settings->ena_ap == 0) 1013 return; 1014 1015 adiv = tda998x_get_adiv(priv, settings->sample_rate); 1016 1017 /* Enable audio ports */ 1018 reg_write(priv, REG_ENA_AP, settings->ena_ap); 1019 reg_write(priv, REG_ENA_ACLK, settings->route->ena_aclk); 1020 reg_write(priv, REG_MUX_AP, settings->route->mux_ap); 1021 reg_write(priv, REG_I2S_FORMAT, settings->i2s_format); 1022 reg_write(priv, REG_AIP_CLKSEL, settings->route->aip_clksel); 1023 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_LAYOUT | 1024 AIP_CNTRL_0_ACR_MAN); /* auto CTS */ 1025 reg_write(priv, REG_CTS_N, settings->cts_n); 1026 reg_write(priv, REG_AUDIO_DIV, adiv); 1027 1028 /* 1029 * This is the approximate value of N, which happens to be 1030 * the recommended values for non-coherent clocks. 1031 */ 1032 n = 128 * settings->sample_rate / 1000; 1033 1034 /* Write the CTS and N values */ 1035 buf[0] = 0x44; 1036 buf[1] = 0x42; 1037 buf[2] = 0x01; 1038 buf[3] = n; 1039 buf[4] = n >> 8; 1040 buf[5] = n >> 16; 1041 reg_write_range(priv, REG_ACR_CTS_0, buf, 6); 1042 1043 /* Reset CTS generator */ 1044 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 1045 reg_clear(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_CTS); 1046 1047 /* Write the channel status 1048 * The REG_CH_STAT_B-registers skip IEC958 AES2 byte, because 1049 * there is a separate register for each I2S wire. 1050 */ 1051 buf[0] = settings->status[0]; 1052 buf[1] = settings->status[1]; 1053 buf[2] = settings->status[3]; 1054 buf[3] = settings->status[4]; 1055 reg_write_range(priv, REG_CH_STAT_B(0), buf, 4); 1056 1057 tda998x_audio_mute(priv, true); 1058 msleep(20); 1059 tda998x_audio_mute(priv, false); 1060 1061 tda998x_write_aif(priv, &settings->cea); 1062 } 1063 1064 static int tda998x_audio_hw_params(struct device *dev, void *data, 1065 struct hdmi_codec_daifmt *daifmt, 1066 struct hdmi_codec_params *params) 1067 { 1068 struct tda998x_priv *priv = dev_get_drvdata(dev); 1069 unsigned int bclk_ratio; 1070 bool spdif = daifmt->fmt == HDMI_SPDIF; 1071 int ret; 1072 struct tda998x_audio_settings audio = { 1073 .sample_rate = params->sample_rate, 1074 .cea = params->cea, 1075 }; 1076 1077 memcpy(audio.status, params->iec.status, 1078 min(sizeof(audio.status), sizeof(params->iec.status))); 1079 1080 switch (daifmt->fmt) { 1081 case HDMI_I2S: 1082 audio.i2s_format = I2S_FORMAT_PHILIPS; 1083 break; 1084 case HDMI_LEFT_J: 1085 audio.i2s_format = I2S_FORMAT_LEFT_J; 1086 break; 1087 case HDMI_RIGHT_J: 1088 audio.i2s_format = I2S_FORMAT_RIGHT_J; 1089 break; 1090 case HDMI_SPDIF: 1091 audio.i2s_format = 0; 1092 break; 1093 default: 1094 dev_err(dev, "%s: Invalid format %d\n", __func__, daifmt->fmt); 1095 return -EINVAL; 1096 } 1097 1098 if (!spdif && 1099 (daifmt->bit_clk_inv || daifmt->frame_clk_inv || 1100 daifmt->bit_clk_provider || daifmt->frame_clk_provider)) { 1101 dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__, 1102 daifmt->bit_clk_inv, daifmt->frame_clk_inv, 1103 daifmt->bit_clk_provider, 1104 daifmt->frame_clk_provider); 1105 return -EINVAL; 1106 } 1107 1108 ret = tda998x_derive_routing(priv, &audio, AUDIO_ROUTE_I2S + spdif); 1109 if (ret < 0) 1110 return ret; 1111 1112 bclk_ratio = spdif ? 64 : params->sample_width * 2; 1113 ret = tda998x_derive_cts_n(priv, &audio, bclk_ratio); 1114 if (ret < 0) 1115 return ret; 1116 1117 mutex_lock(&priv->audio_mutex); 1118 priv->audio = audio; 1119 if (priv->supports_infoframes && priv->sink_has_audio) 1120 tda998x_configure_audio(priv); 1121 mutex_unlock(&priv->audio_mutex); 1122 1123 return 0; 1124 } 1125 1126 static void tda998x_audio_shutdown(struct device *dev, void *data) 1127 { 1128 struct tda998x_priv *priv = dev_get_drvdata(dev); 1129 1130 mutex_lock(&priv->audio_mutex); 1131 1132 reg_write(priv, REG_ENA_AP, 0); 1133 priv->audio.ena_ap = 0; 1134 1135 mutex_unlock(&priv->audio_mutex); 1136 } 1137 1138 static int tda998x_audio_mute_stream(struct device *dev, void *data, 1139 bool enable, int direction) 1140 { 1141 struct tda998x_priv *priv = dev_get_drvdata(dev); 1142 1143 mutex_lock(&priv->audio_mutex); 1144 1145 tda998x_audio_mute(priv, enable); 1146 1147 mutex_unlock(&priv->audio_mutex); 1148 return 0; 1149 } 1150 1151 static int tda998x_audio_get_eld(struct device *dev, void *data, 1152 uint8_t *buf, size_t len) 1153 { 1154 struct tda998x_priv *priv = dev_get_drvdata(dev); 1155 1156 mutex_lock(&priv->audio_mutex); 1157 memcpy(buf, priv->connector.eld, 1158 min(sizeof(priv->connector.eld), len)); 1159 mutex_unlock(&priv->audio_mutex); 1160 1161 return 0; 1162 } 1163 1164 static const struct hdmi_codec_ops audio_codec_ops = { 1165 .hw_params = tda998x_audio_hw_params, 1166 .audio_shutdown = tda998x_audio_shutdown, 1167 .mute_stream = tda998x_audio_mute_stream, 1168 .get_eld = tda998x_audio_get_eld, 1169 }; 1170 1171 static int tda998x_audio_codec_init(struct tda998x_priv *priv, 1172 struct device *dev) 1173 { 1174 struct hdmi_codec_pdata codec_data = { 1175 .ops = &audio_codec_ops, 1176 .max_i2s_channels = 2, 1177 .no_i2s_capture = 1, 1178 .no_spdif_capture = 1, 1179 .no_capture_mute = 1, 1180 }; 1181 1182 if (priv->audio_port_enable[AUDIO_ROUTE_I2S]) 1183 codec_data.i2s = 1; 1184 if (priv->audio_port_enable[AUDIO_ROUTE_SPDIF]) 1185 codec_data.spdif = 1; 1186 1187 priv->audio_pdev = platform_device_register_data( 1188 dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO, 1189 &codec_data, sizeof(codec_data)); 1190 1191 return PTR_ERR_OR_ZERO(priv->audio_pdev); 1192 } 1193 1194 /* DRM connector functions */ 1195 1196 static enum drm_connector_status tda998x_conn_detect(struct tda998x_priv *priv) 1197 { 1198 u8 val = cec_read(priv, REG_CEC_RXSHPDLEV); 1199 1200 return (val & CEC_RXSHPDLEV_HPD) ? connector_status_connected : 1201 connector_status_disconnected; 1202 } 1203 1204 static enum drm_connector_status 1205 tda998x_connector_detect(struct drm_connector *connector, bool force) 1206 { 1207 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1208 1209 return tda998x_conn_detect(priv); 1210 } 1211 1212 static const struct drm_connector_funcs tda998x_connector_funcs = { 1213 .reset = drm_atomic_helper_connector_reset, 1214 .fill_modes = drm_helper_probe_single_connector_modes, 1215 .detect = tda998x_connector_detect, 1216 .destroy = drm_connector_cleanup, 1217 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1218 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1219 }; 1220 1221 static int read_edid_block(void *data, u8 *buf, unsigned int blk, size_t length) 1222 { 1223 struct tda998x_priv *priv = data; 1224 u8 offset, segptr; 1225 int ret, i; 1226 1227 offset = (blk & 1) ? 128 : 0; 1228 segptr = blk / 2; 1229 1230 mutex_lock(&priv->edid_mutex); 1231 1232 reg_write(priv, REG_DDC_ADDR, 0xa0); 1233 reg_write(priv, REG_DDC_OFFS, offset); 1234 reg_write(priv, REG_DDC_SEGM_ADDR, 0x60); 1235 reg_write(priv, REG_DDC_SEGM, segptr); 1236 1237 /* enable reading EDID: */ 1238 priv->wq_edid_wait = 1; 1239 reg_write(priv, REG_EDID_CTRL, 0x1); 1240 1241 /* flag must be cleared by sw: */ 1242 reg_write(priv, REG_EDID_CTRL, 0x0); 1243 1244 /* wait for block read to complete: */ 1245 if (priv->hdmi->irq) { 1246 i = wait_event_timeout(priv->wq_edid, 1247 !priv->wq_edid_wait, 1248 msecs_to_jiffies(100)); 1249 if (i < 0) { 1250 dev_err(&priv->hdmi->dev, "read edid wait err %d\n", i); 1251 ret = i; 1252 goto failed; 1253 } 1254 } else { 1255 for (i = 100; i > 0; i--) { 1256 msleep(1); 1257 ret = reg_read(priv, REG_INT_FLAGS_2); 1258 if (ret < 0) 1259 goto failed; 1260 if (ret & INT_FLAGS_2_EDID_BLK_RD) 1261 break; 1262 } 1263 } 1264 1265 if (i == 0) { 1266 dev_err(&priv->hdmi->dev, "read edid timeout\n"); 1267 ret = -ETIMEDOUT; 1268 goto failed; 1269 } 1270 1271 ret = reg_read_range(priv, REG_EDID_DATA_0, buf, length); 1272 if (ret != length) { 1273 dev_err(&priv->hdmi->dev, "failed to read edid block %d: %d\n", 1274 blk, ret); 1275 goto failed; 1276 } 1277 1278 ret = 0; 1279 1280 failed: 1281 mutex_unlock(&priv->edid_mutex); 1282 return ret; 1283 } 1284 1285 static const struct drm_edid *tda998x_edid_read(struct tda998x_priv *priv, 1286 struct drm_connector *connector) 1287 { 1288 const struct drm_edid *drm_edid; 1289 1290 /* 1291 * If we get killed while waiting for the HPD timeout, return 1292 * no modes found: we are not in a restartable path, so we 1293 * can't handle signals gracefully. 1294 */ 1295 if (tda998x_edid_delay_wait(priv)) 1296 return NULL; 1297 1298 if (priv->rev == TDA19988) 1299 reg_clear(priv, REG_TX4, TX4_PD_RAM); 1300 1301 drm_edid = drm_edid_read_custom(connector, read_edid_block, priv); 1302 1303 if (priv->rev == TDA19988) 1304 reg_set(priv, REG_TX4, TX4_PD_RAM); 1305 1306 return drm_edid; 1307 } 1308 1309 static int tda998x_connector_get_modes(struct drm_connector *connector) 1310 { 1311 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1312 const struct drm_edid *drm_edid; 1313 int n; 1314 1315 drm_edid = tda998x_edid_read(priv, connector); 1316 drm_edid_connector_update(connector, drm_edid); 1317 cec_notifier_set_phys_addr(priv->cec_notify, 1318 connector->display_info.source_physical_address); 1319 1320 if (!drm_edid) { 1321 dev_warn(&priv->hdmi->dev, "failed to read EDID\n"); 1322 return 0; 1323 } 1324 1325 mutex_lock(&priv->audio_mutex); 1326 n = drm_edid_connector_add_modes(connector); 1327 priv->sink_has_audio = connector->display_info.has_audio; 1328 mutex_unlock(&priv->audio_mutex); 1329 1330 drm_edid_free(drm_edid); 1331 1332 return n; 1333 } 1334 1335 static struct drm_encoder * 1336 tda998x_connector_best_encoder(struct drm_connector *connector) 1337 { 1338 struct tda998x_priv *priv = conn_to_tda998x_priv(connector); 1339 1340 return priv->bridge.encoder; 1341 } 1342 1343 static 1344 const struct drm_connector_helper_funcs tda998x_connector_helper_funcs = { 1345 .get_modes = tda998x_connector_get_modes, 1346 .best_encoder = tda998x_connector_best_encoder, 1347 }; 1348 1349 static int tda998x_connector_init(struct tda998x_priv *priv, 1350 struct drm_device *drm) 1351 { 1352 struct drm_connector *connector = &priv->connector; 1353 int ret; 1354 1355 connector->interlace_allowed = 1; 1356 1357 if (priv->hdmi->irq) 1358 connector->polled = DRM_CONNECTOR_POLL_HPD; 1359 else 1360 connector->polled = DRM_CONNECTOR_POLL_CONNECT | 1361 DRM_CONNECTOR_POLL_DISCONNECT; 1362 1363 drm_connector_helper_add(connector, &tda998x_connector_helper_funcs); 1364 ret = drm_connector_init(drm, connector, &tda998x_connector_funcs, 1365 DRM_MODE_CONNECTOR_HDMIA); 1366 if (ret) 1367 return ret; 1368 1369 drm_connector_attach_encoder(&priv->connector, 1370 priv->bridge.encoder); 1371 1372 return 0; 1373 } 1374 1375 /* DRM bridge functions */ 1376 1377 static int tda998x_bridge_attach(struct drm_bridge *bridge, 1378 struct drm_encoder *encoder, 1379 enum drm_bridge_attach_flags flags) 1380 { 1381 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1382 1383 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 1384 return 0; 1385 1386 return tda998x_connector_init(priv, bridge->dev); 1387 } 1388 1389 static void tda998x_bridge_detach(struct drm_bridge *bridge) 1390 { 1391 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1392 1393 if (priv->connector.dev) 1394 drm_connector_cleanup(&priv->connector); 1395 } 1396 1397 static enum drm_mode_status tda998x_bridge_mode_valid(struct drm_bridge *bridge, 1398 const struct drm_display_info *info, 1399 const struct drm_display_mode *mode) 1400 { 1401 /* TDA19988 dotclock can go up to 165MHz */ 1402 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1403 1404 if (mode->clock > ((priv->rev == TDA19988) ? 165000 : 150000)) 1405 return MODE_CLOCK_HIGH; 1406 if (mode->htotal >= BIT(13)) 1407 return MODE_BAD_HVALUE; 1408 if (mode->vtotal >= BIT(11)) 1409 return MODE_BAD_VVALUE; 1410 return MODE_OK; 1411 } 1412 1413 static void tda998x_bridge_enable(struct drm_bridge *bridge, 1414 struct drm_atomic_commit *commit) 1415 { 1416 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1417 1418 if (!priv->is_on) { 1419 /* enable video ports, audio will be enabled later */ 1420 reg_write(priv, REG_ENA_VP_0, 0xff); 1421 reg_write(priv, REG_ENA_VP_1, 0xff); 1422 reg_write(priv, REG_ENA_VP_2, 0xff); 1423 /* set muxing after enabling ports: */ 1424 reg_write(priv, REG_VIP_CNTRL_0, priv->vip_cntrl_0); 1425 reg_write(priv, REG_VIP_CNTRL_1, priv->vip_cntrl_1); 1426 reg_write(priv, REG_VIP_CNTRL_2, priv->vip_cntrl_2); 1427 1428 priv->is_on = true; 1429 } 1430 } 1431 1432 static void tda998x_bridge_disable(struct drm_bridge *bridge, 1433 struct drm_atomic_commit *commit) 1434 { 1435 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1436 1437 if (priv->is_on) { 1438 /* disable video ports */ 1439 reg_write(priv, REG_ENA_VP_0, 0x00); 1440 reg_write(priv, REG_ENA_VP_1, 0x00); 1441 reg_write(priv, REG_ENA_VP_2, 0x00); 1442 1443 priv->is_on = false; 1444 } 1445 } 1446 1447 static void tda998x_bridge_mode_set(struct drm_bridge *bridge, 1448 const struct drm_display_mode *mode, 1449 const struct drm_display_mode *adjusted_mode) 1450 { 1451 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1452 unsigned long tmds_clock; 1453 u16 ref_pix, ref_line, n_pix, n_line; 1454 u16 hs_pix_s, hs_pix_e; 1455 u16 vs1_pix_s, vs1_pix_e, vs1_line_s, vs1_line_e; 1456 u16 vs2_pix_s, vs2_pix_e, vs2_line_s, vs2_line_e; 1457 u16 vwin1_line_s, vwin1_line_e; 1458 u16 vwin2_line_s, vwin2_line_e; 1459 u16 de_pix_s, de_pix_e; 1460 u8 reg, div, rep, sel_clk; 1461 1462 /* 1463 * Since we are "computer" like, our source invariably produces 1464 * full-range RGB. If the monitor supports full-range, then use 1465 * it, otherwise reduce to limited-range. 1466 */ 1467 priv->rgb_quant_range = 1468 priv->connector.display_info.rgb_quant_range_selectable ? 1469 HDMI_QUANTIZATION_RANGE_FULL : 1470 drm_default_rgb_quant_range(adjusted_mode); 1471 1472 /* 1473 * Internally TDA998x is using ITU-R BT.656 style sync but 1474 * we get VESA style sync. TDA998x is using a reference pixel 1475 * relative to ITU to sync to the input frame and for output 1476 * sync generation. Currently, we are using reference detection 1477 * from HS/VS, i.e. REFPIX/REFLINE denote frame start sync point 1478 * which is position of rising VS with coincident rising HS. 1479 * 1480 * Now there is some issues to take care of: 1481 * - HDMI data islands require sync-before-active 1482 * - TDA998x register values must be > 0 to be enabled 1483 * - REFLINE needs an additional offset of +1 1484 * - REFPIX needs an addtional offset of +1 for UYUV and +3 for RGB 1485 * 1486 * So we add +1 to all horizontal and vertical register values, 1487 * plus an additional +3 for REFPIX as we are using RGB input only. 1488 */ 1489 n_pix = mode->htotal; 1490 n_line = mode->vtotal; 1491 1492 hs_pix_e = mode->hsync_end - mode->hdisplay; 1493 hs_pix_s = mode->hsync_start - mode->hdisplay; 1494 de_pix_e = mode->htotal; 1495 de_pix_s = mode->htotal - mode->hdisplay; 1496 ref_pix = 3 + hs_pix_s; 1497 1498 /* 1499 * Attached LCD controllers may generate broken sync. Allow 1500 * those to adjust the position of the rising VS edge by adding 1501 * HSKEW to ref_pix. 1502 */ 1503 if (adjusted_mode->flags & DRM_MODE_FLAG_HSKEW) 1504 ref_pix += adjusted_mode->hskew; 1505 1506 if ((mode->flags & DRM_MODE_FLAG_INTERLACE) == 0) { 1507 ref_line = 1 + mode->vsync_start - mode->vdisplay; 1508 vwin1_line_s = mode->vtotal - mode->vdisplay - 1; 1509 vwin1_line_e = vwin1_line_s + mode->vdisplay; 1510 vs1_pix_s = vs1_pix_e = hs_pix_s; 1511 vs1_line_s = mode->vsync_start - mode->vdisplay; 1512 vs1_line_e = vs1_line_s + 1513 mode->vsync_end - mode->vsync_start; 1514 vwin2_line_s = vwin2_line_e = 0; 1515 vs2_pix_s = vs2_pix_e = 0; 1516 vs2_line_s = vs2_line_e = 0; 1517 } else { 1518 ref_line = 1 + (mode->vsync_start - mode->vdisplay)/2; 1519 vwin1_line_s = (mode->vtotal - mode->vdisplay)/2; 1520 vwin1_line_e = vwin1_line_s + mode->vdisplay/2; 1521 vs1_pix_s = vs1_pix_e = hs_pix_s; 1522 vs1_line_s = (mode->vsync_start - mode->vdisplay)/2; 1523 vs1_line_e = vs1_line_s + 1524 (mode->vsync_end - mode->vsync_start)/2; 1525 vwin2_line_s = vwin1_line_s + mode->vtotal/2; 1526 vwin2_line_e = vwin2_line_s + mode->vdisplay/2; 1527 vs2_pix_s = vs2_pix_e = hs_pix_s + mode->htotal/2; 1528 vs2_line_s = vs1_line_s + mode->vtotal/2 ; 1529 vs2_line_e = vs2_line_s + 1530 (mode->vsync_end - mode->vsync_start)/2; 1531 } 1532 1533 /* 1534 * Select pixel repeat depending on the double-clock flag 1535 * (which means we have to repeat each pixel once.) 1536 */ 1537 rep = mode->flags & DRM_MODE_FLAG_DBLCLK ? 1 : 0; 1538 sel_clk = SEL_CLK_ENA_SC_CLK | SEL_CLK_SEL_CLK1 | 1539 SEL_CLK_SEL_VRF_CLK(rep ? 2 : 0); 1540 1541 /* the TMDS clock is scaled up by the pixel repeat */ 1542 tmds_clock = mode->clock * (1 + rep); 1543 1544 /* 1545 * The divisor is power-of-2. The TDA9983B datasheet gives 1546 * this as ranges of Msample/s, which is 10x the TMDS clock: 1547 * 0 - 800 to 1500 Msample/s 1548 * 1 - 400 to 800 Msample/s 1549 * 2 - 200 to 400 Msample/s 1550 * 3 - as 2 above 1551 */ 1552 for (div = 0; div < 3; div++) 1553 if (80000 >> div <= tmds_clock) 1554 break; 1555 1556 mutex_lock(&priv->audio_mutex); 1557 1558 priv->tmds_clock = tmds_clock; 1559 1560 /* mute the audio FIFO: */ 1561 reg_set(priv, REG_AIP_CNTRL_0, AIP_CNTRL_0_RST_FIFO); 1562 1563 /* set HDMI HDCP mode off: */ 1564 reg_write(priv, REG_TBG_CNTRL_1, TBG_CNTRL_1_DWIN_DIS); 1565 reg_clear(priv, REG_TX33, TX33_HDMI); 1566 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(0)); 1567 1568 /* no pre-filter or interpolator: */ 1569 reg_write(priv, REG_HVF_CNTRL_0, HVF_CNTRL_0_PREFIL(0) | 1570 HVF_CNTRL_0_INTPOL(0)); 1571 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_PREFILT); 1572 reg_write(priv, REG_VIP_CNTRL_5, VIP_CNTRL_5_SP_CNT(0)); 1573 reg_write(priv, REG_VIP_CNTRL_4, VIP_CNTRL_4_BLANKIT(0) | 1574 VIP_CNTRL_4_BLC(0)); 1575 1576 reg_clear(priv, REG_PLL_SERIAL_1, PLL_SERIAL_1_SRL_MAN_IZ); 1577 reg_clear(priv, REG_PLL_SERIAL_3, PLL_SERIAL_3_SRL_CCIR | 1578 PLL_SERIAL_3_SRL_DE); 1579 reg_write(priv, REG_SERIALIZER, 0); 1580 reg_write(priv, REG_HVF_CNTRL_1, HVF_CNTRL_1_VQR(0)); 1581 1582 reg_write(priv, REG_RPT_CNTRL, RPT_CNTRL_REPEAT(rep)); 1583 reg_write(priv, REG_SEL_CLK, sel_clk); 1584 reg_write(priv, REG_PLL_SERIAL_2, PLL_SERIAL_2_SRL_NOSC(div) | 1585 PLL_SERIAL_2_SRL_PR(rep)); 1586 1587 /* set color matrix according to output rgb quant range */ 1588 if (priv->rgb_quant_range == HDMI_QUANTIZATION_RANGE_LIMITED) { 1589 static u8 tda998x_full_to_limited_range[] = { 1590 MAT_CONTRL_MAT_SC(2), 1591 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 1592 0x03, 0x6f, 0x00, 0x00, 0x00, 0x00, 1593 0x00, 0x00, 0x03, 0x6f, 0x00, 0x00, 1594 0x00, 0x00, 0x00, 0x00, 0x03, 0x6f, 1595 0x00, 0x40, 0x00, 0x40, 0x00, 0x40 1596 }; 1597 reg_clear(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC); 1598 reg_write_range(priv, REG_MAT_CONTRL, 1599 tda998x_full_to_limited_range, 1600 sizeof(tda998x_full_to_limited_range)); 1601 } else { 1602 reg_write(priv, REG_MAT_CONTRL, MAT_CONTRL_MAT_BP | 1603 MAT_CONTRL_MAT_SC(1)); 1604 reg_set(priv, REG_FEAT_POWERDOWN, FEAT_POWERDOWN_CSC); 1605 } 1606 1607 /* set BIAS tmds value: */ 1608 reg_write(priv, REG_ANA_GENERAL, 0x09); 1609 1610 /* 1611 * Sync on rising HSYNC/VSYNC 1612 */ 1613 reg = VIP_CNTRL_3_SYNC_HS; 1614 1615 /* 1616 * TDA19988 requires high-active sync at input stage, 1617 * so invert low-active sync provided by master encoder here 1618 */ 1619 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1620 reg |= VIP_CNTRL_3_H_TGL; 1621 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1622 reg |= VIP_CNTRL_3_V_TGL; 1623 reg_write(priv, REG_VIP_CNTRL_3, reg); 1624 1625 reg_write(priv, REG_VIDFORMAT, 0x00); 1626 reg_write16(priv, REG_REFPIX_MSB, ref_pix); 1627 reg_write16(priv, REG_REFLINE_MSB, ref_line); 1628 reg_write16(priv, REG_NPIX_MSB, n_pix); 1629 reg_write16(priv, REG_NLINE_MSB, n_line); 1630 reg_write16(priv, REG_VS_LINE_STRT_1_MSB, vs1_line_s); 1631 reg_write16(priv, REG_VS_PIX_STRT_1_MSB, vs1_pix_s); 1632 reg_write16(priv, REG_VS_LINE_END_1_MSB, vs1_line_e); 1633 reg_write16(priv, REG_VS_PIX_END_1_MSB, vs1_pix_e); 1634 reg_write16(priv, REG_VS_LINE_STRT_2_MSB, vs2_line_s); 1635 reg_write16(priv, REG_VS_PIX_STRT_2_MSB, vs2_pix_s); 1636 reg_write16(priv, REG_VS_LINE_END_2_MSB, vs2_line_e); 1637 reg_write16(priv, REG_VS_PIX_END_2_MSB, vs2_pix_e); 1638 reg_write16(priv, REG_HS_PIX_START_MSB, hs_pix_s); 1639 reg_write16(priv, REG_HS_PIX_STOP_MSB, hs_pix_e); 1640 reg_write16(priv, REG_VWIN_START_1_MSB, vwin1_line_s); 1641 reg_write16(priv, REG_VWIN_END_1_MSB, vwin1_line_e); 1642 reg_write16(priv, REG_VWIN_START_2_MSB, vwin2_line_s); 1643 reg_write16(priv, REG_VWIN_END_2_MSB, vwin2_line_e); 1644 reg_write16(priv, REG_DE_START_MSB, de_pix_s); 1645 reg_write16(priv, REG_DE_STOP_MSB, de_pix_e); 1646 1647 if (priv->rev == TDA19988) { 1648 /* let incoming pixels fill the active space (if any) */ 1649 reg_write(priv, REG_ENABLE_SPACE, 0x00); 1650 } 1651 1652 /* 1653 * Always generate sync polarity relative to input sync and 1654 * revert input stage toggled sync at output stage 1655 */ 1656 reg = TBG_CNTRL_1_DWIN_DIS | TBG_CNTRL_1_TGL_EN; 1657 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1658 reg |= TBG_CNTRL_1_H_TGL; 1659 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1660 reg |= TBG_CNTRL_1_V_TGL; 1661 reg_write(priv, REG_TBG_CNTRL_1, reg); 1662 1663 /* must be last register set: */ 1664 reg_write(priv, REG_TBG_CNTRL_0, 0); 1665 1666 /* CEA-861B section 6 says that: 1667 * CEA version 1 (CEA-861) has no support for infoframes. 1668 * CEA version 2 (CEA-861A) supports version 1 AVI infoframes, 1669 * and optional basic audio. 1670 * CEA version 3 (CEA-861B) supports version 1 and 2 AVI infoframes, 1671 * and optional digital audio, with audio infoframes. 1672 * 1673 * Since we only support generation of version 2 AVI infoframes, 1674 * ignore CEA version 2 and below (iow, behave as if we're a 1675 * CEA-861 source.) 1676 */ 1677 priv->supports_infoframes = priv->connector.display_info.cea_rev >= 3; 1678 1679 if (priv->supports_infoframes) { 1680 /* We need to turn HDMI HDCP stuff on to get audio through */ 1681 reg &= ~TBG_CNTRL_1_DWIN_DIS; 1682 reg_write(priv, REG_TBG_CNTRL_1, reg); 1683 reg_write(priv, REG_ENC_CNTRL, ENC_CNTRL_CTL_CODE(1)); 1684 reg_set(priv, REG_TX33, TX33_HDMI); 1685 1686 tda998x_write_avi(priv, adjusted_mode); 1687 tda998x_write_vsi(priv, adjusted_mode); 1688 1689 if (priv->sink_has_audio) 1690 tda998x_configure_audio(priv); 1691 } 1692 1693 mutex_unlock(&priv->audio_mutex); 1694 } 1695 1696 static const struct drm_edid * 1697 tda998x_bridge_edid_read(struct drm_bridge *bridge, 1698 struct drm_connector *connector) 1699 { 1700 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1701 const struct drm_edid *drm_edid; 1702 const struct edid *edid; 1703 1704 drm_edid = tda998x_edid_read(priv, connector); 1705 if (!drm_edid) { 1706 dev_dbg(&priv->hdmi->dev, "failed to get edid\n"); 1707 return NULL; 1708 } 1709 1710 /* 1711 * FIXME: This should use connector->display_info.has_audio from 1712 * a path that has read the EDID and called 1713 * drm_edid_connector_update(). 1714 */ 1715 edid = drm_edid_raw(drm_edid); 1716 1717 dev_dbg(&priv->hdmi->dev, "got edid: width[%d] x height[%d]\n", 1718 edid->width_cm, edid->height_cm); 1719 1720 priv->sink_has_audio = drm_detect_monitor_audio(edid); 1721 cec_notifier_set_phys_addr_from_edid(priv->cec_notify, edid); 1722 1723 return drm_edid; 1724 } 1725 1726 static enum drm_connector_status 1727 tda998x_bridge_detect(struct drm_bridge *bridge, 1728 struct drm_connector *connector) 1729 { 1730 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1731 1732 return tda998x_conn_detect(priv); 1733 } 1734 1735 static void tda998x_bridge_hpd_enable(struct drm_bridge *bridge) 1736 { 1737 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1738 1739 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD); 1740 } 1741 1742 static void tda998x_bridge_hpd_disable(struct drm_bridge *bridge) 1743 { 1744 struct tda998x_priv *priv = bridge_to_tda998x_priv(bridge); 1745 1746 cec_write(priv, REG_CEC_RXSHPDINTENA, 0); 1747 } 1748 1749 static const struct drm_bridge_funcs tda998x_bridge_funcs = { 1750 .atomic_create_state = drm_atomic_helper_bridge_create_state, 1751 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1752 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1753 .attach = tda998x_bridge_attach, 1754 .detach = tda998x_bridge_detach, 1755 .mode_valid = tda998x_bridge_mode_valid, 1756 .atomic_disable = tda998x_bridge_disable, 1757 .mode_set = tda998x_bridge_mode_set, 1758 .atomic_enable = tda998x_bridge_enable, 1759 .edid_read = tda998x_bridge_edid_read, 1760 .detect = tda998x_bridge_detect, 1761 .hpd_enable = tda998x_bridge_hpd_enable, 1762 .hpd_disable = tda998x_bridge_hpd_disable, 1763 }; 1764 1765 /* I2C driver functions */ 1766 1767 static int tda998x_get_audio_ports(struct tda998x_priv *priv, 1768 struct device_node *np) 1769 { 1770 const __be32 *port_data; 1771 u32 size; 1772 int i; 1773 1774 port_data = of_get_property(np, "audio-ports", &size); 1775 if (!port_data) 1776 return 0; 1777 1778 size /= sizeof(u32); 1779 if (size > 2 * ARRAY_SIZE(priv->audio_port_enable) || size % 2 != 0) { 1780 dev_err(&priv->hdmi->dev, 1781 "Bad number of elements in audio-ports dt-property\n"); 1782 return -EINVAL; 1783 } 1784 1785 size /= 2; 1786 1787 for (i = 0; i < size; i++) { 1788 unsigned int route; 1789 u8 afmt = be32_to_cpup(&port_data[2*i]); 1790 u8 ena_ap = be32_to_cpup(&port_data[2*i+1]); 1791 1792 switch (afmt) { 1793 case TDA998x_I2S: 1794 route = AUDIO_ROUTE_I2S; 1795 break; 1796 case TDA998x_SPDIF: 1797 route = AUDIO_ROUTE_SPDIF; 1798 break; 1799 default: 1800 dev_err(&priv->hdmi->dev, 1801 "Bad audio format %u\n", afmt); 1802 return -EINVAL; 1803 } 1804 1805 if (!ena_ap) { 1806 dev_err(&priv->hdmi->dev, "invalid zero port config\n"); 1807 continue; 1808 } 1809 1810 if (priv->audio_port_enable[route]) { 1811 dev_err(&priv->hdmi->dev, 1812 "%s format already configured\n", 1813 route == AUDIO_ROUTE_SPDIF ? "SPDIF" : "I2S"); 1814 return -EINVAL; 1815 } 1816 1817 priv->audio_port_enable[route] = ena_ap; 1818 } 1819 return 0; 1820 } 1821 1822 static int 1823 tda998x_probe(struct i2c_client *client) 1824 { 1825 struct device_node *np = client->dev.of_node; 1826 struct device *dev = &client->dev; 1827 struct i2c_board_info cec_info; 1828 struct tda998x_priv *priv; 1829 int rev_lo, rev_hi, ret; 1830 u32 video; 1831 1832 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1833 dev_warn(&client->dev, "adapter does not support I2C\n"); 1834 return -EIO; 1835 } 1836 1837 priv = devm_drm_bridge_alloc(dev, struct tda998x_priv, bridge, &tda998x_bridge_funcs); 1838 if (IS_ERR(priv)) 1839 return PTR_ERR(priv); 1840 1841 dev_set_drvdata(dev, priv); 1842 1843 mutex_init(&priv->mutex); /* protect the page access */ 1844 mutex_init(&priv->audio_mutex); /* protect access from audio thread */ 1845 mutex_init(&priv->edid_mutex); 1846 INIT_LIST_HEAD(&priv->bridge.list); 1847 init_waitqueue_head(&priv->edid_delay_waitq); 1848 timer_setup(&priv->edid_delay_timer, tda998x_edid_delay_done, 0); 1849 INIT_WORK(&priv->detect_work, tda998x_detect_work); 1850 1851 priv->vip_cntrl_0 = VIP_CNTRL_0_SWAP_A(2) | VIP_CNTRL_0_SWAP_B(3); 1852 priv->vip_cntrl_1 = VIP_CNTRL_1_SWAP_C(0) | VIP_CNTRL_1_SWAP_D(1); 1853 priv->vip_cntrl_2 = VIP_CNTRL_2_SWAP_E(4) | VIP_CNTRL_2_SWAP_F(5); 1854 1855 /* CEC I2C address bound to TDA998x I2C addr by configuration pins */ 1856 priv->cec_addr = 0x34 + (client->addr & 0x03); 1857 priv->current_page = 0xff; 1858 priv->hdmi = client; 1859 1860 /* wake up the device: */ 1861 cec_write(priv, REG_CEC_ENAMODS, 1862 CEC_ENAMODS_EN_RXSENS | CEC_ENAMODS_EN_HDMI); 1863 1864 tda998x_reset(priv); 1865 1866 /* read version: */ 1867 rev_lo = reg_read(priv, REG_VERSION_LSB); 1868 if (rev_lo < 0) { 1869 dev_err(dev, "failed to read version: %d\n", rev_lo); 1870 ret = rev_lo; 1871 goto cancel_work; 1872 } 1873 1874 rev_hi = reg_read(priv, REG_VERSION_MSB); 1875 if (rev_hi < 0) { 1876 dev_err(dev, "failed to read version: %d\n", rev_hi); 1877 ret = rev_hi; 1878 goto cancel_work; 1879 } 1880 1881 priv->rev = rev_lo | rev_hi << 8; 1882 1883 /* mask off feature bits: */ 1884 priv->rev &= ~0x30; /* not-hdcp and not-scalar bit */ 1885 1886 switch (priv->rev) { 1887 case TDA9989N2: 1888 dev_info(dev, "found TDA9989 n2"); 1889 break; 1890 case TDA19989: 1891 dev_info(dev, "found TDA19989"); 1892 break; 1893 case TDA19989N2: 1894 dev_info(dev, "found TDA19989 n2"); 1895 break; 1896 case TDA19988: 1897 dev_info(dev, "found TDA19988"); 1898 break; 1899 default: 1900 dev_err(dev, "found unsupported device: %04x\n", priv->rev); 1901 ret = -ENXIO; 1902 goto cancel_work; 1903 } 1904 1905 /* after reset, enable DDC: */ 1906 reg_write(priv, REG_DDC_DISABLE, 0x00); 1907 1908 /* set clock on DDC channel: */ 1909 reg_write(priv, REG_TX3, 39); 1910 1911 /* if necessary, disable multi-master: */ 1912 if (priv->rev == TDA19989) 1913 reg_set(priv, REG_I2C_MASTER, I2C_MASTER_DIS_MM); 1914 1915 cec_write(priv, REG_CEC_FRO_IM_CLK_CTRL, 1916 CEC_FRO_IM_CLK_CTRL_GHOST_DIS | CEC_FRO_IM_CLK_CTRL_IMCLK_SEL); 1917 1918 /* ensure interrupts are disabled */ 1919 cec_write(priv, REG_CEC_RXSHPDINTENA, 0); 1920 1921 /* clear pending interrupts */ 1922 cec_read(priv, REG_CEC_RXSHPDINT); 1923 reg_read(priv, REG_INT_FLAGS_0); 1924 reg_read(priv, REG_INT_FLAGS_1); 1925 reg_read(priv, REG_INT_FLAGS_2); 1926 1927 /* initialize the optional IRQ */ 1928 if (client->irq) { 1929 unsigned long irq_flags; 1930 1931 /* init read EDID waitqueue and HDP work */ 1932 init_waitqueue_head(&priv->wq_edid); 1933 1934 irq_flags = 1935 irqd_get_trigger_type(irq_get_irq_data(client->irq)); 1936 1937 priv->cec_glue.irq_flags = irq_flags; 1938 1939 irq_flags |= IRQF_SHARED | IRQF_ONESHOT; 1940 ret = request_threaded_irq(client->irq, NULL, 1941 tda998x_irq_thread, irq_flags, 1942 "tda998x", priv); 1943 if (ret) { 1944 dev_err(dev, "failed to request IRQ#%u: %d\n", 1945 client->irq, ret); 1946 goto cancel_work; 1947 } 1948 1949 /* enable HPD irq */ 1950 cec_write(priv, REG_CEC_RXSHPDINTENA, CEC_RXSHPDLEV_HPD); 1951 priv->bridge.ops = DRM_BRIDGE_OP_HPD; 1952 } 1953 1954 priv->cec_notify = cec_notifier_conn_register(dev, NULL, NULL); 1955 if (!priv->cec_notify) { 1956 ret = -ENOMEM; 1957 goto free_irq; 1958 } 1959 1960 priv->cec_glue.parent = dev; 1961 priv->cec_glue.data = priv; 1962 priv->cec_glue.init = tda998x_cec_hook_init; 1963 priv->cec_glue.exit = tda998x_cec_hook_exit; 1964 priv->cec_glue.open = tda998x_cec_hook_open; 1965 priv->cec_glue.release = tda998x_cec_hook_release; 1966 1967 /* 1968 * Some TDA998x are actually two I2C devices merged onto one piece 1969 * of silicon: TDA9989 and TDA19989 combine the HDMI transmitter 1970 * with a slightly modified TDA9950 CEC device. The CEC device 1971 * is at the TDA9950 address, with the address pins strapped across 1972 * to the TDA998x address pins. Hence, it always has the same 1973 * offset. 1974 */ 1975 memset(&cec_info, 0, sizeof(cec_info)); 1976 strscpy(cec_info.type, "tda9950", sizeof(cec_info.type)); 1977 cec_info.addr = priv->cec_addr; 1978 cec_info.platform_data = &priv->cec_glue; 1979 cec_info.irq = client->irq; 1980 1981 priv->cec = i2c_new_client_device(client->adapter, &cec_info); 1982 if (IS_ERR(priv->cec)) { 1983 ret = PTR_ERR(priv->cec); 1984 goto notifier_conn_unregister; 1985 } 1986 1987 /* enable EDID read irq: */ 1988 reg_set(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 1989 1990 if (np) { 1991 /* get the device tree parameters */ 1992 ret = of_property_read_u32(np, "video-ports", &video); 1993 if (ret == 0) { 1994 priv->vip_cntrl_0 = video >> 16; 1995 priv->vip_cntrl_1 = video >> 8; 1996 priv->vip_cntrl_2 = video; 1997 } 1998 1999 ret = tda998x_get_audio_ports(priv, np); 2000 if (ret) 2001 goto unregister_dev; 2002 2003 if (priv->audio_port_enable[AUDIO_ROUTE_I2S] || 2004 priv->audio_port_enable[AUDIO_ROUTE_SPDIF]) 2005 tda998x_audio_codec_init(priv, &client->dev); 2006 } 2007 2008 #ifdef CONFIG_OF 2009 priv->bridge.of_node = dev->of_node; 2010 #endif 2011 2012 priv->bridge.ops |= DRM_BRIDGE_OP_EDID | DRM_BRIDGE_OP_DETECT; 2013 priv->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 2014 drm_bridge_add(&priv->bridge); 2015 2016 return 0; 2017 2018 unregister_dev: 2019 i2c_unregister_device(priv->cec); 2020 notifier_conn_unregister: 2021 cec_notifier_conn_unregister(priv->cec_notify); 2022 free_irq: 2023 if (client->irq) { 2024 cec_write(priv, REG_CEC_RXSHPDINTENA, 0); 2025 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 2026 free_irq(client->irq, priv); 2027 } 2028 cancel_work: 2029 timer_delete_sync(&priv->edid_delay_timer); 2030 cancel_work_sync(&priv->detect_work); 2031 return ret; 2032 } 2033 2034 static void tda998x_remove(struct i2c_client *client) 2035 { 2036 struct tda998x_priv *priv = dev_get_drvdata(&client->dev); 2037 2038 drm_bridge_remove(&priv->bridge); 2039 2040 if (priv->audio_pdev) 2041 platform_device_unregister(priv->audio_pdev); 2042 2043 i2c_unregister_device(priv->cec); 2044 2045 cec_notifier_conn_unregister(priv->cec_notify); 2046 2047 /* disable all IRQs and free the IRQ handler */ 2048 if (client->irq) { 2049 cec_write(priv, REG_CEC_RXSHPDINTENA, 0); 2050 reg_clear(priv, REG_INT_FLAGS_2, INT_FLAGS_2_EDID_BLK_RD); 2051 free_irq(priv->hdmi->irq, priv); 2052 } 2053 2054 timer_delete_sync(&priv->edid_delay_timer); 2055 cancel_work_sync(&priv->detect_work); 2056 } 2057 2058 #ifdef CONFIG_OF 2059 static const struct of_device_id tda998x_dt_ids[] = { 2060 { .compatible = "nxp,tda998x", }, 2061 { } 2062 }; 2063 MODULE_DEVICE_TABLE(of, tda998x_dt_ids); 2064 #endif 2065 2066 static const struct i2c_device_id tda998x_ids[] = { 2067 { .name = "tda998x" }, 2068 { } 2069 }; 2070 MODULE_DEVICE_TABLE(i2c, tda998x_ids); 2071 2072 static struct i2c_driver tda998x_driver = { 2073 .probe = tda998x_probe, 2074 .remove = tda998x_remove, 2075 .driver = { 2076 .name = "tda998x", 2077 .of_match_table = of_match_ptr(tda998x_dt_ids), 2078 }, 2079 .id_table = tda998x_ids, 2080 }; 2081 2082 module_i2c_driver(tda998x_driver); 2083 2084 MODULE_AUTHOR("Rob Clark <robdclark@gmail.com"); 2085 MODULE_DESCRIPTION("NXP Semiconductors TDA998X HDMI Encoder"); 2086 MODULE_LICENSE("GPL"); 2087