1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/i2c.h> 11 #include <linux/kernel.h> 12 #include <linux/math64.h> 13 #include <linux/media-bus-format.h> 14 #include <linux/minmax.h> 15 #include <linux/module.h> 16 #include <linux/regmap.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/slab.h> 19 #include <linux/units.h> 20 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_drv.h> 23 #include <drm/drm_mipi_dsi.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_panel.h> 26 #include <video/mipi_display.h> 27 #include <video/videomode.h> 28 29 /* Global (16-bit addressable) */ 30 #define TC358768_CHIPID 0x0000 31 #define TC358768_SYSCTL 0x0002 32 #define TC358768_CONFCTL 0x0004 33 #define TC358768_VSDLY 0x0006 34 #define TC358768_DATAFMT 0x0008 35 #define TC358768_GPIOEN 0x000E 36 #define TC358768_GPIODIR 0x0010 37 #define TC358768_GPIOIN 0x0012 38 #define TC358768_GPIOOUT 0x0014 39 #define TC358768_PLLCTL0 0x0016 40 #define TC358768_PLLCTL1 0x0018 41 #define TC358768_CMDBYTE 0x0022 42 #define TC358768_PP_MISC 0x0032 43 #define TC358768_DSITX_DT 0x0050 44 #define TC358768_FIFOSTATUS 0x00F8 45 46 /* Debug (16-bit addressable) */ 47 #define TC358768_VBUFCTRL 0x00E0 48 #define TC358768_DBG_WIDTH 0x00E2 49 #define TC358768_DBG_VBLANK 0x00E4 50 #define TC358768_DBG_DATA 0x00E8 51 52 /* TX PHY (32-bit addressable) */ 53 #define TC358768_CLW_DPHYCONTTX 0x0100 54 #define TC358768_D0W_DPHYCONTTX 0x0104 55 #define TC358768_D1W_DPHYCONTTX 0x0108 56 #define TC358768_D2W_DPHYCONTTX 0x010C 57 #define TC358768_D3W_DPHYCONTTX 0x0110 58 #define TC358768_CLW_CNTRL 0x0140 59 #define TC358768_D0W_CNTRL 0x0144 60 #define TC358768_D1W_CNTRL 0x0148 61 #define TC358768_D2W_CNTRL 0x014C 62 #define TC358768_D3W_CNTRL 0x0150 63 64 /* TX PPI (32-bit addressable) */ 65 #define TC358768_STARTCNTRL 0x0204 66 #define TC358768_DSITXSTATUS 0x0208 67 #define TC358768_LINEINITCNT 0x0210 68 #define TC358768_LPTXTIMECNT 0x0214 69 #define TC358768_TCLK_HEADERCNT 0x0218 70 #define TC358768_TCLK_TRAILCNT 0x021C 71 #define TC358768_THS_HEADERCNT 0x0220 72 #define TC358768_TWAKEUP 0x0224 73 #define TC358768_TCLK_POSTCNT 0x0228 74 #define TC358768_THS_TRAILCNT 0x022C 75 #define TC358768_HSTXVREGCNT 0x0230 76 #define TC358768_HSTXVREGEN 0x0234 77 #define TC358768_TXOPTIONCNTRL 0x0238 78 #define TC358768_BTACNTRL1 0x023C 79 80 /* TX CTRL (32-bit addressable) */ 81 #define TC358768_DSI_CONTROL 0x040C 82 #define TC358768_DSI_STATUS 0x0410 83 #define TC358768_DSI_INT 0x0414 84 #define TC358768_DSI_INT_ENA 0x0418 85 #define TC358768_DSICMD_RDFIFO 0x0430 86 #define TC358768_DSI_ACKERR 0x0434 87 #define TC358768_DSI_ACKERR_INTENA 0x0438 88 #define TC358768_DSI_ACKERR_HALT 0x043c 89 #define TC358768_DSI_RXERR 0x0440 90 #define TC358768_DSI_RXERR_INTENA 0x0444 91 #define TC358768_DSI_RXERR_HALT 0x0448 92 #define TC358768_DSI_ERR 0x044C 93 #define TC358768_DSI_ERR_INTENA 0x0450 94 #define TC358768_DSI_ERR_HALT 0x0454 95 #define TC358768_DSI_CONFW 0x0500 96 #define TC358768_DSI_LPCMD 0x0500 97 #define TC358768_DSI_RESET 0x0504 98 #define TC358768_DSI_INT_CLR 0x050C 99 #define TC358768_DSI_START 0x0518 100 101 /* DSITX CTRL (16-bit addressable) */ 102 #define TC358768_DSICMD_TX 0x0600 103 #define TC358768_DSICMD_TYPE 0x0602 104 #define TC358768_DSICMD_WC 0x0604 105 #define TC358768_DSICMD_WD0 0x0610 106 #define TC358768_DSICMD_WD1 0x0612 107 #define TC358768_DSICMD_WD2 0x0614 108 #define TC358768_DSICMD_WD3 0x0616 109 #define TC358768_DSI_EVENT 0x0620 110 #define TC358768_DSI_VSW 0x0622 111 #define TC358768_DSI_VBPR 0x0624 112 #define TC358768_DSI_VACT 0x0626 113 #define TC358768_DSI_HSW 0x0628 114 #define TC358768_DSI_HBPR 0x062A 115 #define TC358768_DSI_HACT 0x062C 116 117 /* TC358768_DSI_CONTROL (0x040C) register */ 118 #define TC358768_DSI_CONTROL_DIS_MODE BIT(15) 119 #define TC358768_DSI_CONTROL_TXMD BIT(7) 120 #define TC358768_DSI_CONTROL_HSCKMD BIT(5) 121 #define TC358768_DSI_CONTROL_EOTDIS BIT(0) 122 123 /* TC358768_DSI_CONFW (0x0500) register */ 124 #define TC358768_DSI_CONFW_MODE_SET (5 << 29) 125 #define TC358768_DSI_CONFW_MODE_CLR (6 << 29) 126 #define TC358768_DSI_CONFW_ADDR_DSI_CONTROL (0x3 << 24) 127 128 static const char * const tc358768_supplies[] = { 129 "vddc", "vddmipi", "vddio" 130 }; 131 132 struct tc358768_dsi_output { 133 struct mipi_dsi_device *dev; 134 struct drm_panel *panel; 135 struct drm_bridge *bridge; 136 }; 137 138 struct tc358768_priv { 139 struct device *dev; 140 struct regmap *regmap; 141 struct gpio_desc *reset_gpio; 142 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)]; 143 struct clk *refclk; 144 int enabled; 145 int error; 146 147 struct mipi_dsi_host dsi_host; 148 struct drm_bridge bridge; 149 struct tc358768_dsi_output output; 150 151 u32 pd_lines; /* number of Parallel Port Input Data Lines */ 152 u32 dsi_lanes; /* number of DSI Lanes */ 153 u32 dsi_bpp; /* number of Bits Per Pixel over DSI */ 154 155 /* Parameters for PLL programming */ 156 u32 fbd; /* PLL feedback divider */ 157 u32 prd; /* PLL input divider */ 158 u32 frs; /* PLL Freqency range for HSCK (post divider) */ 159 160 u32 dsiclk; /* pll_clk / 2 */ 161 u32 pclk; /* incoming pclk rate */ 162 }; 163 164 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host 165 *host) 166 { 167 return container_of(host, struct tc358768_priv, dsi_host); 168 } 169 170 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge 171 *bridge) 172 { 173 return container_of(bridge, struct tc358768_priv, bridge); 174 } 175 176 static int tc358768_clear_error(struct tc358768_priv *priv) 177 { 178 int ret = priv->error; 179 180 priv->error = 0; 181 return ret; 182 } 183 184 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val) 185 { 186 /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ 187 int tmpval = val; 188 size_t count = 2; 189 190 if (priv->error) 191 return; 192 193 /* 16-bit register? */ 194 if (reg < 0x100 || reg >= 0x600) 195 count = 1; 196 197 priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count); 198 } 199 200 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val) 201 { 202 size_t count = 2; 203 204 if (priv->error) 205 return; 206 207 /* 16-bit register? */ 208 if (reg < 0x100 || reg >= 0x600) { 209 *val = 0; 210 count = 1; 211 } 212 213 priv->error = regmap_bulk_read(priv->regmap, reg, val, count); 214 } 215 216 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask, 217 u32 val) 218 { 219 u32 tmp, orig; 220 221 tc358768_read(priv, reg, &orig); 222 223 if (priv->error) 224 return; 225 226 tmp = orig & ~mask; 227 tmp |= val & mask; 228 if (tmp != orig) 229 tc358768_write(priv, reg, tmp); 230 } 231 232 static int tc358768_sw_reset(struct tc358768_priv *priv) 233 { 234 /* Assert Reset */ 235 tc358768_write(priv, TC358768_SYSCTL, 1); 236 /* Release Reset, Exit Sleep */ 237 tc358768_write(priv, TC358768_SYSCTL, 0); 238 239 return tc358768_clear_error(priv); 240 } 241 242 static void tc358768_hw_enable(struct tc358768_priv *priv) 243 { 244 int ret; 245 246 if (priv->enabled) 247 return; 248 249 ret = clk_prepare_enable(priv->refclk); 250 if (ret < 0) 251 dev_err(priv->dev, "error enabling refclk (%d)\n", ret); 252 253 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 254 if (ret < 0) 255 dev_err(priv->dev, "error enabling regulators (%d)\n", ret); 256 257 if (priv->reset_gpio) 258 usleep_range(200, 300); 259 260 /* 261 * The RESX is active low (GPIO_ACTIVE_LOW). 262 * DEASSERT (value = 0) the reset_gpio to enable the chip 263 */ 264 gpiod_set_value_cansleep(priv->reset_gpio, 0); 265 266 /* wait for encoder clocks to stabilize */ 267 usleep_range(1000, 2000); 268 269 priv->enabled = true; 270 } 271 272 static void tc358768_hw_disable(struct tc358768_priv *priv) 273 { 274 int ret; 275 276 if (!priv->enabled) 277 return; 278 279 /* 280 * The RESX is active low (GPIO_ACTIVE_LOW). 281 * ASSERT (value = 1) the reset_gpio to disable the chip 282 */ 283 gpiod_set_value_cansleep(priv->reset_gpio, 1); 284 285 ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 286 priv->supplies); 287 if (ret < 0) 288 dev_err(priv->dev, "error disabling regulators (%d)\n", ret); 289 290 clk_disable_unprepare(priv->refclk); 291 292 priv->enabled = false; 293 } 294 295 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk) 296 { 297 return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp); 298 } 299 300 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk) 301 { 302 return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes); 303 } 304 305 static int tc358768_calc_pll(struct tc358768_priv *priv, 306 const struct drm_display_mode *mode, 307 bool verify_only) 308 { 309 static const u32 frs_limits[] = { 310 1000000000, 311 500000000, 312 250000000, 313 125000000, 314 62500000 315 }; 316 unsigned long refclk; 317 u32 prd, target_pll, i, max_pll, min_pll; 318 u32 frs, best_diff, best_pll, best_prd, best_fbd; 319 320 target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000); 321 322 /* pll_clk = RefClk * FBD / PRD * (1 / (2^FRS)) */ 323 324 for (i = 0; i < ARRAY_SIZE(frs_limits); i++) 325 if (target_pll >= frs_limits[i]) 326 break; 327 328 if (i == ARRAY_SIZE(frs_limits) || i == 0) 329 return -EINVAL; 330 331 frs = i - 1; 332 max_pll = frs_limits[i - 1]; 333 min_pll = frs_limits[i]; 334 335 refclk = clk_get_rate(priv->refclk); 336 337 best_diff = UINT_MAX; 338 best_pll = 0; 339 best_prd = 0; 340 best_fbd = 0; 341 342 for (prd = 1; prd <= 16; ++prd) { 343 u32 divisor = prd * (1 << frs); 344 u32 fbd; 345 346 for (fbd = 1; fbd <= 512; ++fbd) { 347 u32 pll, diff, pll_in; 348 349 pll = (u32)div_u64((u64)refclk * fbd, divisor); 350 351 if (pll >= max_pll || pll < min_pll) 352 continue; 353 354 pll_in = (u32)div_u64((u64)refclk, prd); 355 if (pll_in < 4000000) 356 continue; 357 358 diff = max(pll, target_pll) - min(pll, target_pll); 359 360 if (diff < best_diff) { 361 best_diff = diff; 362 best_pll = pll; 363 best_prd = prd; 364 best_fbd = fbd; 365 366 if (best_diff == 0) 367 goto found; 368 } 369 } 370 } 371 372 if (best_diff == UINT_MAX) { 373 dev_err(priv->dev, "could not find suitable PLL setup\n"); 374 return -EINVAL; 375 } 376 377 found: 378 if (verify_only) 379 return 0; 380 381 priv->fbd = best_fbd; 382 priv->prd = best_prd; 383 priv->frs = frs; 384 priv->dsiclk = best_pll / 2; 385 priv->pclk = mode->clock * 1000; 386 387 return 0; 388 } 389 390 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host, 391 struct mipi_dsi_device *dev) 392 { 393 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 394 struct drm_bridge *bridge; 395 struct drm_panel *panel; 396 struct device_node *ep; 397 int ret; 398 399 if (dev->lanes > 4) { 400 dev_err(priv->dev, "unsupported number of data lanes(%u)\n", 401 dev->lanes); 402 return -EINVAL; 403 } 404 405 /* 406 * tc358768 supports both Video and Pulse mode, but the driver only 407 * implements Video (event) mode currently 408 */ 409 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) { 410 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n"); 411 return -ENOTSUPP; 412 } 413 414 /* 415 * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only 416 * RGB888 is verified. 417 */ 418 if (dev->format != MIPI_DSI_FMT_RGB888) { 419 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n"); 420 return -ENOTSUPP; 421 } 422 423 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel, 424 &bridge); 425 if (ret) 426 return ret; 427 428 if (panel) { 429 bridge = drm_panel_bridge_add_typed(panel, 430 DRM_MODE_CONNECTOR_DSI); 431 if (IS_ERR(bridge)) 432 return PTR_ERR(bridge); 433 } 434 435 priv->output.dev = dev; 436 priv->output.bridge = bridge; 437 priv->output.panel = panel; 438 439 priv->dsi_lanes = dev->lanes; 440 priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format); 441 442 /* get input ep (port0/endpoint0) */ 443 ret = -EINVAL; 444 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0); 445 if (ep) { 446 ret = of_property_read_u32(ep, "bus-width", &priv->pd_lines); 447 if (ret) 448 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines); 449 450 of_node_put(ep); 451 } 452 453 if (ret) 454 priv->pd_lines = priv->dsi_bpp; 455 456 drm_bridge_add(&priv->bridge); 457 458 return 0; 459 } 460 461 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host, 462 struct mipi_dsi_device *dev) 463 { 464 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 465 466 drm_bridge_remove(&priv->bridge); 467 if (priv->output.panel) 468 drm_panel_bridge_remove(priv->output.bridge); 469 470 return 0; 471 } 472 473 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host, 474 const struct mipi_dsi_msg *msg) 475 { 476 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 477 struct mipi_dsi_packet packet; 478 int ret; 479 480 if (!priv->enabled) { 481 dev_err(priv->dev, "Bridge is not enabled\n"); 482 return -ENODEV; 483 } 484 485 if (msg->rx_len) { 486 dev_warn(priv->dev, "MIPI rx is not supported\n"); 487 return -ENOTSUPP; 488 } 489 490 if (msg->tx_len > 8) { 491 dev_warn(priv->dev, "Maximum 8 byte MIPI tx is supported\n"); 492 return -ENOTSUPP; 493 } 494 495 ret = mipi_dsi_create_packet(&packet, msg); 496 if (ret) 497 return ret; 498 499 if (mipi_dsi_packet_format_is_short(msg->type)) { 500 tc358768_write(priv, TC358768_DSICMD_TYPE, 501 (0x10 << 8) | (packet.header[0] & 0x3f)); 502 tc358768_write(priv, TC358768_DSICMD_WC, 0); 503 tc358768_write(priv, TC358768_DSICMD_WD0, 504 (packet.header[2] << 8) | packet.header[1]); 505 } else { 506 int i; 507 508 tc358768_write(priv, TC358768_DSICMD_TYPE, 509 (0x40 << 8) | (packet.header[0] & 0x3f)); 510 tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length); 511 for (i = 0; i < packet.payload_length; i += 2) { 512 u16 val = packet.payload[i]; 513 514 if (i + 1 < packet.payload_length) 515 val |= packet.payload[i + 1] << 8; 516 517 tc358768_write(priv, TC358768_DSICMD_WD0 + i, val); 518 } 519 } 520 521 /* start transfer */ 522 tc358768_write(priv, TC358768_DSICMD_TX, 1); 523 524 ret = tc358768_clear_error(priv); 525 if (ret) 526 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 527 else 528 ret = packet.size; 529 530 return ret; 531 } 532 533 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = { 534 .attach = tc358768_dsi_host_attach, 535 .detach = tc358768_dsi_host_detach, 536 .transfer = tc358768_dsi_host_transfer, 537 }; 538 539 static int tc358768_bridge_attach(struct drm_bridge *bridge, 540 enum drm_bridge_attach_flags flags) 541 { 542 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 543 544 if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) { 545 dev_err(priv->dev, "needs atomic updates support\n"); 546 return -ENOTSUPP; 547 } 548 549 return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge, 550 flags); 551 } 552 553 static enum drm_mode_status 554 tc358768_bridge_mode_valid(struct drm_bridge *bridge, 555 const struct drm_display_info *info, 556 const struct drm_display_mode *mode) 557 { 558 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 559 560 if (tc358768_calc_pll(priv, mode, true)) 561 return MODE_CLOCK_RANGE; 562 563 return MODE_OK; 564 } 565 566 static void tc358768_bridge_disable(struct drm_bridge *bridge) 567 { 568 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 569 int ret; 570 571 /* set FrmStop */ 572 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15)); 573 574 /* wait at least for one frame */ 575 msleep(50); 576 577 /* clear PP_en */ 578 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0); 579 580 /* set RstPtr */ 581 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14)); 582 583 ret = tc358768_clear_error(priv); 584 if (ret) 585 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 586 } 587 588 static void tc358768_bridge_post_disable(struct drm_bridge *bridge) 589 { 590 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 591 592 tc358768_hw_disable(priv); 593 } 594 595 static int tc358768_setup_pll(struct tc358768_priv *priv, 596 const struct drm_display_mode *mode) 597 { 598 u32 fbd, prd, frs; 599 int ret; 600 601 ret = tc358768_calc_pll(priv, mode, false); 602 if (ret) { 603 dev_err(priv->dev, "PLL calculation failed: %d\n", ret); 604 return ret; 605 } 606 607 fbd = priv->fbd; 608 prd = priv->prd; 609 frs = priv->frs; 610 611 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n", 612 clk_get_rate(priv->refclk), fbd, prd, frs); 613 dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, HSByteClk %u\n", 614 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4); 615 dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n", 616 tc358768_pll_to_pclk(priv, priv->dsiclk * 2), 617 mode->clock * 1000); 618 619 /* PRD[15:12] FBD[8:0] */ 620 tc358768_write(priv, TC358768_PLLCTL0, ((prd - 1) << 12) | (fbd - 1)); 621 622 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */ 623 tc358768_write(priv, TC358768_PLLCTL1, 624 (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0)); 625 626 /* wait for lock */ 627 usleep_range(1000, 2000); 628 629 /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */ 630 tc358768_write(priv, TC358768_PLLCTL1, 631 (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0)); 632 633 return tc358768_clear_error(priv); 634 } 635 636 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps) 637 { 638 return DIV_ROUND_UP(ns * 1000, period_ps); 639 } 640 641 static u32 tc358768_ps_to_ns(u32 ps) 642 { 643 return ps / 1000; 644 } 645 646 static u32 tc358768_dpi_to_ns(u32 val, u32 pclk) 647 { 648 return (u32)div_u64((u64)val * NANO, pclk); 649 } 650 651 /* Convert value in DPI pixel clock units to DSI byte count */ 652 static u32 tc358768_dpi_to_dsi_bytes(struct tc358768_priv *priv, u32 val) 653 { 654 u64 m = (u64)val * priv->dsiclk / 4 * priv->dsi_lanes; 655 u64 n = priv->pclk; 656 657 return (u32)div_u64(m + n - 1, n); 658 } 659 660 static u32 tc358768_dsi_bytes_to_ns(struct tc358768_priv *priv, u32 val) 661 { 662 u64 m = (u64)val * NANO; 663 u64 n = priv->dsiclk / 4 * priv->dsi_lanes; 664 665 return (u32)div_u64(m, n); 666 } 667 668 static void tc358768_bridge_pre_enable(struct drm_bridge *bridge) 669 { 670 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 671 struct mipi_dsi_device *dsi_dev = priv->output.dev; 672 unsigned long mode_flags = dsi_dev->mode_flags; 673 u32 val, val2, lptxcnt, hact, data_type; 674 s32 raw_val; 675 const struct drm_display_mode *mode; 676 u32 hsbyteclk_ps, dsiclk_ps, ui_ps; 677 u32 dsiclk, hsbyteclk; 678 int ret, i; 679 struct videomode vm; 680 struct device *dev = priv->dev; 681 /* In pixelclock units */ 682 u32 dpi_htot, dpi_data_start; 683 /* In byte units */ 684 u32 dsi_dpi_htot, dsi_dpi_data_start; 685 u32 dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp; 686 const u32 dsi_hss = 4; /* HSS is a short packet (4 bytes) */ 687 /* In hsbyteclk units */ 688 u32 dsi_vsdly; 689 const u32 internal_dly = 40; 690 691 if (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 692 dev_warn_once(dev, "Non-continuous mode unimplemented, falling back to continuous\n"); 693 mode_flags &= ~MIPI_DSI_CLOCK_NON_CONTINUOUS; 694 } 695 696 tc358768_hw_enable(priv); 697 698 ret = tc358768_sw_reset(priv); 699 if (ret) { 700 dev_err(dev, "Software reset failed: %d\n", ret); 701 tc358768_hw_disable(priv); 702 return; 703 } 704 705 mode = &bridge->encoder->crtc->state->adjusted_mode; 706 ret = tc358768_setup_pll(priv, mode); 707 if (ret) { 708 dev_err(dev, "PLL setup failed: %d\n", ret); 709 tc358768_hw_disable(priv); 710 return; 711 } 712 713 drm_display_mode_to_videomode(mode, &vm); 714 715 dsiclk = priv->dsiclk; 716 hsbyteclk = dsiclk / 4; 717 718 /* Data Format Control Register */ 719 val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ 720 switch (dsi_dev->format) { 721 case MIPI_DSI_FMT_RGB888: 722 val |= (0x3 << 4); 723 hact = vm.hactive * 3; 724 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 725 break; 726 case MIPI_DSI_FMT_RGB666: 727 val |= (0x4 << 4); 728 hact = vm.hactive * 3; 729 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 730 break; 731 732 case MIPI_DSI_FMT_RGB666_PACKED: 733 val |= (0x4 << 4) | BIT(3); 734 hact = vm.hactive * 18 / 8; 735 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 736 break; 737 738 case MIPI_DSI_FMT_RGB565: 739 val |= (0x5 << 4); 740 hact = vm.hactive * 2; 741 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 742 break; 743 default: 744 dev_err(dev, "Invalid data format (%u)\n", 745 dsi_dev->format); 746 tc358768_hw_disable(priv); 747 return; 748 } 749 750 /* 751 * There are three important things to make TC358768 work correctly, 752 * which are not trivial to manage: 753 * 754 * 1. Keep the DPI line-time and the DSI line-time as close to each 755 * other as possible. 756 * 2. TC358768 goes to LP mode after each line's active area. The DSI 757 * HFP period has to be long enough for entering and exiting LP mode. 758 * But it is not clear how to calculate this. 759 * 3. VSDly (video start delay) has to be long enough to ensure that the 760 * DSI TX does not start transmitting until we have started receiving 761 * pixel data from the DPI input. It is not clear how to calculate 762 * this either. 763 */ 764 765 dpi_htot = vm.hactive + vm.hfront_porch + vm.hsync_len + vm.hback_porch; 766 dpi_data_start = vm.hsync_len + vm.hback_porch; 767 768 dev_dbg(dev, "dpi horiz timing (pclk): %u + %u + %u + %u = %u\n", 769 vm.hsync_len, vm.hback_porch, vm.hactive, vm.hfront_porch, 770 dpi_htot); 771 772 dev_dbg(dev, "dpi horiz timing (ns): %u + %u + %u + %u = %u\n", 773 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock), 774 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock), 775 tc358768_dpi_to_ns(vm.hactive, vm.pixelclock), 776 tc358768_dpi_to_ns(vm.hfront_porch, vm.pixelclock), 777 tc358768_dpi_to_ns(dpi_htot, vm.pixelclock)); 778 779 dev_dbg(dev, "dpi data start (ns): %u + %u = %u\n", 780 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock), 781 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock), 782 tc358768_dpi_to_ns(dpi_data_start, vm.pixelclock)); 783 784 dsi_dpi_htot = tc358768_dpi_to_dsi_bytes(priv, dpi_htot); 785 dsi_dpi_data_start = tc358768_dpi_to_dsi_bytes(priv, dpi_data_start); 786 787 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 788 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, vm.hsync_len); 789 dsi_hbp = tc358768_dpi_to_dsi_bytes(priv, vm.hback_porch); 790 } else { 791 /* HBP is included in HSW in event mode */ 792 dsi_hbp = 0; 793 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, 794 vm.hsync_len + 795 vm.hback_porch); 796 797 /* 798 * The pixel packet includes the actual pixel data, and: 799 * DSI packet header = 4 bytes 800 * DCS code = 1 byte 801 * DSI packet footer = 2 bytes 802 */ 803 dsi_hact = hact + 4 + 1 + 2; 804 805 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; 806 807 /* 808 * Here we should check if HFP is long enough for entering LP 809 * and exiting LP, but it's not clear how to calculate that. 810 * Instead, this is a naive algorithm that just adjusts the HFP 811 * and HSW so that HFP is (at least) roughly 2/3 of the total 812 * blanking time. 813 */ 814 if (dsi_hfp < (dsi_hfp + dsi_hsw + dsi_hss) * 2 / 3) { 815 u32 old_hfp = dsi_hfp; 816 u32 old_hsw = dsi_hsw; 817 u32 tot = dsi_hfp + dsi_hsw + dsi_hss; 818 819 dsi_hsw = tot / 3; 820 821 /* 822 * Seems like sometimes HSW has to be divisible by num-lanes, but 823 * not always... 824 */ 825 dsi_hsw = roundup(dsi_hsw, priv->dsi_lanes); 826 827 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; 828 829 dev_dbg(dev, 830 "hfp too short, adjusting dsi hfp and dsi hsw from %u, %u to %u, %u\n", 831 old_hfp, old_hsw, dsi_hfp, dsi_hsw); 832 } 833 834 dev_dbg(dev, 835 "dsi horiz timing (bytes): %u, %u + %u + %u + %u = %u\n", 836 dsi_hss, dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp, 837 dsi_hss + dsi_hsw + dsi_hbp + dsi_hact + dsi_hfp); 838 839 dev_dbg(dev, "dsi horiz timing (ns): %u + %u + %u + %u + %u = %u\n", 840 tc358768_dsi_bytes_to_ns(priv, dsi_hss), 841 tc358768_dsi_bytes_to_ns(priv, dsi_hsw), 842 tc358768_dsi_bytes_to_ns(priv, dsi_hbp), 843 tc358768_dsi_bytes_to_ns(priv, dsi_hact), 844 tc358768_dsi_bytes_to_ns(priv, dsi_hfp), 845 tc358768_dsi_bytes_to_ns(priv, dsi_hss + dsi_hsw + 846 dsi_hbp + dsi_hact + dsi_hfp)); 847 } 848 849 /* VSDly calculation */ 850 851 /* Start with the HW internal delay */ 852 dsi_vsdly = internal_dly; 853 854 /* Convert to byte units as the other variables are in byte units */ 855 dsi_vsdly *= priv->dsi_lanes; 856 857 /* Do we need more delay, in addition to the internal? */ 858 if (dsi_dpi_data_start > dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp) { 859 dsi_vsdly = dsi_dpi_data_start - dsi_hss - dsi_hsw - dsi_hbp; 860 dsi_vsdly = roundup(dsi_vsdly, priv->dsi_lanes); 861 } 862 863 dev_dbg(dev, "dsi data start (bytes) %u + %u + %u + %u = %u\n", 864 dsi_vsdly, dsi_hss, dsi_hsw, dsi_hbp, 865 dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp); 866 867 dev_dbg(dev, "dsi data start (ns) %u + %u + %u + %u = %u\n", 868 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly), 869 tc358768_dsi_bytes_to_ns(priv, dsi_hss), 870 tc358768_dsi_bytes_to_ns(priv, dsi_hsw), 871 tc358768_dsi_bytes_to_ns(priv, dsi_hbp), 872 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp)); 873 874 /* Convert back to hsbyteclk */ 875 dsi_vsdly /= priv->dsi_lanes; 876 877 /* 878 * The docs say that there is an internal delay of 40 cycles. 879 * However, we get underflows if we follow that rule. If we 880 * instead ignore the internal delay, things work. So either 881 * the docs are wrong or the calculations are wrong. 882 * 883 * As a temporary fix, add the internal delay here, to counter 884 * the subtraction when writing the register. 885 */ 886 dsi_vsdly += internal_dly; 887 888 /* Clamp to the register max */ 889 if (dsi_vsdly - internal_dly > 0x3ff) { 890 dev_warn(dev, "VSDly too high, underflows likely\n"); 891 dsi_vsdly = 0x3ff + internal_dly; 892 } 893 894 /* VSDly[9:0] */ 895 tc358768_write(priv, TC358768_VSDLY, dsi_vsdly - internal_dly); 896 897 tc358768_write(priv, TC358768_DATAFMT, val); 898 tc358768_write(priv, TC358768_DSITX_DT, data_type); 899 900 /* Enable D-PHY (HiZ->LP11) */ 901 tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000); 902 /* Enable lanes */ 903 for (i = 0; i < dsi_dev->lanes; i++) 904 tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000); 905 906 /* DSI Timings */ 907 hsbyteclk_ps = (u32)div_u64(PICO, hsbyteclk); 908 dsiclk_ps = (u32)div_u64(PICO, dsiclk); 909 ui_ps = dsiclk_ps / 2; 910 dev_dbg(dev, "dsiclk: %u ps, ui %u ps, hsbyteclk %u ps\n", dsiclk_ps, 911 ui_ps, hsbyteclk_ps); 912 913 /* LP11 > 100us for D-PHY Rx Init */ 914 val = tc358768_ns_to_cnt(100 * 1000, hsbyteclk_ps) - 1; 915 dev_dbg(dev, "LINEINITCNT: %u\n", val); 916 tc358768_write(priv, TC358768_LINEINITCNT, val); 917 918 /* LPTimeCnt > 50ns */ 919 val = tc358768_ns_to_cnt(50, hsbyteclk_ps) - 1; 920 lptxcnt = val; 921 dev_dbg(dev, "LPTXTIMECNT: %u\n", val); 922 tc358768_write(priv, TC358768_LPTXTIMECNT, val); 923 924 /* 38ns < TCLK_PREPARE < 95ns */ 925 val = tc358768_ns_to_cnt(65, hsbyteclk_ps) - 1; 926 dev_dbg(dev, "TCLK_PREPARECNT %u\n", val); 927 /* TCLK_PREPARE + TCLK_ZERO > 300ns */ 928 val2 = tc358768_ns_to_cnt(300 - tc358768_ps_to_ns(2 * ui_ps), 929 hsbyteclk_ps) - 2; 930 dev_dbg(dev, "TCLK_ZEROCNT %u\n", val2); 931 val |= val2 << 8; 932 tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); 933 934 /* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */ 935 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(2 * ui_ps), hsbyteclk_ps) - 5; 936 val = clamp(raw_val, 0, 127); 937 dev_dbg(dev, "TCLK_TRAILCNT: %u\n", val); 938 tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); 939 940 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ 941 val = 50 + tc358768_ps_to_ns(4 * ui_ps); 942 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) - 1; 943 dev_dbg(dev, "THS_PREPARECNT %u\n", val); 944 /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ 945 raw_val = tc358768_ns_to_cnt(145 - tc358768_ps_to_ns(3 * ui_ps), hsbyteclk_ps) - 10; 946 val2 = clamp(raw_val, 0, 127); 947 dev_dbg(dev, "THS_ZEROCNT %u\n", val2); 948 val |= val2 << 8; 949 tc358768_write(priv, TC358768_THS_HEADERCNT, val); 950 951 /* TWAKEUP > 1ms in lptxcnt steps */ 952 val = tc358768_ns_to_cnt(1020000, hsbyteclk_ps); 953 val = val / (lptxcnt + 1) - 1; 954 dev_dbg(dev, "TWAKEUP: %u\n", val); 955 tc358768_write(priv, TC358768_TWAKEUP, val); 956 957 /* TCLK_POSTCNT > 60ns + 52*UI */ 958 val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(52 * ui_ps), 959 hsbyteclk_ps) - 3; 960 dev_dbg(dev, "TCLK_POSTCNT: %u\n", val); 961 tc358768_write(priv, TC358768_TCLK_POSTCNT, val); 962 963 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ 964 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(18 * ui_ps), 965 hsbyteclk_ps) - 4; 966 val = clamp(raw_val, 0, 15); 967 dev_dbg(dev, "THS_TRAILCNT: %u\n", val); 968 tc358768_write(priv, TC358768_THS_TRAILCNT, val); 969 970 val = BIT(0); 971 for (i = 0; i < dsi_dev->lanes; i++) 972 val |= BIT(i + 1); 973 tc358768_write(priv, TC358768_HSTXVREGEN, val); 974 975 tc358768_write(priv, TC358768_TXOPTIONCNTRL, 976 (mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); 977 978 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ 979 val = tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4); 980 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) / 4 - 1; 981 dev_dbg(dev, "TXTAGOCNT: %u\n", val); 982 val2 = tc358768_ns_to_cnt(tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps), 983 hsbyteclk_ps) - 2; 984 dev_dbg(dev, "RXTASURECNT: %u\n", val2); 985 val = val << 16 | val2; 986 tc358768_write(priv, TC358768_BTACNTRL1, val); 987 988 /* START[0] */ 989 tc358768_write(priv, TC358768_STARTCNTRL, 1); 990 991 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 992 /* Set pulse mode */ 993 tc358768_write(priv, TC358768_DSI_EVENT, 0); 994 995 /* vact */ 996 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); 997 998 /* vsw */ 999 tc358768_write(priv, TC358768_DSI_VSW, vm.vsync_len); 1000 1001 /* vbp */ 1002 tc358768_write(priv, TC358768_DSI_VBPR, vm.vback_porch); 1003 } else { 1004 /* Set event mode */ 1005 tc358768_write(priv, TC358768_DSI_EVENT, 1); 1006 1007 /* vact */ 1008 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); 1009 1010 /* vsw (+ vbp) */ 1011 tc358768_write(priv, TC358768_DSI_VSW, 1012 vm.vsync_len + vm.vback_porch); 1013 1014 /* vbp (not used in event mode) */ 1015 tc358768_write(priv, TC358768_DSI_VBPR, 0); 1016 } 1017 1018 /* hsw (bytes) */ 1019 tc358768_write(priv, TC358768_DSI_HSW, dsi_hsw); 1020 1021 /* hbp (bytes) */ 1022 tc358768_write(priv, TC358768_DSI_HBPR, dsi_hbp); 1023 1024 /* hact (bytes) */ 1025 tc358768_write(priv, TC358768_DSI_HACT, hact); 1026 1027 /* VSYNC polarity */ 1028 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), 1029 (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0); 1030 1031 /* HSYNC polarity */ 1032 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), 1033 (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0); 1034 1035 /* Start DSI Tx */ 1036 tc358768_write(priv, TC358768_DSI_START, 0x1); 1037 1038 /* Configure DSI_Control register */ 1039 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 1040 val |= TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD | 1041 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS; 1042 tc358768_write(priv, TC358768_DSI_CONFW, val); 1043 1044 val = TC358768_DSI_CONFW_MODE_SET | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 1045 val |= (dsi_dev->lanes - 1) << 1; 1046 1047 val |= TC358768_DSI_CONTROL_TXMD; 1048 1049 if (!(mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 1050 val |= TC358768_DSI_CONTROL_HSCKMD; 1051 1052 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 1053 val |= TC358768_DSI_CONTROL_EOTDIS; 1054 1055 tc358768_write(priv, TC358768_DSI_CONFW, val); 1056 1057 val = TC358768_DSI_CONFW_MODE_CLR | TC358768_DSI_CONFW_ADDR_DSI_CONTROL; 1058 val |= TC358768_DSI_CONTROL_DIS_MODE; /* DSI mode */ 1059 tc358768_write(priv, TC358768_DSI_CONFW, val); 1060 1061 ret = tc358768_clear_error(priv); 1062 if (ret) { 1063 dev_err(dev, "Bridge pre_enable failed: %d\n", ret); 1064 tc358768_bridge_disable(bridge); 1065 tc358768_bridge_post_disable(bridge); 1066 } 1067 } 1068 1069 static void tc358768_bridge_enable(struct drm_bridge *bridge) 1070 { 1071 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 1072 int ret; 1073 1074 if (!priv->enabled) { 1075 dev_err(priv->dev, "Bridge is not enabled\n"); 1076 return; 1077 } 1078 1079 /* clear FrmStop and RstPtr */ 1080 tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0); 1081 1082 /* set PP_en */ 1083 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6)); 1084 1085 ret = tc358768_clear_error(priv); 1086 if (ret) { 1087 dev_err(priv->dev, "Bridge enable failed: %d\n", ret); 1088 tc358768_bridge_disable(bridge); 1089 tc358768_bridge_post_disable(bridge); 1090 } 1091 } 1092 1093 #define MAX_INPUT_SEL_FORMATS 1 1094 1095 static u32 * 1096 tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 1097 struct drm_bridge_state *bridge_state, 1098 struct drm_crtc_state *crtc_state, 1099 struct drm_connector_state *conn_state, 1100 u32 output_fmt, 1101 unsigned int *num_input_fmts) 1102 { 1103 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 1104 u32 *input_fmts; 1105 1106 *num_input_fmts = 0; 1107 1108 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 1109 GFP_KERNEL); 1110 if (!input_fmts) 1111 return NULL; 1112 1113 switch (priv->pd_lines) { 1114 case 16: 1115 input_fmts[0] = MEDIA_BUS_FMT_RGB565_1X16; 1116 break; 1117 case 18: 1118 input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X18; 1119 break; 1120 default: 1121 case 24: 1122 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 1123 break; 1124 } 1125 1126 *num_input_fmts = MAX_INPUT_SEL_FORMATS; 1127 1128 return input_fmts; 1129 } 1130 1131 static bool tc358768_mode_fixup(struct drm_bridge *bridge, 1132 const struct drm_display_mode *mode, 1133 struct drm_display_mode *adjusted_mode) 1134 { 1135 /* Default to positive sync */ 1136 1137 if (!(adjusted_mode->flags & 1138 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 1139 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; 1140 1141 if (!(adjusted_mode->flags & 1142 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 1143 adjusted_mode->flags |= DRM_MODE_FLAG_PVSYNC; 1144 1145 return true; 1146 } 1147 1148 static const struct drm_bridge_funcs tc358768_bridge_funcs = { 1149 .attach = tc358768_bridge_attach, 1150 .mode_valid = tc358768_bridge_mode_valid, 1151 .mode_fixup = tc358768_mode_fixup, 1152 .pre_enable = tc358768_bridge_pre_enable, 1153 .enable = tc358768_bridge_enable, 1154 .disable = tc358768_bridge_disable, 1155 .post_disable = tc358768_bridge_post_disable, 1156 1157 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1158 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1159 .atomic_reset = drm_atomic_helper_bridge_reset, 1160 .atomic_get_input_bus_fmts = tc358768_atomic_get_input_bus_fmts, 1161 }; 1162 1163 static const struct drm_bridge_timings default_tc358768_timings = { 1164 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 1165 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE 1166 | DRM_BUS_FLAG_DE_HIGH, 1167 }; 1168 1169 static bool tc358768_is_reserved_reg(unsigned int reg) 1170 { 1171 switch (reg) { 1172 case 0x114 ... 0x13f: 1173 case 0x200: 1174 case 0x20c: 1175 case 0x400 ... 0x408: 1176 case 0x41c ... 0x42f: 1177 return true; 1178 default: 1179 return false; 1180 } 1181 } 1182 1183 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg) 1184 { 1185 if (tc358768_is_reserved_reg(reg)) 1186 return false; 1187 1188 switch (reg) { 1189 case TC358768_CHIPID: 1190 case TC358768_FIFOSTATUS: 1191 case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2): 1192 case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2): 1193 case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2): 1194 return false; 1195 default: 1196 return true; 1197 } 1198 } 1199 1200 static bool tc358768_readable_reg(struct device *dev, unsigned int reg) 1201 { 1202 if (tc358768_is_reserved_reg(reg)) 1203 return false; 1204 1205 switch (reg) { 1206 case TC358768_STARTCNTRL: 1207 case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2): 1208 case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2): 1209 case TC358768_DSI_START ... (TC358768_DSI_START + 2): 1210 case TC358768_DBG_DATA: 1211 return false; 1212 default: 1213 return true; 1214 } 1215 } 1216 1217 static const struct regmap_config tc358768_regmap_config = { 1218 .name = "tc358768", 1219 .reg_bits = 16, 1220 .val_bits = 16, 1221 .max_register = TC358768_DSI_HACT, 1222 .cache_type = REGCACHE_NONE, 1223 .writeable_reg = tc358768_writeable_reg, 1224 .readable_reg = tc358768_readable_reg, 1225 .reg_format_endian = REGMAP_ENDIAN_BIG, 1226 .val_format_endian = REGMAP_ENDIAN_BIG, 1227 }; 1228 1229 static const struct i2c_device_id tc358768_i2c_ids[] = { 1230 { "tc358768", 0 }, 1231 { "tc358778", 0 }, 1232 { } 1233 }; 1234 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids); 1235 1236 static const struct of_device_id tc358768_of_ids[] = { 1237 { .compatible = "toshiba,tc358768", }, 1238 { .compatible = "toshiba,tc358778", }, 1239 { } 1240 }; 1241 MODULE_DEVICE_TABLE(of, tc358768_of_ids); 1242 1243 static int tc358768_get_regulators(struct tc358768_priv *priv) 1244 { 1245 int i, ret; 1246 1247 for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i) 1248 priv->supplies[i].supply = tc358768_supplies[i]; 1249 1250 ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies), 1251 priv->supplies); 1252 if (ret < 0) 1253 dev_err(priv->dev, "failed to get regulators: %d\n", ret); 1254 1255 return ret; 1256 } 1257 1258 static int tc358768_i2c_probe(struct i2c_client *client) 1259 { 1260 struct tc358768_priv *priv; 1261 struct device *dev = &client->dev; 1262 struct device_node *np = dev->of_node; 1263 int ret; 1264 1265 if (!np) 1266 return -ENODEV; 1267 1268 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1269 if (!priv) 1270 return -ENOMEM; 1271 1272 dev_set_drvdata(dev, priv); 1273 priv->dev = dev; 1274 1275 ret = tc358768_get_regulators(priv); 1276 if (ret) 1277 return ret; 1278 1279 priv->refclk = devm_clk_get(dev, "refclk"); 1280 if (IS_ERR(priv->refclk)) 1281 return PTR_ERR(priv->refclk); 1282 1283 /* 1284 * RESX is low active, to disable tc358768 initially (keep in reset) 1285 * the gpio line must be LOW. This is the ASSERTED state of 1286 * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED). 1287 */ 1288 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1289 GPIOD_OUT_HIGH); 1290 if (IS_ERR(priv->reset_gpio)) 1291 return PTR_ERR(priv->reset_gpio); 1292 1293 priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config); 1294 if (IS_ERR(priv->regmap)) { 1295 dev_err(dev, "Failed to init regmap\n"); 1296 return PTR_ERR(priv->regmap); 1297 } 1298 1299 priv->dsi_host.dev = dev; 1300 priv->dsi_host.ops = &tc358768_dsi_host_ops; 1301 1302 priv->bridge.funcs = &tc358768_bridge_funcs; 1303 priv->bridge.timings = &default_tc358768_timings; 1304 priv->bridge.of_node = np; 1305 1306 i2c_set_clientdata(client, priv); 1307 1308 return mipi_dsi_host_register(&priv->dsi_host); 1309 } 1310 1311 static void tc358768_i2c_remove(struct i2c_client *client) 1312 { 1313 struct tc358768_priv *priv = i2c_get_clientdata(client); 1314 1315 mipi_dsi_host_unregister(&priv->dsi_host); 1316 } 1317 1318 static struct i2c_driver tc358768_driver = { 1319 .driver = { 1320 .name = "tc358768", 1321 .of_match_table = tc358768_of_ids, 1322 }, 1323 .id_table = tc358768_i2c_ids, 1324 .probe = tc358768_i2c_probe, 1325 .remove = tc358768_i2c_remove, 1326 }; 1327 module_i2c_driver(tc358768_driver); 1328 1329 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); 1330 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge"); 1331 MODULE_LICENSE("GPL v2"); 1332