1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/i2c.h> 11 #include <linux/kernel.h> 12 #include <linux/math64.h> 13 #include <linux/media-bus-format.h> 14 #include <linux/minmax.h> 15 #include <linux/module.h> 16 #include <linux/regmap.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/slab.h> 19 #include <linux/units.h> 20 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_drv.h> 23 #include <drm/drm_mipi_dsi.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_panel.h> 26 #include <video/mipi_display.h> 27 #include <video/videomode.h> 28 29 /* Global (16-bit addressable) */ 30 #define TC358768_CHIPID 0x0000 31 #define TC358768_SYSCTL 0x0002 32 #define TC358768_CONFCTL 0x0004 33 #define TC358768_VSDLY 0x0006 34 #define TC358768_DATAFMT 0x0008 35 #define TC358768_GPIOEN 0x000E 36 #define TC358768_GPIODIR 0x0010 37 #define TC358768_GPIOIN 0x0012 38 #define TC358768_GPIOOUT 0x0014 39 #define TC358768_PLLCTL0 0x0016 40 #define TC358768_PLLCTL1 0x0018 41 #define TC358768_CMDBYTE 0x0022 42 #define TC358768_PP_MISC 0x0032 43 #define TC358768_DSITX_DT 0x0050 44 #define TC358768_FIFOSTATUS 0x00F8 45 46 /* Debug (16-bit addressable) */ 47 #define TC358768_VBUFCTRL 0x00E0 48 #define TC358768_VBUFCTRL_VBUF_EN BIT(15) 49 #define TC358768_VBUFCTRL_TX_EN BIT(14) 50 #define TC358768_VBUFCTRL_MASK BIT(13) 51 #define TC358768_DBG_WIDTH 0x00E2 52 #define TC358768_DBG_VBLANK 0x00E4 53 #define TC358768_DBG_DATA 0x00E8 54 55 /* TX PHY (32-bit addressable) */ 56 #define TC358768_CLW_DPHYCONTTX 0x0100 57 #define TC358768_D0W_DPHYCONTTX 0x0104 58 #define TC358768_D1W_DPHYCONTTX 0x0108 59 #define TC358768_D2W_DPHYCONTTX 0x010C 60 #define TC358768_D3W_DPHYCONTTX 0x0110 61 #define TC358768_CLW_CNTRL 0x0140 62 #define TC358768_D0W_CNTRL 0x0144 63 #define TC358768_D1W_CNTRL 0x0148 64 #define TC358768_D2W_CNTRL 0x014C 65 #define TC358768_D3W_CNTRL 0x0150 66 67 /* TX PPI (32-bit addressable) */ 68 #define TC358768_STARTCNTRL 0x0204 69 #define TC358768_DSITXSTATUS 0x0208 70 #define TC358768_LINEINITCNT 0x0210 71 #define TC358768_LPTXTIMECNT 0x0214 72 #define TC358768_TCLK_HEADERCNT 0x0218 73 #define TC358768_TCLK_TRAILCNT 0x021C 74 #define TC358768_THS_HEADERCNT 0x0220 75 #define TC358768_TWAKEUP 0x0224 76 #define TC358768_TCLK_POSTCNT 0x0228 77 #define TC358768_THS_TRAILCNT 0x022C 78 #define TC358768_HSTXVREGCNT 0x0230 79 #define TC358768_HSTXVREGEN 0x0234 80 #define TC358768_TXOPTIONCNTRL 0x0238 81 #define TC358768_BTACNTRL1 0x023C 82 83 /* TX CTRL (32-bit addressable) */ 84 #define TC358768_DSI_CONTROL 0x040C 85 #define TC358768_DSI_STATUS 0x0410 86 #define TC358768_DSI_INT 0x0414 87 #define TC358768_DSI_INT_ENA 0x0418 88 #define TC358768_DSICMD_RDFIFO 0x0430 89 #define TC358768_DSI_ACKERR 0x0434 90 #define TC358768_DSI_ACKERR_INTENA 0x0438 91 #define TC358768_DSI_ACKERR_HALT 0x043c 92 #define TC358768_DSI_RXERR 0x0440 93 #define TC358768_DSI_RXERR_INTENA 0x0444 94 #define TC358768_DSI_RXERR_HALT 0x0448 95 #define TC358768_DSI_ERR 0x044C 96 #define TC358768_DSI_ERR_INTENA 0x0450 97 #define TC358768_DSI_ERR_HALT 0x0454 98 #define TC358768_DSI_CONFW 0x0500 99 #define TC358768_DSI_LPCMD 0x0500 100 #define TC358768_DSI_RESET 0x0504 101 #define TC358768_DSI_INT_CLR 0x050C 102 #define TC358768_DSI_START 0x0518 103 104 /* DSITX CTRL (16-bit addressable) */ 105 #define TC358768_DSICMD_TX 0x0600 106 #define TC358768_DSICMD_TYPE 0x0602 107 #define TC358768_DSICMD_WC 0x0604 108 #define TC358768_DSICMD_WD0 0x0610 109 #define TC358768_DSICMD_WD1 0x0612 110 #define TC358768_DSICMD_WD2 0x0614 111 #define TC358768_DSICMD_WD3 0x0616 112 #define TC358768_DSI_EVENT 0x0620 113 #define TC358768_DSI_VSW 0x0622 114 #define TC358768_DSI_VBPR 0x0624 115 #define TC358768_DSI_VACT 0x0626 116 #define TC358768_DSI_HSW 0x0628 117 #define TC358768_DSI_HBPR 0x062A 118 #define TC358768_DSI_HACT 0x062C 119 120 /* TC358768_DSI_CONTROL (0x040C) register */ 121 #define TC358768_DSI_CONTROL_DSI_MODE BIT(15) 122 #define TC358768_DSI_CONTROL_TXMD BIT(7) 123 #define TC358768_DSI_CONTROL_HSCKMD BIT(5) 124 #define TC358768_DSI_CONTROL_EOTDIS BIT(0) 125 126 /* TC358768_DSI_CONFW (0x0500) register */ 127 #define TC358768_DSI_CONFW_MODE_SET (5 << 29) 128 #define TC358768_DSI_CONFW_MODE_CLR (6 << 29) 129 #define TC358768_DSI_CONFW_ADDR(x) ((x) << 24) 130 131 /* TC358768_DSICMD_TX (0x0600) register */ 132 #define TC358768_DSI_CMDTX_DC_START BIT(0) 133 134 static const char * const tc358768_supplies[] = { 135 "vddc", "vddmipi", "vddio" 136 }; 137 138 struct tc358768_dsi_output { 139 struct mipi_dsi_device *dev; 140 struct drm_panel *panel; 141 struct drm_bridge *bridge; 142 }; 143 144 struct tc358768_priv { 145 struct device *dev; 146 struct regmap *regmap; 147 struct gpio_desc *reset_gpio; 148 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)]; 149 struct clk *refclk; 150 int enabled; 151 int error; 152 153 struct mipi_dsi_host dsi_host; 154 struct drm_bridge bridge; 155 struct tc358768_dsi_output output; 156 157 u32 pd_lines; /* number of Parallel Port Input Data Lines */ 158 u32 dsi_lanes; /* number of DSI Lanes */ 159 u32 dsi_bpp; /* number of Bits Per Pixel over DSI */ 160 161 /* Parameters for PLL programming */ 162 u32 fbd; /* PLL feedback divider */ 163 u32 prd; /* PLL input divider */ 164 u32 frs; /* PLL Freqency range for HSCK (post divider) */ 165 166 u32 dsiclk; /* pll_clk / 2 */ 167 u32 pclk; /* incoming pclk rate */ 168 }; 169 170 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host 171 *host) 172 { 173 return container_of(host, struct tc358768_priv, dsi_host); 174 } 175 176 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge 177 *bridge) 178 { 179 return container_of(bridge, struct tc358768_priv, bridge); 180 } 181 182 static int tc358768_clear_error(struct tc358768_priv *priv) 183 { 184 int ret = priv->error; 185 186 priv->error = 0; 187 return ret; 188 } 189 190 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val) 191 { 192 /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ 193 int tmpval = val; 194 size_t count = 2; 195 196 if (priv->error) 197 return; 198 199 /* 16-bit register? */ 200 if (reg < 0x100 || reg >= 0x600) 201 count = 1; 202 203 priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count); 204 } 205 206 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val) 207 { 208 size_t count = 2; 209 210 if (priv->error) 211 return; 212 213 /* 16-bit register? */ 214 if (reg < 0x100 || reg >= 0x600) { 215 *val = 0; 216 count = 1; 217 } 218 219 priv->error = regmap_bulk_read(priv->regmap, reg, val, count); 220 } 221 222 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask, 223 u32 val) 224 { 225 u32 tmp, orig; 226 227 tc358768_read(priv, reg, &orig); 228 229 if (priv->error) 230 return; 231 232 tmp = orig & ~mask; 233 tmp |= val & mask; 234 if (tmp != orig) 235 tc358768_write(priv, reg, tmp); 236 } 237 238 static void tc358768_confw_update_bits(struct tc358768_priv *priv, u16 reg, 239 u16 mask, u16 val) 240 { 241 u8 confw_addr; 242 u32 confw_val; 243 244 switch (reg) { 245 case TC358768_DSI_CONTROL: 246 confw_addr = 0x3; 247 break; 248 default: 249 priv->error = -EINVAL; 250 return; 251 } 252 253 if (mask != val) { 254 confw_val = TC358768_DSI_CONFW_MODE_CLR | 255 TC358768_DSI_CONFW_ADDR(confw_addr) | 256 mask; 257 tc358768_write(priv, TC358768_DSI_CONFW, confw_val); 258 } 259 260 if (val & mask) { 261 confw_val = TC358768_DSI_CONFW_MODE_SET | 262 TC358768_DSI_CONFW_ADDR(confw_addr) | 263 (val & mask); 264 tc358768_write(priv, TC358768_DSI_CONFW, confw_val); 265 } 266 } 267 268 static void tc358768_dsicmd_tx(struct tc358768_priv *priv) 269 { 270 u32 val; 271 272 /* start transfer */ 273 tc358768_write(priv, TC358768_DSICMD_TX, TC358768_DSI_CMDTX_DC_START); 274 if (priv->error) 275 return; 276 277 /* wait transfer completion */ 278 priv->error = regmap_read_poll_timeout(priv->regmap, TC358768_DSICMD_TX, val, 279 (val & TC358768_DSI_CMDTX_DC_START) == 0, 280 100, 100000); 281 } 282 283 static int tc358768_sw_reset(struct tc358768_priv *priv) 284 { 285 /* Assert Reset */ 286 tc358768_write(priv, TC358768_SYSCTL, 1); 287 /* Release Reset, Exit Sleep */ 288 tc358768_write(priv, TC358768_SYSCTL, 0); 289 290 return tc358768_clear_error(priv); 291 } 292 293 static void tc358768_hw_enable(struct tc358768_priv *priv) 294 { 295 int ret; 296 297 if (priv->enabled) 298 return; 299 300 ret = clk_prepare_enable(priv->refclk); 301 if (ret < 0) 302 dev_err(priv->dev, "error enabling refclk (%d)\n", ret); 303 304 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 305 if (ret < 0) 306 dev_err(priv->dev, "error enabling regulators (%d)\n", ret); 307 308 if (priv->reset_gpio) 309 usleep_range(200, 300); 310 311 /* 312 * The RESX is active low (GPIO_ACTIVE_LOW). 313 * DEASSERT (value = 0) the reset_gpio to enable the chip 314 */ 315 gpiod_set_value_cansleep(priv->reset_gpio, 0); 316 317 /* wait for encoder clocks to stabilize */ 318 usleep_range(1000, 2000); 319 320 priv->enabled = true; 321 } 322 323 static void tc358768_hw_disable(struct tc358768_priv *priv) 324 { 325 int ret; 326 327 if (!priv->enabled) 328 return; 329 330 /* 331 * The RESX is active low (GPIO_ACTIVE_LOW). 332 * ASSERT (value = 1) the reset_gpio to disable the chip 333 */ 334 gpiod_set_value_cansleep(priv->reset_gpio, 1); 335 336 ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 337 priv->supplies); 338 if (ret < 0) 339 dev_err(priv->dev, "error disabling regulators (%d)\n", ret); 340 341 clk_disable_unprepare(priv->refclk); 342 343 priv->enabled = false; 344 } 345 346 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk) 347 { 348 return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp); 349 } 350 351 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk) 352 { 353 return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes); 354 } 355 356 static int tc358768_calc_pll(struct tc358768_priv *priv, 357 const struct drm_display_mode *mode, 358 bool verify_only) 359 { 360 static const u32 frs_limits[] = { 361 1000000000, 362 500000000, 363 250000000, 364 125000000, 365 62500000 366 }; 367 unsigned long refclk; 368 u32 prd, target_pll, i, max_pll, min_pll; 369 u32 frs, best_diff, best_pll, best_prd, best_fbd; 370 371 target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000); 372 373 /* pll_clk = RefClk * FBD / PRD * (1 / (2^FRS)) */ 374 375 for (i = 0; i < ARRAY_SIZE(frs_limits); i++) 376 if (target_pll >= frs_limits[i]) 377 break; 378 379 if (i == ARRAY_SIZE(frs_limits) || i == 0) 380 return -EINVAL; 381 382 frs = i - 1; 383 max_pll = frs_limits[i - 1]; 384 min_pll = frs_limits[i]; 385 386 refclk = clk_get_rate(priv->refclk); 387 388 best_diff = UINT_MAX; 389 best_pll = 0; 390 best_prd = 0; 391 best_fbd = 0; 392 393 for (prd = 1; prd <= 16; ++prd) { 394 u32 divisor = prd * (1 << frs); 395 u32 fbd; 396 397 for (fbd = 1; fbd <= 512; ++fbd) { 398 u32 pll, diff, pll_in; 399 400 pll = (u32)div_u64((u64)refclk * fbd, divisor); 401 402 if (pll >= max_pll || pll < min_pll) 403 continue; 404 405 pll_in = (u32)div_u64((u64)refclk, prd); 406 if (pll_in < 4000000) 407 continue; 408 409 diff = max(pll, target_pll) - min(pll, target_pll); 410 411 if (diff < best_diff) { 412 best_diff = diff; 413 best_pll = pll; 414 best_prd = prd; 415 best_fbd = fbd; 416 417 if (best_diff == 0) 418 goto found; 419 } 420 } 421 } 422 423 if (best_diff == UINT_MAX) { 424 dev_err(priv->dev, "could not find suitable PLL setup\n"); 425 return -EINVAL; 426 } 427 428 found: 429 if (verify_only) 430 return 0; 431 432 priv->fbd = best_fbd; 433 priv->prd = best_prd; 434 priv->frs = frs; 435 priv->dsiclk = best_pll / 2; 436 priv->pclk = mode->clock * 1000; 437 438 return 0; 439 } 440 441 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host, 442 struct mipi_dsi_device *dev) 443 { 444 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 445 struct drm_bridge *bridge; 446 struct drm_panel *panel; 447 struct device_node *ep; 448 int ret; 449 450 if (dev->lanes > 4) { 451 dev_err(priv->dev, "unsupported number of data lanes(%u)\n", 452 dev->lanes); 453 return -EINVAL; 454 } 455 456 /* 457 * tc358768 supports both Video and Pulse mode, but the driver only 458 * implements Video (event) mode currently 459 */ 460 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) { 461 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n"); 462 return -ENOTSUPP; 463 } 464 465 /* 466 * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only 467 * RGB888 is verified. 468 */ 469 if (dev->format != MIPI_DSI_FMT_RGB888) { 470 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n"); 471 return -ENOTSUPP; 472 } 473 474 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel, 475 &bridge); 476 if (ret) 477 return ret; 478 479 if (panel) { 480 bridge = drm_panel_bridge_add_typed(panel, 481 DRM_MODE_CONNECTOR_DSI); 482 if (IS_ERR(bridge)) 483 return PTR_ERR(bridge); 484 485 bridge->pre_enable_prev_first = true; 486 } 487 488 priv->output.dev = dev; 489 priv->output.bridge = bridge; 490 priv->output.panel = panel; 491 492 priv->dsi_lanes = dev->lanes; 493 priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format); 494 495 /* get input ep (port0/endpoint0) */ 496 ret = -EINVAL; 497 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0); 498 if (ep) { 499 ret = of_property_read_u32(ep, "bus-width", &priv->pd_lines); 500 if (ret) 501 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines); 502 503 of_node_put(ep); 504 } 505 506 if (ret) 507 priv->pd_lines = priv->dsi_bpp; 508 509 drm_bridge_add(&priv->bridge); 510 511 return 0; 512 } 513 514 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host, 515 struct mipi_dsi_device *dev) 516 { 517 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 518 519 drm_bridge_remove(&priv->bridge); 520 if (priv->output.panel) 521 drm_panel_bridge_remove(priv->output.bridge); 522 523 return 0; 524 } 525 526 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host, 527 const struct mipi_dsi_msg *msg) 528 { 529 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 530 struct mipi_dsi_packet packet; 531 int ret; 532 533 if (!priv->enabled) { 534 dev_err(priv->dev, "Bridge is not enabled\n"); 535 return -ENODEV; 536 } 537 538 if (msg->rx_len) { 539 dev_warn(priv->dev, "MIPI rx is not supported\n"); 540 return -ENOTSUPP; 541 } 542 543 if (msg->tx_len > 1024) { 544 dev_warn(priv->dev, "Maximum 1024 byte MIPI tx is supported\n"); 545 return -EINVAL; 546 } 547 548 if (msg->tx_len > 8) { 549 u32 confctl; 550 551 tc358768_read(priv, TC358768_CONFCTL, &confctl); 552 553 if (confctl & BIT(6)) { 554 dev_warn(priv->dev, 555 "Video is currently active. Unable to transmit long command\n"); 556 return -EBUSY; 557 } 558 } 559 560 ret = mipi_dsi_create_packet(&packet, msg); 561 if (ret) 562 return ret; 563 564 if (mipi_dsi_packet_format_is_short(msg->type)) { 565 tc358768_write(priv, TC358768_DSICMD_TYPE, 566 (0x10 << 8) | (packet.header[0] & 0x3f)); 567 tc358768_write(priv, TC358768_DSICMD_WC, 0); 568 tc358768_write(priv, TC358768_DSICMD_WD0, 569 (packet.header[2] << 8) | packet.header[1]); 570 tc358768_dsicmd_tx(priv); 571 } else if (packet.payload_length <= 8) { 572 tc358768_write(priv, TC358768_DSICMD_TYPE, 573 (0x40 << 8) | (packet.header[0] & 0x3f)); 574 tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length); 575 576 for (int i = 0; i < packet.payload_length; i += 2) { 577 u16 val = packet.payload[i]; 578 579 if (i + 1 < packet.payload_length) 580 val |= packet.payload[i + 1] << 8; 581 tc358768_write(priv, TC358768_DSICMD_WD0 + i, val); 582 } 583 584 tc358768_dsicmd_tx(priv); 585 } else { 586 unsigned long tx_sleep_us; 587 size_t len; 588 589 /* For packets over 8 bytes we need to use the video buffer */ 590 tc358768_write(priv, TC358768_DATAFMT, BIT(0)); /* txdt_en */ 591 tc358768_write(priv, TC358768_DSITX_DT, packet.header[0] & 0x3f); 592 tc358768_write(priv, TC358768_CMDBYTE, packet.payload_length); 593 tc358768_write(priv, TC358768_VBUFCTRL, TC358768_VBUFCTRL_VBUF_EN); 594 595 /* 596 * Write the payload in 2-byte chunks, and pad with zeroes to 597 * align to 4 bytes. 598 */ 599 len = ALIGN(packet.payload_length, 4); 600 601 for (int i = 0; i < len; i += 2) { 602 u16 val = 0; 603 604 if (i < packet.payload_length) 605 val |= packet.payload[i]; 606 if (i + 1 < packet.payload_length) 607 val |= packet.payload[i + 1] << 8; 608 609 tc358768_write(priv, TC358768_DBG_DATA, val); 610 } 611 612 /* Start transmission */ 613 tc358768_write(priv, TC358768_VBUFCTRL, 614 TC358768_VBUFCTRL_VBUF_EN | 615 TC358768_VBUFCTRL_TX_EN | 616 TC358768_VBUFCTRL_MASK); 617 618 /* 619 * The TC358768 spec says to wait until the transmission has 620 * been finished, estimating the sleep time based on the payload 621 * and clock rates. We use a simple safe estimate of 2us per 622 * byte (LP mode transmission). 623 */ 624 tx_sleep_us = packet.payload_length * 2; 625 usleep_range(tx_sleep_us, tx_sleep_us * 2); 626 627 tc358768_write(priv, TC358768_VBUFCTRL, TC358768_VBUFCTRL_MASK); 628 tc358768_write(priv, TC358768_VBUFCTRL, 0); /* Stop transmission */ 629 } 630 631 ret = tc358768_clear_error(priv); 632 if (ret) 633 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 634 else 635 ret = packet.size; 636 637 return ret; 638 } 639 640 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = { 641 .attach = tc358768_dsi_host_attach, 642 .detach = tc358768_dsi_host_detach, 643 .transfer = tc358768_dsi_host_transfer, 644 }; 645 646 static int tc358768_bridge_attach(struct drm_bridge *bridge, 647 struct drm_encoder *encoder, 648 enum drm_bridge_attach_flags flags) 649 { 650 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 651 652 if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) { 653 dev_err(priv->dev, "needs atomic updates support\n"); 654 return -ENOTSUPP; 655 } 656 657 return drm_bridge_attach(encoder, priv->output.bridge, bridge, 658 flags); 659 } 660 661 static enum drm_mode_status 662 tc358768_bridge_mode_valid(struct drm_bridge *bridge, 663 const struct drm_display_info *info, 664 const struct drm_display_mode *mode) 665 { 666 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 667 668 if (tc358768_calc_pll(priv, mode, true)) 669 return MODE_CLOCK_RANGE; 670 671 return MODE_OK; 672 } 673 674 static void tc358768_bridge_atomic_disable(struct drm_bridge *bridge, 675 struct drm_atomic_commit *state) 676 { 677 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 678 int ret; 679 680 /* set FrmStop */ 681 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15)); 682 683 /* wait at least for one frame */ 684 msleep(50); 685 686 /* clear PP_en */ 687 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0); 688 689 /* set RstPtr */ 690 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14)); 691 692 ret = tc358768_clear_error(priv); 693 if (ret) 694 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 695 } 696 697 static void tc358768_bridge_atomic_post_disable(struct drm_bridge *bridge, 698 struct drm_atomic_commit *state) 699 { 700 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 701 702 tc358768_hw_disable(priv); 703 } 704 705 static int tc358768_setup_pll(struct tc358768_priv *priv, 706 const struct drm_display_mode *mode) 707 { 708 u32 fbd, prd, frs; 709 int ret; 710 711 ret = tc358768_calc_pll(priv, mode, false); 712 if (ret) { 713 dev_err(priv->dev, "PLL calculation failed: %d\n", ret); 714 return ret; 715 } 716 717 fbd = priv->fbd; 718 prd = priv->prd; 719 frs = priv->frs; 720 721 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n", 722 clk_get_rate(priv->refclk), fbd, prd, frs); 723 dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, HSByteClk %u\n", 724 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4); 725 dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n", 726 tc358768_pll_to_pclk(priv, priv->dsiclk * 2), 727 mode->clock * 1000); 728 729 /* PRD[15:12] FBD[8:0] */ 730 tc358768_write(priv, TC358768_PLLCTL0, ((prd - 1) << 12) | (fbd - 1)); 731 732 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */ 733 tc358768_write(priv, TC358768_PLLCTL1, 734 (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0)); 735 736 /* wait for lock */ 737 usleep_range(1000, 2000); 738 739 /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */ 740 tc358768_write(priv, TC358768_PLLCTL1, 741 (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0)); 742 743 return tc358768_clear_error(priv); 744 } 745 746 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps) 747 { 748 return DIV_ROUND_UP(ns * 1000, period_ps); 749 } 750 751 static u32 tc358768_ps_to_ns(u32 ps) 752 { 753 return ps / 1000; 754 } 755 756 static u32 tc358768_dpi_to_ns(u32 val, u32 pclk) 757 { 758 return (u32)div_u64((u64)val * NANO, pclk); 759 } 760 761 /* Convert value in DPI pixel clock units to DSI byte count */ 762 static u32 tc358768_dpi_to_dsi_bytes(struct tc358768_priv *priv, u32 val) 763 { 764 u64 m = (u64)val * priv->dsiclk / 4 * priv->dsi_lanes; 765 u64 n = priv->pclk; 766 767 return (u32)div_u64(m + n - 1, n); 768 } 769 770 static u32 tc358768_dsi_bytes_to_ns(struct tc358768_priv *priv, u32 val) 771 { 772 u64 m = (u64)val * NANO; 773 u64 n = priv->dsiclk / 4 * priv->dsi_lanes; 774 775 return (u32)div_u64(m, n); 776 } 777 778 static void tc358768_bridge_atomic_pre_enable(struct drm_bridge *bridge, 779 struct drm_atomic_commit *state) 780 { 781 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 782 struct mipi_dsi_device *dsi_dev = priv->output.dev; 783 u32 val, mask, val2, lptxcnt, hact; 784 s32 raw_val; 785 struct drm_crtc_state *crtc_state; 786 struct drm_connector_state *conn_state; 787 struct drm_connector *connector; 788 const struct drm_display_mode *mode; 789 u32 hsbyteclk_ps, dsiclk_ps, ui_ps; 790 u32 dsiclk, hsbyteclk; 791 int ret, i; 792 struct videomode vm; 793 struct device *dev = priv->dev; 794 /* In pixelclock units */ 795 u32 dpi_htot, dpi_data_start; 796 /* In byte units */ 797 u32 dsi_dpi_htot, dsi_dpi_data_start; 798 u32 dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp; 799 const u32 dsi_hss = 4; /* HSS is a short packet (4 bytes) */ 800 /* In hsbyteclk units */ 801 u32 dsi_vsdly; 802 const u32 internal_dly = 40; 803 804 tc358768_hw_enable(priv); 805 806 ret = tc358768_sw_reset(priv); 807 if (ret) { 808 dev_err(dev, "Software reset failed: %d\n", ret); 809 tc358768_hw_disable(priv); 810 return; 811 } 812 813 /* Release RstPtr so that the video buffer can be used for DSI commands */ 814 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), 0); 815 816 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 817 conn_state = drm_atomic_get_new_connector_state(state, connector); 818 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); 819 mode = &crtc_state->adjusted_mode; 820 ret = tc358768_setup_pll(priv, mode); 821 if (ret) { 822 dev_err(dev, "PLL setup failed: %d\n", ret); 823 tc358768_hw_disable(priv); 824 return; 825 } 826 827 drm_display_mode_to_videomode(mode, &vm); 828 829 dsiclk = priv->dsiclk; 830 hsbyteclk = dsiclk / 4; 831 832 switch (dsi_dev->format) { 833 case MIPI_DSI_FMT_RGB888: 834 hact = vm.hactive * 3; 835 break; 836 case MIPI_DSI_FMT_RGB666: 837 hact = vm.hactive * 3; 838 break; 839 840 case MIPI_DSI_FMT_RGB666_PACKED: 841 hact = vm.hactive * 18 / 8; 842 break; 843 844 case MIPI_DSI_FMT_RGB565: 845 hact = vm.hactive * 2; 846 break; 847 default: 848 dev_err(dev, "Invalid data format (%u)\n", 849 dsi_dev->format); 850 tc358768_hw_disable(priv); 851 return; 852 } 853 854 /* 855 * There are three important things to make TC358768 work correctly, 856 * which are not trivial to manage: 857 * 858 * 1. Keep the DPI line-time and the DSI line-time as close to each 859 * other as possible. 860 * 2. TC358768 goes to LP mode after each line's active area. The DSI 861 * HFP period has to be long enough for entering and exiting LP mode. 862 * But it is not clear how to calculate this. 863 * 3. VSDly (video start delay) has to be long enough to ensure that the 864 * DSI TX does not start transmitting until we have started receiving 865 * pixel data from the DPI input. It is not clear how to calculate 866 * this either. 867 */ 868 869 dpi_htot = vm.hactive + vm.hfront_porch + vm.hsync_len + vm.hback_porch; 870 dpi_data_start = vm.hsync_len + vm.hback_porch; 871 872 dev_dbg(dev, "dpi horiz timing (pclk): %u + %u + %u + %u = %u\n", 873 vm.hsync_len, vm.hback_porch, vm.hactive, vm.hfront_porch, 874 dpi_htot); 875 876 dev_dbg(dev, "dpi horiz timing (ns): %u + %u + %u + %u = %u\n", 877 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock), 878 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock), 879 tc358768_dpi_to_ns(vm.hactive, vm.pixelclock), 880 tc358768_dpi_to_ns(vm.hfront_porch, vm.pixelclock), 881 tc358768_dpi_to_ns(dpi_htot, vm.pixelclock)); 882 883 dev_dbg(dev, "dpi data start (ns): %u + %u = %u\n", 884 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock), 885 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock), 886 tc358768_dpi_to_ns(dpi_data_start, vm.pixelclock)); 887 888 dsi_dpi_htot = tc358768_dpi_to_dsi_bytes(priv, dpi_htot); 889 dsi_dpi_data_start = tc358768_dpi_to_dsi_bytes(priv, dpi_data_start); 890 891 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 892 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, vm.hsync_len); 893 dsi_hbp = tc358768_dpi_to_dsi_bytes(priv, vm.hback_porch); 894 } else { 895 /* HBP is included in HSW in event mode */ 896 dsi_hbp = 0; 897 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, 898 vm.hsync_len + 899 vm.hback_porch); 900 901 /* 902 * The pixel packet includes the actual pixel data, and: 903 * DSI packet header = 4 bytes 904 * DCS code = 1 byte 905 * DSI packet footer = 2 bytes 906 */ 907 dsi_hact = hact + 4 + 1 + 2; 908 909 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; 910 911 /* 912 * Here we should check if HFP is long enough for entering LP 913 * and exiting LP, but it's not clear how to calculate that. 914 * Instead, this is a naive algorithm that just adjusts the HFP 915 * and HSW so that HFP is (at least) roughly 2/3 of the total 916 * blanking time. 917 */ 918 if (dsi_hfp < (dsi_hfp + dsi_hsw + dsi_hss) * 2 / 3) { 919 u32 old_hfp = dsi_hfp; 920 u32 old_hsw = dsi_hsw; 921 u32 tot = dsi_hfp + dsi_hsw + dsi_hss; 922 923 dsi_hsw = tot / 3; 924 925 /* 926 * Seems like sometimes HSW has to be divisible by num-lanes, but 927 * not always... 928 */ 929 dsi_hsw = roundup(dsi_hsw, priv->dsi_lanes); 930 931 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; 932 933 dev_dbg(dev, 934 "hfp too short, adjusting dsi hfp and dsi hsw from %u, %u to %u, %u\n", 935 old_hfp, old_hsw, dsi_hfp, dsi_hsw); 936 } 937 938 dev_dbg(dev, 939 "dsi horiz timing (bytes): %u, %u + %u + %u + %u = %u\n", 940 dsi_hss, dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp, 941 dsi_hss + dsi_hsw + dsi_hbp + dsi_hact + dsi_hfp); 942 943 dev_dbg(dev, "dsi horiz timing (ns): %u + %u + %u + %u + %u = %u\n", 944 tc358768_dsi_bytes_to_ns(priv, dsi_hss), 945 tc358768_dsi_bytes_to_ns(priv, dsi_hsw), 946 tc358768_dsi_bytes_to_ns(priv, dsi_hbp), 947 tc358768_dsi_bytes_to_ns(priv, dsi_hact), 948 tc358768_dsi_bytes_to_ns(priv, dsi_hfp), 949 tc358768_dsi_bytes_to_ns(priv, dsi_hss + dsi_hsw + 950 dsi_hbp + dsi_hact + dsi_hfp)); 951 } 952 953 /* VSDly calculation */ 954 955 /* Start with the HW internal delay */ 956 dsi_vsdly = internal_dly; 957 958 /* Convert to byte units as the other variables are in byte units */ 959 dsi_vsdly *= priv->dsi_lanes; 960 961 /* Do we need more delay, in addition to the internal? */ 962 if (dsi_dpi_data_start > dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp) { 963 dsi_vsdly = dsi_dpi_data_start - dsi_hss - dsi_hsw - dsi_hbp; 964 dsi_vsdly = roundup(dsi_vsdly, priv->dsi_lanes); 965 } 966 967 dev_dbg(dev, "dsi data start (bytes) %u + %u + %u + %u = %u\n", 968 dsi_vsdly, dsi_hss, dsi_hsw, dsi_hbp, 969 dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp); 970 971 dev_dbg(dev, "dsi data start (ns) %u + %u + %u + %u = %u\n", 972 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly), 973 tc358768_dsi_bytes_to_ns(priv, dsi_hss), 974 tc358768_dsi_bytes_to_ns(priv, dsi_hsw), 975 tc358768_dsi_bytes_to_ns(priv, dsi_hbp), 976 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp)); 977 978 /* Convert back to hsbyteclk */ 979 dsi_vsdly /= priv->dsi_lanes; 980 981 /* 982 * The docs say that there is an internal delay of 40 cycles. 983 * However, we get underflows if we follow that rule. If we 984 * instead ignore the internal delay, things work. So either 985 * the docs are wrong or the calculations are wrong. 986 * 987 * As a temporary fix, add the internal delay here, to counter 988 * the subtraction when writing the register. 989 */ 990 dsi_vsdly += internal_dly; 991 992 /* Clamp to the register max */ 993 if (dsi_vsdly - internal_dly > 0x3ff) { 994 dev_warn(dev, "VSDly too high, underflows likely\n"); 995 dsi_vsdly = 0x3ff + internal_dly; 996 } 997 998 /* VSDly[9:0] */ 999 tc358768_write(priv, TC358768_VSDLY, dsi_vsdly - internal_dly); 1000 1001 /* Enable D-PHY (HiZ->LP11) */ 1002 tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000); 1003 /* Enable lanes */ 1004 for (i = 0; i < dsi_dev->lanes; i++) 1005 tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000); 1006 1007 /* DSI Timings */ 1008 hsbyteclk_ps = (u32)div_u64(PICO, hsbyteclk); 1009 dsiclk_ps = (u32)div_u64(PICO, dsiclk); 1010 ui_ps = dsiclk_ps / 2; 1011 dev_dbg(dev, "dsiclk: %u ps, ui %u ps, hsbyteclk %u ps\n", dsiclk_ps, 1012 ui_ps, hsbyteclk_ps); 1013 1014 /* LP11 > 100us for D-PHY Rx Init */ 1015 val = tc358768_ns_to_cnt(100 * 1000, hsbyteclk_ps) - 1; 1016 dev_dbg(dev, "LINEINITCNT: %u\n", val); 1017 tc358768_write(priv, TC358768_LINEINITCNT, val); 1018 1019 /* LPTimeCnt > 50ns */ 1020 val = tc358768_ns_to_cnt(50, hsbyteclk_ps) - 1; 1021 lptxcnt = val; 1022 dev_dbg(dev, "LPTXTIMECNT: %u\n", val); 1023 tc358768_write(priv, TC358768_LPTXTIMECNT, val); 1024 1025 /* 38ns < TCLK_PREPARE < 95ns */ 1026 val = tc358768_ns_to_cnt(65, hsbyteclk_ps) - 1; 1027 dev_dbg(dev, "TCLK_PREPARECNT %u\n", val); 1028 /* TCLK_PREPARE + TCLK_ZERO > 300ns */ 1029 val2 = tc358768_ns_to_cnt(300 - tc358768_ps_to_ns(2 * ui_ps), 1030 hsbyteclk_ps) - 2; 1031 dev_dbg(dev, "TCLK_ZEROCNT %u\n", val2); 1032 val |= val2 << 8; 1033 tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); 1034 1035 /* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */ 1036 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(2 * ui_ps), hsbyteclk_ps) - 5; 1037 val = clamp(raw_val, 0, 127); 1038 dev_dbg(dev, "TCLK_TRAILCNT: %u\n", val); 1039 tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); 1040 1041 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ 1042 val = 50 + tc358768_ps_to_ns(4 * ui_ps); 1043 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) - 1; 1044 dev_dbg(dev, "THS_PREPARECNT %u\n", val); 1045 /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ 1046 raw_val = tc358768_ns_to_cnt(145 - tc358768_ps_to_ns(3 * ui_ps), hsbyteclk_ps) - 10; 1047 val2 = clamp(raw_val, 0, 127); 1048 dev_dbg(dev, "THS_ZEROCNT %u\n", val2); 1049 val |= val2 << 8; 1050 tc358768_write(priv, TC358768_THS_HEADERCNT, val); 1051 1052 /* TWAKEUP > 1ms in lptxcnt steps */ 1053 val = tc358768_ns_to_cnt(1020000, hsbyteclk_ps); 1054 val = val / (lptxcnt + 1) - 1; 1055 dev_dbg(dev, "TWAKEUP: %u\n", val); 1056 tc358768_write(priv, TC358768_TWAKEUP, val); 1057 1058 /* TCLK_POSTCNT > 60ns + 52*UI */ 1059 val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(52 * ui_ps), 1060 hsbyteclk_ps) - 3; 1061 dev_dbg(dev, "TCLK_POSTCNT: %u\n", val); 1062 tc358768_write(priv, TC358768_TCLK_POSTCNT, val); 1063 1064 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ 1065 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(18 * ui_ps), 1066 hsbyteclk_ps) - 4; 1067 val = clamp(raw_val, 0, 15); 1068 dev_dbg(dev, "THS_TRAILCNT: %u\n", val); 1069 tc358768_write(priv, TC358768_THS_TRAILCNT, val); 1070 1071 val = BIT(0); 1072 for (i = 0; i < dsi_dev->lanes; i++) 1073 val |= BIT(i + 1); 1074 tc358768_write(priv, TC358768_HSTXVREGEN, val); 1075 1076 tc358768_write(priv, TC358768_TXOPTIONCNTRL, 1077 (dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); 1078 1079 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ 1080 val = tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4); 1081 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) / 4 - 1; 1082 dev_dbg(dev, "TXTAGOCNT: %u\n", val); 1083 val2 = tc358768_ns_to_cnt(tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps), 1084 hsbyteclk_ps) - 2; 1085 dev_dbg(dev, "RXTASURECNT: %u\n", val2); 1086 val = val << 16 | val2; 1087 tc358768_write(priv, TC358768_BTACNTRL1, val); 1088 1089 /* START[0] */ 1090 tc358768_write(priv, TC358768_STARTCNTRL, 1); 1091 1092 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 1093 /* Set pulse mode */ 1094 tc358768_write(priv, TC358768_DSI_EVENT, 0); 1095 1096 /* vact */ 1097 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); 1098 1099 /* vsw */ 1100 tc358768_write(priv, TC358768_DSI_VSW, vm.vsync_len); 1101 1102 /* vbp */ 1103 tc358768_write(priv, TC358768_DSI_VBPR, vm.vback_porch); 1104 } else { 1105 /* Set event mode */ 1106 tc358768_write(priv, TC358768_DSI_EVENT, 1); 1107 1108 /* vact */ 1109 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); 1110 1111 /* vsw (+ vbp) */ 1112 tc358768_write(priv, TC358768_DSI_VSW, 1113 vm.vsync_len + vm.vback_porch); 1114 1115 /* vbp (not used in event mode) */ 1116 tc358768_write(priv, TC358768_DSI_VBPR, 0); 1117 } 1118 1119 /* hsw (bytes) */ 1120 tc358768_write(priv, TC358768_DSI_HSW, dsi_hsw); 1121 1122 /* hbp (bytes) */ 1123 tc358768_write(priv, TC358768_DSI_HBPR, dsi_hbp); 1124 1125 /* hact (bytes) */ 1126 tc358768_write(priv, TC358768_DSI_HACT, hact); 1127 1128 /* VSYNC polarity */ 1129 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), 1130 (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0); 1131 1132 /* HSYNC polarity */ 1133 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), 1134 (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0); 1135 1136 /* Start DSI Tx */ 1137 tc358768_write(priv, TC358768_DSI_START, 0x1); 1138 1139 /* Configure DSI_Control register */ 1140 val = (dsi_dev->lanes - 1) << 1; 1141 1142 if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM)) 1143 val |= TC358768_DSI_CONTROL_TXMD; 1144 1145 if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 1146 val |= TC358768_DSI_CONTROL_HSCKMD; 1147 1148 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 1149 val |= TC358768_DSI_CONTROL_EOTDIS; 1150 1151 mask = TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD | 1152 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS; 1153 1154 tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, mask, val); 1155 1156 tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, 1157 TC358768_DSI_CONTROL_DSI_MODE, 0); 1158 1159 ret = tc358768_clear_error(priv); 1160 if (ret) 1161 dev_err(dev, "Bridge pre_enable failed: %d\n", ret); 1162 } 1163 1164 static void tc358768_config_video_format(struct tc358768_priv *priv) 1165 { 1166 struct mipi_dsi_device *dsi_dev = priv->output.dev; 1167 u32 val, data_type; 1168 1169 /* Data Format Control Register */ 1170 val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ 1171 switch (dsi_dev->format) { 1172 case MIPI_DSI_FMT_RGB888: 1173 val |= (0x3 << 4); 1174 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 1175 break; 1176 case MIPI_DSI_FMT_RGB666: 1177 val |= (0x4 << 4); 1178 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 1179 break; 1180 case MIPI_DSI_FMT_RGB666_PACKED: 1181 val |= (0x4 << 4) | BIT(3); 1182 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 1183 break; 1184 case MIPI_DSI_FMT_RGB565: 1185 val |= (0x5 << 4); 1186 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 1187 break; 1188 default: 1189 dev_err(priv->dev, "Invalid data format (%u)\n", dsi_dev->format); 1190 return; 1191 } 1192 1193 tc358768_write(priv, TC358768_DATAFMT, val); 1194 tc358768_write(priv, TC358768_DSITX_DT, data_type); 1195 } 1196 1197 static void tc358768_bridge_atomic_enable(struct drm_bridge *bridge, 1198 struct drm_atomic_commit *state) 1199 { 1200 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 1201 int ret; 1202 1203 if (!priv->enabled) { 1204 dev_err(priv->dev, "Bridge is not enabled\n"); 1205 return; 1206 } 1207 1208 /* Configure video format registers */ 1209 tc358768_config_video_format(priv); 1210 1211 /* Enable HS mode for video TX */ 1212 tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, 1213 TC358768_DSI_CONTROL_TXMD, 1214 TC358768_DSI_CONTROL_TXMD); 1215 1216 /* clear FrmStop and RstPtr */ 1217 tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0); 1218 1219 /* set PP_en */ 1220 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6)); 1221 1222 ret = tc358768_clear_error(priv); 1223 if (ret) 1224 dev_err(priv->dev, "Bridge enable failed: %d\n", ret); 1225 } 1226 1227 #define MAX_INPUT_SEL_FORMATS 1 1228 1229 static u32 * 1230 tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 1231 struct drm_bridge_state *bridge_state, 1232 struct drm_crtc_state *crtc_state, 1233 struct drm_connector_state *conn_state, 1234 u32 output_fmt, 1235 unsigned int *num_input_fmts) 1236 { 1237 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 1238 u32 *input_fmts; 1239 1240 *num_input_fmts = 0; 1241 1242 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 1243 GFP_KERNEL); 1244 if (!input_fmts) 1245 return NULL; 1246 1247 switch (priv->pd_lines) { 1248 case 16: 1249 input_fmts[0] = MEDIA_BUS_FMT_RGB565_1X16; 1250 break; 1251 case 18: 1252 input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X18; 1253 break; 1254 default: 1255 case 24: 1256 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 1257 break; 1258 } 1259 1260 *num_input_fmts = MAX_INPUT_SEL_FORMATS; 1261 1262 return input_fmts; 1263 } 1264 1265 static bool tc358768_mode_fixup(struct drm_bridge *bridge, 1266 const struct drm_display_mode *mode, 1267 struct drm_display_mode *adjusted_mode) 1268 { 1269 /* Default to positive sync */ 1270 1271 if (!(adjusted_mode->flags & 1272 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 1273 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; 1274 1275 if (!(adjusted_mode->flags & 1276 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 1277 adjusted_mode->flags |= DRM_MODE_FLAG_PVSYNC; 1278 1279 return true; 1280 } 1281 1282 static const struct drm_bridge_funcs tc358768_bridge_funcs = { 1283 .attach = tc358768_bridge_attach, 1284 .mode_valid = tc358768_bridge_mode_valid, 1285 .mode_fixup = tc358768_mode_fixup, 1286 .atomic_pre_enable = tc358768_bridge_atomic_pre_enable, 1287 .atomic_enable = tc358768_bridge_atomic_enable, 1288 .atomic_disable = tc358768_bridge_atomic_disable, 1289 .atomic_post_disable = tc358768_bridge_atomic_post_disable, 1290 1291 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1292 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1293 .atomic_reset = drm_atomic_helper_bridge_reset, 1294 .atomic_get_input_bus_fmts = tc358768_atomic_get_input_bus_fmts, 1295 }; 1296 1297 static const struct drm_bridge_timings default_tc358768_timings = { 1298 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 1299 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE 1300 | DRM_BUS_FLAG_DE_HIGH, 1301 }; 1302 1303 static bool tc358768_is_reserved_reg(unsigned int reg) 1304 { 1305 switch (reg) { 1306 case 0x114 ... 0x13f: 1307 case 0x200: 1308 case 0x20c: 1309 case 0x400 ... 0x408: 1310 case 0x41c ... 0x42f: 1311 return true; 1312 default: 1313 return false; 1314 } 1315 } 1316 1317 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg) 1318 { 1319 if (tc358768_is_reserved_reg(reg)) 1320 return false; 1321 1322 switch (reg) { 1323 case TC358768_CHIPID: 1324 case TC358768_FIFOSTATUS: 1325 case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2): 1326 case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2): 1327 case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2): 1328 return false; 1329 default: 1330 return true; 1331 } 1332 } 1333 1334 static bool tc358768_readable_reg(struct device *dev, unsigned int reg) 1335 { 1336 if (tc358768_is_reserved_reg(reg)) 1337 return false; 1338 1339 switch (reg) { 1340 case TC358768_STARTCNTRL: 1341 case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2): 1342 case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2): 1343 case TC358768_DSI_START ... (TC358768_DSI_START + 2): 1344 case TC358768_DBG_DATA: 1345 return false; 1346 default: 1347 return true; 1348 } 1349 } 1350 1351 static const struct regmap_config tc358768_regmap_config = { 1352 .name = "tc358768", 1353 .reg_bits = 16, 1354 .val_bits = 16, 1355 .max_register = TC358768_DSI_HACT, 1356 .cache_type = REGCACHE_NONE, 1357 .writeable_reg = tc358768_writeable_reg, 1358 .readable_reg = tc358768_readable_reg, 1359 .reg_format_endian = REGMAP_ENDIAN_BIG, 1360 .val_format_endian = REGMAP_ENDIAN_BIG, 1361 }; 1362 1363 static const struct i2c_device_id tc358768_i2c_ids[] = { 1364 { "tc358768" }, 1365 { "tc358778" }, 1366 { } 1367 }; 1368 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids); 1369 1370 static const struct of_device_id tc358768_of_ids[] = { 1371 { .compatible = "toshiba,tc358768", }, 1372 { .compatible = "toshiba,tc358778", }, 1373 { } 1374 }; 1375 MODULE_DEVICE_TABLE(of, tc358768_of_ids); 1376 1377 static int tc358768_get_regulators(struct tc358768_priv *priv) 1378 { 1379 int i, ret; 1380 1381 for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i) 1382 priv->supplies[i].supply = tc358768_supplies[i]; 1383 1384 ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies), 1385 priv->supplies); 1386 if (ret < 0) 1387 dev_err(priv->dev, "failed to get regulators: %d\n", ret); 1388 1389 return ret; 1390 } 1391 1392 static int tc358768_i2c_probe(struct i2c_client *client) 1393 { 1394 struct tc358768_priv *priv; 1395 struct device *dev = &client->dev; 1396 struct device_node *np = dev->of_node; 1397 int ret; 1398 1399 if (!np) 1400 return -ENODEV; 1401 1402 priv = devm_drm_bridge_alloc(dev, struct tc358768_priv, bridge, 1403 &tc358768_bridge_funcs); 1404 if (IS_ERR(priv)) 1405 return PTR_ERR(priv); 1406 1407 dev_set_drvdata(dev, priv); 1408 priv->dev = dev; 1409 1410 ret = tc358768_get_regulators(priv); 1411 if (ret) 1412 return ret; 1413 1414 priv->refclk = devm_clk_get(dev, "refclk"); 1415 if (IS_ERR(priv->refclk)) 1416 return PTR_ERR(priv->refclk); 1417 1418 /* 1419 * RESX is low active, to disable tc358768 initially (keep in reset) 1420 * the gpio line must be LOW. This is the ASSERTED state of 1421 * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED). 1422 */ 1423 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1424 GPIOD_OUT_HIGH); 1425 if (IS_ERR(priv->reset_gpio)) 1426 return PTR_ERR(priv->reset_gpio); 1427 1428 priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config); 1429 if (IS_ERR(priv->regmap)) { 1430 dev_err(dev, "Failed to init regmap\n"); 1431 return PTR_ERR(priv->regmap); 1432 } 1433 1434 priv->dsi_host.dev = dev; 1435 priv->dsi_host.ops = &tc358768_dsi_host_ops; 1436 1437 priv->bridge.timings = &default_tc358768_timings; 1438 priv->bridge.of_node = np; 1439 1440 i2c_set_clientdata(client, priv); 1441 1442 return mipi_dsi_host_register(&priv->dsi_host); 1443 } 1444 1445 static void tc358768_i2c_remove(struct i2c_client *client) 1446 { 1447 struct tc358768_priv *priv = i2c_get_clientdata(client); 1448 1449 mipi_dsi_host_unregister(&priv->dsi_host); 1450 } 1451 1452 static struct i2c_driver tc358768_driver = { 1453 .driver = { 1454 .name = "tc358768", 1455 .of_match_table = tc358768_of_ids, 1456 }, 1457 .id_table = tc358768_i2c_ids, 1458 .probe = tc358768_i2c_probe, 1459 .remove = tc358768_i2c_remove, 1460 }; 1461 module_i2c_driver(tc358768_driver); 1462 1463 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); 1464 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge"); 1465 MODULE_LICENSE("GPL v2"); 1466