1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) 2020 Texas Instruments Incorporated - https://www.ti.com 4 * Author: Peter Ujfalusi <peter.ujfalusi@ti.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/device.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/i2c.h> 11 #include <linux/kernel.h> 12 #include <linux/math64.h> 13 #include <linux/media-bus-format.h> 14 #include <linux/minmax.h> 15 #include <linux/module.h> 16 #include <linux/regmap.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/slab.h> 19 #include <linux/units.h> 20 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_drv.h> 23 #include <drm/drm_mipi_dsi.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_panel.h> 26 #include <video/mipi_display.h> 27 #include <video/videomode.h> 28 29 /* Global (16-bit addressable) */ 30 #define TC358768_CHIPID 0x0000 31 #define TC358768_SYSCTL 0x0002 32 #define TC358768_CONFCTL 0x0004 33 #define TC358768_VSDLY 0x0006 34 #define TC358768_DATAFMT 0x0008 35 #define TC358768_GPIOEN 0x000E 36 #define TC358768_GPIODIR 0x0010 37 #define TC358768_GPIOIN 0x0012 38 #define TC358768_GPIOOUT 0x0014 39 #define TC358768_PLLCTL0 0x0016 40 #define TC358768_PLLCTL1 0x0018 41 #define TC358768_CMDBYTE 0x0022 42 #define TC358768_PP_MISC 0x0032 43 #define TC358768_DSITX_DT 0x0050 44 #define TC358768_FIFOSTATUS 0x00F8 45 46 /* Debug (16-bit addressable) */ 47 #define TC358768_VBUFCTRL 0x00E0 48 #define TC358768_VBUFCTRL_VBUF_EN BIT(15) 49 #define TC358768_VBUFCTRL_TX_EN BIT(14) 50 #define TC358768_VBUFCTRL_MASK BIT(13) 51 #define TC358768_DBG_WIDTH 0x00E2 52 #define TC358768_DBG_VBLANK 0x00E4 53 #define TC358768_DBG_DATA 0x00E8 54 55 /* TX PHY (32-bit addressable) */ 56 #define TC358768_CLW_DPHYCONTTX 0x0100 57 #define TC358768_D0W_DPHYCONTTX 0x0104 58 #define TC358768_D1W_DPHYCONTTX 0x0108 59 #define TC358768_D2W_DPHYCONTTX 0x010C 60 #define TC358768_D3W_DPHYCONTTX 0x0110 61 #define TC358768_CLW_CNTRL 0x0140 62 #define TC358768_D0W_CNTRL 0x0144 63 #define TC358768_D1W_CNTRL 0x0148 64 #define TC358768_D2W_CNTRL 0x014C 65 #define TC358768_D3W_CNTRL 0x0150 66 67 /* TX PPI (32-bit addressable) */ 68 #define TC358768_STARTCNTRL 0x0204 69 #define TC358768_DSITXSTATUS 0x0208 70 #define TC358768_LINEINITCNT 0x0210 71 #define TC358768_LPTXTIMECNT 0x0214 72 #define TC358768_TCLK_HEADERCNT 0x0218 73 #define TC358768_TCLK_TRAILCNT 0x021C 74 #define TC358768_THS_HEADERCNT 0x0220 75 #define TC358768_TWAKEUP 0x0224 76 #define TC358768_TCLK_POSTCNT 0x0228 77 #define TC358768_THS_TRAILCNT 0x022C 78 #define TC358768_HSTXVREGCNT 0x0230 79 #define TC358768_HSTXVREGEN 0x0234 80 #define TC358768_TXOPTIONCNTRL 0x0238 81 #define TC358768_BTACNTRL1 0x023C 82 83 /* TX CTRL (32-bit addressable) */ 84 #define TC358768_DSI_CONTROL 0x040C 85 #define TC358768_DSI_STATUS 0x0410 86 #define TC358768_DSI_INT 0x0414 87 #define TC358768_DSI_INT_ENA 0x0418 88 #define TC358768_DSICMD_RDFIFO 0x0430 89 #define TC358768_DSI_ACKERR 0x0434 90 #define TC358768_DSI_ACKERR_INTENA 0x0438 91 #define TC358768_DSI_ACKERR_HALT 0x043c 92 #define TC358768_DSI_RXERR 0x0440 93 #define TC358768_DSI_RXERR_INTENA 0x0444 94 #define TC358768_DSI_RXERR_HALT 0x0448 95 #define TC358768_DSI_ERR 0x044C 96 #define TC358768_DSI_ERR_INTENA 0x0450 97 #define TC358768_DSI_ERR_HALT 0x0454 98 #define TC358768_DSI_CONFW 0x0500 99 #define TC358768_DSI_LPCMD 0x0500 100 #define TC358768_DSI_RESET 0x0504 101 #define TC358768_DSI_INT_CLR 0x050C 102 #define TC358768_DSI_START 0x0518 103 104 /* DSITX CTRL (16-bit addressable) */ 105 #define TC358768_DSICMD_TX 0x0600 106 #define TC358768_DSICMD_TYPE 0x0602 107 #define TC358768_DSICMD_WC 0x0604 108 #define TC358768_DSICMD_WD0 0x0610 109 #define TC358768_DSICMD_WD1 0x0612 110 #define TC358768_DSICMD_WD2 0x0614 111 #define TC358768_DSICMD_WD3 0x0616 112 #define TC358768_DSI_EVENT 0x0620 113 #define TC358768_DSI_VSW 0x0622 114 #define TC358768_DSI_VBPR 0x0624 115 #define TC358768_DSI_VACT 0x0626 116 #define TC358768_DSI_HSW 0x0628 117 #define TC358768_DSI_HBPR 0x062A 118 #define TC358768_DSI_HACT 0x062C 119 120 /* TC358768_DSI_CONTROL (0x040C) register */ 121 #define TC358768_DSI_CONTROL_DSI_MODE BIT(15) 122 #define TC358768_DSI_CONTROL_TXMD BIT(7) 123 #define TC358768_DSI_CONTROL_HSCKMD BIT(5) 124 #define TC358768_DSI_CONTROL_EOTDIS BIT(0) 125 126 /* TC358768_DSI_CONFW (0x0500) register */ 127 #define TC358768_DSI_CONFW_MODE_SET (5 << 29) 128 #define TC358768_DSI_CONFW_MODE_CLR (6 << 29) 129 #define TC358768_DSI_CONFW_ADDR(x) ((x) << 24) 130 131 /* TC358768_DSICMD_TX (0x0600) register */ 132 #define TC358768_DSI_CMDTX_DC_START BIT(0) 133 134 static const char * const tc358768_supplies[] = { 135 "vddc", "vddmipi", "vddio" 136 }; 137 138 struct tc358768_dsi_output { 139 struct mipi_dsi_device *dev; 140 struct drm_panel *panel; 141 struct drm_bridge *bridge; 142 }; 143 144 struct tc358768_priv { 145 struct device *dev; 146 struct regmap *regmap; 147 struct gpio_desc *reset_gpio; 148 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358768_supplies)]; 149 struct clk *refclk; 150 int enabled; 151 int error; 152 153 struct mipi_dsi_host dsi_host; 154 struct drm_bridge bridge; 155 struct tc358768_dsi_output output; 156 157 u32 pd_lines; /* number of Parallel Port Input Data Lines */ 158 u32 dsi_lanes; /* number of DSI Lanes */ 159 u32 dsi_bpp; /* number of Bits Per Pixel over DSI */ 160 161 /* Parameters for PLL programming */ 162 u32 fbd; /* PLL feedback divider */ 163 u32 prd; /* PLL input divider */ 164 u32 frs; /* PLL Freqency range for HSCK (post divider) */ 165 166 u32 dsiclk; /* pll_clk / 2 */ 167 u32 pclk; /* incoming pclk rate */ 168 }; 169 170 static inline struct tc358768_priv *dsi_host_to_tc358768(struct mipi_dsi_host 171 *host) 172 { 173 return container_of(host, struct tc358768_priv, dsi_host); 174 } 175 176 static inline struct tc358768_priv *bridge_to_tc358768(struct drm_bridge 177 *bridge) 178 { 179 return container_of(bridge, struct tc358768_priv, bridge); 180 } 181 182 static int tc358768_clear_error(struct tc358768_priv *priv) 183 { 184 int ret = priv->error; 185 186 priv->error = 0; 187 return ret; 188 } 189 190 static void tc358768_write(struct tc358768_priv *priv, u32 reg, u32 val) 191 { 192 /* work around https://gcc.gnu.org/bugzilla/show_bug.cgi?id=81715 */ 193 int tmpval = val; 194 size_t count = 2; 195 196 if (priv->error) 197 return; 198 199 /* 16-bit register? */ 200 if (reg < 0x100 || reg >= 0x600) 201 count = 1; 202 203 priv->error = regmap_bulk_write(priv->regmap, reg, &tmpval, count); 204 } 205 206 static void tc358768_read(struct tc358768_priv *priv, u32 reg, u32 *val) 207 { 208 size_t count = 2; 209 210 if (priv->error) 211 return; 212 213 /* 16-bit register? */ 214 if (reg < 0x100 || reg >= 0x600) { 215 *val = 0; 216 count = 1; 217 } 218 219 priv->error = regmap_bulk_read(priv->regmap, reg, val, count); 220 } 221 222 static void tc358768_update_bits(struct tc358768_priv *priv, u32 reg, u32 mask, 223 u32 val) 224 { 225 u32 tmp, orig; 226 227 tc358768_read(priv, reg, &orig); 228 229 if (priv->error) 230 return; 231 232 tmp = orig & ~mask; 233 tmp |= val & mask; 234 if (tmp != orig) 235 tc358768_write(priv, reg, tmp); 236 } 237 238 static void tc358768_confw_update_bits(struct tc358768_priv *priv, u16 reg, 239 u16 mask, u16 val) 240 { 241 u8 confw_addr; 242 u32 confw_val; 243 244 switch (reg) { 245 case TC358768_DSI_CONTROL: 246 confw_addr = 0x3; 247 break; 248 default: 249 priv->error = -EINVAL; 250 return; 251 } 252 253 if (mask != val) { 254 confw_val = TC358768_DSI_CONFW_MODE_CLR | 255 TC358768_DSI_CONFW_ADDR(confw_addr) | 256 mask; 257 tc358768_write(priv, TC358768_DSI_CONFW, confw_val); 258 } 259 260 if (val & mask) { 261 confw_val = TC358768_DSI_CONFW_MODE_SET | 262 TC358768_DSI_CONFW_ADDR(confw_addr) | 263 (val & mask); 264 tc358768_write(priv, TC358768_DSI_CONFW, confw_val); 265 } 266 } 267 268 static void tc358768_dsicmd_tx(struct tc358768_priv *priv) 269 { 270 u32 val; 271 272 /* start transfer */ 273 tc358768_write(priv, TC358768_DSICMD_TX, TC358768_DSI_CMDTX_DC_START); 274 if (priv->error) 275 return; 276 277 /* wait transfer completion */ 278 priv->error = regmap_read_poll_timeout(priv->regmap, TC358768_DSICMD_TX, val, 279 (val & TC358768_DSI_CMDTX_DC_START) == 0, 280 100, 100000); 281 } 282 283 static int tc358768_sw_reset(struct tc358768_priv *priv) 284 { 285 /* Assert Reset */ 286 tc358768_write(priv, TC358768_SYSCTL, 1); 287 /* Release Reset, Exit Sleep */ 288 tc358768_write(priv, TC358768_SYSCTL, 0); 289 290 return tc358768_clear_error(priv); 291 } 292 293 static void tc358768_hw_enable(struct tc358768_priv *priv) 294 { 295 int ret; 296 297 if (priv->enabled) 298 return; 299 300 ret = clk_prepare_enable(priv->refclk); 301 if (ret < 0) 302 dev_err(priv->dev, "error enabling refclk (%d)\n", ret); 303 304 ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); 305 if (ret < 0) 306 dev_err(priv->dev, "error enabling regulators (%d)\n", ret); 307 308 if (priv->reset_gpio) 309 usleep_range(200, 300); 310 311 /* 312 * The RESX is active low (GPIO_ACTIVE_LOW). 313 * DEASSERT (value = 0) the reset_gpio to enable the chip 314 */ 315 gpiod_set_value_cansleep(priv->reset_gpio, 0); 316 317 /* wait for encoder clocks to stabilize */ 318 usleep_range(1000, 2000); 319 320 priv->enabled = true; 321 } 322 323 static void tc358768_hw_disable(struct tc358768_priv *priv) 324 { 325 int ret; 326 327 if (!priv->enabled) 328 return; 329 330 /* 331 * The RESX is active low (GPIO_ACTIVE_LOW). 332 * ASSERT (value = 1) the reset_gpio to disable the chip 333 */ 334 gpiod_set_value_cansleep(priv->reset_gpio, 1); 335 336 ret = regulator_bulk_disable(ARRAY_SIZE(priv->supplies), 337 priv->supplies); 338 if (ret < 0) 339 dev_err(priv->dev, "error disabling regulators (%d)\n", ret); 340 341 clk_disable_unprepare(priv->refclk); 342 343 priv->enabled = false; 344 } 345 346 static u32 tc358768_pll_to_pclk(struct tc358768_priv *priv, u32 pll_clk) 347 { 348 return (u32)div_u64((u64)pll_clk * priv->dsi_lanes, priv->dsi_bpp); 349 } 350 351 static u32 tc358768_pclk_to_pll(struct tc358768_priv *priv, u32 pclk) 352 { 353 return (u32)div_u64((u64)pclk * priv->dsi_bpp, priv->dsi_lanes); 354 } 355 356 static int tc358768_calc_pll(struct tc358768_priv *priv, 357 const struct drm_display_mode *mode, 358 bool verify_only) 359 { 360 static const u32 frs_limits[] = { 361 1000000000, 362 500000000, 363 250000000, 364 125000000, 365 62500000 366 }; 367 unsigned long refclk; 368 u32 prd, target_pll, i, max_pll, min_pll; 369 u32 frs, best_diff, best_pll, best_prd, best_fbd; 370 371 target_pll = tc358768_pclk_to_pll(priv, mode->clock * 1000); 372 373 /* pll_clk = RefClk * FBD / PRD * (1 / (2^FRS)) */ 374 375 for (i = 0; i < ARRAY_SIZE(frs_limits); i++) 376 if (target_pll >= frs_limits[i]) 377 break; 378 379 if (i == ARRAY_SIZE(frs_limits) || i == 0) 380 return -EINVAL; 381 382 frs = i - 1; 383 max_pll = frs_limits[i - 1]; 384 min_pll = frs_limits[i]; 385 386 refclk = clk_get_rate(priv->refclk); 387 388 best_diff = UINT_MAX; 389 best_pll = 0; 390 best_prd = 0; 391 best_fbd = 0; 392 393 for (prd = 1; prd <= 16; ++prd) { 394 u32 divisor = prd * (1 << frs); 395 u32 fbd; 396 397 for (fbd = 1; fbd <= 512; ++fbd) { 398 u32 pll, diff, pll_in; 399 400 pll = (u32)div_u64((u64)refclk * fbd, divisor); 401 402 if (pll >= max_pll || pll < min_pll) 403 continue; 404 405 pll_in = (u32)div_u64((u64)refclk, prd); 406 if (pll_in < 4000000) 407 continue; 408 409 diff = max(pll, target_pll) - min(pll, target_pll); 410 411 if (diff < best_diff) { 412 best_diff = diff; 413 best_pll = pll; 414 best_prd = prd; 415 best_fbd = fbd; 416 417 if (best_diff == 0) 418 goto found; 419 } 420 } 421 } 422 423 if (best_diff == UINT_MAX) { 424 dev_err(priv->dev, "could not find suitable PLL setup\n"); 425 return -EINVAL; 426 } 427 428 found: 429 if (verify_only) 430 return 0; 431 432 priv->fbd = best_fbd; 433 priv->prd = best_prd; 434 priv->frs = frs; 435 priv->dsiclk = best_pll / 2; 436 priv->pclk = mode->clock * 1000; 437 438 return 0; 439 } 440 441 static int tc358768_dsi_host_attach(struct mipi_dsi_host *host, 442 struct mipi_dsi_device *dev) 443 { 444 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 445 struct drm_bridge *bridge; 446 struct drm_panel *panel; 447 struct device_node *ep; 448 int ret; 449 450 if (dev->lanes > 4) { 451 dev_err(priv->dev, "unsupported number of data lanes(%u)\n", 452 dev->lanes); 453 return -EINVAL; 454 } 455 456 /* 457 * tc358768 supports both Video and Pulse mode, but the driver only 458 * implements Video (event) mode currently 459 */ 460 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) { 461 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n"); 462 return -ENOTSUPP; 463 } 464 465 /* 466 * tc358768 supports RGB888, RGB666, RGB666_PACKED and RGB565, but only 467 * RGB888 is verified. 468 */ 469 if (dev->format != MIPI_DSI_FMT_RGB888) { 470 dev_warn(priv->dev, "Only MIPI_DSI_FMT_RGB888 tested!\n"); 471 return -ENOTSUPP; 472 } 473 474 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel, 475 &bridge); 476 if (ret) 477 return ret; 478 479 if (panel) { 480 bridge = drm_panel_bridge_add_typed(panel, 481 DRM_MODE_CONNECTOR_DSI); 482 drm_panel_put(panel); 483 if (IS_ERR(bridge)) 484 return PTR_ERR(bridge); 485 486 bridge->pre_enable_prev_first = true; 487 } 488 489 priv->output.dev = dev; 490 priv->output.bridge = bridge; 491 priv->output.panel = panel; 492 493 priv->dsi_lanes = dev->lanes; 494 priv->dsi_bpp = mipi_dsi_pixel_format_to_bpp(dev->format); 495 496 /* get input ep (port0/endpoint0) */ 497 ret = -EINVAL; 498 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0); 499 if (ep) { 500 ret = of_property_read_u32(ep, "bus-width", &priv->pd_lines); 501 if (ret) 502 ret = of_property_read_u32(ep, "data-lines", &priv->pd_lines); 503 504 of_node_put(ep); 505 } 506 507 if (ret) 508 priv->pd_lines = priv->dsi_bpp; 509 510 drm_bridge_add(&priv->bridge); 511 512 return 0; 513 } 514 515 static int tc358768_dsi_host_detach(struct mipi_dsi_host *host, 516 struct mipi_dsi_device *dev) 517 { 518 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 519 520 drm_bridge_remove(&priv->bridge); 521 if (priv->output.panel) 522 drm_panel_bridge_remove(priv->output.bridge); 523 524 return 0; 525 } 526 527 static ssize_t tc358768_dsi_host_transfer(struct mipi_dsi_host *host, 528 const struct mipi_dsi_msg *msg) 529 { 530 struct tc358768_priv *priv = dsi_host_to_tc358768(host); 531 struct mipi_dsi_packet packet; 532 int ret; 533 534 if (!priv->enabled) { 535 dev_err(priv->dev, "Bridge is not enabled\n"); 536 return -ENODEV; 537 } 538 539 if (msg->rx_len) { 540 dev_warn(priv->dev, "MIPI rx is not supported\n"); 541 return -ENOTSUPP; 542 } 543 544 if (msg->tx_len > 1024) { 545 dev_warn(priv->dev, "Maximum 1024 byte MIPI tx is supported\n"); 546 return -EINVAL; 547 } 548 549 if (msg->tx_len > 8) { 550 u32 confctl; 551 552 tc358768_read(priv, TC358768_CONFCTL, &confctl); 553 554 if (confctl & BIT(6)) { 555 dev_warn(priv->dev, 556 "Video is currently active. Unable to transmit long command\n"); 557 return -EBUSY; 558 } 559 } 560 561 ret = mipi_dsi_create_packet(&packet, msg); 562 if (ret) 563 return ret; 564 565 if (mipi_dsi_packet_format_is_short(msg->type)) { 566 tc358768_write(priv, TC358768_DSICMD_TYPE, 567 (0x10 << 8) | (packet.header[0] & 0x3f)); 568 tc358768_write(priv, TC358768_DSICMD_WC, 0); 569 tc358768_write(priv, TC358768_DSICMD_WD0, 570 (packet.header[2] << 8) | packet.header[1]); 571 tc358768_dsicmd_tx(priv); 572 } else if (packet.payload_length <= 8) { 573 tc358768_write(priv, TC358768_DSICMD_TYPE, 574 (0x40 << 8) | (packet.header[0] & 0x3f)); 575 tc358768_write(priv, TC358768_DSICMD_WC, packet.payload_length); 576 577 for (int i = 0; i < packet.payload_length; i += 2) { 578 u16 val = packet.payload[i]; 579 580 if (i + 1 < packet.payload_length) 581 val |= packet.payload[i + 1] << 8; 582 tc358768_write(priv, TC358768_DSICMD_WD0 + i, val); 583 } 584 585 tc358768_dsicmd_tx(priv); 586 } else { 587 unsigned long tx_sleep_us; 588 size_t len; 589 590 /* For packets over 8 bytes we need to use the video buffer */ 591 tc358768_write(priv, TC358768_DATAFMT, BIT(0)); /* txdt_en */ 592 tc358768_write(priv, TC358768_DSITX_DT, packet.header[0] & 0x3f); 593 tc358768_write(priv, TC358768_CMDBYTE, packet.payload_length); 594 tc358768_write(priv, TC358768_VBUFCTRL, TC358768_VBUFCTRL_VBUF_EN); 595 596 /* 597 * Write the payload in 2-byte chunks, and pad with zeroes to 598 * align to 4 bytes. 599 */ 600 len = ALIGN(packet.payload_length, 4); 601 602 for (int i = 0; i < len; i += 2) { 603 u16 val = 0; 604 605 if (i < packet.payload_length) 606 val |= packet.payload[i]; 607 if (i + 1 < packet.payload_length) 608 val |= packet.payload[i + 1] << 8; 609 610 tc358768_write(priv, TC358768_DBG_DATA, val); 611 } 612 613 /* Start transmission */ 614 tc358768_write(priv, TC358768_VBUFCTRL, 615 TC358768_VBUFCTRL_VBUF_EN | 616 TC358768_VBUFCTRL_TX_EN | 617 TC358768_VBUFCTRL_MASK); 618 619 /* 620 * The TC358768 spec says to wait until the transmission has 621 * been finished, estimating the sleep time based on the payload 622 * and clock rates. We use a simple safe estimate of 2us per 623 * byte (LP mode transmission). 624 */ 625 tx_sleep_us = packet.payload_length * 2; 626 usleep_range(tx_sleep_us, tx_sleep_us * 2); 627 628 tc358768_write(priv, TC358768_VBUFCTRL, TC358768_VBUFCTRL_MASK); 629 tc358768_write(priv, TC358768_VBUFCTRL, 0); /* Stop transmission */ 630 } 631 632 ret = tc358768_clear_error(priv); 633 if (ret) 634 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 635 else 636 ret = packet.size; 637 638 return ret; 639 } 640 641 static const struct mipi_dsi_host_ops tc358768_dsi_host_ops = { 642 .attach = tc358768_dsi_host_attach, 643 .detach = tc358768_dsi_host_detach, 644 .transfer = tc358768_dsi_host_transfer, 645 }; 646 647 static int tc358768_bridge_attach(struct drm_bridge *bridge, 648 struct drm_encoder *encoder, 649 enum drm_bridge_attach_flags flags) 650 { 651 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 652 653 if (!drm_core_check_feature(bridge->dev, DRIVER_ATOMIC)) { 654 dev_err(priv->dev, "needs atomic updates support\n"); 655 return -ENOTSUPP; 656 } 657 658 return drm_bridge_attach(encoder, priv->output.bridge, bridge, 659 flags); 660 } 661 662 static enum drm_mode_status 663 tc358768_bridge_mode_valid(struct drm_bridge *bridge, 664 const struct drm_display_info *info, 665 const struct drm_display_mode *mode) 666 { 667 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 668 669 if (tc358768_calc_pll(priv, mode, true)) 670 return MODE_CLOCK_RANGE; 671 672 return MODE_OK; 673 } 674 675 static void tc358768_bridge_atomic_disable(struct drm_bridge *bridge, 676 struct drm_atomic_commit *state) 677 { 678 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 679 int ret; 680 681 /* set FrmStop */ 682 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(15), BIT(15)); 683 684 /* wait at least for one frame */ 685 msleep(50); 686 687 /* clear PP_en */ 688 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), 0); 689 690 /* set RstPtr */ 691 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), BIT(14)); 692 693 ret = tc358768_clear_error(priv); 694 if (ret) 695 dev_warn(priv->dev, "Software disable failed: %d\n", ret); 696 } 697 698 static void tc358768_bridge_atomic_post_disable(struct drm_bridge *bridge, 699 struct drm_atomic_commit *state) 700 { 701 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 702 703 tc358768_hw_disable(priv); 704 } 705 706 static int tc358768_setup_pll(struct tc358768_priv *priv, 707 const struct drm_display_mode *mode) 708 { 709 u32 fbd, prd, frs; 710 int ret; 711 712 ret = tc358768_calc_pll(priv, mode, false); 713 if (ret) { 714 dev_err(priv->dev, "PLL calculation failed: %d\n", ret); 715 return ret; 716 } 717 718 fbd = priv->fbd; 719 prd = priv->prd; 720 frs = priv->frs; 721 722 dev_dbg(priv->dev, "PLL: refclk %lu, fbd %u, prd %u, frs %u\n", 723 clk_get_rate(priv->refclk), fbd, prd, frs); 724 dev_dbg(priv->dev, "PLL: pll_clk: %u, DSIClk %u, HSByteClk %u\n", 725 priv->dsiclk * 2, priv->dsiclk, priv->dsiclk / 4); 726 dev_dbg(priv->dev, "PLL: pclk %u (panel: %u)\n", 727 tc358768_pll_to_pclk(priv, priv->dsiclk * 2), 728 mode->clock * 1000); 729 730 /* PRD[15:12] FBD[8:0] */ 731 tc358768_write(priv, TC358768_PLLCTL0, ((prd - 1) << 12) | (fbd - 1)); 732 733 /* FRS[11:10] LBWS[9:8] CKEN[4] RESETB[1] EN[0] */ 734 tc358768_write(priv, TC358768_PLLCTL1, 735 (frs << 10) | (0x2 << 8) | BIT(1) | BIT(0)); 736 737 /* wait for lock */ 738 usleep_range(1000, 2000); 739 740 /* FRS[11:10] LBWS[9:8] CKEN[4] PLL_CKEN[4] RESETB[1] EN[0] */ 741 tc358768_write(priv, TC358768_PLLCTL1, 742 (frs << 10) | (0x2 << 8) | BIT(4) | BIT(1) | BIT(0)); 743 744 return tc358768_clear_error(priv); 745 } 746 747 static u32 tc358768_ns_to_cnt(u32 ns, u32 period_ps) 748 { 749 return DIV_ROUND_UP(ns * 1000, period_ps); 750 } 751 752 static u32 tc358768_ps_to_ns(u32 ps) 753 { 754 return ps / 1000; 755 } 756 757 static u32 tc358768_dpi_to_ns(u32 val, u32 pclk) 758 { 759 return (u32)div_u64((u64)val * NANO, pclk); 760 } 761 762 /* Convert value in DPI pixel clock units to DSI byte count */ 763 static u32 tc358768_dpi_to_dsi_bytes(struct tc358768_priv *priv, u32 val) 764 { 765 u64 m = (u64)val * priv->dsiclk / 4 * priv->dsi_lanes; 766 u64 n = priv->pclk; 767 768 return (u32)div_u64(m + n - 1, n); 769 } 770 771 static u32 tc358768_dsi_bytes_to_ns(struct tc358768_priv *priv, u32 val) 772 { 773 u64 m = (u64)val * NANO; 774 u64 n = priv->dsiclk / 4 * priv->dsi_lanes; 775 776 return (u32)div_u64(m, n); 777 } 778 779 static void tc358768_bridge_atomic_pre_enable(struct drm_bridge *bridge, 780 struct drm_atomic_commit *state) 781 { 782 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 783 struct mipi_dsi_device *dsi_dev = priv->output.dev; 784 u32 val, mask, val2, lptxcnt, hact; 785 s32 raw_val; 786 struct drm_crtc_state *crtc_state; 787 struct drm_connector_state *conn_state; 788 struct drm_connector *connector; 789 const struct drm_display_mode *mode; 790 u32 hsbyteclk_ps, dsiclk_ps, ui_ps; 791 u32 dsiclk, hsbyteclk; 792 int ret, i; 793 struct videomode vm; 794 struct device *dev = priv->dev; 795 /* In pixelclock units */ 796 u32 dpi_htot, dpi_data_start; 797 /* In byte units */ 798 u32 dsi_dpi_htot, dsi_dpi_data_start; 799 u32 dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp; 800 const u32 dsi_hss = 4; /* HSS is a short packet (4 bytes) */ 801 /* In hsbyteclk units */ 802 u32 dsi_vsdly; 803 const u32 internal_dly = 40; 804 805 tc358768_hw_enable(priv); 806 807 ret = tc358768_sw_reset(priv); 808 if (ret) { 809 dev_err(dev, "Software reset failed: %d\n", ret); 810 tc358768_hw_disable(priv); 811 return; 812 } 813 814 /* Release RstPtr so that the video buffer can be used for DSI commands */ 815 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(14), 0); 816 817 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 818 conn_state = drm_atomic_get_new_connector_state(state, connector); 819 crtc_state = drm_atomic_get_new_crtc_state(state, conn_state->crtc); 820 mode = &crtc_state->adjusted_mode; 821 ret = tc358768_setup_pll(priv, mode); 822 if (ret) { 823 dev_err(dev, "PLL setup failed: %d\n", ret); 824 tc358768_hw_disable(priv); 825 return; 826 } 827 828 drm_display_mode_to_videomode(mode, &vm); 829 830 dsiclk = priv->dsiclk; 831 hsbyteclk = dsiclk / 4; 832 833 switch (dsi_dev->format) { 834 case MIPI_DSI_FMT_RGB888: 835 hact = vm.hactive * 3; 836 break; 837 case MIPI_DSI_FMT_RGB666: 838 hact = vm.hactive * 3; 839 break; 840 841 case MIPI_DSI_FMT_RGB666_PACKED: 842 hact = vm.hactive * 18 / 8; 843 break; 844 845 case MIPI_DSI_FMT_RGB565: 846 hact = vm.hactive * 2; 847 break; 848 default: 849 dev_err(dev, "Invalid data format (%u)\n", 850 dsi_dev->format); 851 tc358768_hw_disable(priv); 852 return; 853 } 854 855 /* 856 * There are three important things to make TC358768 work correctly, 857 * which are not trivial to manage: 858 * 859 * 1. Keep the DPI line-time and the DSI line-time as close to each 860 * other as possible. 861 * 2. TC358768 goes to LP mode after each line's active area. The DSI 862 * HFP period has to be long enough for entering and exiting LP mode. 863 * But it is not clear how to calculate this. 864 * 3. VSDly (video start delay) has to be long enough to ensure that the 865 * DSI TX does not start transmitting until we have started receiving 866 * pixel data from the DPI input. It is not clear how to calculate 867 * this either. 868 */ 869 870 dpi_htot = vm.hactive + vm.hfront_porch + vm.hsync_len + vm.hback_porch; 871 dpi_data_start = vm.hsync_len + vm.hback_porch; 872 873 dev_dbg(dev, "dpi horiz timing (pclk): %u + %u + %u + %u = %u\n", 874 vm.hsync_len, vm.hback_porch, vm.hactive, vm.hfront_porch, 875 dpi_htot); 876 877 dev_dbg(dev, "dpi horiz timing (ns): %u + %u + %u + %u = %u\n", 878 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock), 879 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock), 880 tc358768_dpi_to_ns(vm.hactive, vm.pixelclock), 881 tc358768_dpi_to_ns(vm.hfront_porch, vm.pixelclock), 882 tc358768_dpi_to_ns(dpi_htot, vm.pixelclock)); 883 884 dev_dbg(dev, "dpi data start (ns): %u + %u = %u\n", 885 tc358768_dpi_to_ns(vm.hsync_len, vm.pixelclock), 886 tc358768_dpi_to_ns(vm.hback_porch, vm.pixelclock), 887 tc358768_dpi_to_ns(dpi_data_start, vm.pixelclock)); 888 889 dsi_dpi_htot = tc358768_dpi_to_dsi_bytes(priv, dpi_htot); 890 dsi_dpi_data_start = tc358768_dpi_to_dsi_bytes(priv, dpi_data_start); 891 892 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 893 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, vm.hsync_len); 894 dsi_hbp = tc358768_dpi_to_dsi_bytes(priv, vm.hback_porch); 895 } else { 896 /* HBP is included in HSW in event mode */ 897 dsi_hbp = 0; 898 dsi_hsw = tc358768_dpi_to_dsi_bytes(priv, 899 vm.hsync_len + 900 vm.hback_porch); 901 902 /* 903 * The pixel packet includes the actual pixel data, and: 904 * DSI packet header = 4 bytes 905 * DCS code = 1 byte 906 * DSI packet footer = 2 bytes 907 */ 908 dsi_hact = hact + 4 + 1 + 2; 909 910 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; 911 912 /* 913 * Here we should check if HFP is long enough for entering LP 914 * and exiting LP, but it's not clear how to calculate that. 915 * Instead, this is a naive algorithm that just adjusts the HFP 916 * and HSW so that HFP is (at least) roughly 2/3 of the total 917 * blanking time. 918 */ 919 if (dsi_hfp < (dsi_hfp + dsi_hsw + dsi_hss) * 2 / 3) { 920 u32 old_hfp = dsi_hfp; 921 u32 old_hsw = dsi_hsw; 922 u32 tot = dsi_hfp + dsi_hsw + dsi_hss; 923 924 dsi_hsw = tot / 3; 925 926 /* 927 * Seems like sometimes HSW has to be divisible by num-lanes, but 928 * not always... 929 */ 930 dsi_hsw = roundup(dsi_hsw, priv->dsi_lanes); 931 932 dsi_hfp = dsi_dpi_htot - dsi_hact - dsi_hsw - dsi_hss; 933 934 dev_dbg(dev, 935 "hfp too short, adjusting dsi hfp and dsi hsw from %u, %u to %u, %u\n", 936 old_hfp, old_hsw, dsi_hfp, dsi_hsw); 937 } 938 939 dev_dbg(dev, 940 "dsi horiz timing (bytes): %u, %u + %u + %u + %u = %u\n", 941 dsi_hss, dsi_hsw, dsi_hbp, dsi_hact, dsi_hfp, 942 dsi_hss + dsi_hsw + dsi_hbp + dsi_hact + dsi_hfp); 943 944 dev_dbg(dev, "dsi horiz timing (ns): %u + %u + %u + %u + %u = %u\n", 945 tc358768_dsi_bytes_to_ns(priv, dsi_hss), 946 tc358768_dsi_bytes_to_ns(priv, dsi_hsw), 947 tc358768_dsi_bytes_to_ns(priv, dsi_hbp), 948 tc358768_dsi_bytes_to_ns(priv, dsi_hact), 949 tc358768_dsi_bytes_to_ns(priv, dsi_hfp), 950 tc358768_dsi_bytes_to_ns(priv, dsi_hss + dsi_hsw + 951 dsi_hbp + dsi_hact + dsi_hfp)); 952 } 953 954 /* VSDly calculation */ 955 956 /* Start with the HW internal delay */ 957 dsi_vsdly = internal_dly; 958 959 /* Convert to byte units as the other variables are in byte units */ 960 dsi_vsdly *= priv->dsi_lanes; 961 962 /* Do we need more delay, in addition to the internal? */ 963 if (dsi_dpi_data_start > dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp) { 964 dsi_vsdly = dsi_dpi_data_start - dsi_hss - dsi_hsw - dsi_hbp; 965 dsi_vsdly = roundup(dsi_vsdly, priv->dsi_lanes); 966 } 967 968 dev_dbg(dev, "dsi data start (bytes) %u + %u + %u + %u = %u\n", 969 dsi_vsdly, dsi_hss, dsi_hsw, dsi_hbp, 970 dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp); 971 972 dev_dbg(dev, "dsi data start (ns) %u + %u + %u + %u = %u\n", 973 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly), 974 tc358768_dsi_bytes_to_ns(priv, dsi_hss), 975 tc358768_dsi_bytes_to_ns(priv, dsi_hsw), 976 tc358768_dsi_bytes_to_ns(priv, dsi_hbp), 977 tc358768_dsi_bytes_to_ns(priv, dsi_vsdly + dsi_hss + dsi_hsw + dsi_hbp)); 978 979 /* Convert back to hsbyteclk */ 980 dsi_vsdly /= priv->dsi_lanes; 981 982 /* 983 * The docs say that there is an internal delay of 40 cycles. 984 * However, we get underflows if we follow that rule. If we 985 * instead ignore the internal delay, things work. So either 986 * the docs are wrong or the calculations are wrong. 987 * 988 * As a temporary fix, add the internal delay here, to counter 989 * the subtraction when writing the register. 990 */ 991 dsi_vsdly += internal_dly; 992 993 /* Clamp to the register max */ 994 if (dsi_vsdly - internal_dly > 0x3ff) { 995 dev_warn(dev, "VSDly too high, underflows likely\n"); 996 dsi_vsdly = 0x3ff + internal_dly; 997 } 998 999 /* VSDly[9:0] */ 1000 tc358768_write(priv, TC358768_VSDLY, dsi_vsdly - internal_dly); 1001 1002 /* Enable D-PHY (HiZ->LP11) */ 1003 tc358768_write(priv, TC358768_CLW_CNTRL, 0x0000); 1004 /* Enable lanes */ 1005 for (i = 0; i < dsi_dev->lanes; i++) 1006 tc358768_write(priv, TC358768_D0W_CNTRL + i * 4, 0x0000); 1007 1008 /* DSI Timings */ 1009 hsbyteclk_ps = (u32)div_u64(PICO, hsbyteclk); 1010 dsiclk_ps = (u32)div_u64(PICO, dsiclk); 1011 ui_ps = dsiclk_ps / 2; 1012 dev_dbg(dev, "dsiclk: %u ps, ui %u ps, hsbyteclk %u ps\n", dsiclk_ps, 1013 ui_ps, hsbyteclk_ps); 1014 1015 /* LP11 > 100us for D-PHY Rx Init */ 1016 val = tc358768_ns_to_cnt(100 * 1000, hsbyteclk_ps) - 1; 1017 dev_dbg(dev, "LINEINITCNT: %u\n", val); 1018 tc358768_write(priv, TC358768_LINEINITCNT, val); 1019 1020 /* LPTimeCnt > 50ns */ 1021 val = tc358768_ns_to_cnt(50, hsbyteclk_ps) - 1; 1022 lptxcnt = val; 1023 dev_dbg(dev, "LPTXTIMECNT: %u\n", val); 1024 tc358768_write(priv, TC358768_LPTXTIMECNT, val); 1025 1026 /* 38ns < TCLK_PREPARE < 95ns */ 1027 val = tc358768_ns_to_cnt(65, hsbyteclk_ps) - 1; 1028 dev_dbg(dev, "TCLK_PREPARECNT %u\n", val); 1029 /* TCLK_PREPARE + TCLK_ZERO > 300ns */ 1030 val2 = tc358768_ns_to_cnt(300 - tc358768_ps_to_ns(2 * ui_ps), 1031 hsbyteclk_ps) - 2; 1032 dev_dbg(dev, "TCLK_ZEROCNT %u\n", val2); 1033 val |= val2 << 8; 1034 tc358768_write(priv, TC358768_TCLK_HEADERCNT, val); 1035 1036 /* TCLK_TRAIL > 60ns AND TEOT <= 105 ns + 12*UI */ 1037 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(2 * ui_ps), hsbyteclk_ps) - 5; 1038 val = clamp(raw_val, 0, 127); 1039 dev_dbg(dev, "TCLK_TRAILCNT: %u\n", val); 1040 tc358768_write(priv, TC358768_TCLK_TRAILCNT, val); 1041 1042 /* 40ns + 4*UI < THS_PREPARE < 85ns + 6*UI */ 1043 val = 50 + tc358768_ps_to_ns(4 * ui_ps); 1044 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) - 1; 1045 dev_dbg(dev, "THS_PREPARECNT %u\n", val); 1046 /* THS_PREPARE + THS_ZERO > 145ns + 10*UI */ 1047 raw_val = tc358768_ns_to_cnt(145 - tc358768_ps_to_ns(3 * ui_ps), hsbyteclk_ps) - 10; 1048 val2 = clamp(raw_val, 0, 127); 1049 dev_dbg(dev, "THS_ZEROCNT %u\n", val2); 1050 val |= val2 << 8; 1051 tc358768_write(priv, TC358768_THS_HEADERCNT, val); 1052 1053 /* TWAKEUP > 1ms in lptxcnt steps */ 1054 val = tc358768_ns_to_cnt(1020000, hsbyteclk_ps); 1055 val = val / (lptxcnt + 1) - 1; 1056 dev_dbg(dev, "TWAKEUP: %u\n", val); 1057 tc358768_write(priv, TC358768_TWAKEUP, val); 1058 1059 /* TCLK_POSTCNT > 60ns + 52*UI */ 1060 val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(52 * ui_ps), 1061 hsbyteclk_ps) - 3; 1062 dev_dbg(dev, "TCLK_POSTCNT: %u\n", val); 1063 tc358768_write(priv, TC358768_TCLK_POSTCNT, val); 1064 1065 /* max(60ns + 4*UI, 8*UI) < THS_TRAILCNT < 105ns + 12*UI */ 1066 raw_val = tc358768_ns_to_cnt(60 + tc358768_ps_to_ns(18 * ui_ps), 1067 hsbyteclk_ps) - 4; 1068 val = clamp(raw_val, 0, 15); 1069 dev_dbg(dev, "THS_TRAILCNT: %u\n", val); 1070 tc358768_write(priv, TC358768_THS_TRAILCNT, val); 1071 1072 val = BIT(0); 1073 for (i = 0; i < dsi_dev->lanes; i++) 1074 val |= BIT(i + 1); 1075 tc358768_write(priv, TC358768_HSTXVREGEN, val); 1076 1077 tc358768_write(priv, TC358768_TXOPTIONCNTRL, 1078 (dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? 0 : BIT(0)); 1079 1080 /* TXTAGOCNT[26:16] RXTASURECNT[10:0] */ 1081 val = tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps * 4); 1082 val = tc358768_ns_to_cnt(val, hsbyteclk_ps) / 4 - 1; 1083 dev_dbg(dev, "TXTAGOCNT: %u\n", val); 1084 val2 = tc358768_ns_to_cnt(tc358768_ps_to_ns((lptxcnt + 1) * hsbyteclk_ps), 1085 hsbyteclk_ps) - 2; 1086 dev_dbg(dev, "RXTASURECNT: %u\n", val2); 1087 val = val << 16 | val2; 1088 tc358768_write(priv, TC358768_BTACNTRL1, val); 1089 1090 /* START[0] */ 1091 tc358768_write(priv, TC358768_STARTCNTRL, 1); 1092 1093 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 1094 /* Set pulse mode */ 1095 tc358768_write(priv, TC358768_DSI_EVENT, 0); 1096 1097 /* vact */ 1098 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); 1099 1100 /* vsw */ 1101 tc358768_write(priv, TC358768_DSI_VSW, vm.vsync_len); 1102 1103 /* vbp */ 1104 tc358768_write(priv, TC358768_DSI_VBPR, vm.vback_porch); 1105 } else { 1106 /* Set event mode */ 1107 tc358768_write(priv, TC358768_DSI_EVENT, 1); 1108 1109 /* vact */ 1110 tc358768_write(priv, TC358768_DSI_VACT, vm.vactive); 1111 1112 /* vsw (+ vbp) */ 1113 tc358768_write(priv, TC358768_DSI_VSW, 1114 vm.vsync_len + vm.vback_porch); 1115 1116 /* vbp (not used in event mode) */ 1117 tc358768_write(priv, TC358768_DSI_VBPR, 0); 1118 } 1119 1120 /* hsw (bytes) */ 1121 tc358768_write(priv, TC358768_DSI_HSW, dsi_hsw); 1122 1123 /* hbp (bytes) */ 1124 tc358768_write(priv, TC358768_DSI_HBPR, dsi_hbp); 1125 1126 /* hact (bytes) */ 1127 tc358768_write(priv, TC358768_DSI_HACT, hact); 1128 1129 /* VSYNC polarity */ 1130 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(5), 1131 (mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIT(5) : 0); 1132 1133 /* HSYNC polarity */ 1134 tc358768_update_bits(priv, TC358768_PP_MISC, BIT(0), 1135 (mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIT(0) : 0); 1136 1137 /* Start DSI Tx */ 1138 tc358768_write(priv, TC358768_DSI_START, 0x1); 1139 1140 /* Configure DSI_Control register */ 1141 val = (dsi_dev->lanes - 1) << 1; 1142 1143 if (!(dsi_dev->mode_flags & MIPI_DSI_MODE_LPM)) 1144 val |= TC358768_DSI_CONTROL_TXMD; 1145 1146 if (!(dsi_dev->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)) 1147 val |= TC358768_DSI_CONTROL_HSCKMD; 1148 1149 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 1150 val |= TC358768_DSI_CONTROL_EOTDIS; 1151 1152 mask = TC358768_DSI_CONTROL_TXMD | TC358768_DSI_CONTROL_HSCKMD | 1153 0x3 << 1 | TC358768_DSI_CONTROL_EOTDIS; 1154 1155 tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, mask, val); 1156 1157 tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, 1158 TC358768_DSI_CONTROL_DSI_MODE, 0); 1159 1160 ret = tc358768_clear_error(priv); 1161 if (ret) 1162 dev_err(dev, "Bridge pre_enable failed: %d\n", ret); 1163 } 1164 1165 static void tc358768_config_video_format(struct tc358768_priv *priv) 1166 { 1167 struct mipi_dsi_device *dsi_dev = priv->output.dev; 1168 u32 val, data_type; 1169 1170 /* Data Format Control Register */ 1171 val = BIT(2) | BIT(1) | BIT(0); /* rdswap_en | dsitx_en | txdt_en */ 1172 switch (dsi_dev->format) { 1173 case MIPI_DSI_FMT_RGB888: 1174 val |= (0x3 << 4); 1175 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_24; 1176 break; 1177 case MIPI_DSI_FMT_RGB666: 1178 val |= (0x4 << 4); 1179 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_18; 1180 break; 1181 case MIPI_DSI_FMT_RGB666_PACKED: 1182 val |= (0x4 << 4) | BIT(3); 1183 data_type = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 1184 break; 1185 case MIPI_DSI_FMT_RGB565: 1186 val |= (0x5 << 4); 1187 data_type = MIPI_DSI_PACKED_PIXEL_STREAM_16; 1188 break; 1189 default: 1190 dev_err(priv->dev, "Invalid data format (%u)\n", dsi_dev->format); 1191 return; 1192 } 1193 1194 tc358768_write(priv, TC358768_DATAFMT, val); 1195 tc358768_write(priv, TC358768_DSITX_DT, data_type); 1196 } 1197 1198 static void tc358768_bridge_atomic_enable(struct drm_bridge *bridge, 1199 struct drm_atomic_commit *state) 1200 { 1201 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 1202 int ret; 1203 1204 if (!priv->enabled) { 1205 dev_err(priv->dev, "Bridge is not enabled\n"); 1206 return; 1207 } 1208 1209 /* Configure video format registers */ 1210 tc358768_config_video_format(priv); 1211 1212 /* Enable HS mode for video TX */ 1213 tc358768_confw_update_bits(priv, TC358768_DSI_CONTROL, 1214 TC358768_DSI_CONTROL_TXMD, 1215 TC358768_DSI_CONTROL_TXMD); 1216 1217 /* clear FrmStop and RstPtr */ 1218 tc358768_update_bits(priv, TC358768_PP_MISC, 0x3 << 14, 0); 1219 1220 /* set PP_en */ 1221 tc358768_update_bits(priv, TC358768_CONFCTL, BIT(6), BIT(6)); 1222 1223 ret = tc358768_clear_error(priv); 1224 if (ret) 1225 dev_err(priv->dev, "Bridge enable failed: %d\n", ret); 1226 } 1227 1228 #define MAX_INPUT_SEL_FORMATS 1 1229 1230 static u32 * 1231 tc358768_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 1232 struct drm_bridge_state *bridge_state, 1233 struct drm_crtc_state *crtc_state, 1234 struct drm_connector_state *conn_state, 1235 u32 output_fmt, 1236 unsigned int *num_input_fmts) 1237 { 1238 struct tc358768_priv *priv = bridge_to_tc358768(bridge); 1239 u32 *input_fmts; 1240 1241 *num_input_fmts = 0; 1242 1243 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 1244 GFP_KERNEL); 1245 if (!input_fmts) 1246 return NULL; 1247 1248 switch (priv->pd_lines) { 1249 case 16: 1250 input_fmts[0] = MEDIA_BUS_FMT_RGB565_1X16; 1251 break; 1252 case 18: 1253 input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X18; 1254 break; 1255 default: 1256 case 24: 1257 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 1258 break; 1259 } 1260 1261 *num_input_fmts = MAX_INPUT_SEL_FORMATS; 1262 1263 return input_fmts; 1264 } 1265 1266 static bool tc358768_mode_fixup(struct drm_bridge *bridge, 1267 const struct drm_display_mode *mode, 1268 struct drm_display_mode *adjusted_mode) 1269 { 1270 /* Default to positive sync */ 1271 1272 if (!(adjusted_mode->flags & 1273 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 1274 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; 1275 1276 if (!(adjusted_mode->flags & 1277 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 1278 adjusted_mode->flags |= DRM_MODE_FLAG_PVSYNC; 1279 1280 return true; 1281 } 1282 1283 static const struct drm_bridge_funcs tc358768_bridge_funcs = { 1284 .attach = tc358768_bridge_attach, 1285 .mode_valid = tc358768_bridge_mode_valid, 1286 .mode_fixup = tc358768_mode_fixup, 1287 .atomic_pre_enable = tc358768_bridge_atomic_pre_enable, 1288 .atomic_enable = tc358768_bridge_atomic_enable, 1289 .atomic_disable = tc358768_bridge_atomic_disable, 1290 .atomic_post_disable = tc358768_bridge_atomic_post_disable, 1291 1292 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1293 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1294 .atomic_create_state = drm_atomic_helper_bridge_create_state, 1295 .atomic_get_input_bus_fmts = tc358768_atomic_get_input_bus_fmts, 1296 }; 1297 1298 static const struct drm_bridge_timings default_tc358768_timings = { 1299 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 1300 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE 1301 | DRM_BUS_FLAG_DE_HIGH, 1302 }; 1303 1304 static bool tc358768_is_reserved_reg(unsigned int reg) 1305 { 1306 switch (reg) { 1307 case 0x114 ... 0x13f: 1308 case 0x200: 1309 case 0x20c: 1310 case 0x400 ... 0x408: 1311 case 0x41c ... 0x42f: 1312 return true; 1313 default: 1314 return false; 1315 } 1316 } 1317 1318 static bool tc358768_writeable_reg(struct device *dev, unsigned int reg) 1319 { 1320 if (tc358768_is_reserved_reg(reg)) 1321 return false; 1322 1323 switch (reg) { 1324 case TC358768_CHIPID: 1325 case TC358768_FIFOSTATUS: 1326 case TC358768_DSITXSTATUS ... (TC358768_DSITXSTATUS + 2): 1327 case TC358768_DSI_CONTROL ... (TC358768_DSI_INT_ENA + 2): 1328 case TC358768_DSICMD_RDFIFO ... (TC358768_DSI_ERR_HALT + 2): 1329 return false; 1330 default: 1331 return true; 1332 } 1333 } 1334 1335 static bool tc358768_readable_reg(struct device *dev, unsigned int reg) 1336 { 1337 if (tc358768_is_reserved_reg(reg)) 1338 return false; 1339 1340 switch (reg) { 1341 case TC358768_STARTCNTRL: 1342 case TC358768_DSI_CONFW ... (TC358768_DSI_CONFW + 2): 1343 case TC358768_DSI_INT_CLR ... (TC358768_DSI_INT_CLR + 2): 1344 case TC358768_DSI_START ... (TC358768_DSI_START + 2): 1345 case TC358768_DBG_DATA: 1346 return false; 1347 default: 1348 return true; 1349 } 1350 } 1351 1352 static const struct regmap_config tc358768_regmap_config = { 1353 .name = "tc358768", 1354 .reg_bits = 16, 1355 .val_bits = 16, 1356 .max_register = TC358768_DSI_HACT, 1357 .cache_type = REGCACHE_NONE, 1358 .writeable_reg = tc358768_writeable_reg, 1359 .readable_reg = tc358768_readable_reg, 1360 .reg_format_endian = REGMAP_ENDIAN_BIG, 1361 .val_format_endian = REGMAP_ENDIAN_BIG, 1362 }; 1363 1364 static const struct i2c_device_id tc358768_i2c_ids[] = { 1365 { .name = "tc358768" }, 1366 { .name = "tc358778" }, 1367 { } 1368 }; 1369 MODULE_DEVICE_TABLE(i2c, tc358768_i2c_ids); 1370 1371 static const struct of_device_id tc358768_of_ids[] = { 1372 { .compatible = "toshiba,tc358768", }, 1373 { .compatible = "toshiba,tc358778", }, 1374 { } 1375 }; 1376 MODULE_DEVICE_TABLE(of, tc358768_of_ids); 1377 1378 static int tc358768_get_regulators(struct tc358768_priv *priv) 1379 { 1380 int i, ret; 1381 1382 for (i = 0; i < ARRAY_SIZE(priv->supplies); ++i) 1383 priv->supplies[i].supply = tc358768_supplies[i]; 1384 1385 ret = devm_regulator_bulk_get(priv->dev, ARRAY_SIZE(priv->supplies), 1386 priv->supplies); 1387 if (ret < 0) 1388 dev_err(priv->dev, "failed to get regulators: %d\n", ret); 1389 1390 return ret; 1391 } 1392 1393 static int tc358768_i2c_probe(struct i2c_client *client) 1394 { 1395 struct tc358768_priv *priv; 1396 struct device *dev = &client->dev; 1397 struct device_node *np = dev->of_node; 1398 int ret; 1399 1400 if (!np) 1401 return -ENODEV; 1402 1403 priv = devm_drm_bridge_alloc(dev, struct tc358768_priv, bridge, 1404 &tc358768_bridge_funcs); 1405 if (IS_ERR(priv)) 1406 return PTR_ERR(priv); 1407 1408 dev_set_drvdata(dev, priv); 1409 priv->dev = dev; 1410 1411 ret = tc358768_get_regulators(priv); 1412 if (ret) 1413 return ret; 1414 1415 priv->refclk = devm_clk_get(dev, "refclk"); 1416 if (IS_ERR(priv->refclk)) 1417 return PTR_ERR(priv->refclk); 1418 1419 /* 1420 * RESX is low active, to disable tc358768 initially (keep in reset) 1421 * the gpio line must be LOW. This is the ASSERTED state of 1422 * GPIO_ACTIVE_LOW (GPIOD_OUT_HIGH == ASSERTED). 1423 */ 1424 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset", 1425 GPIOD_OUT_HIGH); 1426 if (IS_ERR(priv->reset_gpio)) 1427 return PTR_ERR(priv->reset_gpio); 1428 1429 priv->regmap = devm_regmap_init_i2c(client, &tc358768_regmap_config); 1430 if (IS_ERR(priv->regmap)) { 1431 dev_err(dev, "Failed to init regmap\n"); 1432 return PTR_ERR(priv->regmap); 1433 } 1434 1435 priv->dsi_host.dev = dev; 1436 priv->dsi_host.ops = &tc358768_dsi_host_ops; 1437 1438 priv->bridge.timings = &default_tc358768_timings; 1439 priv->bridge.of_node = np; 1440 1441 i2c_set_clientdata(client, priv); 1442 1443 return mipi_dsi_host_register(&priv->dsi_host); 1444 } 1445 1446 static void tc358768_i2c_remove(struct i2c_client *client) 1447 { 1448 struct tc358768_priv *priv = i2c_get_clientdata(client); 1449 1450 mipi_dsi_host_unregister(&priv->dsi_host); 1451 } 1452 1453 static struct i2c_driver tc358768_driver = { 1454 .driver = { 1455 .name = "tc358768", 1456 .of_match_table = tc358768_of_ids, 1457 }, 1458 .id_table = tc358768_i2c_ids, 1459 .probe = tc358768_i2c_probe, 1460 .remove = tc358768_i2c_remove, 1461 }; 1462 module_i2c_driver(tc358768_driver); 1463 1464 MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); 1465 MODULE_DESCRIPTION("TC358768AXBG/TC358778XBG DSI bridge"); 1466 MODULE_LICENSE("GPL v2"); 1467