1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver 4 * 5 * The TC358767/TC358867/TC9595 can operate in multiple modes. 6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP . 7 * 8 * Copyright (C) 2016 CogentEmbedded Inc 9 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com> 10 * 11 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de> 12 * 13 * Copyright (C) 2016 Zodiac Inflight Innovations 14 * 15 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c 16 * 17 * Copyright (C) 2012 Texas Instruments 18 * Author: Rob Clark <robdclark@gmail.com> 19 */ 20 21 #include <linux/bitfield.h> 22 #include <linux/clk.h> 23 #include <linux/device.h> 24 #include <linux/gpio/consumer.h> 25 #include <linux/i2c.h> 26 #include <linux/kernel.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/regmap.h> 30 #include <linux/slab.h> 31 32 #include <drm/display/drm_dp_helper.h> 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_bridge.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_mipi_dsi.h> 37 #include <drm/drm_of.h> 38 #include <drm/drm_panel.h> 39 #include <drm/drm_print.h> 40 #include <drm/drm_probe_helper.h> 41 42 /* Registers */ 43 44 /* DSI D-PHY Layer registers */ 45 #define D0W_DPHYCONTTX 0x0004 46 #define CLW_DPHYCONTTX 0x0020 47 #define D0W_DPHYCONTRX 0x0024 48 #define D1W_DPHYCONTRX 0x0028 49 #define D2W_DPHYCONTRX 0x002c 50 #define D3W_DPHYCONTRX 0x0030 51 #define COM_DPHYCONTRX 0x0038 52 #define CLW_CNTRL 0x0040 53 #define D0W_CNTRL 0x0044 54 #define D1W_CNTRL 0x0048 55 #define D2W_CNTRL 0x004c 56 #define D3W_CNTRL 0x0050 57 #define TESTMODE_CNTRL 0x0054 58 59 /* PPI layer registers */ 60 #define PPI_STARTPPI 0x0104 /* START control bit */ 61 #define PPI_BUSYPPI 0x0108 /* PPI busy status */ 62 #define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */ 63 #define LPX_PERIOD 3 64 #define PPI_LANEENABLE 0x0134 65 #define PPI_TX_RX_TA 0x013c 66 #define TTA_GET 0x40000 67 #define TTA_SURE 6 68 #define PPI_D0S_ATMR 0x0144 69 #define PPI_D1S_ATMR 0x0148 70 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */ 71 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */ 72 #define PPI_D2S_CLRSIPOCOUNT 0x016c /* Assertion timer for Lane 2 */ 73 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */ 74 #define PPI_START_FUNCTION BIT(0) 75 76 /* DSI layer registers */ 77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */ 78 #define DSI_BUSYDSI 0x0208 /* DSI busy status */ 79 #define DSI_LANEENABLE 0x0210 /* Enables each lane */ 80 #define DSI_RX_START BIT(0) 81 82 /* Lane enable PPI and DSI register bits */ 83 #define LANEENABLE_CLEN BIT(0) 84 #define LANEENABLE_L0EN BIT(1) 85 #define LANEENABLE_L1EN BIT(2) 86 #define LANEENABLE_L2EN BIT(1) 87 #define LANEENABLE_L3EN BIT(2) 88 89 #define DSI_LANESTATUS0 0x0214 /* DSI lane status 0 */ 90 #define DSI_LANESTATUS1 0x0218 /* DSI lane status 1 */ 91 #define DSI_INTSTATUS 0x0220 /* Interrupt Status */ 92 #define DSI_INTMASK 0x0224 /* Interrupt Mask */ 93 #define DSI_INTCLR 0x0228 /* Interrupt Clear */ 94 #define DSI_LPTXTO 0x0230 /* LPTX Time Out Counter */ 95 96 /* DSI General Registers */ 97 #define DSIERRCNT 0x0300 /* DSI Error Count Register */ 98 99 /* DSI Application Layer Registers */ 100 #define APLCTRL 0x0400 /* Application layer Control Register */ 101 #define RDPKTLN 0x0404 /* DSI Read packet Length Register */ 102 103 /* Display Parallel Input Interface */ 104 #define DPIPXLFMT 0x0440 105 #define VS_POL_ACTIVE_LOW (1 << 10) 106 #define HS_POL_ACTIVE_LOW (1 << 9) 107 #define DE_POL_ACTIVE_HIGH (0 << 8) 108 #define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */ 109 #define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */ 110 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */ 111 #define DPI_BPP_RGB888 (0 << 0) 112 #define DPI_BPP_RGB666 (1 << 0) 113 #define DPI_BPP_RGB565 (2 << 0) 114 115 /* Display Parallel Output Interface */ 116 #define POCTRL 0x0448 117 #define POCTRL_S2P BIT(7) 118 #define POCTRL_PCLK_POL BIT(3) 119 #define POCTRL_VS_POL BIT(2) 120 #define POCTRL_HS_POL BIT(1) 121 #define POCTRL_DE_POL BIT(0) 122 123 /* Video Path */ 124 #define VPCTRL0 0x0450 125 #define VSDELAY GENMASK(31, 20) 126 #define OPXLFMT_RGB666 (0 << 8) 127 #define OPXLFMT_RGB888 (1 << 8) 128 #define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */ 129 #define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */ 130 #define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */ 131 #define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */ 132 #define HTIM01 0x0454 133 #define HPW GENMASK(8, 0) 134 #define HBPR GENMASK(24, 16) 135 #define HTIM02 0x0458 136 #define HDISPR GENMASK(10, 0) 137 #define HFPR GENMASK(24, 16) 138 #define VTIM01 0x045c 139 #define VSPR GENMASK(7, 0) 140 #define VBPR GENMASK(23, 16) 141 #define VTIM02 0x0460 142 #define VFPR GENMASK(23, 16) 143 #define VDISPR GENMASK(10, 0) 144 #define VFUEN0 0x0464 145 #define VFUEN BIT(0) /* Video Frame Timing Upload */ 146 147 /* System */ 148 #define TC_IDREG 0x0500 /* Chip ID and Revision ID */ 149 #define SYSBOOT 0x0504 /* System BootStrap Status Register */ 150 #define SYSSTAT 0x0508 /* System Status Register */ 151 #define SYSRSTENB 0x050c /* System Reset/Enable Register */ 152 #define ENBI2C (1 << 0) 153 #define ENBLCD0 (1 << 2) 154 #define ENBBM (1 << 3) 155 #define ENBDSIRX (1 << 4) 156 #define ENBREG (1 << 5) 157 #define ENBHDCP (1 << 8) 158 #define SYSCTRL 0x0510 /* System Control Register */ 159 #define DP0_AUDSRC_NO_INPUT (0 << 3) 160 #define DP0_AUDSRC_I2S_RX (1 << 3) 161 #define DP0_VIDSRC_NO_INPUT (0 << 0) 162 #define DP0_VIDSRC_DSI_RX (1 << 0) 163 #define DP0_VIDSRC_DPI_RX (2 << 0) 164 #define DP0_VIDSRC_COLOR_BAR (3 << 0) 165 #define GPIOM 0x0540 /* GPIO Mode Control Register */ 166 #define GPIOC 0x0544 /* GPIO Direction Control Register */ 167 #define GPIOO 0x0548 /* GPIO Output Register */ 168 #define GPIOI 0x054c /* GPIO Input Register */ 169 #define INTCTL_G 0x0560 /* General Interrupts Control Register */ 170 #define INTSTS_G 0x0564 /* General Interrupts Status Register */ 171 172 #define INT_SYSERR BIT(16) 173 #define INT_GPIO_H(x) (1 << (x == 0 ? 2 : 10)) 174 #define INT_GPIO_LC(x) (1 << (x == 0 ? 3 : 11)) 175 176 #define TEST_INT_C 0x0570 /* Test Interrupts Control Register */ 177 #define TEST_INT_S 0x0574 /* Test Interrupts Status Register */ 178 179 #define INT_GP0_LCNT 0x0584 /* Interrupt GPIO0 Low Count Value Register */ 180 #define INT_GP1_LCNT 0x0588 /* Interrupt GPIO1 Low Count Value Register */ 181 182 /* Control */ 183 #define DP0CTL 0x0600 184 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */ 185 #define EF_EN BIT(5) /* Enable Enhanced Framing */ 186 #define VID_EN BIT(1) /* Video transmission enable */ 187 #define DP_EN BIT(0) /* Enable DPTX function */ 188 189 /* Clocks */ 190 #define DP0_VIDMNGEN0 0x0610 /* DP0 Video Force M Value Register */ 191 #define DP0_VIDMNGEN1 0x0614 /* DP0 Video Force N Value Register */ 192 #define DP0_VMNGENSTATUS 0x0618 /* DP0 Video Current M Value Register */ 193 #define DP0_AUDMNGEN0 0x0628 /* DP0 Audio Force M Value Register */ 194 #define DP0_AUDMNGEN1 0x062c /* DP0 Audio Force N Value Register */ 195 #define DP0_AMNGENSTATUS 0x0630 /* DP0 Audio Current M Value Register */ 196 197 /* Main Channel */ 198 #define DP0_SECSAMPLE 0x0640 199 #define DP0_VIDSYNCDELAY 0x0644 200 #define VID_SYNC_DLY GENMASK(15, 0) 201 #define THRESH_DLY GENMASK(31, 16) 202 203 #define DP0_TOTALVAL 0x0648 204 #define H_TOTAL GENMASK(15, 0) 205 #define V_TOTAL GENMASK(31, 16) 206 #define DP0_STARTVAL 0x064c 207 #define H_START GENMASK(15, 0) 208 #define V_START GENMASK(31, 16) 209 #define DP0_ACTIVEVAL 0x0650 210 #define H_ACT GENMASK(15, 0) 211 #define V_ACT GENMASK(31, 16) 212 213 #define DP0_SYNCVAL 0x0654 214 #define VS_WIDTH GENMASK(30, 16) 215 #define HS_WIDTH GENMASK(14, 0) 216 #define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15) 217 #define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31) 218 #define DP0_MISC 0x0658 219 #define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */ 220 #define MAX_TU_SYMBOL GENMASK(28, 23) 221 #define TU_SIZE GENMASK(21, 16) 222 #define BPC_6 (0 << 5) 223 #define BPC_8 (1 << 5) 224 225 /* AUX channel */ 226 #define DP0_AUXCFG0 0x0660 227 #define DP0_AUXCFG0_BSIZE GENMASK(11, 8) 228 #define DP0_AUXCFG0_ADDR_ONLY BIT(4) 229 #define DP0_AUXCFG1 0x0664 230 #define AUX_RX_FILTER_EN BIT(16) 231 232 #define DP0_AUXADDR 0x0668 233 #define DP0_AUXWDATA(i) (0x066c + (i) * 4) 234 #define DP0_AUXRDATA(i) (0x067c + (i) * 4) 235 #define DP0_AUXSTATUS 0x068c 236 #define AUX_BYTES GENMASK(15, 8) 237 #define AUX_STATUS GENMASK(7, 4) 238 #define AUX_TIMEOUT BIT(1) 239 #define AUX_BUSY BIT(0) 240 #define DP0_AUXI2CADR 0x0698 241 242 /* Link Training */ 243 #define DP0_SRCCTRL 0x06a0 244 #define DP0_SRCCTRL_SCRMBLDIS BIT(13) 245 #define DP0_SRCCTRL_EN810B BIT(12) 246 #define DP0_SRCCTRL_NOTP (0 << 8) 247 #define DP0_SRCCTRL_TP1 (1 << 8) 248 #define DP0_SRCCTRL_TP2 (2 << 8) 249 #define DP0_SRCCTRL_LANESKEW BIT(7) 250 #define DP0_SRCCTRL_SSCG BIT(3) 251 #define DP0_SRCCTRL_LANES_1 (0 << 2) 252 #define DP0_SRCCTRL_LANES_2 (1 << 2) 253 #define DP0_SRCCTRL_BW27 (1 << 1) 254 #define DP0_SRCCTRL_BW162 (0 << 1) 255 #define DP0_SRCCTRL_AUTOCORRECT BIT(0) 256 #define DP0_LTSTAT 0x06d0 257 #define LT_LOOPDONE BIT(13) 258 #define LT_STATUS_MASK (0x1f << 8) 259 #define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4) 260 #define LT_INTERLANE_ALIGN_DONE BIT(3) 261 #define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS) 262 #define DP0_SNKLTCHGREQ 0x06d4 263 #define DP0_LTLOOPCTRL 0x06d8 264 #define DP0_SNKLTCTRL 0x06e4 265 #define DP0_TPATDAT0 0x06e8 /* DP0 Test Pattern bits 29 to 0 */ 266 #define DP0_TPATDAT1 0x06ec /* DP0 Test Pattern bits 59 to 30 */ 267 #define DP0_TPATDAT2 0x06f0 /* DP0 Test Pattern bits 89 to 60 */ 268 #define DP0_TPATDAT3 0x06f4 /* DP0 Test Pattern bits 119 to 90 */ 269 270 #define AUDCFG0 0x0700 /* DP0 Audio Config0 Register */ 271 #define AUDCFG1 0x0704 /* DP0 Audio Config1 Register */ 272 #define AUDIFDATA0 0x0708 /* DP0 Audio Info Frame Bytes 3 to 0 */ 273 #define AUDIFDATA1 0x070c /* DP0 Audio Info Frame Bytes 7 to 4 */ 274 #define AUDIFDATA2 0x0710 /* DP0 Audio Info Frame Bytes 11 to 8 */ 275 #define AUDIFDATA3 0x0714 /* DP0 Audio Info Frame Bytes 15 to 12 */ 276 #define AUDIFDATA4 0x0718 /* DP0 Audio Info Frame Bytes 19 to 16 */ 277 #define AUDIFDATA5 0x071c /* DP0 Audio Info Frame Bytes 23 to 20 */ 278 #define AUDIFDATA6 0x0720 /* DP0 Audio Info Frame Bytes 27 to 24 */ 279 280 #define DP1_SRCCTRL 0x07a0 /* DP1 Control Register */ 281 282 /* PHY */ 283 #define DP_PHY_CTRL 0x0800 284 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */ 285 #define BGREN BIT(25) /* AUX PHY BGR Enable */ 286 #define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */ 287 #define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */ 288 #define PHY_RDY BIT(16) /* PHY Main Channels Ready */ 289 #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */ 290 #define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */ 291 #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */ 292 #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */ 293 #define DP_PHY_CFG_WR 0x0810 /* DP PHY Configuration Test Write Register */ 294 #define DP_PHY_CFG_RD 0x0814 /* DP PHY Configuration Test Read Register */ 295 #define DP0_AUX_PHY_CTRL 0x0820 /* DP0 AUX PHY Control Register */ 296 #define DP0_MAIN_PHY_DBG 0x0840 /* DP0 Main PHY Test Debug Register */ 297 298 /* I2S */ 299 #define I2SCFG 0x0880 /* I2S Audio Config 0 Register */ 300 #define I2SCH0STAT0 0x0888 /* I2S Audio Channel 0 Status Bytes 3 to 0 */ 301 #define I2SCH0STAT1 0x088c /* I2S Audio Channel 0 Status Bytes 7 to 4 */ 302 #define I2SCH0STAT2 0x0890 /* I2S Audio Channel 0 Status Bytes 11 to 8 */ 303 #define I2SCH0STAT3 0x0894 /* I2S Audio Channel 0 Status Bytes 15 to 12 */ 304 #define I2SCH0STAT4 0x0898 /* I2S Audio Channel 0 Status Bytes 19 to 16 */ 305 #define I2SCH0STAT5 0x089c /* I2S Audio Channel 0 Status Bytes 23 to 20 */ 306 #define I2SCH1STAT0 0x08a0 /* I2S Audio Channel 1 Status Bytes 3 to 0 */ 307 #define I2SCH1STAT1 0x08a4 /* I2S Audio Channel 1 Status Bytes 7 to 4 */ 308 #define I2SCH1STAT2 0x08a8 /* I2S Audio Channel 1 Status Bytes 11 to 8 */ 309 #define I2SCH1STAT3 0x08ac /* I2S Audio Channel 1 Status Bytes 15 to 12 */ 310 #define I2SCH1STAT4 0x08b0 /* I2S Audio Channel 1 Status Bytes 19 to 16 */ 311 #define I2SCH1STAT5 0x08b4 /* I2S Audio Channel 1 Status Bytes 23 to 20 */ 312 313 /* PLL */ 314 #define DP0_PLLCTRL 0x0900 315 #define DP1_PLLCTRL 0x0904 /* not defined in DS */ 316 #define PXL_PLLCTRL 0x0908 317 #define PLLUPDATE BIT(2) 318 #define PLLBYP BIT(1) 319 #define PLLEN BIT(0) 320 #define PXL_PLLPARAM 0x0914 321 #define IN_SEL_REFCLK (0 << 14) 322 #define SYS_PLLPARAM 0x0918 323 #define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */ 324 #define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */ 325 #define REF_FREQ_26M (2 << 8) /* 26 MHz */ 326 #define REF_FREQ_13M (3 << 8) /* 13 MHz */ 327 #define SYSCLK_SEL_LSCLK (0 << 4) 328 #define LSCLK_DIV_1 (0 << 0) 329 #define LSCLK_DIV_2 (1 << 0) 330 331 /* Test & Debug */ 332 #define TSTCTL 0x0a00 333 #define COLOR_R GENMASK(31, 24) 334 #define COLOR_G GENMASK(23, 16) 335 #define COLOR_B GENMASK(15, 8) 336 #define ENI2CFILTER BIT(4) 337 #define COLOR_BAR_MODE GENMASK(1, 0) 338 #define COLOR_BAR_MODE_BARS 2 339 #define PLL_DBG 0x0a04 340 341 static bool tc_test_pattern; 342 module_param_named(test, tc_test_pattern, bool, 0644); 343 344 struct tc_edp_link { 345 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 346 unsigned int rate; 347 u8 num_lanes; 348 u8 assr; 349 bool scrambler_dis; 350 bool spread; 351 }; 352 353 struct tc_data { 354 struct device *dev; 355 struct regmap *regmap; 356 struct drm_dp_aux aux; 357 358 struct drm_bridge bridge; 359 struct drm_bridge *panel_bridge; 360 struct drm_connector connector; 361 362 struct mipi_dsi_device *dsi; 363 364 /* link settings */ 365 struct tc_edp_link link; 366 367 /* current mode */ 368 struct drm_display_mode mode; 369 370 u32 rev; 371 u8 assr; 372 373 struct gpio_desc *sd_gpio; 374 struct gpio_desc *reset_gpio; 375 struct clk *refclk; 376 377 /* do we have IRQ */ 378 bool have_irq; 379 380 /* Input connector type, DSI and not DPI. */ 381 bool input_connector_dsi; 382 383 /* HPD pin number (0 or 1) or -ENODEV */ 384 int hpd_pin; 385 }; 386 387 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a) 388 { 389 return container_of(a, struct tc_data, aux); 390 } 391 392 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b) 393 { 394 return container_of(b, struct tc_data, bridge); 395 } 396 397 static inline struct tc_data *connector_to_tc(struct drm_connector *c) 398 { 399 return container_of(c, struct tc_data, connector); 400 } 401 402 static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr, 403 unsigned int cond_mask, 404 unsigned int cond_value, 405 unsigned long sleep_us, u64 timeout_us) 406 { 407 unsigned int val; 408 409 return regmap_read_poll_timeout(tc->regmap, addr, val, 410 (val & cond_mask) == cond_value, 411 sleep_us, timeout_us); 412 } 413 414 static int tc_aux_wait_busy(struct tc_data *tc) 415 { 416 return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000); 417 } 418 419 static int tc_aux_write_data(struct tc_data *tc, const void *data, 420 size_t size) 421 { 422 u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 }; 423 int ret, count = ALIGN(size, sizeof(u32)); 424 425 memcpy(auxwdata, data, size); 426 427 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count); 428 if (ret) 429 return ret; 430 431 return size; 432 } 433 434 static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size) 435 { 436 u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)]; 437 int ret, count = ALIGN(size, sizeof(u32)); 438 439 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count); 440 if (ret) 441 return ret; 442 443 memcpy(data, auxrdata, size); 444 445 return size; 446 } 447 448 static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size) 449 { 450 u32 auxcfg0 = msg->request; 451 452 if (size) 453 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1); 454 else 455 auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY; 456 457 return auxcfg0; 458 } 459 460 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux, 461 struct drm_dp_aux_msg *msg) 462 { 463 struct tc_data *tc = aux_to_tc(aux); 464 size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size); 465 u8 request = msg->request & ~DP_AUX_I2C_MOT; 466 u32 auxstatus; 467 int ret; 468 469 ret = tc_aux_wait_busy(tc); 470 if (ret) 471 return ret; 472 473 switch (request) { 474 case DP_AUX_NATIVE_READ: 475 case DP_AUX_I2C_READ: 476 break; 477 case DP_AUX_NATIVE_WRITE: 478 case DP_AUX_I2C_WRITE: 479 if (size) { 480 ret = tc_aux_write_data(tc, msg->buffer, size); 481 if (ret < 0) 482 return ret; 483 } 484 break; 485 default: 486 return -EINVAL; 487 } 488 489 /* Store address */ 490 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address); 491 if (ret) 492 return ret; 493 /* Start transfer */ 494 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size)); 495 if (ret) 496 return ret; 497 498 ret = tc_aux_wait_busy(tc); 499 if (ret) 500 return ret; 501 502 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus); 503 if (ret) 504 return ret; 505 506 if (auxstatus & AUX_TIMEOUT) 507 return -ETIMEDOUT; 508 /* 509 * For some reason address-only DP_AUX_I2C_WRITE (MOT), still 510 * reports 1 byte transferred in its status. To deal we that 511 * we ignore aux_bytes field if we know that this was an 512 * address-only transfer 513 */ 514 if (size) 515 size = FIELD_GET(AUX_BYTES, auxstatus); 516 msg->reply = FIELD_GET(AUX_STATUS, auxstatus); 517 518 switch (request) { 519 case DP_AUX_NATIVE_READ: 520 case DP_AUX_I2C_READ: 521 if (size) 522 return tc_aux_read_data(tc, msg->buffer, size); 523 break; 524 } 525 526 return size; 527 } 528 529 static const char * const training_pattern1_errors[] = { 530 "No errors", 531 "Aux write error", 532 "Aux read error", 533 "Max voltage reached error", 534 "Loop counter expired error", 535 "res", "res", "res" 536 }; 537 538 static const char * const training_pattern2_errors[] = { 539 "No errors", 540 "Aux write error", 541 "Aux read error", 542 "Clock recovery failed error", 543 "Loop counter expired error", 544 "res", "res", "res" 545 }; 546 547 static u32 tc_srcctrl(struct tc_data *tc) 548 { 549 /* 550 * No training pattern, skew lane 1 data by two LSCLK cycles with 551 * respect to lane 0 data, AutoCorrect Mode = 0 552 */ 553 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B; 554 555 if (tc->link.scrambler_dis) 556 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */ 557 if (tc->link.spread) 558 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */ 559 if (tc->link.num_lanes == 2) 560 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */ 561 if (tc->link.rate != 162000) 562 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */ 563 return reg; 564 } 565 566 static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl) 567 { 568 int ret; 569 570 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN); 571 if (ret) 572 return ret; 573 574 /* Wait for PLL to lock: up to 7.5 ms, depending on refclk */ 575 usleep_range(15000, 20000); 576 577 return 0; 578 } 579 580 static int tc_pxl_pll_calc(struct tc_data *tc, u32 refclk, u32 pixelclock, 581 int *out_best_pixelclock, u32 *out_pxl_pllparam) 582 { 583 int i_pre, best_pre = 1; 584 int i_post, best_post = 1; 585 int div, best_div = 1; 586 int mul, best_mul = 1; 587 int delta, best_delta; 588 int ext_div[] = {1, 2, 3, 5, 7}; 589 int clk_min, clk_max; 590 int best_pixelclock = 0; 591 int vco_hi = 0; 592 u32 pxl_pllparam; 593 594 /* 595 * refclk * mul / (ext_pre_div * pre_div) should be in range: 596 * - DPI ..... 0 to 100 MHz 597 * - (e)DP ... 150 to 650 MHz 598 */ 599 if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) { 600 clk_min = 0; 601 clk_max = 100000000; 602 } else { 603 clk_min = 150000000; 604 clk_max = 650000000; 605 } 606 607 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, 608 refclk); 609 best_delta = pixelclock; 610 /* Loop over all possible ext_divs, skipping invalid configurations */ 611 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) { 612 /* 613 * refclk / ext_pre_div should be in the 1 to 200 MHz range. 614 * We don't allow any refclk > 200 MHz, only check lower bounds. 615 */ 616 if (refclk / ext_div[i_pre] < 1000000) 617 continue; 618 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) { 619 for (div = 1; div <= 16; div++) { 620 u32 clk, iclk; 621 u64 tmp; 622 623 /* PCLK PLL input unit clock ... 6..40 MHz */ 624 iclk = refclk / (div * ext_div[i_pre]); 625 if (iclk < 6000000 || iclk > 40000000) 626 continue; 627 628 tmp = pixelclock * ext_div[i_pre] * 629 ext_div[i_post] * div; 630 do_div(tmp, refclk); 631 mul = tmp; 632 633 /* Check limits */ 634 if ((mul < 1) || (mul > 128)) 635 continue; 636 637 clk = (refclk / ext_div[i_pre] / div) * mul; 638 if ((clk > clk_max) || (clk < clk_min)) 639 continue; 640 641 clk = clk / ext_div[i_post]; 642 delta = clk - pixelclock; 643 644 if (abs(delta) < abs(best_delta)) { 645 best_pre = i_pre; 646 best_post = i_post; 647 best_div = div; 648 best_mul = mul; 649 best_delta = delta; 650 best_pixelclock = clk; 651 } 652 } 653 } 654 } 655 if (best_pixelclock == 0) { 656 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n", 657 pixelclock); 658 return -EINVAL; 659 } 660 661 dev_dbg(tc->dev, "PLL: got %d, delta %d\n", best_pixelclock, best_delta); 662 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, 663 ext_div[best_pre], best_div, best_mul, ext_div[best_post]); 664 665 /* if VCO >= 300 MHz */ 666 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000) 667 vco_hi = 1; 668 /* see DS */ 669 if (best_div == 16) 670 best_div = 0; 671 if (best_mul == 128) 672 best_mul = 0; 673 674 pxl_pllparam = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */ 675 pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */ 676 pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */ 677 pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */ 678 pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */ 679 pxl_pllparam |= best_mul; /* Multiplier for PLL */ 680 681 if (out_best_pixelclock) 682 *out_best_pixelclock = best_pixelclock; 683 684 if (out_pxl_pllparam) 685 *out_pxl_pllparam = pxl_pllparam; 686 687 return 0; 688 } 689 690 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) 691 { 692 u32 pxl_pllparam = 0; 693 int ret; 694 695 ret = tc_pxl_pll_calc(tc, refclk, pixelclock, NULL, &pxl_pllparam); 696 if (ret) 697 return ret; 698 699 /* Power up PLL and switch to bypass */ 700 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN); 701 if (ret) 702 return ret; 703 704 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam); 705 if (ret) 706 return ret; 707 708 /* Force PLL parameter update and disable bypass */ 709 return tc_pllupdate(tc, PXL_PLLCTRL); 710 } 711 712 static int tc_pxl_pll_dis(struct tc_data *tc) 713 { 714 /* Enable PLL bypass, power down PLL */ 715 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP); 716 } 717 718 static int tc_stream_clock_calc(struct tc_data *tc) 719 { 720 /* 721 * If the Stream clock and Link Symbol clock are 722 * asynchronous with each other, the value of M changes over 723 * time. This way of generating link clock and stream 724 * clock is called Asynchronous Clock mode. The value M 725 * must change while the value N stays constant. The 726 * value of N in this Asynchronous Clock mode must be set 727 * to 2^15 or 32,768. 728 * 729 * LSCLK = 1/10 of high speed link clock 730 * 731 * f_STRMCLK = M/N * f_LSCLK 732 * M/N = f_STRMCLK / f_LSCLK 733 * 734 */ 735 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768); 736 } 737 738 static int tc_set_syspllparam(struct tc_data *tc) 739 { 740 unsigned long rate; 741 u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_1; 742 743 rate = clk_get_rate(tc->refclk); 744 switch (rate) { 745 case 38400000: 746 pllparam |= REF_FREQ_38M4; 747 break; 748 case 26000000: 749 pllparam |= REF_FREQ_26M; 750 break; 751 case 19200000: 752 pllparam |= REF_FREQ_19M2; 753 break; 754 case 13000000: 755 pllparam |= REF_FREQ_13M; 756 break; 757 default: 758 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); 759 return -EINVAL; 760 } 761 762 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam); 763 } 764 765 static int tc_aux_link_setup(struct tc_data *tc) 766 { 767 int ret; 768 u32 dp0_auxcfg1; 769 770 /* Setup DP-PHY / PLL */ 771 ret = tc_set_syspllparam(tc); 772 if (ret) 773 goto err; 774 775 ret = regmap_write(tc->regmap, DP_PHY_CTRL, 776 BGREN | PWR_SW_EN | PHY_A0_EN); 777 if (ret) 778 goto err; 779 /* 780 * Initially PLLs are in bypass. Force PLL parameter update, 781 * disable PLL bypass, enable PLL 782 */ 783 ret = tc_pllupdate(tc, DP0_PLLCTRL); 784 if (ret) 785 goto err; 786 787 ret = tc_pllupdate(tc, DP1_PLLCTRL); 788 if (ret) 789 goto err; 790 791 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000); 792 if (ret == -ETIMEDOUT) { 793 dev_err(tc->dev, "Timeout waiting for PHY to become ready"); 794 return ret; 795 } else if (ret) { 796 goto err; 797 } 798 799 /* Setup AUX link */ 800 dp0_auxcfg1 = AUX_RX_FILTER_EN; 801 dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */ 802 dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */ 803 804 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1); 805 if (ret) 806 goto err; 807 808 /* Register DP AUX channel */ 809 tc->aux.name = "TC358767 AUX i2c adapter"; 810 tc->aux.dev = tc->dev; 811 tc->aux.transfer = tc_aux_transfer; 812 drm_dp_aux_init(&tc->aux); 813 814 return 0; 815 err: 816 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret); 817 return ret; 818 } 819 820 static int tc_get_display_props(struct tc_data *tc) 821 { 822 u8 revision, num_lanes; 823 unsigned int rate; 824 int ret; 825 u8 reg; 826 827 /* Read DP Rx Link Capability */ 828 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd, 829 DP_RECEIVER_CAP_SIZE); 830 if (ret < 0) 831 goto err_dpcd_read; 832 833 revision = tc->link.dpcd[DP_DPCD_REV]; 834 rate = drm_dp_max_link_rate(tc->link.dpcd); 835 num_lanes = drm_dp_max_lane_count(tc->link.dpcd); 836 837 if (rate != 162000 && rate != 270000) { 838 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n"); 839 rate = 270000; 840 } 841 842 tc->link.rate = rate; 843 844 if (num_lanes > 2) { 845 dev_dbg(tc->dev, "Falling to 2 lanes\n"); 846 num_lanes = 2; 847 } 848 849 tc->link.num_lanes = num_lanes; 850 851 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®); 852 if (ret < 0) 853 goto err_dpcd_read; 854 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5; 855 856 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®); 857 if (ret < 0) 858 goto err_dpcd_read; 859 860 tc->link.scrambler_dis = false; 861 /* read assr */ 862 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®); 863 if (ret < 0) 864 goto err_dpcd_read; 865 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; 866 867 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", 868 revision >> 4, revision & 0x0f, 869 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps", 870 tc->link.num_lanes, 871 drm_dp_enhanced_frame_cap(tc->link.dpcd) ? 872 "enhanced" : "default"); 873 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n", 874 tc->link.spread ? "0.5%" : "0.0%", 875 tc->link.scrambler_dis ? "disabled" : "enabled"); 876 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", 877 tc->link.assr, tc->assr); 878 879 return 0; 880 881 err_dpcd_read: 882 dev_err(tc->dev, "failed to read DPCD: %d\n", ret); 883 return ret; 884 } 885 886 static int tc_set_common_video_mode(struct tc_data *tc, 887 const struct drm_display_mode *mode) 888 { 889 int left_margin = mode->htotal - mode->hsync_end; 890 int right_margin = mode->hsync_start - mode->hdisplay; 891 int hsync_len = mode->hsync_end - mode->hsync_start; 892 int upper_margin = mode->vtotal - mode->vsync_end; 893 int lower_margin = mode->vsync_start - mode->vdisplay; 894 int vsync_len = mode->vsync_end - mode->vsync_start; 895 int ret; 896 897 dev_dbg(tc->dev, "set mode %dx%d\n", 898 mode->hdisplay, mode->vdisplay); 899 dev_dbg(tc->dev, "H margin %d,%d sync %d\n", 900 left_margin, right_margin, hsync_len); 901 dev_dbg(tc->dev, "V margin %d,%d sync %d\n", 902 upper_margin, lower_margin, vsync_len); 903 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); 904 905 /* 906 * LCD Ctl Frame Size 907 * datasheet is not clear of vsdelay in case of DPI 908 * assume we do not need any delay when DPI is a source of 909 * sync signals 910 */ 911 ret = regmap_write(tc->regmap, VPCTRL0, 912 FIELD_PREP(VSDELAY, right_margin + 10) | 913 OPXLFMT_RGB888 | FRMSYNC_ENABLED | MSF_DISABLED); 914 if (ret) 915 return ret; 916 917 ret = regmap_write(tc->regmap, HTIM01, 918 FIELD_PREP(HBPR, ALIGN(left_margin, 2)) | 919 FIELD_PREP(HPW, ALIGN(hsync_len, 2))); 920 if (ret) 921 return ret; 922 923 ret = regmap_write(tc->regmap, HTIM02, 924 FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) | 925 FIELD_PREP(HFPR, ALIGN(right_margin, 2))); 926 if (ret) 927 return ret; 928 929 ret = regmap_write(tc->regmap, VTIM01, 930 FIELD_PREP(VBPR, upper_margin) | 931 FIELD_PREP(VSPR, vsync_len)); 932 if (ret) 933 return ret; 934 935 ret = regmap_write(tc->regmap, VTIM02, 936 FIELD_PREP(VFPR, lower_margin) | 937 FIELD_PREP(VDISPR, mode->vdisplay)); 938 if (ret) 939 return ret; 940 941 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */ 942 if (ret) 943 return ret; 944 945 /* Test pattern settings */ 946 ret = regmap_write(tc->regmap, TSTCTL, 947 FIELD_PREP(COLOR_R, 120) | 948 FIELD_PREP(COLOR_G, 20) | 949 FIELD_PREP(COLOR_B, 99) | 950 ENI2CFILTER | 951 FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS)); 952 953 return ret; 954 } 955 956 static int tc_set_dpi_video_mode(struct tc_data *tc, 957 const struct drm_display_mode *mode) 958 { 959 u32 value = POCTRL_S2P; 960 961 if (tc->mode.flags & DRM_MODE_FLAG_NHSYNC) 962 value |= POCTRL_HS_POL; 963 964 if (tc->mode.flags & DRM_MODE_FLAG_NVSYNC) 965 value |= POCTRL_VS_POL; 966 967 return regmap_write(tc->regmap, POCTRL, value); 968 } 969 970 static int tc_set_edp_video_mode(struct tc_data *tc, 971 const struct drm_display_mode *mode) 972 { 973 int ret; 974 int vid_sync_dly; 975 int max_tu_symbol; 976 977 int left_margin = mode->htotal - mode->hsync_end; 978 int hsync_len = mode->hsync_end - mode->hsync_start; 979 int upper_margin = mode->vtotal - mode->vsync_end; 980 int vsync_len = mode->vsync_end - mode->vsync_start; 981 u32 dp0_syncval; 982 u32 bits_per_pixel = 24; 983 u32 in_bw, out_bw; 984 u32 dpipxlfmt; 985 986 /* 987 * Recommended maximum number of symbols transferred in a transfer unit: 988 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size, 989 * (output active video bandwidth in bytes)) 990 * Must be less than tu_size. 991 */ 992 993 in_bw = mode->clock * bits_per_pixel / 8; 994 out_bw = tc->link.num_lanes * tc->link.rate; 995 max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw); 996 997 /* DP Main Stream Attributes */ 998 vid_sync_dly = hsync_len + left_margin + mode->hdisplay; 999 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY, 1000 FIELD_PREP(THRESH_DLY, max_tu_symbol) | 1001 FIELD_PREP(VID_SYNC_DLY, vid_sync_dly)); 1002 1003 ret = regmap_write(tc->regmap, DP0_TOTALVAL, 1004 FIELD_PREP(H_TOTAL, mode->htotal) | 1005 FIELD_PREP(V_TOTAL, mode->vtotal)); 1006 if (ret) 1007 return ret; 1008 1009 ret = regmap_write(tc->regmap, DP0_STARTVAL, 1010 FIELD_PREP(H_START, left_margin + hsync_len) | 1011 FIELD_PREP(V_START, upper_margin + vsync_len)); 1012 if (ret) 1013 return ret; 1014 1015 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL, 1016 FIELD_PREP(V_ACT, mode->vdisplay) | 1017 FIELD_PREP(H_ACT, mode->hdisplay)); 1018 if (ret) 1019 return ret; 1020 1021 dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) | 1022 FIELD_PREP(HS_WIDTH, hsync_len); 1023 1024 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1025 dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW; 1026 1027 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1028 dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW; 1029 1030 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval); 1031 if (ret) 1032 return ret; 1033 1034 dpipxlfmt = DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888; 1035 1036 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1037 dpipxlfmt |= VS_POL_ACTIVE_LOW; 1038 1039 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1040 dpipxlfmt |= HS_POL_ACTIVE_LOW; 1041 1042 ret = regmap_write(tc->regmap, DPIPXLFMT, dpipxlfmt); 1043 if (ret) 1044 return ret; 1045 1046 ret = regmap_write(tc->regmap, DP0_MISC, 1047 FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) | 1048 FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) | 1049 BPC_8); 1050 return ret; 1051 } 1052 1053 static int tc_wait_link_training(struct tc_data *tc) 1054 { 1055 u32 value; 1056 int ret; 1057 1058 ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE, 1059 LT_LOOPDONE, 500, 100000); 1060 if (ret) { 1061 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n"); 1062 return ret; 1063 } 1064 1065 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value); 1066 if (ret) 1067 return ret; 1068 1069 return (value >> 8) & 0x7; 1070 } 1071 1072 static int tc_main_link_enable(struct tc_data *tc) 1073 { 1074 struct drm_dp_aux *aux = &tc->aux; 1075 struct device *dev = tc->dev; 1076 u32 dp_phy_ctrl; 1077 u32 value; 1078 int ret; 1079 u8 tmp[DP_LINK_STATUS_SIZE]; 1080 1081 dev_dbg(tc->dev, "link enable\n"); 1082 1083 ret = regmap_read(tc->regmap, DP0CTL, &value); 1084 if (ret) 1085 return ret; 1086 1087 if (WARN_ON(value & DP_EN)) { 1088 ret = regmap_write(tc->regmap, DP0CTL, 0); 1089 if (ret) 1090 return ret; 1091 } 1092 1093 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc)); 1094 if (ret) 1095 return ret; 1096 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */ 1097 ret = regmap_write(tc->regmap, DP1_SRCCTRL, 1098 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | 1099 ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0)); 1100 if (ret) 1101 return ret; 1102 1103 ret = tc_set_syspllparam(tc); 1104 if (ret) 1105 return ret; 1106 1107 /* Setup Main Link */ 1108 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN; 1109 if (tc->link.num_lanes == 2) 1110 dp_phy_ctrl |= PHY_2LANE; 1111 1112 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); 1113 if (ret) 1114 return ret; 1115 1116 /* PLL setup */ 1117 ret = tc_pllupdate(tc, DP0_PLLCTRL); 1118 if (ret) 1119 return ret; 1120 1121 ret = tc_pllupdate(tc, DP1_PLLCTRL); 1122 if (ret) 1123 return ret; 1124 1125 /* Reset/Enable Main Links */ 1126 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST; 1127 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); 1128 usleep_range(100, 200); 1129 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST); 1130 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); 1131 1132 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000); 1133 if (ret) { 1134 dev_err(dev, "timeout waiting for phy become ready"); 1135 return ret; 1136 } 1137 1138 /* Set misc: 8 bits per color */ 1139 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); 1140 if (ret) 1141 return ret; 1142 1143 /* 1144 * ASSR mode 1145 * on TC358767 side ASSR configured through strap pin 1146 * seems there is no way to change this setting from SW 1147 * 1148 * check is tc configured for same mode 1149 */ 1150 if (tc->assr != tc->link.assr) { 1151 dev_dbg(dev, "Trying to set display to ASSR: %d\n", 1152 tc->assr); 1153 /* try to set ASSR on display side */ 1154 tmp[0] = tc->assr; 1155 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]); 1156 if (ret < 0) 1157 goto err_dpcd_read; 1158 /* read back */ 1159 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp); 1160 if (ret < 0) 1161 goto err_dpcd_read; 1162 1163 if (tmp[0] != tc->assr) { 1164 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n", 1165 tc->assr); 1166 /* trying with disabled scrambler */ 1167 tc->link.scrambler_dis = true; 1168 } 1169 } 1170 1171 /* Setup Link & DPRx Config for Training */ 1172 tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate); 1173 tmp[1] = tc->link.num_lanes; 1174 1175 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) 1176 tmp[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 1177 1178 ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, tmp, 2); 1179 if (ret < 0) 1180 goto err_dpcd_write; 1181 1182 /* DOWNSPREAD_CTRL */ 1183 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; 1184 /* MAIN_LINK_CHANNEL_CODING_SET */ 1185 tmp[1] = DP_SET_ANSI_8B10B; 1186 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2); 1187 if (ret < 0) 1188 goto err_dpcd_write; 1189 1190 /* Reset voltage-swing & pre-emphasis */ 1191 tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 1192 DP_TRAIN_PRE_EMPH_LEVEL_0; 1193 ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2); 1194 if (ret < 0) 1195 goto err_dpcd_write; 1196 1197 /* Clock-Recovery */ 1198 1199 /* Set DPCD 0x102 for Training Pattern 1 */ 1200 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, 1201 DP_LINK_SCRAMBLING_DISABLE | 1202 DP_TRAINING_PATTERN_1); 1203 if (ret) 1204 return ret; 1205 1206 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL, 1207 (15 << 28) | /* Defer Iteration Count */ 1208 (15 << 24) | /* Loop Iteration Count */ 1209 (0xd << 0)); /* Loop Timer Delay */ 1210 if (ret) 1211 return ret; 1212 1213 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 1214 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | 1215 DP0_SRCCTRL_AUTOCORRECT | 1216 DP0_SRCCTRL_TP1); 1217 if (ret) 1218 return ret; 1219 1220 /* Enable DP0 to start Link Training */ 1221 ret = regmap_write(tc->regmap, DP0CTL, 1222 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ? 1223 EF_EN : 0) | DP_EN); 1224 if (ret) 1225 return ret; 1226 1227 /* wait */ 1228 1229 ret = tc_wait_link_training(tc); 1230 if (ret < 0) 1231 return ret; 1232 1233 if (ret) { 1234 dev_err(tc->dev, "Link training phase 1 failed: %s\n", 1235 training_pattern1_errors[ret]); 1236 return -ENODEV; 1237 } 1238 1239 /* Channel Equalization */ 1240 1241 /* Set DPCD 0x102 for Training Pattern 2 */ 1242 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, 1243 DP_LINK_SCRAMBLING_DISABLE | 1244 DP_TRAINING_PATTERN_2); 1245 if (ret) 1246 return ret; 1247 1248 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 1249 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | 1250 DP0_SRCCTRL_AUTOCORRECT | 1251 DP0_SRCCTRL_TP2); 1252 if (ret) 1253 return ret; 1254 1255 /* wait */ 1256 ret = tc_wait_link_training(tc); 1257 if (ret < 0) 1258 return ret; 1259 1260 if (ret) { 1261 dev_err(tc->dev, "Link training phase 2 failed: %s\n", 1262 training_pattern2_errors[ret]); 1263 return -ENODEV; 1264 } 1265 1266 /* 1267 * Toshiba's documentation suggests to first clear DPCD 0x102, then 1268 * clear the training pattern bit in DP0_SRCCTRL. Testing shows 1269 * that the link sometimes drops if those steps are done in that order, 1270 * but if the steps are done in reverse order, the link stays up. 1271 * 1272 * So we do the steps differently than documented here. 1273 */ 1274 1275 /* Clear Training Pattern, set AutoCorrect Mode = 1 */ 1276 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) | 1277 DP0_SRCCTRL_AUTOCORRECT); 1278 if (ret) 1279 return ret; 1280 1281 /* Clear DPCD 0x102 */ 1282 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */ 1283 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00; 1284 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]); 1285 if (ret < 0) 1286 goto err_dpcd_write; 1287 1288 /* Check link status */ 1289 ret = drm_dp_dpcd_read_link_status(aux, tmp); 1290 if (ret < 0) 1291 goto err_dpcd_read; 1292 1293 ret = 0; 1294 1295 value = tmp[0] & DP_CHANNEL_EQ_BITS; 1296 1297 if (value != DP_CHANNEL_EQ_BITS) { 1298 dev_err(tc->dev, "Lane 0 failed: %x\n", value); 1299 ret = -ENODEV; 1300 } 1301 1302 if (tc->link.num_lanes == 2) { 1303 value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS; 1304 1305 if (value != DP_CHANNEL_EQ_BITS) { 1306 dev_err(tc->dev, "Lane 1 failed: %x\n", value); 1307 ret = -ENODEV; 1308 } 1309 1310 if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) { 1311 dev_err(tc->dev, "Interlane align failed\n"); 1312 ret = -ENODEV; 1313 } 1314 } 1315 1316 if (ret) { 1317 dev_err(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[0]); 1318 dev_err(dev, "0x0203 LANE2_3_STATUS 0x%02x\n", tmp[1]); 1319 dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]); 1320 dev_err(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[3]); 1321 dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", tmp[4]); 1322 dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3: 0x%02x\n", tmp[5]); 1323 return ret; 1324 } 1325 1326 return 0; 1327 err_dpcd_read: 1328 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret); 1329 return ret; 1330 err_dpcd_write: 1331 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); 1332 return ret; 1333 } 1334 1335 static int tc_main_link_disable(struct tc_data *tc) 1336 { 1337 int ret; 1338 1339 dev_dbg(tc->dev, "link disable\n"); 1340 1341 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0); 1342 if (ret) 1343 return ret; 1344 1345 ret = regmap_write(tc->regmap, DP0CTL, 0); 1346 if (ret) 1347 return ret; 1348 1349 return regmap_update_bits(tc->regmap, DP_PHY_CTRL, 1350 PHY_M0_RST | PHY_M1_RST | PHY_M0_EN, 1351 PHY_M0_RST | PHY_M1_RST); 1352 } 1353 1354 static int tc_dsi_rx_enable(struct tc_data *tc) 1355 { 1356 u32 value; 1357 int ret; 1358 1359 regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 5); 1360 regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 5); 1361 regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 5); 1362 regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 5); 1363 regmap_write(tc->regmap, PPI_D0S_ATMR, 0); 1364 regmap_write(tc->regmap, PPI_D1S_ATMR, 0); 1365 regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE); 1366 regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD); 1367 1368 value = ((LANEENABLE_L0EN << tc->dsi->lanes) - LANEENABLE_L0EN) | 1369 LANEENABLE_CLEN; 1370 regmap_write(tc->regmap, PPI_LANEENABLE, value); 1371 regmap_write(tc->regmap, DSI_LANEENABLE, value); 1372 1373 /* Set input interface */ 1374 value = DP0_AUDSRC_NO_INPUT; 1375 if (tc_test_pattern) 1376 value |= DP0_VIDSRC_COLOR_BAR; 1377 else 1378 value |= DP0_VIDSRC_DSI_RX; 1379 ret = regmap_write(tc->regmap, SYSCTRL, value); 1380 if (ret) 1381 return ret; 1382 1383 usleep_range(120, 150); 1384 1385 regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION); 1386 regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START); 1387 1388 return 0; 1389 } 1390 1391 static int tc_dpi_rx_enable(struct tc_data *tc) 1392 { 1393 u32 value; 1394 1395 /* Set input interface */ 1396 value = DP0_AUDSRC_NO_INPUT; 1397 if (tc_test_pattern) 1398 value |= DP0_VIDSRC_COLOR_BAR; 1399 else 1400 value |= DP0_VIDSRC_DPI_RX; 1401 return regmap_write(tc->regmap, SYSCTRL, value); 1402 } 1403 1404 static int tc_dpi_stream_enable(struct tc_data *tc) 1405 { 1406 int ret; 1407 1408 dev_dbg(tc->dev, "enable video stream\n"); 1409 1410 /* Setup PLL */ 1411 ret = tc_set_syspllparam(tc); 1412 if (ret) 1413 return ret; 1414 1415 /* 1416 * Initially PLLs are in bypass. Force PLL parameter update, 1417 * disable PLL bypass, enable PLL 1418 */ 1419 ret = tc_pllupdate(tc, DP0_PLLCTRL); 1420 if (ret) 1421 return ret; 1422 1423 ret = tc_pllupdate(tc, DP1_PLLCTRL); 1424 if (ret) 1425 return ret; 1426 1427 /* Pixel PLL must always be enabled for DPI mode */ 1428 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), 1429 1000 * tc->mode.clock); 1430 if (ret) 1431 return ret; 1432 1433 ret = tc_set_common_video_mode(tc, &tc->mode); 1434 if (ret) 1435 return ret; 1436 1437 ret = tc_set_dpi_video_mode(tc, &tc->mode); 1438 if (ret) 1439 return ret; 1440 1441 return tc_dsi_rx_enable(tc); 1442 } 1443 1444 static int tc_dpi_stream_disable(struct tc_data *tc) 1445 { 1446 dev_dbg(tc->dev, "disable video stream\n"); 1447 1448 tc_pxl_pll_dis(tc); 1449 1450 return 0; 1451 } 1452 1453 static int tc_edp_stream_enable(struct tc_data *tc) 1454 { 1455 int ret; 1456 u32 value; 1457 1458 dev_dbg(tc->dev, "enable video stream\n"); 1459 1460 /* 1461 * Pixel PLL must be enabled for DSI input mode and test pattern. 1462 * 1463 * Per TC9595XBG datasheet Revision 0.1 2018-12-27 Figure 4.18 1464 * "Clock Mode Selection and Clock Sources", either Pixel PLL 1465 * or DPI_PCLK supplies StrmClk. DPI_PCLK is only available in 1466 * case valid Pixel Clock are supplied to the chip DPI input. 1467 * In case built-in test pattern is desired OR DSI input mode 1468 * is used, DPI_PCLK is not available and thus Pixel PLL must 1469 * be used instead. 1470 */ 1471 if (tc->input_connector_dsi || tc_test_pattern) { 1472 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), 1473 1000 * tc->mode.clock); 1474 if (ret) 1475 return ret; 1476 } 1477 1478 ret = tc_set_common_video_mode(tc, &tc->mode); 1479 if (ret) 1480 return ret; 1481 1482 ret = tc_set_edp_video_mode(tc, &tc->mode); 1483 if (ret) 1484 return ret; 1485 1486 /* Set M/N */ 1487 ret = tc_stream_clock_calc(tc); 1488 if (ret) 1489 return ret; 1490 1491 value = VID_MN_GEN | DP_EN; 1492 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) 1493 value |= EF_EN; 1494 ret = regmap_write(tc->regmap, DP0CTL, value); 1495 if (ret) 1496 return ret; 1497 /* 1498 * VID_EN assertion should be delayed by at least N * LSCLK 1499 * cycles from the time VID_MN_GEN is enabled in order to 1500 * generate stable values for VID_M. LSCLK is 270 MHz or 1501 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(), 1502 * so a delay of at least 203 us should suffice. 1503 */ 1504 usleep_range(500, 1000); 1505 value |= VID_EN; 1506 ret = regmap_write(tc->regmap, DP0CTL, value); 1507 if (ret) 1508 return ret; 1509 1510 /* Set input interface */ 1511 if (tc->input_connector_dsi) 1512 return tc_dsi_rx_enable(tc); 1513 else 1514 return tc_dpi_rx_enable(tc); 1515 } 1516 1517 static int tc_edp_stream_disable(struct tc_data *tc) 1518 { 1519 int ret; 1520 1521 dev_dbg(tc->dev, "disable video stream\n"); 1522 1523 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0); 1524 if (ret) 1525 return ret; 1526 1527 tc_pxl_pll_dis(tc); 1528 1529 return 0; 1530 } 1531 1532 static void 1533 tc_dpi_bridge_atomic_enable(struct drm_bridge *bridge, 1534 struct drm_bridge_state *old_bridge_state) 1535 1536 { 1537 struct tc_data *tc = bridge_to_tc(bridge); 1538 int ret; 1539 1540 ret = tc_dpi_stream_enable(tc); 1541 if (ret < 0) { 1542 dev_err(tc->dev, "main link stream start error: %d\n", ret); 1543 tc_main_link_disable(tc); 1544 return; 1545 } 1546 } 1547 1548 static void 1549 tc_dpi_bridge_atomic_disable(struct drm_bridge *bridge, 1550 struct drm_bridge_state *old_bridge_state) 1551 { 1552 struct tc_data *tc = bridge_to_tc(bridge); 1553 int ret; 1554 1555 ret = tc_dpi_stream_disable(tc); 1556 if (ret < 0) 1557 dev_err(tc->dev, "main link stream stop error: %d\n", ret); 1558 } 1559 1560 static void 1561 tc_edp_bridge_atomic_enable(struct drm_bridge *bridge, 1562 struct drm_bridge_state *old_bridge_state) 1563 { 1564 struct tc_data *tc = bridge_to_tc(bridge); 1565 int ret; 1566 1567 ret = tc_get_display_props(tc); 1568 if (ret < 0) { 1569 dev_err(tc->dev, "failed to read display props: %d\n", ret); 1570 return; 1571 } 1572 1573 ret = tc_main_link_enable(tc); 1574 if (ret < 0) { 1575 dev_err(tc->dev, "main link enable error: %d\n", ret); 1576 return; 1577 } 1578 1579 ret = tc_edp_stream_enable(tc); 1580 if (ret < 0) { 1581 dev_err(tc->dev, "main link stream start error: %d\n", ret); 1582 tc_main_link_disable(tc); 1583 return; 1584 } 1585 } 1586 1587 static void 1588 tc_edp_bridge_atomic_disable(struct drm_bridge *bridge, 1589 struct drm_bridge_state *old_bridge_state) 1590 { 1591 struct tc_data *tc = bridge_to_tc(bridge); 1592 int ret; 1593 1594 ret = tc_edp_stream_disable(tc); 1595 if (ret < 0) 1596 dev_err(tc->dev, "main link stream stop error: %d\n", ret); 1597 1598 ret = tc_main_link_disable(tc); 1599 if (ret < 0) 1600 dev_err(tc->dev, "main link disable error: %d\n", ret); 1601 } 1602 1603 static int tc_dpi_atomic_check(struct drm_bridge *bridge, 1604 struct drm_bridge_state *bridge_state, 1605 struct drm_crtc_state *crtc_state, 1606 struct drm_connector_state *conn_state) 1607 { 1608 struct tc_data *tc = bridge_to_tc(bridge); 1609 int adjusted_clock = 0; 1610 int ret; 1611 1612 ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), 1613 crtc_state->mode.clock * 1000, 1614 &adjusted_clock, NULL); 1615 if (ret) 1616 return ret; 1617 1618 crtc_state->adjusted_mode.clock = adjusted_clock / 1000; 1619 1620 /* DSI->DPI interface clock limitation: upto 100 MHz */ 1621 if (crtc_state->adjusted_mode.clock > 100000) 1622 return -EINVAL; 1623 1624 return 0; 1625 } 1626 1627 static int tc_edp_atomic_check(struct drm_bridge *bridge, 1628 struct drm_bridge_state *bridge_state, 1629 struct drm_crtc_state *crtc_state, 1630 struct drm_connector_state *conn_state) 1631 { 1632 struct tc_data *tc = bridge_to_tc(bridge); 1633 int adjusted_clock = 0; 1634 int ret; 1635 1636 ret = tc_pxl_pll_calc(tc, clk_get_rate(tc->refclk), 1637 crtc_state->mode.clock * 1000, 1638 &adjusted_clock, NULL); 1639 if (ret) 1640 return ret; 1641 1642 crtc_state->adjusted_mode.clock = adjusted_clock / 1000; 1643 1644 /* DPI->(e)DP interface clock limitation: upto 154 MHz */ 1645 if (crtc_state->adjusted_mode.clock > 154000) 1646 return -EINVAL; 1647 1648 return 0; 1649 } 1650 1651 static enum drm_mode_status 1652 tc_dpi_mode_valid(struct drm_bridge *bridge, 1653 const struct drm_display_info *info, 1654 const struct drm_display_mode *mode) 1655 { 1656 /* DPI interface clock limitation: upto 100 MHz */ 1657 if (mode->clock > 100000) 1658 return MODE_CLOCK_HIGH; 1659 1660 return MODE_OK; 1661 } 1662 1663 static enum drm_mode_status 1664 tc_edp_mode_valid(struct drm_bridge *bridge, 1665 const struct drm_display_info *info, 1666 const struct drm_display_mode *mode) 1667 { 1668 struct tc_data *tc = bridge_to_tc(bridge); 1669 u32 req, avail; 1670 u32 bits_per_pixel = 24; 1671 1672 /* DPI->(e)DP interface clock limitation: up to 154 MHz */ 1673 if (mode->clock > 154000) 1674 return MODE_CLOCK_HIGH; 1675 1676 req = mode->clock * bits_per_pixel / 8; 1677 avail = tc->link.num_lanes * tc->link.rate; 1678 1679 if (req > avail) 1680 return MODE_BAD; 1681 1682 return MODE_OK; 1683 } 1684 1685 static void tc_bridge_mode_set(struct drm_bridge *bridge, 1686 const struct drm_display_mode *mode, 1687 const struct drm_display_mode *adj) 1688 { 1689 struct tc_data *tc = bridge_to_tc(bridge); 1690 1691 drm_mode_copy(&tc->mode, mode); 1692 } 1693 1694 static const struct drm_edid *tc_edid_read(struct drm_bridge *bridge, 1695 struct drm_connector *connector) 1696 { 1697 struct tc_data *tc = bridge_to_tc(bridge); 1698 1699 return drm_edid_read_ddc(connector, &tc->aux.ddc); 1700 } 1701 1702 static int tc_connector_get_modes(struct drm_connector *connector) 1703 { 1704 struct tc_data *tc = connector_to_tc(connector); 1705 int num_modes; 1706 const struct drm_edid *drm_edid; 1707 int ret; 1708 1709 ret = tc_get_display_props(tc); 1710 if (ret < 0) { 1711 dev_err(tc->dev, "failed to read display props: %d\n", ret); 1712 return 0; 1713 } 1714 1715 if (tc->panel_bridge) { 1716 num_modes = drm_bridge_get_modes(tc->panel_bridge, connector); 1717 if (num_modes > 0) 1718 return num_modes; 1719 } 1720 1721 drm_edid = tc_edid_read(&tc->bridge, connector); 1722 drm_edid_connector_update(connector, drm_edid); 1723 num_modes = drm_edid_connector_add_modes(connector); 1724 drm_edid_free(drm_edid); 1725 1726 return num_modes; 1727 } 1728 1729 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = { 1730 .get_modes = tc_connector_get_modes, 1731 }; 1732 1733 static enum drm_connector_status tc_bridge_detect(struct drm_bridge *bridge) 1734 { 1735 struct tc_data *tc = bridge_to_tc(bridge); 1736 bool conn; 1737 u32 val; 1738 int ret; 1739 1740 ret = regmap_read(tc->regmap, GPIOI, &val); 1741 if (ret) 1742 return connector_status_unknown; 1743 1744 conn = val & BIT(tc->hpd_pin); 1745 1746 if (conn) 1747 return connector_status_connected; 1748 else 1749 return connector_status_disconnected; 1750 } 1751 1752 static enum drm_connector_status 1753 tc_connector_detect(struct drm_connector *connector, bool force) 1754 { 1755 struct tc_data *tc = connector_to_tc(connector); 1756 1757 if (tc->hpd_pin >= 0) 1758 return tc_bridge_detect(&tc->bridge); 1759 1760 if (tc->panel_bridge) 1761 return connector_status_connected; 1762 else 1763 return connector_status_unknown; 1764 } 1765 1766 static const struct drm_connector_funcs tc_connector_funcs = { 1767 .detect = tc_connector_detect, 1768 .fill_modes = drm_helper_probe_single_connector_modes, 1769 .destroy = drm_connector_cleanup, 1770 .reset = drm_atomic_helper_connector_reset, 1771 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1772 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1773 }; 1774 1775 static int tc_dpi_bridge_attach(struct drm_bridge *bridge, 1776 enum drm_bridge_attach_flags flags) 1777 { 1778 struct tc_data *tc = bridge_to_tc(bridge); 1779 1780 if (!tc->panel_bridge) 1781 return 0; 1782 1783 return drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge, 1784 &tc->bridge, flags); 1785 } 1786 1787 static int tc_edp_bridge_attach(struct drm_bridge *bridge, 1788 enum drm_bridge_attach_flags flags) 1789 { 1790 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1791 struct tc_data *tc = bridge_to_tc(bridge); 1792 struct drm_device *drm = bridge->dev; 1793 int ret; 1794 1795 if (tc->panel_bridge) { 1796 /* If a connector is required then this driver shall create it */ 1797 ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge, 1798 &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); 1799 if (ret) 1800 return ret; 1801 } 1802 1803 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 1804 return 0; 1805 1806 tc->aux.drm_dev = drm; 1807 ret = drm_dp_aux_register(&tc->aux); 1808 if (ret < 0) 1809 return ret; 1810 1811 /* Create DP/eDP connector */ 1812 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs); 1813 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type); 1814 if (ret) 1815 goto aux_unregister; 1816 1817 /* Don't poll if don't have HPD connected */ 1818 if (tc->hpd_pin >= 0) { 1819 if (tc->have_irq) 1820 tc->connector.polled = DRM_CONNECTOR_POLL_HPD; 1821 else 1822 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 1823 DRM_CONNECTOR_POLL_DISCONNECT; 1824 } 1825 1826 drm_display_info_set_bus_formats(&tc->connector.display_info, 1827 &bus_format, 1); 1828 tc->connector.display_info.bus_flags = 1829 DRM_BUS_FLAG_DE_HIGH | 1830 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE | 1831 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE; 1832 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder); 1833 1834 return 0; 1835 aux_unregister: 1836 drm_dp_aux_unregister(&tc->aux); 1837 return ret; 1838 } 1839 1840 static void tc_edp_bridge_detach(struct drm_bridge *bridge) 1841 { 1842 drm_dp_aux_unregister(&bridge_to_tc(bridge)->aux); 1843 } 1844 1845 #define MAX_INPUT_SEL_FORMATS 1 1846 #define MAX_OUTPUT_SEL_FORMATS 1 1847 1848 static u32 * 1849 tc_dpi_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 1850 struct drm_bridge_state *bridge_state, 1851 struct drm_crtc_state *crtc_state, 1852 struct drm_connector_state *conn_state, 1853 u32 output_fmt, 1854 unsigned int *num_input_fmts) 1855 { 1856 u32 *input_fmts; 1857 1858 *num_input_fmts = 0; 1859 1860 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 1861 GFP_KERNEL); 1862 if (!input_fmts) 1863 return NULL; 1864 1865 /* This is the DSI-end bus format */ 1866 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 1867 *num_input_fmts = 1; 1868 1869 return input_fmts; 1870 } 1871 1872 static u32 * 1873 tc_edp_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 1874 struct drm_bridge_state *bridge_state, 1875 struct drm_crtc_state *crtc_state, 1876 struct drm_connector_state *conn_state, 1877 unsigned int *num_output_fmts) 1878 { 1879 u32 *output_fmts; 1880 1881 *num_output_fmts = 0; 1882 1883 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), 1884 GFP_KERNEL); 1885 if (!output_fmts) 1886 return NULL; 1887 1888 output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 1889 *num_output_fmts = 1; 1890 1891 return output_fmts; 1892 } 1893 1894 static const struct drm_bridge_funcs tc_dpi_bridge_funcs = { 1895 .attach = tc_dpi_bridge_attach, 1896 .mode_valid = tc_dpi_mode_valid, 1897 .mode_set = tc_bridge_mode_set, 1898 .atomic_check = tc_dpi_atomic_check, 1899 .atomic_enable = tc_dpi_bridge_atomic_enable, 1900 .atomic_disable = tc_dpi_bridge_atomic_disable, 1901 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1902 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1903 .atomic_reset = drm_atomic_helper_bridge_reset, 1904 .atomic_get_input_bus_fmts = tc_dpi_atomic_get_input_bus_fmts, 1905 }; 1906 1907 static const struct drm_bridge_funcs tc_edp_bridge_funcs = { 1908 .attach = tc_edp_bridge_attach, 1909 .detach = tc_edp_bridge_detach, 1910 .mode_valid = tc_edp_mode_valid, 1911 .mode_set = tc_bridge_mode_set, 1912 .atomic_check = tc_edp_atomic_check, 1913 .atomic_enable = tc_edp_bridge_atomic_enable, 1914 .atomic_disable = tc_edp_bridge_atomic_disable, 1915 .detect = tc_bridge_detect, 1916 .edid_read = tc_edid_read, 1917 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1918 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1919 .atomic_reset = drm_atomic_helper_bridge_reset, 1920 .atomic_get_input_bus_fmts = drm_atomic_helper_bridge_propagate_bus_fmt, 1921 .atomic_get_output_bus_fmts = tc_edp_atomic_get_output_bus_fmts, 1922 }; 1923 1924 static bool tc_readable_reg(struct device *dev, unsigned int reg) 1925 { 1926 switch (reg) { 1927 /* DSI D-PHY Layer */ 1928 case 0x004: 1929 case 0x020: 1930 case 0x024: 1931 case 0x028: 1932 case 0x02c: 1933 case 0x030: 1934 case 0x038: 1935 case 0x040: 1936 case 0x044: 1937 case 0x048: 1938 case 0x04c: 1939 case 0x050: 1940 case 0x054: 1941 /* DSI PPI Layer */ 1942 case PPI_STARTPPI: 1943 case 0x108: 1944 case 0x110: 1945 case PPI_LPTXTIMECNT: 1946 case PPI_LANEENABLE: 1947 case PPI_TX_RX_TA: 1948 case 0x140: 1949 case PPI_D0S_ATMR: 1950 case PPI_D1S_ATMR: 1951 case 0x14c: 1952 case 0x150: 1953 case PPI_D0S_CLRSIPOCOUNT: 1954 case PPI_D1S_CLRSIPOCOUNT: 1955 case PPI_D2S_CLRSIPOCOUNT: 1956 case PPI_D3S_CLRSIPOCOUNT: 1957 case 0x180: 1958 case 0x184: 1959 case 0x188: 1960 case 0x18c: 1961 case 0x190: 1962 case 0x1a0: 1963 case 0x1a4: 1964 case 0x1a8: 1965 case 0x1ac: 1966 case 0x1b0: 1967 case 0x1c0: 1968 case 0x1c4: 1969 case 0x1c8: 1970 case 0x1cc: 1971 case 0x1d0: 1972 case 0x1e0: 1973 case 0x1e4: 1974 case 0x1f0: 1975 case 0x1f4: 1976 /* DSI Protocol Layer */ 1977 case DSI_STARTDSI: 1978 case DSI_BUSYDSI: 1979 case DSI_LANEENABLE: 1980 case DSI_LANESTATUS0: 1981 case DSI_LANESTATUS1: 1982 case DSI_INTSTATUS: 1983 case 0x224: 1984 case 0x228: 1985 case 0x230: 1986 /* DSI General */ 1987 case DSIERRCNT: 1988 /* DSI Application Layer */ 1989 case 0x400: 1990 case 0x404: 1991 /* DPI */ 1992 case DPIPXLFMT: 1993 /* Parallel Output */ 1994 case POCTRL: 1995 /* Video Path0 Configuration */ 1996 case VPCTRL0: 1997 case HTIM01: 1998 case HTIM02: 1999 case VTIM01: 2000 case VTIM02: 2001 case VFUEN0: 2002 /* System */ 2003 case TC_IDREG: 2004 case 0x504: 2005 case SYSSTAT: 2006 case SYSRSTENB: 2007 case SYSCTRL: 2008 /* I2C */ 2009 case 0x520: 2010 /* GPIO */ 2011 case GPIOM: 2012 case GPIOC: 2013 case GPIOO: 2014 case GPIOI: 2015 /* Interrupt */ 2016 case INTCTL_G: 2017 case INTSTS_G: 2018 case 0x570: 2019 case 0x574: 2020 case INT_GP0_LCNT: 2021 case INT_GP1_LCNT: 2022 /* DisplayPort Control */ 2023 case DP0CTL: 2024 /* DisplayPort Clock */ 2025 case DP0_VIDMNGEN0: 2026 case DP0_VIDMNGEN1: 2027 case DP0_VMNGENSTATUS: 2028 case 0x628: 2029 case 0x62c: 2030 case 0x630: 2031 /* DisplayPort Main Channel */ 2032 case DP0_SECSAMPLE: 2033 case DP0_VIDSYNCDELAY: 2034 case DP0_TOTALVAL: 2035 case DP0_STARTVAL: 2036 case DP0_ACTIVEVAL: 2037 case DP0_SYNCVAL: 2038 case DP0_MISC: 2039 /* DisplayPort Aux Channel */ 2040 case DP0_AUXCFG0: 2041 case DP0_AUXCFG1: 2042 case DP0_AUXADDR: 2043 case 0x66c: 2044 case 0x670: 2045 case 0x674: 2046 case 0x678: 2047 case 0x67c: 2048 case 0x680: 2049 case 0x684: 2050 case 0x688: 2051 case DP0_AUXSTATUS: 2052 case DP0_AUXI2CADR: 2053 /* DisplayPort Link Training */ 2054 case DP0_SRCCTRL: 2055 case DP0_LTSTAT: 2056 case DP0_SNKLTCHGREQ: 2057 case DP0_LTLOOPCTRL: 2058 case DP0_SNKLTCTRL: 2059 case 0x6e8: 2060 case 0x6ec: 2061 case 0x6f0: 2062 case 0x6f4: 2063 /* DisplayPort Audio */ 2064 case 0x700: 2065 case 0x704: 2066 case 0x708: 2067 case 0x70c: 2068 case 0x710: 2069 case 0x714: 2070 case 0x718: 2071 case 0x71c: 2072 case 0x720: 2073 /* DisplayPort Source Control */ 2074 case DP1_SRCCTRL: 2075 /* DisplayPort PHY */ 2076 case DP_PHY_CTRL: 2077 case 0x810: 2078 case 0x814: 2079 case 0x820: 2080 case 0x840: 2081 /* I2S */ 2082 case 0x880: 2083 case 0x888: 2084 case 0x88c: 2085 case 0x890: 2086 case 0x894: 2087 case 0x898: 2088 case 0x89c: 2089 case 0x8a0: 2090 case 0x8a4: 2091 case 0x8a8: 2092 case 0x8ac: 2093 case 0x8b0: 2094 case 0x8b4: 2095 /* PLL */ 2096 case DP0_PLLCTRL: 2097 case DP1_PLLCTRL: 2098 case PXL_PLLCTRL: 2099 case PXL_PLLPARAM: 2100 case SYS_PLLPARAM: 2101 /* HDCP */ 2102 case 0x980: 2103 case 0x984: 2104 case 0x988: 2105 case 0x98c: 2106 case 0x990: 2107 case 0x994: 2108 case 0x998: 2109 case 0x99c: 2110 case 0x9a0: 2111 case 0x9a4: 2112 case 0x9a8: 2113 case 0x9ac: 2114 /* Debug */ 2115 case TSTCTL: 2116 case PLL_DBG: 2117 return true; 2118 } 2119 return false; 2120 } 2121 2122 static const struct regmap_range tc_volatile_ranges[] = { 2123 regmap_reg_range(PPI_BUSYPPI, PPI_BUSYPPI), 2124 regmap_reg_range(DSI_BUSYDSI, DSI_BUSYDSI), 2125 regmap_reg_range(DSI_LANESTATUS0, DSI_INTSTATUS), 2126 regmap_reg_range(DSIERRCNT, DSIERRCNT), 2127 regmap_reg_range(VFUEN0, VFUEN0), 2128 regmap_reg_range(SYSSTAT, SYSSTAT), 2129 regmap_reg_range(GPIOI, GPIOI), 2130 regmap_reg_range(INTSTS_G, INTSTS_G), 2131 regmap_reg_range(DP0_VMNGENSTATUS, DP0_VMNGENSTATUS), 2132 regmap_reg_range(DP0_AMNGENSTATUS, DP0_AMNGENSTATUS), 2133 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS), 2134 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ), 2135 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL), 2136 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL), 2137 }; 2138 2139 static const struct regmap_access_table tc_volatile_table = { 2140 .yes_ranges = tc_volatile_ranges, 2141 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges), 2142 }; 2143 2144 static const struct regmap_range tc_precious_ranges[] = { 2145 regmap_reg_range(SYSSTAT, SYSSTAT), 2146 }; 2147 2148 static const struct regmap_access_table tc_precious_table = { 2149 .yes_ranges = tc_precious_ranges, 2150 .n_yes_ranges = ARRAY_SIZE(tc_precious_ranges), 2151 }; 2152 2153 static const struct regmap_range tc_non_writeable_ranges[] = { 2154 regmap_reg_range(PPI_BUSYPPI, PPI_BUSYPPI), 2155 regmap_reg_range(DSI_BUSYDSI, DSI_BUSYDSI), 2156 regmap_reg_range(DSI_LANESTATUS0, DSI_INTSTATUS), 2157 regmap_reg_range(TC_IDREG, SYSSTAT), 2158 regmap_reg_range(GPIOI, GPIOI), 2159 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ), 2160 }; 2161 2162 static const struct regmap_access_table tc_writeable_table = { 2163 .no_ranges = tc_non_writeable_ranges, 2164 .n_no_ranges = ARRAY_SIZE(tc_non_writeable_ranges), 2165 }; 2166 2167 static const struct regmap_config tc_regmap_config = { 2168 .name = "tc358767", 2169 .reg_bits = 16, 2170 .val_bits = 32, 2171 .reg_stride = 4, 2172 .max_register = PLL_DBG, 2173 .cache_type = REGCACHE_MAPLE, 2174 .readable_reg = tc_readable_reg, 2175 .volatile_table = &tc_volatile_table, 2176 .precious_table = &tc_precious_table, 2177 .wr_table = &tc_writeable_table, 2178 .reg_format_endian = REGMAP_ENDIAN_BIG, 2179 .val_format_endian = REGMAP_ENDIAN_LITTLE, 2180 }; 2181 2182 static irqreturn_t tc_irq_handler(int irq, void *arg) 2183 { 2184 struct tc_data *tc = arg; 2185 u32 val; 2186 int r; 2187 2188 r = regmap_read(tc->regmap, INTSTS_G, &val); 2189 if (r) 2190 return IRQ_NONE; 2191 2192 if (!val) 2193 return IRQ_NONE; 2194 2195 if (val & INT_SYSERR) { 2196 u32 stat = 0; 2197 2198 regmap_read(tc->regmap, SYSSTAT, &stat); 2199 2200 dev_err(tc->dev, "syserr %x\n", stat); 2201 } 2202 2203 if (tc->hpd_pin >= 0 && tc->bridge.dev && tc->aux.drm_dev) { 2204 /* 2205 * H is triggered when the GPIO goes high. 2206 * 2207 * LC is triggered when the GPIO goes low and stays low for 2208 * the duration of LCNT 2209 */ 2210 bool h = val & INT_GPIO_H(tc->hpd_pin); 2211 bool lc = val & INT_GPIO_LC(tc->hpd_pin); 2212 2213 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin, 2214 h ? "H" : "", lc ? "LC" : ""); 2215 2216 if (h || lc) 2217 drm_kms_helper_hotplug_event(tc->bridge.dev); 2218 } 2219 2220 regmap_write(tc->regmap, INTSTS_G, val); 2221 2222 return IRQ_HANDLED; 2223 } 2224 2225 static int tc_mipi_dsi_host_attach(struct tc_data *tc) 2226 { 2227 struct device *dev = tc->dev; 2228 struct device_node *host_node; 2229 struct device_node *endpoint; 2230 struct mipi_dsi_device *dsi; 2231 struct mipi_dsi_host *host; 2232 const struct mipi_dsi_device_info info = { 2233 .type = "tc358767", 2234 .channel = 0, 2235 .node = NULL, 2236 }; 2237 int dsi_lanes, ret; 2238 2239 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); 2240 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4); 2241 host_node = of_graph_get_remote_port_parent(endpoint); 2242 host = of_find_mipi_dsi_host_by_node(host_node); 2243 of_node_put(host_node); 2244 of_node_put(endpoint); 2245 2246 if (!host) 2247 return -EPROBE_DEFER; 2248 2249 if (dsi_lanes < 0) 2250 return dsi_lanes; 2251 2252 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 2253 if (IS_ERR(dsi)) 2254 return dev_err_probe(dev, PTR_ERR(dsi), 2255 "failed to create dsi device\n"); 2256 2257 tc->dsi = dsi; 2258 dsi->lanes = dsi_lanes; 2259 dsi->format = MIPI_DSI_FMT_RGB888; 2260 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 2261 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; 2262 2263 ret = devm_mipi_dsi_attach(dev, dsi); 2264 if (ret < 0) { 2265 dev_err(dev, "failed to attach dsi to host: %d\n", ret); 2266 return ret; 2267 } 2268 2269 return 0; 2270 } 2271 2272 static int tc_probe_dpi_bridge_endpoint(struct tc_data *tc) 2273 { 2274 struct device *dev = tc->dev; 2275 struct drm_bridge *bridge; 2276 struct drm_panel *panel; 2277 int ret; 2278 2279 /* port@1 is the DPI input/output port */ 2280 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, &bridge); 2281 if (ret && ret != -ENODEV) 2282 return ret; 2283 2284 if (panel) { 2285 bridge = devm_drm_panel_bridge_add(dev, panel); 2286 if (IS_ERR(bridge)) 2287 return PTR_ERR(bridge); 2288 } 2289 2290 if (bridge) { 2291 tc->panel_bridge = bridge; 2292 tc->bridge.type = DRM_MODE_CONNECTOR_DPI; 2293 tc->bridge.funcs = &tc_dpi_bridge_funcs; 2294 2295 return 0; 2296 } 2297 2298 return ret; 2299 } 2300 2301 static int tc_probe_edp_bridge_endpoint(struct tc_data *tc) 2302 { 2303 struct device *dev = tc->dev; 2304 struct drm_panel *panel; 2305 int ret; 2306 2307 /* port@2 is the output port */ 2308 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, NULL); 2309 if (ret && ret != -ENODEV) 2310 return ret; 2311 2312 if (panel) { 2313 struct drm_bridge *panel_bridge; 2314 2315 panel_bridge = devm_drm_panel_bridge_add(dev, panel); 2316 if (IS_ERR(panel_bridge)) 2317 return PTR_ERR(panel_bridge); 2318 2319 tc->panel_bridge = panel_bridge; 2320 tc->bridge.type = DRM_MODE_CONNECTOR_eDP; 2321 } else { 2322 tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort; 2323 } 2324 2325 tc->bridge.funcs = &tc_edp_bridge_funcs; 2326 if (tc->hpd_pin >= 0) 2327 tc->bridge.ops |= DRM_BRIDGE_OP_DETECT; 2328 tc->bridge.ops |= DRM_BRIDGE_OP_EDID; 2329 2330 return 0; 2331 } 2332 2333 static int tc_probe_bridge_endpoint(struct tc_data *tc) 2334 { 2335 struct device *dev = tc->dev; 2336 struct of_endpoint endpoint; 2337 struct device_node *node = NULL; 2338 const u8 mode_dpi_to_edp = BIT(1) | BIT(2); 2339 const u8 mode_dpi_to_dp = BIT(1); 2340 const u8 mode_dsi_to_edp = BIT(0) | BIT(2); 2341 const u8 mode_dsi_to_dp = BIT(0); 2342 const u8 mode_dsi_to_dpi = BIT(0) | BIT(1); 2343 u8 mode = 0; 2344 2345 /* 2346 * Determine bridge configuration. 2347 * 2348 * Port allocation: 2349 * port@0 - DSI input 2350 * port@1 - DPI input/output 2351 * port@2 - eDP output 2352 * 2353 * Possible connections: 2354 * DPI -> port@1 -> port@2 -> eDP :: [port@0 is not connected] 2355 * DSI -> port@0 -> port@2 -> eDP :: [port@1 is not connected] 2356 * DSI -> port@0 -> port@1 -> DPI :: [port@2 is not connected] 2357 */ 2358 2359 for_each_endpoint_of_node(dev->of_node, node) { 2360 of_graph_parse_endpoint(node, &endpoint); 2361 if (endpoint.port > 2) { 2362 of_node_put(node); 2363 return -EINVAL; 2364 } 2365 mode |= BIT(endpoint.port); 2366 } 2367 2368 if (mode == mode_dpi_to_edp || mode == mode_dpi_to_dp) { 2369 tc->input_connector_dsi = false; 2370 return tc_probe_edp_bridge_endpoint(tc); 2371 } else if (mode == mode_dsi_to_dpi) { 2372 tc->input_connector_dsi = true; 2373 return tc_probe_dpi_bridge_endpoint(tc); 2374 } else if (mode == mode_dsi_to_edp || mode == mode_dsi_to_dp) { 2375 tc->input_connector_dsi = true; 2376 return tc_probe_edp_bridge_endpoint(tc); 2377 } 2378 2379 dev_warn(dev, "Invalid mode (0x%x) is not supported!\n", mode); 2380 2381 return -EINVAL; 2382 } 2383 2384 static int tc_probe(struct i2c_client *client) 2385 { 2386 struct device *dev = &client->dev; 2387 struct tc_data *tc; 2388 int ret; 2389 2390 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL); 2391 if (!tc) 2392 return -ENOMEM; 2393 2394 tc->dev = dev; 2395 2396 ret = tc_probe_bridge_endpoint(tc); 2397 if (ret) 2398 return ret; 2399 2400 tc->refclk = devm_clk_get_enabled(dev, "ref"); 2401 if (IS_ERR(tc->refclk)) 2402 return dev_err_probe(dev, PTR_ERR(tc->refclk), 2403 "Failed to get and enable the ref clk\n"); 2404 2405 /* tRSTW = 100 cycles , at 13 MHz that is ~7.69 us */ 2406 usleep_range(10, 15); 2407 2408 /* Shut down GPIO is optional */ 2409 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); 2410 if (IS_ERR(tc->sd_gpio)) 2411 return PTR_ERR(tc->sd_gpio); 2412 2413 if (tc->sd_gpio) { 2414 gpiod_set_value_cansleep(tc->sd_gpio, 0); 2415 usleep_range(5000, 10000); 2416 } 2417 2418 /* Reset GPIO is optional */ 2419 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 2420 if (IS_ERR(tc->reset_gpio)) 2421 return PTR_ERR(tc->reset_gpio); 2422 2423 if (tc->reset_gpio) { 2424 gpiod_set_value_cansleep(tc->reset_gpio, 1); 2425 usleep_range(5000, 10000); 2426 } 2427 2428 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config); 2429 if (IS_ERR(tc->regmap)) { 2430 ret = PTR_ERR(tc->regmap); 2431 dev_err(dev, "Failed to initialize regmap: %d\n", ret); 2432 return ret; 2433 } 2434 2435 ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin", 2436 &tc->hpd_pin); 2437 if (ret) { 2438 tc->hpd_pin = -ENODEV; 2439 } else { 2440 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) { 2441 dev_err(dev, "failed to parse HPD number\n"); 2442 return -EINVAL; 2443 } 2444 } 2445 2446 if (client->irq > 0) { 2447 /* enable SysErr */ 2448 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR); 2449 2450 ret = devm_request_threaded_irq(dev, client->irq, 2451 NULL, tc_irq_handler, 2452 IRQF_ONESHOT, 2453 "tc358767-irq", tc); 2454 if (ret) { 2455 dev_err(dev, "failed to register dp interrupt\n"); 2456 return ret; 2457 } 2458 2459 tc->have_irq = true; 2460 } 2461 2462 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev); 2463 if (ret) { 2464 dev_err(tc->dev, "can not read device ID: %d\n", ret); 2465 return ret; 2466 } 2467 2468 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) { 2469 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev); 2470 return -EINVAL; 2471 } 2472 2473 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ 2474 2475 if (!tc->reset_gpio) { 2476 /* 2477 * If the reset pin isn't present, do a software reset. It isn't 2478 * as thorough as the hardware reset, as we can't reset the I2C 2479 * communication block for obvious reasons, but it's getting the 2480 * chip into a defined state. 2481 */ 2482 regmap_update_bits(tc->regmap, SYSRSTENB, 2483 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP, 2484 0); 2485 regmap_update_bits(tc->regmap, SYSRSTENB, 2486 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP, 2487 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP); 2488 usleep_range(5000, 10000); 2489 } 2490 2491 if (tc->hpd_pin >= 0) { 2492 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT; 2493 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin); 2494 2495 /* Set LCNT to 2ms */ 2496 regmap_write(tc->regmap, lcnt_reg, 2497 clk_get_rate(tc->refclk) * 2 / 1000); 2498 /* We need the "alternate" mode for HPD */ 2499 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin)); 2500 2501 if (tc->have_irq) { 2502 /* enable H & LC */ 2503 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc); 2504 } 2505 } 2506 2507 if (tc->bridge.type != DRM_MODE_CONNECTOR_DPI) { /* (e)DP output */ 2508 ret = tc_aux_link_setup(tc); 2509 if (ret) 2510 return ret; 2511 } 2512 2513 tc->bridge.of_node = dev->of_node; 2514 drm_bridge_add(&tc->bridge); 2515 2516 i2c_set_clientdata(client, tc); 2517 2518 if (tc->input_connector_dsi) { /* DSI input */ 2519 ret = tc_mipi_dsi_host_attach(tc); 2520 if (ret) { 2521 drm_bridge_remove(&tc->bridge); 2522 return ret; 2523 } 2524 } 2525 2526 return 0; 2527 } 2528 2529 static void tc_remove(struct i2c_client *client) 2530 { 2531 struct tc_data *tc = i2c_get_clientdata(client); 2532 2533 drm_bridge_remove(&tc->bridge); 2534 } 2535 2536 static const struct i2c_device_id tc358767_i2c_ids[] = { 2537 { "tc358767", 0 }, 2538 { } 2539 }; 2540 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids); 2541 2542 static const struct of_device_id tc358767_of_ids[] = { 2543 { .compatible = "toshiba,tc358767", }, 2544 { } 2545 }; 2546 MODULE_DEVICE_TABLE(of, tc358767_of_ids); 2547 2548 static struct i2c_driver tc358767_driver = { 2549 .driver = { 2550 .name = "tc358767", 2551 .of_match_table = tc358767_of_ids, 2552 }, 2553 .id_table = tc358767_i2c_ids, 2554 .probe = tc_probe, 2555 .remove = tc_remove, 2556 }; 2557 module_i2c_driver(tc358767_driver); 2558 2559 MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>"); 2560 MODULE_DESCRIPTION("tc358767 eDP encoder driver"); 2561 MODULE_LICENSE("GPL"); 2562