1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * TC358767/TC358867/TC9595 DSI/DPI-to-DPI/(e)DP bridge driver 4 * 5 * The TC358767/TC358867/TC9595 can operate in multiple modes. 6 * All modes are supported -- DPI->(e)DP / DSI->DPI / DSI->(e)DP . 7 * 8 * Copyright (C) 2016 CogentEmbedded Inc 9 * Author: Andrey Gusakov <andrey.gusakov@cogentembedded.com> 10 * 11 * Copyright (C) 2016 Pengutronix, Philipp Zabel <p.zabel@pengutronix.de> 12 * 13 * Copyright (C) 2016 Zodiac Inflight Innovations 14 * 15 * Initially based on: drivers/gpu/drm/i2c/tda998x_drv.c 16 * 17 * Copyright (C) 2012 Texas Instruments 18 * Author: Rob Clark <robdclark@gmail.com> 19 */ 20 21 #include <linux/bitfield.h> 22 #include <linux/clk.h> 23 #include <linux/device.h> 24 #include <linux/gpio/consumer.h> 25 #include <linux/i2c.h> 26 #include <linux/kernel.h> 27 #include <linux/media-bus-format.h> 28 #include <linux/module.h> 29 #include <linux/regmap.h> 30 #include <linux/slab.h> 31 32 #include <drm/display/drm_dp_helper.h> 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_bridge.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_mipi_dsi.h> 37 #include <drm/drm_of.h> 38 #include <drm/drm_panel.h> 39 #include <drm/drm_print.h> 40 #include <drm/drm_probe_helper.h> 41 42 /* Registers */ 43 44 /* DSI D-PHY Layer registers */ 45 #define D0W_DPHYCONTTX 0x0004 46 #define CLW_DPHYCONTTX 0x0020 47 #define D0W_DPHYCONTRX 0x0024 48 #define D1W_DPHYCONTRX 0x0028 49 #define D2W_DPHYCONTRX 0x002c 50 #define D3W_DPHYCONTRX 0x0030 51 #define COM_DPHYCONTRX 0x0038 52 #define CLW_CNTRL 0x0040 53 #define D0W_CNTRL 0x0044 54 #define D1W_CNTRL 0x0048 55 #define D2W_CNTRL 0x004c 56 #define D3W_CNTRL 0x0050 57 #define TESTMODE_CNTRL 0x0054 58 59 /* PPI layer registers */ 60 #define PPI_STARTPPI 0x0104 /* START control bit */ 61 #define PPI_BUSYPPI 0x0108 /* PPI busy status */ 62 #define PPI_LPTXTIMECNT 0x0114 /* LPTX timing signal */ 63 #define LPX_PERIOD 3 64 #define PPI_LANEENABLE 0x0134 65 #define PPI_TX_RX_TA 0x013c 66 #define TTA_GET 0x40000 67 #define TTA_SURE 6 68 #define PPI_D0S_ATMR 0x0144 69 #define PPI_D1S_ATMR 0x0148 70 #define PPI_D0S_CLRSIPOCOUNT 0x0164 /* Assertion timer for Lane 0 */ 71 #define PPI_D1S_CLRSIPOCOUNT 0x0168 /* Assertion timer for Lane 1 */ 72 #define PPI_D2S_CLRSIPOCOUNT 0x016c /* Assertion timer for Lane 2 */ 73 #define PPI_D3S_CLRSIPOCOUNT 0x0170 /* Assertion timer for Lane 3 */ 74 #define PPI_START_FUNCTION BIT(0) 75 76 /* DSI layer registers */ 77 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */ 78 #define DSI_BUSYDSI 0x0208 /* DSI busy status */ 79 #define DSI_LANEENABLE 0x0210 /* Enables each lane */ 80 #define DSI_RX_START BIT(0) 81 82 /* Lane enable PPI and DSI register bits */ 83 #define LANEENABLE_CLEN BIT(0) 84 #define LANEENABLE_L0EN BIT(1) 85 #define LANEENABLE_L1EN BIT(2) 86 #define LANEENABLE_L2EN BIT(1) 87 #define LANEENABLE_L3EN BIT(2) 88 89 #define DSI_LANESTATUS0 0x0214 /* DSI lane status 0 */ 90 #define DSI_LANESTATUS1 0x0218 /* DSI lane status 1 */ 91 #define DSI_INTSTATUS 0x0220 /* Interrupt Status */ 92 #define DSI_INTMASK 0x0224 /* Interrupt Mask */ 93 #define DSI_INTCLR 0x0228 /* Interrupt Clear */ 94 #define DSI_LPTXTO 0x0230 /* LPTX Time Out Counter */ 95 96 /* DSI General Registers */ 97 #define DSIERRCNT 0x0300 /* DSI Error Count Register */ 98 99 /* DSI Application Layer Registers */ 100 #define APLCTRL 0x0400 /* Application layer Control Register */ 101 #define RDPKTLN 0x0404 /* DSI Read packet Length Register */ 102 103 /* Display Parallel Input Interface */ 104 #define DPIPXLFMT 0x0440 105 #define VS_POL_ACTIVE_LOW (1 << 10) 106 #define HS_POL_ACTIVE_LOW (1 << 9) 107 #define DE_POL_ACTIVE_HIGH (0 << 8) 108 #define SUB_CFG_TYPE_CONFIG1 (0 << 2) /* LSB aligned */ 109 #define SUB_CFG_TYPE_CONFIG2 (1 << 2) /* Loosely Packed */ 110 #define SUB_CFG_TYPE_CONFIG3 (2 << 2) /* LSB aligned 8-bit */ 111 #define DPI_BPP_RGB888 (0 << 0) 112 #define DPI_BPP_RGB666 (1 << 0) 113 #define DPI_BPP_RGB565 (2 << 0) 114 115 /* Display Parallel Output Interface */ 116 #define POCTRL 0x0448 117 #define POCTRL_S2P BIT(7) 118 #define POCTRL_PCLK_POL BIT(3) 119 #define POCTRL_VS_POL BIT(2) 120 #define POCTRL_HS_POL BIT(1) 121 #define POCTRL_DE_POL BIT(0) 122 123 /* Video Path */ 124 #define VPCTRL0 0x0450 125 #define VSDELAY GENMASK(31, 20) 126 #define OPXLFMT_RGB666 (0 << 8) 127 #define OPXLFMT_RGB888 (1 << 8) 128 #define FRMSYNC_DISABLED (0 << 4) /* Video Timing Gen Disabled */ 129 #define FRMSYNC_ENABLED (1 << 4) /* Video Timing Gen Enabled */ 130 #define MSF_DISABLED (0 << 0) /* Magic Square FRC disabled */ 131 #define MSF_ENABLED (1 << 0) /* Magic Square FRC enabled */ 132 #define HTIM01 0x0454 133 #define HPW GENMASK(8, 0) 134 #define HBPR GENMASK(24, 16) 135 #define HTIM02 0x0458 136 #define HDISPR GENMASK(10, 0) 137 #define HFPR GENMASK(24, 16) 138 #define VTIM01 0x045c 139 #define VSPR GENMASK(7, 0) 140 #define VBPR GENMASK(23, 16) 141 #define VTIM02 0x0460 142 #define VFPR GENMASK(23, 16) 143 #define VDISPR GENMASK(10, 0) 144 #define VFUEN0 0x0464 145 #define VFUEN BIT(0) /* Video Frame Timing Upload */ 146 147 /* System */ 148 #define TC_IDREG 0x0500 /* Chip ID and Revision ID */ 149 #define SYSBOOT 0x0504 /* System BootStrap Status Register */ 150 #define SYSSTAT 0x0508 /* System Status Register */ 151 #define SYSRSTENB 0x050c /* System Reset/Enable Register */ 152 #define ENBI2C (1 << 0) 153 #define ENBLCD0 (1 << 2) 154 #define ENBBM (1 << 3) 155 #define ENBDSIRX (1 << 4) 156 #define ENBREG (1 << 5) 157 #define ENBHDCP (1 << 8) 158 #define SYSCTRL 0x0510 /* System Control Register */ 159 #define DP0_AUDSRC_NO_INPUT (0 << 3) 160 #define DP0_AUDSRC_I2S_RX (1 << 3) 161 #define DP0_VIDSRC_NO_INPUT (0 << 0) 162 #define DP0_VIDSRC_DSI_RX (1 << 0) 163 #define DP0_VIDSRC_DPI_RX (2 << 0) 164 #define DP0_VIDSRC_COLOR_BAR (3 << 0) 165 #define GPIOM 0x0540 /* GPIO Mode Control Register */ 166 #define GPIOC 0x0544 /* GPIO Direction Control Register */ 167 #define GPIOO 0x0548 /* GPIO Output Register */ 168 #define GPIOI 0x054c /* GPIO Input Register */ 169 #define INTCTL_G 0x0560 /* General Interrupts Control Register */ 170 #define INTSTS_G 0x0564 /* General Interrupts Status Register */ 171 172 #define INT_SYSERR BIT(16) 173 #define INT_GPIO_H(x) (1 << (x == 0 ? 2 : 10)) 174 #define INT_GPIO_LC(x) (1 << (x == 0 ? 3 : 11)) 175 176 #define TEST_INT_C 0x0570 /* Test Interrupts Control Register */ 177 #define TEST_INT_S 0x0574 /* Test Interrupts Status Register */ 178 179 #define INT_GP0_LCNT 0x0584 /* Interrupt GPIO0 Low Count Value Register */ 180 #define INT_GP1_LCNT 0x0588 /* Interrupt GPIO1 Low Count Value Register */ 181 182 /* Control */ 183 #define DP0CTL 0x0600 184 #define VID_MN_GEN BIT(6) /* Auto-generate M/N values */ 185 #define EF_EN BIT(5) /* Enable Enhanced Framing */ 186 #define VID_EN BIT(1) /* Video transmission enable */ 187 #define DP_EN BIT(0) /* Enable DPTX function */ 188 189 /* Clocks */ 190 #define DP0_VIDMNGEN0 0x0610 /* DP0 Video Force M Value Register */ 191 #define DP0_VIDMNGEN1 0x0614 /* DP0 Video Force N Value Register */ 192 #define DP0_VMNGENSTATUS 0x0618 /* DP0 Video Current M Value Register */ 193 #define DP0_AUDMNGEN0 0x0628 /* DP0 Audio Force M Value Register */ 194 #define DP0_AUDMNGEN1 0x062c /* DP0 Audio Force N Value Register */ 195 #define DP0_AMNGENSTATUS 0x0630 /* DP0 Audio Current M Value Register */ 196 197 /* Main Channel */ 198 #define DP0_SECSAMPLE 0x0640 199 #define DP0_VIDSYNCDELAY 0x0644 200 #define VID_SYNC_DLY GENMASK(15, 0) 201 #define THRESH_DLY GENMASK(31, 16) 202 203 #define DP0_TOTALVAL 0x0648 204 #define H_TOTAL GENMASK(15, 0) 205 #define V_TOTAL GENMASK(31, 16) 206 #define DP0_STARTVAL 0x064c 207 #define H_START GENMASK(15, 0) 208 #define V_START GENMASK(31, 16) 209 #define DP0_ACTIVEVAL 0x0650 210 #define H_ACT GENMASK(15, 0) 211 #define V_ACT GENMASK(31, 16) 212 213 #define DP0_SYNCVAL 0x0654 214 #define VS_WIDTH GENMASK(30, 16) 215 #define HS_WIDTH GENMASK(14, 0) 216 #define SYNCVAL_HS_POL_ACTIVE_LOW (1 << 15) 217 #define SYNCVAL_VS_POL_ACTIVE_LOW (1 << 31) 218 #define DP0_MISC 0x0658 219 #define TU_SIZE_RECOMMENDED (63) /* LSCLK cycles per TU */ 220 #define MAX_TU_SYMBOL GENMASK(28, 23) 221 #define TU_SIZE GENMASK(21, 16) 222 #define BPC_6 (0 << 5) 223 #define BPC_8 (1 << 5) 224 225 /* AUX channel */ 226 #define DP0_AUXCFG0 0x0660 227 #define DP0_AUXCFG0_BSIZE GENMASK(11, 8) 228 #define DP0_AUXCFG0_ADDR_ONLY BIT(4) 229 #define DP0_AUXCFG1 0x0664 230 #define AUX_RX_FILTER_EN BIT(16) 231 232 #define DP0_AUXADDR 0x0668 233 #define DP0_AUXWDATA(i) (0x066c + (i) * 4) 234 #define DP0_AUXRDATA(i) (0x067c + (i) * 4) 235 #define DP0_AUXSTATUS 0x068c 236 #define AUX_BYTES GENMASK(15, 8) 237 #define AUX_STATUS GENMASK(7, 4) 238 #define AUX_TIMEOUT BIT(1) 239 #define AUX_BUSY BIT(0) 240 #define DP0_AUXI2CADR 0x0698 241 242 /* Link Training */ 243 #define DP0_SRCCTRL 0x06a0 244 #define DP0_SRCCTRL_SCRMBLDIS BIT(13) 245 #define DP0_SRCCTRL_EN810B BIT(12) 246 #define DP0_SRCCTRL_NOTP (0 << 8) 247 #define DP0_SRCCTRL_TP1 (1 << 8) 248 #define DP0_SRCCTRL_TP2 (2 << 8) 249 #define DP0_SRCCTRL_LANESKEW BIT(7) 250 #define DP0_SRCCTRL_SSCG BIT(3) 251 #define DP0_SRCCTRL_LANES_1 (0 << 2) 252 #define DP0_SRCCTRL_LANES_2 (1 << 2) 253 #define DP0_SRCCTRL_BW27 (1 << 1) 254 #define DP0_SRCCTRL_BW162 (0 << 1) 255 #define DP0_SRCCTRL_AUTOCORRECT BIT(0) 256 #define DP0_LTSTAT 0x06d0 257 #define LT_LOOPDONE BIT(13) 258 #define LT_STATUS_MASK (0x1f << 8) 259 #define LT_CHANNEL1_EQ_BITS (DP_CHANNEL_EQ_BITS << 4) 260 #define LT_INTERLANE_ALIGN_DONE BIT(3) 261 #define LT_CHANNEL0_EQ_BITS (DP_CHANNEL_EQ_BITS) 262 #define DP0_SNKLTCHGREQ 0x06d4 263 #define DP0_LTLOOPCTRL 0x06d8 264 #define DP0_SNKLTCTRL 0x06e4 265 #define DP0_TPATDAT0 0x06e8 /* DP0 Test Pattern bits 29 to 0 */ 266 #define DP0_TPATDAT1 0x06ec /* DP0 Test Pattern bits 59 to 30 */ 267 #define DP0_TPATDAT2 0x06f0 /* DP0 Test Pattern bits 89 to 60 */ 268 #define DP0_TPATDAT3 0x06f4 /* DP0 Test Pattern bits 119 to 90 */ 269 270 #define AUDCFG0 0x0700 /* DP0 Audio Config0 Register */ 271 #define AUDCFG1 0x0704 /* DP0 Audio Config1 Register */ 272 #define AUDIFDATA0 0x0708 /* DP0 Audio Info Frame Bytes 3 to 0 */ 273 #define AUDIFDATA1 0x070c /* DP0 Audio Info Frame Bytes 7 to 4 */ 274 #define AUDIFDATA2 0x0710 /* DP0 Audio Info Frame Bytes 11 to 8 */ 275 #define AUDIFDATA3 0x0714 /* DP0 Audio Info Frame Bytes 15 to 12 */ 276 #define AUDIFDATA4 0x0718 /* DP0 Audio Info Frame Bytes 19 to 16 */ 277 #define AUDIFDATA5 0x071c /* DP0 Audio Info Frame Bytes 23 to 20 */ 278 #define AUDIFDATA6 0x0720 /* DP0 Audio Info Frame Bytes 27 to 24 */ 279 280 #define DP1_SRCCTRL 0x07a0 /* DP1 Control Register */ 281 282 /* PHY */ 283 #define DP_PHY_CTRL 0x0800 284 #define DP_PHY_RST BIT(28) /* DP PHY Global Soft Reset */ 285 #define BGREN BIT(25) /* AUX PHY BGR Enable */ 286 #define PWR_SW_EN BIT(24) /* PHY Power Switch Enable */ 287 #define PHY_M1_RST BIT(12) /* Reset PHY1 Main Channel */ 288 #define PHY_RDY BIT(16) /* PHY Main Channels Ready */ 289 #define PHY_M0_RST BIT(8) /* Reset PHY0 Main Channel */ 290 #define PHY_2LANE BIT(2) /* PHY Enable 2 lanes */ 291 #define PHY_A0_EN BIT(1) /* PHY Aux Channel0 Enable */ 292 #define PHY_M0_EN BIT(0) /* PHY Main Channel0 Enable */ 293 #define DP_PHY_CFG_WR 0x0810 /* DP PHY Configuration Test Write Register */ 294 #define DP_PHY_CFG_RD 0x0814 /* DP PHY Configuration Test Read Register */ 295 #define DP0_AUX_PHY_CTRL 0x0820 /* DP0 AUX PHY Control Register */ 296 #define DP0_MAIN_PHY_DBG 0x0840 /* DP0 Main PHY Test Debug Register */ 297 298 /* I2S */ 299 #define I2SCFG 0x0880 /* I2S Audio Config 0 Register */ 300 #define I2SCH0STAT0 0x0888 /* I2S Audio Channel 0 Status Bytes 3 to 0 */ 301 #define I2SCH0STAT1 0x088c /* I2S Audio Channel 0 Status Bytes 7 to 4 */ 302 #define I2SCH0STAT2 0x0890 /* I2S Audio Channel 0 Status Bytes 11 to 8 */ 303 #define I2SCH0STAT3 0x0894 /* I2S Audio Channel 0 Status Bytes 15 to 12 */ 304 #define I2SCH0STAT4 0x0898 /* I2S Audio Channel 0 Status Bytes 19 to 16 */ 305 #define I2SCH0STAT5 0x089c /* I2S Audio Channel 0 Status Bytes 23 to 20 */ 306 #define I2SCH1STAT0 0x08a0 /* I2S Audio Channel 1 Status Bytes 3 to 0 */ 307 #define I2SCH1STAT1 0x08a4 /* I2S Audio Channel 1 Status Bytes 7 to 4 */ 308 #define I2SCH1STAT2 0x08a8 /* I2S Audio Channel 1 Status Bytes 11 to 8 */ 309 #define I2SCH1STAT3 0x08ac /* I2S Audio Channel 1 Status Bytes 15 to 12 */ 310 #define I2SCH1STAT4 0x08b0 /* I2S Audio Channel 1 Status Bytes 19 to 16 */ 311 #define I2SCH1STAT5 0x08b4 /* I2S Audio Channel 1 Status Bytes 23 to 20 */ 312 313 /* PLL */ 314 #define DP0_PLLCTRL 0x0900 315 #define DP1_PLLCTRL 0x0904 /* not defined in DS */ 316 #define PXL_PLLCTRL 0x0908 317 #define PLLUPDATE BIT(2) 318 #define PLLBYP BIT(1) 319 #define PLLEN BIT(0) 320 #define PXL_PLLPARAM 0x0914 321 #define IN_SEL_REFCLK (0 << 14) 322 #define SYS_PLLPARAM 0x0918 323 #define REF_FREQ_38M4 (0 << 8) /* 38.4 MHz */ 324 #define REF_FREQ_19M2 (1 << 8) /* 19.2 MHz */ 325 #define REF_FREQ_26M (2 << 8) /* 26 MHz */ 326 #define REF_FREQ_13M (3 << 8) /* 13 MHz */ 327 #define SYSCLK_SEL_LSCLK (0 << 4) 328 #define LSCLK_DIV_1 (0 << 0) 329 #define LSCLK_DIV_2 (1 << 0) 330 331 /* Test & Debug */ 332 #define TSTCTL 0x0a00 333 #define COLOR_R GENMASK(31, 24) 334 #define COLOR_G GENMASK(23, 16) 335 #define COLOR_B GENMASK(15, 8) 336 #define ENI2CFILTER BIT(4) 337 #define COLOR_BAR_MODE GENMASK(1, 0) 338 #define COLOR_BAR_MODE_BARS 2 339 #define PLL_DBG 0x0a04 340 341 static bool tc_test_pattern; 342 module_param_named(test, tc_test_pattern, bool, 0644); 343 344 struct tc_edp_link { 345 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 346 unsigned int rate; 347 u8 num_lanes; 348 u8 assr; 349 bool scrambler_dis; 350 bool spread; 351 }; 352 353 struct tc_data { 354 struct device *dev; 355 struct regmap *regmap; 356 struct drm_dp_aux aux; 357 358 struct drm_bridge bridge; 359 struct drm_bridge *panel_bridge; 360 struct drm_connector connector; 361 362 struct mipi_dsi_device *dsi; 363 364 /* link settings */ 365 struct tc_edp_link link; 366 367 /* current mode */ 368 struct drm_display_mode mode; 369 370 u32 rev; 371 u8 assr; 372 373 struct gpio_desc *sd_gpio; 374 struct gpio_desc *reset_gpio; 375 struct clk *refclk; 376 377 /* do we have IRQ */ 378 bool have_irq; 379 380 /* Input connector type, DSI and not DPI. */ 381 bool input_connector_dsi; 382 383 /* HPD pin number (0 or 1) or -ENODEV */ 384 int hpd_pin; 385 386 /* Number of pixels to subtract from a line due to pixel clock delta */ 387 u32 line_pixel_subtract; 388 }; 389 390 static inline struct tc_data *aux_to_tc(struct drm_dp_aux *a) 391 { 392 return container_of(a, struct tc_data, aux); 393 } 394 395 static inline struct tc_data *bridge_to_tc(struct drm_bridge *b) 396 { 397 return container_of(b, struct tc_data, bridge); 398 } 399 400 static inline struct tc_data *connector_to_tc(struct drm_connector *c) 401 { 402 return container_of(c, struct tc_data, connector); 403 } 404 405 static inline int tc_poll_timeout(struct tc_data *tc, unsigned int addr, 406 unsigned int cond_mask, 407 unsigned int cond_value, 408 unsigned long sleep_us, u64 timeout_us) 409 { 410 unsigned int val; 411 412 return regmap_read_poll_timeout(tc->regmap, addr, val, 413 (val & cond_mask) == cond_value, 414 sleep_us, timeout_us); 415 } 416 417 static int tc_aux_wait_busy(struct tc_data *tc) 418 { 419 return tc_poll_timeout(tc, DP0_AUXSTATUS, AUX_BUSY, 0, 100, 100000); 420 } 421 422 static int tc_aux_write_data(struct tc_data *tc, const void *data, 423 size_t size) 424 { 425 u32 auxwdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)] = { 0 }; 426 int ret, count = ALIGN(size, sizeof(u32)); 427 428 memcpy(auxwdata, data, size); 429 430 ret = regmap_raw_write(tc->regmap, DP0_AUXWDATA(0), auxwdata, count); 431 if (ret) 432 return ret; 433 434 return size; 435 } 436 437 static int tc_aux_read_data(struct tc_data *tc, void *data, size_t size) 438 { 439 u32 auxrdata[DP_AUX_MAX_PAYLOAD_BYTES / sizeof(u32)]; 440 int ret, count = ALIGN(size, sizeof(u32)); 441 442 ret = regmap_raw_read(tc->regmap, DP0_AUXRDATA(0), auxrdata, count); 443 if (ret) 444 return ret; 445 446 memcpy(data, auxrdata, size); 447 448 return size; 449 } 450 451 static u32 tc_auxcfg0(struct drm_dp_aux_msg *msg, size_t size) 452 { 453 u32 auxcfg0 = msg->request; 454 455 if (size) 456 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1); 457 else 458 auxcfg0 |= DP0_AUXCFG0_ADDR_ONLY; 459 460 return auxcfg0; 461 } 462 463 static ssize_t tc_aux_transfer(struct drm_dp_aux *aux, 464 struct drm_dp_aux_msg *msg) 465 { 466 struct tc_data *tc = aux_to_tc(aux); 467 size_t size = min_t(size_t, DP_AUX_MAX_PAYLOAD_BYTES - 1, msg->size); 468 u8 request = msg->request & ~DP_AUX_I2C_MOT; 469 u32 auxstatus; 470 int ret; 471 472 ret = tc_aux_wait_busy(tc); 473 if (ret) 474 return ret; 475 476 switch (request) { 477 case DP_AUX_NATIVE_READ: 478 case DP_AUX_I2C_READ: 479 break; 480 case DP_AUX_NATIVE_WRITE: 481 case DP_AUX_I2C_WRITE: 482 if (size) { 483 ret = tc_aux_write_data(tc, msg->buffer, size); 484 if (ret < 0) 485 return ret; 486 } 487 break; 488 default: 489 return -EINVAL; 490 } 491 492 /* Store address */ 493 ret = regmap_write(tc->regmap, DP0_AUXADDR, msg->address); 494 if (ret) 495 return ret; 496 /* Start transfer */ 497 ret = regmap_write(tc->regmap, DP0_AUXCFG0, tc_auxcfg0(msg, size)); 498 if (ret) 499 return ret; 500 501 ret = tc_aux_wait_busy(tc); 502 if (ret) 503 return ret; 504 505 ret = regmap_read(tc->regmap, DP0_AUXSTATUS, &auxstatus); 506 if (ret) 507 return ret; 508 509 if (auxstatus & AUX_TIMEOUT) 510 return -ETIMEDOUT; 511 /* 512 * For some reason address-only DP_AUX_I2C_WRITE (MOT), still 513 * reports 1 byte transferred in its status. To deal we that 514 * we ignore aux_bytes field if we know that this was an 515 * address-only transfer 516 */ 517 if (size) 518 size = FIELD_GET(AUX_BYTES, auxstatus); 519 msg->reply = FIELD_GET(AUX_STATUS, auxstatus); 520 521 switch (request) { 522 case DP_AUX_NATIVE_READ: 523 case DP_AUX_I2C_READ: 524 if (size) 525 return tc_aux_read_data(tc, msg->buffer, size); 526 break; 527 } 528 529 return size; 530 } 531 532 static const char * const training_pattern1_errors[] = { 533 "No errors", 534 "Aux write error", 535 "Aux read error", 536 "Max voltage reached error", 537 "Loop counter expired error", 538 "res", "res", "res" 539 }; 540 541 static const char * const training_pattern2_errors[] = { 542 "No errors", 543 "Aux write error", 544 "Aux read error", 545 "Clock recovery failed error", 546 "Loop counter expired error", 547 "res", "res", "res" 548 }; 549 550 static u32 tc_srcctrl(struct tc_data *tc) 551 { 552 /* 553 * No training pattern, skew lane 1 data by two LSCLK cycles with 554 * respect to lane 0 data, AutoCorrect Mode = 0 555 */ 556 u32 reg = DP0_SRCCTRL_NOTP | DP0_SRCCTRL_LANESKEW | DP0_SRCCTRL_EN810B; 557 558 if (tc->link.scrambler_dis) 559 reg |= DP0_SRCCTRL_SCRMBLDIS; /* Scrambler Disabled */ 560 if (tc->link.spread) 561 reg |= DP0_SRCCTRL_SSCG; /* Spread Spectrum Enable */ 562 if (tc->link.num_lanes == 2) 563 reg |= DP0_SRCCTRL_LANES_2; /* Two Main Channel Lanes */ 564 if (tc->link.rate != 162000) 565 reg |= DP0_SRCCTRL_BW27; /* 2.7 Gbps link */ 566 return reg; 567 } 568 569 static int tc_pllupdate(struct tc_data *tc, unsigned int pllctrl) 570 { 571 int ret; 572 573 ret = regmap_write(tc->regmap, pllctrl, PLLUPDATE | PLLEN); 574 if (ret) 575 return ret; 576 577 /* Wait for PLL to lock: up to 7.5 ms, depending on refclk */ 578 usleep_range(15000, 20000); 579 580 return 0; 581 } 582 583 static u32 div64_round_up(u64 v, u32 d) 584 { 585 return div_u64(v + d - 1, d); 586 } 587 588 static int tc_pxl_pll_en(struct tc_data *tc, u32 refclk, u32 pixelclock) 589 { 590 int ret; 591 int i_pre, best_pre = 1; 592 int i_post, best_post = 1; 593 int div, best_div = 1; 594 int mul, best_mul = 1; 595 int delta, best_delta; 596 int ext_div[] = {1, 2, 3, 5, 7}; 597 int clk_min, clk_max; 598 int best_pixelclock = 0; 599 int vco_hi = 0; 600 u32 pxl_pllparam; 601 602 /* 603 * refclk * mul / (ext_pre_div * pre_div) should be in range: 604 * - DPI ..... 0 to 100 MHz 605 * - (e)DP ... 150 to 650 MHz 606 */ 607 if (tc->bridge.type == DRM_MODE_CONNECTOR_DPI) { 608 clk_min = 0; 609 clk_max = 100000000; 610 } else { 611 clk_min = 150000000; 612 clk_max = 650000000; 613 } 614 615 dev_dbg(tc->dev, "PLL: requested %d pixelclock, ref %d\n", pixelclock, 616 refclk); 617 best_delta = pixelclock; 618 /* Loop over all possible ext_divs, skipping invalid configurations */ 619 for (i_pre = 0; i_pre < ARRAY_SIZE(ext_div); i_pre++) { 620 /* 621 * refclk / ext_pre_div should be in the 1 to 200 MHz range. 622 * We don't allow any refclk > 200 MHz, only check lower bounds. 623 */ 624 if (refclk / ext_div[i_pre] < 1000000) 625 continue; 626 for (i_post = 0; i_post < ARRAY_SIZE(ext_div); i_post++) { 627 for (div = 1; div <= 16; div++) { 628 u32 clk, iclk; 629 u64 tmp; 630 631 /* PCLK PLL input unit clock ... 6..40 MHz */ 632 iclk = refclk / (div * ext_div[i_pre]); 633 if (iclk < 6000000 || iclk > 40000000) 634 continue; 635 636 tmp = pixelclock * ext_div[i_pre] * 637 ext_div[i_post] * div; 638 do_div(tmp, refclk); 639 mul = tmp; 640 641 /* Check limits */ 642 if ((mul < 1) || (mul > 128)) 643 continue; 644 645 clk = (refclk / ext_div[i_pre] / div) * mul; 646 if ((clk > clk_max) || (clk < clk_min)) 647 continue; 648 649 clk = clk / ext_div[i_post]; 650 delta = clk - pixelclock; 651 652 if (abs(delta) < abs(best_delta)) { 653 best_pre = i_pre; 654 best_post = i_post; 655 best_div = div; 656 best_mul = mul; 657 best_delta = delta; 658 best_pixelclock = clk; 659 } 660 } 661 } 662 } 663 if (best_pixelclock == 0) { 664 dev_err(tc->dev, "Failed to calc clock for %d pixelclock\n", 665 pixelclock); 666 return -EINVAL; 667 } 668 669 tc->line_pixel_subtract = tc->mode.htotal - 670 div64_round_up(tc->mode.htotal * (u64)best_pixelclock, pixelclock); 671 672 dev_dbg(tc->dev, "PLL: got %d, delta %d (subtract %d px)\n", best_pixelclock, 673 best_delta, tc->line_pixel_subtract); 674 dev_dbg(tc->dev, "PLL: %d / %d / %d * %d / %d\n", refclk, 675 ext_div[best_pre], best_div, best_mul, ext_div[best_post]); 676 677 /* if VCO >= 300 MHz */ 678 if (refclk / ext_div[best_pre] / best_div * best_mul >= 300000000) 679 vco_hi = 1; 680 /* see DS */ 681 if (best_div == 16) 682 best_div = 0; 683 if (best_mul == 128) 684 best_mul = 0; 685 686 /* Power up PLL and switch to bypass */ 687 ret = regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP | PLLEN); 688 if (ret) 689 return ret; 690 691 pxl_pllparam = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */ 692 pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */ 693 pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */ 694 pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */ 695 pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */ 696 pxl_pllparam |= best_mul; /* Multiplier for PLL */ 697 698 ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam); 699 if (ret) 700 return ret; 701 702 /* Force PLL parameter update and disable bypass */ 703 return tc_pllupdate(tc, PXL_PLLCTRL); 704 } 705 706 static int tc_pxl_pll_dis(struct tc_data *tc) 707 { 708 /* Enable PLL bypass, power down PLL */ 709 return regmap_write(tc->regmap, PXL_PLLCTRL, PLLBYP); 710 } 711 712 static int tc_stream_clock_calc(struct tc_data *tc) 713 { 714 /* 715 * If the Stream clock and Link Symbol clock are 716 * asynchronous with each other, the value of M changes over 717 * time. This way of generating link clock and stream 718 * clock is called Asynchronous Clock mode. The value M 719 * must change while the value N stays constant. The 720 * value of N in this Asynchronous Clock mode must be set 721 * to 2^15 or 32,768. 722 * 723 * LSCLK = 1/10 of high speed link clock 724 * 725 * f_STRMCLK = M/N * f_LSCLK 726 * M/N = f_STRMCLK / f_LSCLK 727 * 728 */ 729 return regmap_write(tc->regmap, DP0_VIDMNGEN1, 32768); 730 } 731 732 static int tc_set_syspllparam(struct tc_data *tc) 733 { 734 unsigned long rate; 735 u32 pllparam = SYSCLK_SEL_LSCLK | LSCLK_DIV_2; 736 737 rate = clk_get_rate(tc->refclk); 738 switch (rate) { 739 case 38400000: 740 pllparam |= REF_FREQ_38M4; 741 break; 742 case 26000000: 743 pllparam |= REF_FREQ_26M; 744 break; 745 case 19200000: 746 pllparam |= REF_FREQ_19M2; 747 break; 748 case 13000000: 749 pllparam |= REF_FREQ_13M; 750 break; 751 default: 752 dev_err(tc->dev, "Invalid refclk rate: %lu Hz\n", rate); 753 return -EINVAL; 754 } 755 756 return regmap_write(tc->regmap, SYS_PLLPARAM, pllparam); 757 } 758 759 static int tc_aux_link_setup(struct tc_data *tc) 760 { 761 int ret; 762 u32 dp0_auxcfg1; 763 764 /* Setup DP-PHY / PLL */ 765 ret = tc_set_syspllparam(tc); 766 if (ret) 767 goto err; 768 769 ret = regmap_write(tc->regmap, DP_PHY_CTRL, 770 BGREN | PWR_SW_EN | PHY_A0_EN); 771 if (ret) 772 goto err; 773 /* 774 * Initially PLLs are in bypass. Force PLL parameter update, 775 * disable PLL bypass, enable PLL 776 */ 777 ret = tc_pllupdate(tc, DP0_PLLCTRL); 778 if (ret) 779 goto err; 780 781 ret = tc_pllupdate(tc, DP1_PLLCTRL); 782 if (ret) 783 goto err; 784 785 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 100, 100000); 786 if (ret == -ETIMEDOUT) { 787 dev_err(tc->dev, "Timeout waiting for PHY to become ready"); 788 return ret; 789 } else if (ret) { 790 goto err; 791 } 792 793 /* Setup AUX link */ 794 dp0_auxcfg1 = AUX_RX_FILTER_EN; 795 dp0_auxcfg1 |= 0x06 << 8; /* Aux Bit Period Calculator Threshold */ 796 dp0_auxcfg1 |= 0x3f << 0; /* Aux Response Timeout Timer */ 797 798 ret = regmap_write(tc->regmap, DP0_AUXCFG1, dp0_auxcfg1); 799 if (ret) 800 goto err; 801 802 /* Register DP AUX channel */ 803 tc->aux.name = "TC358767 AUX i2c adapter"; 804 tc->aux.dev = tc->dev; 805 tc->aux.transfer = tc_aux_transfer; 806 drm_dp_aux_init(&tc->aux); 807 808 return 0; 809 err: 810 dev_err(tc->dev, "tc_aux_link_setup failed: %d\n", ret); 811 return ret; 812 } 813 814 static int tc_get_display_props(struct tc_data *tc) 815 { 816 u8 revision, num_lanes; 817 unsigned int rate; 818 int ret; 819 u8 reg; 820 821 /* Read DP Rx Link Capability */ 822 ret = drm_dp_dpcd_read(&tc->aux, DP_DPCD_REV, tc->link.dpcd, 823 DP_RECEIVER_CAP_SIZE); 824 if (ret < 0) 825 goto err_dpcd_read; 826 827 revision = tc->link.dpcd[DP_DPCD_REV]; 828 rate = drm_dp_max_link_rate(tc->link.dpcd); 829 num_lanes = drm_dp_max_lane_count(tc->link.dpcd); 830 831 if (rate != 162000 && rate != 270000) { 832 dev_dbg(tc->dev, "Falling to 2.7 Gbps rate\n"); 833 rate = 270000; 834 } 835 836 tc->link.rate = rate; 837 838 if (num_lanes > 2) { 839 dev_dbg(tc->dev, "Falling to 2 lanes\n"); 840 num_lanes = 2; 841 } 842 843 tc->link.num_lanes = num_lanes; 844 845 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAX_DOWNSPREAD, ®); 846 if (ret < 0) 847 goto err_dpcd_read; 848 tc->link.spread = reg & DP_MAX_DOWNSPREAD_0_5; 849 850 ret = drm_dp_dpcd_readb(&tc->aux, DP_MAIN_LINK_CHANNEL_CODING, ®); 851 if (ret < 0) 852 goto err_dpcd_read; 853 854 tc->link.scrambler_dis = false; 855 /* read assr */ 856 ret = drm_dp_dpcd_readb(&tc->aux, DP_EDP_CONFIGURATION_SET, ®); 857 if (ret < 0) 858 goto err_dpcd_read; 859 tc->link.assr = reg & DP_ALTERNATE_SCRAMBLER_RESET_ENABLE; 860 861 dev_dbg(tc->dev, "DPCD rev: %d.%d, rate: %s, lanes: %d, framing: %s\n", 862 revision >> 4, revision & 0x0f, 863 (tc->link.rate == 162000) ? "1.62Gbps" : "2.7Gbps", 864 tc->link.num_lanes, 865 drm_dp_enhanced_frame_cap(tc->link.dpcd) ? 866 "enhanced" : "default"); 867 dev_dbg(tc->dev, "Downspread: %s, scrambler: %s\n", 868 tc->link.spread ? "0.5%" : "0.0%", 869 tc->link.scrambler_dis ? "disabled" : "enabled"); 870 dev_dbg(tc->dev, "Display ASSR: %d, TC358767 ASSR: %d\n", 871 tc->link.assr, tc->assr); 872 873 return 0; 874 875 err_dpcd_read: 876 dev_err(tc->dev, "failed to read DPCD: %d\n", ret); 877 return ret; 878 } 879 880 static int tc_set_common_video_mode(struct tc_data *tc, 881 const struct drm_display_mode *mode) 882 { 883 int left_margin = mode->htotal - mode->hsync_end; 884 int right_margin = mode->hsync_start - mode->hdisplay; 885 int hsync_len = mode->hsync_end - mode->hsync_start; 886 int upper_margin = mode->vtotal - mode->vsync_end; 887 int lower_margin = mode->vsync_start - mode->vdisplay; 888 int vsync_len = mode->vsync_end - mode->vsync_start; 889 int ret; 890 891 dev_dbg(tc->dev, "set mode %dx%d\n", 892 mode->hdisplay, mode->vdisplay); 893 dev_dbg(tc->dev, "H margin %d,%d sync %d\n", 894 left_margin, right_margin, hsync_len); 895 dev_dbg(tc->dev, "V margin %d,%d sync %d\n", 896 upper_margin, lower_margin, vsync_len); 897 dev_dbg(tc->dev, "total: %dx%d\n", mode->htotal, mode->vtotal); 898 899 if (right_margin > tc->line_pixel_subtract) { 900 right_margin -= tc->line_pixel_subtract; 901 } else { 902 dev_err(tc->dev, "Bridge pixel clock too slow for mode\n"); 903 right_margin = 0; 904 } 905 906 /* 907 * LCD Ctl Frame Size 908 * datasheet is not clear of vsdelay in case of DPI 909 * assume we do not need any delay when DPI is a source of 910 * sync signals 911 */ 912 ret = regmap_write(tc->regmap, VPCTRL0, 913 FIELD_PREP(VSDELAY, right_margin + 10) | 914 OPXLFMT_RGB888 | FRMSYNC_ENABLED | MSF_DISABLED); 915 if (ret) 916 return ret; 917 918 ret = regmap_write(tc->regmap, HTIM01, 919 FIELD_PREP(HBPR, ALIGN(left_margin, 2)) | 920 FIELD_PREP(HPW, ALIGN(hsync_len, 2))); 921 if (ret) 922 return ret; 923 924 ret = regmap_write(tc->regmap, HTIM02, 925 FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) | 926 FIELD_PREP(HFPR, ALIGN(right_margin, 2))); 927 if (ret) 928 return ret; 929 930 ret = regmap_write(tc->regmap, VTIM01, 931 FIELD_PREP(VBPR, upper_margin) | 932 FIELD_PREP(VSPR, vsync_len)); 933 if (ret) 934 return ret; 935 936 ret = regmap_write(tc->regmap, VTIM02, 937 FIELD_PREP(VFPR, lower_margin) | 938 FIELD_PREP(VDISPR, mode->vdisplay)); 939 if (ret) 940 return ret; 941 942 ret = regmap_write(tc->regmap, VFUEN0, VFUEN); /* update settings */ 943 if (ret) 944 return ret; 945 946 /* Test pattern settings */ 947 ret = regmap_write(tc->regmap, TSTCTL, 948 FIELD_PREP(COLOR_R, 120) | 949 FIELD_PREP(COLOR_G, 20) | 950 FIELD_PREP(COLOR_B, 99) | 951 ENI2CFILTER | 952 FIELD_PREP(COLOR_BAR_MODE, COLOR_BAR_MODE_BARS)); 953 954 return ret; 955 } 956 957 static int tc_set_dpi_video_mode(struct tc_data *tc, 958 const struct drm_display_mode *mode) 959 { 960 u32 value = POCTRL_S2P; 961 962 if (tc->mode.flags & DRM_MODE_FLAG_NHSYNC) 963 value |= POCTRL_HS_POL; 964 965 if (tc->mode.flags & DRM_MODE_FLAG_NVSYNC) 966 value |= POCTRL_VS_POL; 967 968 return regmap_write(tc->regmap, POCTRL, value); 969 } 970 971 static int tc_set_edp_video_mode(struct tc_data *tc, 972 const struct drm_display_mode *mode) 973 { 974 int ret; 975 int vid_sync_dly; 976 int max_tu_symbol; 977 978 int left_margin = mode->htotal - mode->hsync_end; 979 int hsync_len = mode->hsync_end - mode->hsync_start; 980 int upper_margin = mode->vtotal - mode->vsync_end; 981 int vsync_len = mode->vsync_end - mode->vsync_start; 982 u32 dp0_syncval; 983 u32 bits_per_pixel = 24; 984 u32 in_bw, out_bw; 985 u32 dpipxlfmt; 986 987 /* 988 * Recommended maximum number of symbols transferred in a transfer unit: 989 * DIV_ROUND_UP((input active video bandwidth in bytes) * tu_size, 990 * (output active video bandwidth in bytes)) 991 * Must be less than tu_size. 992 */ 993 994 in_bw = mode->clock * bits_per_pixel / 8; 995 out_bw = tc->link.num_lanes * tc->link.rate; 996 max_tu_symbol = DIV_ROUND_UP(in_bw * TU_SIZE_RECOMMENDED, out_bw); 997 998 /* DP Main Stream Attributes */ 999 vid_sync_dly = hsync_len + left_margin + mode->hdisplay; 1000 ret = regmap_write(tc->regmap, DP0_VIDSYNCDELAY, 1001 FIELD_PREP(THRESH_DLY, max_tu_symbol) | 1002 FIELD_PREP(VID_SYNC_DLY, vid_sync_dly)); 1003 1004 ret = regmap_write(tc->regmap, DP0_TOTALVAL, 1005 FIELD_PREP(H_TOTAL, mode->htotal) | 1006 FIELD_PREP(V_TOTAL, mode->vtotal)); 1007 if (ret) 1008 return ret; 1009 1010 ret = regmap_write(tc->regmap, DP0_STARTVAL, 1011 FIELD_PREP(H_START, left_margin + hsync_len) | 1012 FIELD_PREP(V_START, upper_margin + vsync_len)); 1013 if (ret) 1014 return ret; 1015 1016 ret = regmap_write(tc->regmap, DP0_ACTIVEVAL, 1017 FIELD_PREP(V_ACT, mode->vdisplay) | 1018 FIELD_PREP(H_ACT, mode->hdisplay)); 1019 if (ret) 1020 return ret; 1021 1022 dp0_syncval = FIELD_PREP(VS_WIDTH, vsync_len) | 1023 FIELD_PREP(HS_WIDTH, hsync_len); 1024 1025 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1026 dp0_syncval |= SYNCVAL_VS_POL_ACTIVE_LOW; 1027 1028 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1029 dp0_syncval |= SYNCVAL_HS_POL_ACTIVE_LOW; 1030 1031 ret = regmap_write(tc->regmap, DP0_SYNCVAL, dp0_syncval); 1032 if (ret) 1033 return ret; 1034 1035 dpipxlfmt = DE_POL_ACTIVE_HIGH | SUB_CFG_TYPE_CONFIG1 | DPI_BPP_RGB888; 1036 1037 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 1038 dpipxlfmt |= VS_POL_ACTIVE_LOW; 1039 1040 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 1041 dpipxlfmt |= HS_POL_ACTIVE_LOW; 1042 1043 ret = regmap_write(tc->regmap, DPIPXLFMT, dpipxlfmt); 1044 if (ret) 1045 return ret; 1046 1047 ret = regmap_write(tc->regmap, DP0_MISC, 1048 FIELD_PREP(MAX_TU_SYMBOL, max_tu_symbol) | 1049 FIELD_PREP(TU_SIZE, TU_SIZE_RECOMMENDED) | 1050 BPC_8); 1051 return ret; 1052 } 1053 1054 static int tc_wait_link_training(struct tc_data *tc) 1055 { 1056 u32 value; 1057 int ret; 1058 1059 ret = tc_poll_timeout(tc, DP0_LTSTAT, LT_LOOPDONE, 1060 LT_LOOPDONE, 500, 100000); 1061 if (ret) { 1062 dev_err(tc->dev, "Link training timeout waiting for LT_LOOPDONE!\n"); 1063 return ret; 1064 } 1065 1066 ret = regmap_read(tc->regmap, DP0_LTSTAT, &value); 1067 if (ret) 1068 return ret; 1069 1070 return (value >> 8) & 0x7; 1071 } 1072 1073 static int tc_main_link_enable(struct tc_data *tc) 1074 { 1075 struct drm_dp_aux *aux = &tc->aux; 1076 struct device *dev = tc->dev; 1077 u32 dp_phy_ctrl; 1078 u32 value; 1079 int ret; 1080 u8 tmp[DP_LINK_STATUS_SIZE]; 1081 1082 dev_dbg(tc->dev, "link enable\n"); 1083 1084 ret = regmap_read(tc->regmap, DP0CTL, &value); 1085 if (ret) 1086 return ret; 1087 1088 if (WARN_ON(value & DP_EN)) { 1089 ret = regmap_write(tc->regmap, DP0CTL, 0); 1090 if (ret) 1091 return ret; 1092 } 1093 1094 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc)); 1095 if (ret) 1096 return ret; 1097 /* SSCG and BW27 on DP1 must be set to the same as on DP0 */ 1098 ret = regmap_write(tc->regmap, DP1_SRCCTRL, 1099 (tc->link.spread ? DP0_SRCCTRL_SSCG : 0) | 1100 ((tc->link.rate != 162000) ? DP0_SRCCTRL_BW27 : 0)); 1101 if (ret) 1102 return ret; 1103 1104 ret = tc_set_syspllparam(tc); 1105 if (ret) 1106 return ret; 1107 1108 /* Setup Main Link */ 1109 dp_phy_ctrl = BGREN | PWR_SW_EN | PHY_A0_EN | PHY_M0_EN; 1110 if (tc->link.num_lanes == 2) 1111 dp_phy_ctrl |= PHY_2LANE; 1112 1113 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); 1114 if (ret) 1115 return ret; 1116 1117 /* PLL setup */ 1118 ret = tc_pllupdate(tc, DP0_PLLCTRL); 1119 if (ret) 1120 return ret; 1121 1122 ret = tc_pllupdate(tc, DP1_PLLCTRL); 1123 if (ret) 1124 return ret; 1125 1126 /* Reset/Enable Main Links */ 1127 dp_phy_ctrl |= DP_PHY_RST | PHY_M1_RST | PHY_M0_RST; 1128 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); 1129 usleep_range(100, 200); 1130 dp_phy_ctrl &= ~(DP_PHY_RST | PHY_M1_RST | PHY_M0_RST); 1131 ret = regmap_write(tc->regmap, DP_PHY_CTRL, dp_phy_ctrl); 1132 1133 ret = tc_poll_timeout(tc, DP_PHY_CTRL, PHY_RDY, PHY_RDY, 500, 100000); 1134 if (ret) { 1135 dev_err(dev, "timeout waiting for phy become ready"); 1136 return ret; 1137 } 1138 1139 /* Set misc: 8 bits per color */ 1140 ret = regmap_update_bits(tc->regmap, DP0_MISC, BPC_8, BPC_8); 1141 if (ret) 1142 return ret; 1143 1144 /* 1145 * ASSR mode 1146 * on TC358767 side ASSR configured through strap pin 1147 * seems there is no way to change this setting from SW 1148 * 1149 * check is tc configured for same mode 1150 */ 1151 if (tc->assr != tc->link.assr) { 1152 dev_dbg(dev, "Trying to set display to ASSR: %d\n", 1153 tc->assr); 1154 /* try to set ASSR on display side */ 1155 tmp[0] = tc->assr; 1156 ret = drm_dp_dpcd_writeb(aux, DP_EDP_CONFIGURATION_SET, tmp[0]); 1157 if (ret < 0) 1158 goto err_dpcd_read; 1159 /* read back */ 1160 ret = drm_dp_dpcd_readb(aux, DP_EDP_CONFIGURATION_SET, tmp); 1161 if (ret < 0) 1162 goto err_dpcd_read; 1163 1164 if (tmp[0] != tc->assr) { 1165 dev_dbg(dev, "Failed to switch display ASSR to %d, falling back to unscrambled mode\n", 1166 tc->assr); 1167 /* trying with disabled scrambler */ 1168 tc->link.scrambler_dis = true; 1169 } 1170 } 1171 1172 /* Setup Link & DPRx Config for Training */ 1173 tmp[0] = drm_dp_link_rate_to_bw_code(tc->link.rate); 1174 tmp[1] = tc->link.num_lanes; 1175 1176 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) 1177 tmp[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 1178 1179 ret = drm_dp_dpcd_write(aux, DP_LINK_BW_SET, tmp, 2); 1180 if (ret < 0) 1181 goto err_dpcd_write; 1182 1183 /* DOWNSPREAD_CTRL */ 1184 tmp[0] = tc->link.spread ? DP_SPREAD_AMP_0_5 : 0x00; 1185 /* MAIN_LINK_CHANNEL_CODING_SET */ 1186 tmp[1] = DP_SET_ANSI_8B10B; 1187 ret = drm_dp_dpcd_write(aux, DP_DOWNSPREAD_CTRL, tmp, 2); 1188 if (ret < 0) 1189 goto err_dpcd_write; 1190 1191 /* Reset voltage-swing & pre-emphasis */ 1192 tmp[0] = tmp[1] = DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | 1193 DP_TRAIN_PRE_EMPH_LEVEL_0; 1194 ret = drm_dp_dpcd_write(aux, DP_TRAINING_LANE0_SET, tmp, 2); 1195 if (ret < 0) 1196 goto err_dpcd_write; 1197 1198 /* Clock-Recovery */ 1199 1200 /* Set DPCD 0x102 for Training Pattern 1 */ 1201 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, 1202 DP_LINK_SCRAMBLING_DISABLE | 1203 DP_TRAINING_PATTERN_1); 1204 if (ret) 1205 return ret; 1206 1207 ret = regmap_write(tc->regmap, DP0_LTLOOPCTRL, 1208 (15 << 28) | /* Defer Iteration Count */ 1209 (15 << 24) | /* Loop Iteration Count */ 1210 (0xd << 0)); /* Loop Timer Delay */ 1211 if (ret) 1212 return ret; 1213 1214 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 1215 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | 1216 DP0_SRCCTRL_AUTOCORRECT | 1217 DP0_SRCCTRL_TP1); 1218 if (ret) 1219 return ret; 1220 1221 /* Enable DP0 to start Link Training */ 1222 ret = regmap_write(tc->regmap, DP0CTL, 1223 (drm_dp_enhanced_frame_cap(tc->link.dpcd) ? 1224 EF_EN : 0) | DP_EN); 1225 if (ret) 1226 return ret; 1227 1228 /* wait */ 1229 1230 ret = tc_wait_link_training(tc); 1231 if (ret < 0) 1232 return ret; 1233 1234 if (ret) { 1235 dev_err(tc->dev, "Link training phase 1 failed: %s\n", 1236 training_pattern1_errors[ret]); 1237 return -ENODEV; 1238 } 1239 1240 /* Channel Equalization */ 1241 1242 /* Set DPCD 0x102 for Training Pattern 2 */ 1243 ret = regmap_write(tc->regmap, DP0_SNKLTCTRL, 1244 DP_LINK_SCRAMBLING_DISABLE | 1245 DP_TRAINING_PATTERN_2); 1246 if (ret) 1247 return ret; 1248 1249 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 1250 tc_srcctrl(tc) | DP0_SRCCTRL_SCRMBLDIS | 1251 DP0_SRCCTRL_AUTOCORRECT | 1252 DP0_SRCCTRL_TP2); 1253 if (ret) 1254 return ret; 1255 1256 /* wait */ 1257 ret = tc_wait_link_training(tc); 1258 if (ret < 0) 1259 return ret; 1260 1261 if (ret) { 1262 dev_err(tc->dev, "Link training phase 2 failed: %s\n", 1263 training_pattern2_errors[ret]); 1264 return -ENODEV; 1265 } 1266 1267 /* 1268 * Toshiba's documentation suggests to first clear DPCD 0x102, then 1269 * clear the training pattern bit in DP0_SRCCTRL. Testing shows 1270 * that the link sometimes drops if those steps are done in that order, 1271 * but if the steps are done in reverse order, the link stays up. 1272 * 1273 * So we do the steps differently than documented here. 1274 */ 1275 1276 /* Clear Training Pattern, set AutoCorrect Mode = 1 */ 1277 ret = regmap_write(tc->regmap, DP0_SRCCTRL, tc_srcctrl(tc) | 1278 DP0_SRCCTRL_AUTOCORRECT); 1279 if (ret) 1280 return ret; 1281 1282 /* Clear DPCD 0x102 */ 1283 /* Note: Can Not use DP0_SNKLTCTRL (0x06E4) short cut */ 1284 tmp[0] = tc->link.scrambler_dis ? DP_LINK_SCRAMBLING_DISABLE : 0x00; 1285 ret = drm_dp_dpcd_writeb(aux, DP_TRAINING_PATTERN_SET, tmp[0]); 1286 if (ret < 0) 1287 goto err_dpcd_write; 1288 1289 /* Check link status */ 1290 ret = drm_dp_dpcd_read_link_status(aux, tmp); 1291 if (ret < 0) 1292 goto err_dpcd_read; 1293 1294 ret = 0; 1295 1296 value = tmp[0] & DP_CHANNEL_EQ_BITS; 1297 1298 if (value != DP_CHANNEL_EQ_BITS) { 1299 dev_err(tc->dev, "Lane 0 failed: %x\n", value); 1300 ret = -ENODEV; 1301 } 1302 1303 if (tc->link.num_lanes == 2) { 1304 value = (tmp[0] >> 4) & DP_CHANNEL_EQ_BITS; 1305 1306 if (value != DP_CHANNEL_EQ_BITS) { 1307 dev_err(tc->dev, "Lane 1 failed: %x\n", value); 1308 ret = -ENODEV; 1309 } 1310 1311 if (!(tmp[2] & DP_INTERLANE_ALIGN_DONE)) { 1312 dev_err(tc->dev, "Interlane align failed\n"); 1313 ret = -ENODEV; 1314 } 1315 } 1316 1317 if (ret) { 1318 dev_err(dev, "0x0202 LANE0_1_STATUS: 0x%02x\n", tmp[0]); 1319 dev_err(dev, "0x0203 LANE2_3_STATUS 0x%02x\n", tmp[1]); 1320 dev_err(dev, "0x0204 LANE_ALIGN_STATUS_UPDATED: 0x%02x\n", tmp[2]); 1321 dev_err(dev, "0x0205 SINK_STATUS: 0x%02x\n", tmp[3]); 1322 dev_err(dev, "0x0206 ADJUST_REQUEST_LANE0_1: 0x%02x\n", tmp[4]); 1323 dev_err(dev, "0x0207 ADJUST_REQUEST_LANE2_3: 0x%02x\n", tmp[5]); 1324 return ret; 1325 } 1326 1327 return 0; 1328 err_dpcd_read: 1329 dev_err(tc->dev, "Failed to read DPCD: %d\n", ret); 1330 return ret; 1331 err_dpcd_write: 1332 dev_err(tc->dev, "Failed to write DPCD: %d\n", ret); 1333 return ret; 1334 } 1335 1336 static int tc_main_link_disable(struct tc_data *tc) 1337 { 1338 int ret; 1339 1340 dev_dbg(tc->dev, "link disable\n"); 1341 1342 ret = regmap_write(tc->regmap, DP0_SRCCTRL, 0); 1343 if (ret) 1344 return ret; 1345 1346 ret = regmap_write(tc->regmap, DP0CTL, 0); 1347 if (ret) 1348 return ret; 1349 1350 return regmap_update_bits(tc->regmap, DP_PHY_CTRL, 1351 PHY_M0_RST | PHY_M1_RST | PHY_M0_EN, 1352 PHY_M0_RST | PHY_M1_RST); 1353 } 1354 1355 static int tc_dsi_rx_enable(struct tc_data *tc) 1356 { 1357 u32 value; 1358 int ret; 1359 1360 regmap_write(tc->regmap, PPI_D0S_CLRSIPOCOUNT, 25); 1361 regmap_write(tc->regmap, PPI_D1S_CLRSIPOCOUNT, 25); 1362 regmap_write(tc->regmap, PPI_D2S_CLRSIPOCOUNT, 25); 1363 regmap_write(tc->regmap, PPI_D3S_CLRSIPOCOUNT, 25); 1364 regmap_write(tc->regmap, PPI_D0S_ATMR, 0); 1365 regmap_write(tc->regmap, PPI_D1S_ATMR, 0); 1366 regmap_write(tc->regmap, PPI_TX_RX_TA, TTA_GET | TTA_SURE); 1367 regmap_write(tc->regmap, PPI_LPTXTIMECNT, LPX_PERIOD); 1368 1369 value = ((LANEENABLE_L0EN << tc->dsi->lanes) - LANEENABLE_L0EN) | 1370 LANEENABLE_CLEN; 1371 regmap_write(tc->regmap, PPI_LANEENABLE, value); 1372 regmap_write(tc->regmap, DSI_LANEENABLE, value); 1373 1374 /* Set input interface */ 1375 value = DP0_AUDSRC_NO_INPUT; 1376 if (tc_test_pattern) 1377 value |= DP0_VIDSRC_COLOR_BAR; 1378 else 1379 value |= DP0_VIDSRC_DSI_RX; 1380 ret = regmap_write(tc->regmap, SYSCTRL, value); 1381 if (ret) 1382 return ret; 1383 1384 usleep_range(120, 150); 1385 1386 regmap_write(tc->regmap, PPI_STARTPPI, PPI_START_FUNCTION); 1387 regmap_write(tc->regmap, DSI_STARTDSI, DSI_RX_START); 1388 1389 return 0; 1390 } 1391 1392 static int tc_dpi_rx_enable(struct tc_data *tc) 1393 { 1394 u32 value; 1395 1396 /* Set input interface */ 1397 value = DP0_AUDSRC_NO_INPUT; 1398 if (tc_test_pattern) 1399 value |= DP0_VIDSRC_COLOR_BAR; 1400 else 1401 value |= DP0_VIDSRC_DPI_RX; 1402 return regmap_write(tc->regmap, SYSCTRL, value); 1403 } 1404 1405 static int tc_dpi_stream_enable(struct tc_data *tc) 1406 { 1407 int ret; 1408 1409 dev_dbg(tc->dev, "enable video stream\n"); 1410 1411 /* Setup PLL */ 1412 ret = tc_set_syspllparam(tc); 1413 if (ret) 1414 return ret; 1415 1416 /* 1417 * Initially PLLs are in bypass. Force PLL parameter update, 1418 * disable PLL bypass, enable PLL 1419 */ 1420 ret = tc_pllupdate(tc, DP0_PLLCTRL); 1421 if (ret) 1422 return ret; 1423 1424 ret = tc_pllupdate(tc, DP1_PLLCTRL); 1425 if (ret) 1426 return ret; 1427 1428 /* Pixel PLL must always be enabled for DPI mode */ 1429 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), 1430 1000 * tc->mode.clock); 1431 if (ret) 1432 return ret; 1433 1434 ret = tc_set_common_video_mode(tc, &tc->mode); 1435 if (ret) 1436 return ret; 1437 1438 ret = tc_set_dpi_video_mode(tc, &tc->mode); 1439 if (ret) 1440 return ret; 1441 1442 return tc_dsi_rx_enable(tc); 1443 } 1444 1445 static int tc_dpi_stream_disable(struct tc_data *tc) 1446 { 1447 dev_dbg(tc->dev, "disable video stream\n"); 1448 1449 tc_pxl_pll_dis(tc); 1450 1451 return 0; 1452 } 1453 1454 static int tc_edp_stream_enable(struct tc_data *tc) 1455 { 1456 int ret; 1457 u32 value; 1458 1459 dev_dbg(tc->dev, "enable video stream\n"); 1460 1461 /* 1462 * Pixel PLL must be enabled for DSI input mode and test pattern. 1463 * 1464 * Per TC9595XBG datasheet Revision 0.1 2018-12-27 Figure 4.18 1465 * "Clock Mode Selection and Clock Sources", either Pixel PLL 1466 * or DPI_PCLK supplies StrmClk. DPI_PCLK is only available in 1467 * case valid Pixel Clock are supplied to the chip DPI input. 1468 * In case built-in test pattern is desired OR DSI input mode 1469 * is used, DPI_PCLK is not available and thus Pixel PLL must 1470 * be used instead. 1471 */ 1472 if (tc->input_connector_dsi || tc_test_pattern) { 1473 ret = tc_pxl_pll_en(tc, clk_get_rate(tc->refclk), 1474 1000 * tc->mode.clock); 1475 if (ret) 1476 return ret; 1477 } 1478 1479 ret = tc_set_common_video_mode(tc, &tc->mode); 1480 if (ret) 1481 return ret; 1482 1483 ret = tc_set_edp_video_mode(tc, &tc->mode); 1484 if (ret) 1485 return ret; 1486 1487 /* Set M/N */ 1488 ret = tc_stream_clock_calc(tc); 1489 if (ret) 1490 return ret; 1491 1492 value = VID_MN_GEN | DP_EN; 1493 if (drm_dp_enhanced_frame_cap(tc->link.dpcd)) 1494 value |= EF_EN; 1495 ret = regmap_write(tc->regmap, DP0CTL, value); 1496 if (ret) 1497 return ret; 1498 /* 1499 * VID_EN assertion should be delayed by at least N * LSCLK 1500 * cycles from the time VID_MN_GEN is enabled in order to 1501 * generate stable values for VID_M. LSCLK is 270 MHz or 1502 * 162 MHz, VID_N is set to 32768 in tc_stream_clock_calc(), 1503 * so a delay of at least 203 us should suffice. 1504 */ 1505 usleep_range(500, 1000); 1506 value |= VID_EN; 1507 ret = regmap_write(tc->regmap, DP0CTL, value); 1508 if (ret) 1509 return ret; 1510 1511 /* Set input interface */ 1512 if (tc->input_connector_dsi) 1513 return tc_dsi_rx_enable(tc); 1514 else 1515 return tc_dpi_rx_enable(tc); 1516 } 1517 1518 static int tc_edp_stream_disable(struct tc_data *tc) 1519 { 1520 int ret; 1521 1522 dev_dbg(tc->dev, "disable video stream\n"); 1523 1524 ret = regmap_update_bits(tc->regmap, DP0CTL, VID_EN, 0); 1525 if (ret) 1526 return ret; 1527 1528 tc_pxl_pll_dis(tc); 1529 1530 return 0; 1531 } 1532 1533 static void 1534 tc_dpi_bridge_atomic_enable(struct drm_bridge *bridge, 1535 struct drm_bridge_state *old_bridge_state) 1536 1537 { 1538 struct tc_data *tc = bridge_to_tc(bridge); 1539 int ret; 1540 1541 ret = tc_dpi_stream_enable(tc); 1542 if (ret < 0) { 1543 dev_err(tc->dev, "main link stream start error: %d\n", ret); 1544 tc_main_link_disable(tc); 1545 return; 1546 } 1547 } 1548 1549 static void 1550 tc_dpi_bridge_atomic_disable(struct drm_bridge *bridge, 1551 struct drm_bridge_state *old_bridge_state) 1552 { 1553 struct tc_data *tc = bridge_to_tc(bridge); 1554 int ret; 1555 1556 ret = tc_dpi_stream_disable(tc); 1557 if (ret < 0) 1558 dev_err(tc->dev, "main link stream stop error: %d\n", ret); 1559 } 1560 1561 static void 1562 tc_edp_bridge_atomic_enable(struct drm_bridge *bridge, 1563 struct drm_bridge_state *old_bridge_state) 1564 { 1565 struct tc_data *tc = bridge_to_tc(bridge); 1566 int ret; 1567 1568 ret = tc_get_display_props(tc); 1569 if (ret < 0) { 1570 dev_err(tc->dev, "failed to read display props: %d\n", ret); 1571 return; 1572 } 1573 1574 ret = tc_main_link_enable(tc); 1575 if (ret < 0) { 1576 dev_err(tc->dev, "main link enable error: %d\n", ret); 1577 return; 1578 } 1579 1580 ret = tc_edp_stream_enable(tc); 1581 if (ret < 0) { 1582 dev_err(tc->dev, "main link stream start error: %d\n", ret); 1583 tc_main_link_disable(tc); 1584 return; 1585 } 1586 } 1587 1588 static void 1589 tc_edp_bridge_atomic_disable(struct drm_bridge *bridge, 1590 struct drm_bridge_state *old_bridge_state) 1591 { 1592 struct tc_data *tc = bridge_to_tc(bridge); 1593 int ret; 1594 1595 ret = tc_edp_stream_disable(tc); 1596 if (ret < 0) 1597 dev_err(tc->dev, "main link stream stop error: %d\n", ret); 1598 1599 ret = tc_main_link_disable(tc); 1600 if (ret < 0) 1601 dev_err(tc->dev, "main link disable error: %d\n", ret); 1602 } 1603 1604 static int tc_dpi_atomic_check(struct drm_bridge *bridge, 1605 struct drm_bridge_state *bridge_state, 1606 struct drm_crtc_state *crtc_state, 1607 struct drm_connector_state *conn_state) 1608 { 1609 /* DSI->DPI interface clock limitation: upto 100 MHz */ 1610 if (crtc_state->adjusted_mode.clock > 100000) 1611 return -EINVAL; 1612 1613 return 0; 1614 } 1615 1616 static int tc_edp_atomic_check(struct drm_bridge *bridge, 1617 struct drm_bridge_state *bridge_state, 1618 struct drm_crtc_state *crtc_state, 1619 struct drm_connector_state *conn_state) 1620 { 1621 /* DPI->(e)DP interface clock limitation: upto 154 MHz */ 1622 if (crtc_state->adjusted_mode.clock > 154000) 1623 return -EINVAL; 1624 1625 return 0; 1626 } 1627 1628 static enum drm_mode_status 1629 tc_dpi_mode_valid(struct drm_bridge *bridge, 1630 const struct drm_display_info *info, 1631 const struct drm_display_mode *mode) 1632 { 1633 /* DPI interface clock limitation: upto 100 MHz */ 1634 if (mode->clock > 100000) 1635 return MODE_CLOCK_HIGH; 1636 1637 return MODE_OK; 1638 } 1639 1640 static enum drm_mode_status 1641 tc_edp_mode_valid(struct drm_bridge *bridge, 1642 const struct drm_display_info *info, 1643 const struct drm_display_mode *mode) 1644 { 1645 struct tc_data *tc = bridge_to_tc(bridge); 1646 u32 req, avail; 1647 u32 bits_per_pixel = 24; 1648 1649 /* DPI->(e)DP interface clock limitation: up to 154 MHz */ 1650 if (mode->clock > 154000) 1651 return MODE_CLOCK_HIGH; 1652 1653 req = mode->clock * bits_per_pixel / 8; 1654 avail = tc->link.num_lanes * tc->link.rate; 1655 1656 if (req > avail) 1657 return MODE_BAD; 1658 1659 return MODE_OK; 1660 } 1661 1662 static void tc_bridge_mode_set(struct drm_bridge *bridge, 1663 const struct drm_display_mode *mode, 1664 const struct drm_display_mode *adj) 1665 { 1666 struct tc_data *tc = bridge_to_tc(bridge); 1667 1668 drm_mode_copy(&tc->mode, mode); 1669 } 1670 1671 static const struct drm_edid *tc_edid_read(struct drm_bridge *bridge, 1672 struct drm_connector *connector) 1673 { 1674 struct tc_data *tc = bridge_to_tc(bridge); 1675 1676 return drm_edid_read_ddc(connector, &tc->aux.ddc); 1677 } 1678 1679 static int tc_connector_get_modes(struct drm_connector *connector) 1680 { 1681 struct tc_data *tc = connector_to_tc(connector); 1682 int num_modes; 1683 const struct drm_edid *drm_edid; 1684 int ret; 1685 1686 ret = tc_get_display_props(tc); 1687 if (ret < 0) { 1688 dev_err(tc->dev, "failed to read display props: %d\n", ret); 1689 return 0; 1690 } 1691 1692 if (tc->panel_bridge) { 1693 num_modes = drm_bridge_get_modes(tc->panel_bridge, connector); 1694 if (num_modes > 0) 1695 return num_modes; 1696 } 1697 1698 drm_edid = tc_edid_read(&tc->bridge, connector); 1699 drm_edid_connector_update(connector, drm_edid); 1700 num_modes = drm_edid_connector_add_modes(connector); 1701 drm_edid_free(drm_edid); 1702 1703 return num_modes; 1704 } 1705 1706 static const struct drm_connector_helper_funcs tc_connector_helper_funcs = { 1707 .get_modes = tc_connector_get_modes, 1708 }; 1709 1710 static enum drm_connector_status tc_bridge_detect(struct drm_bridge *bridge) 1711 { 1712 struct tc_data *tc = bridge_to_tc(bridge); 1713 bool conn; 1714 u32 val; 1715 int ret; 1716 1717 ret = regmap_read(tc->regmap, GPIOI, &val); 1718 if (ret) 1719 return connector_status_unknown; 1720 1721 conn = val & BIT(tc->hpd_pin); 1722 1723 if (conn) 1724 return connector_status_connected; 1725 else 1726 return connector_status_disconnected; 1727 } 1728 1729 static enum drm_connector_status 1730 tc_connector_detect(struct drm_connector *connector, bool force) 1731 { 1732 struct tc_data *tc = connector_to_tc(connector); 1733 1734 if (tc->hpd_pin >= 0) 1735 return tc_bridge_detect(&tc->bridge); 1736 1737 if (tc->panel_bridge) 1738 return connector_status_connected; 1739 else 1740 return connector_status_unknown; 1741 } 1742 1743 static const struct drm_connector_funcs tc_connector_funcs = { 1744 .detect = tc_connector_detect, 1745 .fill_modes = drm_helper_probe_single_connector_modes, 1746 .destroy = drm_connector_cleanup, 1747 .reset = drm_atomic_helper_connector_reset, 1748 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1749 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1750 }; 1751 1752 static int tc_dpi_bridge_attach(struct drm_bridge *bridge, 1753 enum drm_bridge_attach_flags flags) 1754 { 1755 struct tc_data *tc = bridge_to_tc(bridge); 1756 1757 if (!tc->panel_bridge) 1758 return 0; 1759 1760 return drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge, 1761 &tc->bridge, flags); 1762 } 1763 1764 static int tc_edp_bridge_attach(struct drm_bridge *bridge, 1765 enum drm_bridge_attach_flags flags) 1766 { 1767 u32 bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1768 struct tc_data *tc = bridge_to_tc(bridge); 1769 struct drm_device *drm = bridge->dev; 1770 int ret; 1771 1772 if (tc->panel_bridge) { 1773 /* If a connector is required then this driver shall create it */ 1774 ret = drm_bridge_attach(tc->bridge.encoder, tc->panel_bridge, 1775 &tc->bridge, flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); 1776 if (ret) 1777 return ret; 1778 } 1779 1780 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 1781 return 0; 1782 1783 tc->aux.drm_dev = drm; 1784 ret = drm_dp_aux_register(&tc->aux); 1785 if (ret < 0) 1786 return ret; 1787 1788 /* Create DP/eDP connector */ 1789 drm_connector_helper_add(&tc->connector, &tc_connector_helper_funcs); 1790 ret = drm_connector_init(drm, &tc->connector, &tc_connector_funcs, tc->bridge.type); 1791 if (ret) 1792 goto aux_unregister; 1793 1794 /* Don't poll if don't have HPD connected */ 1795 if (tc->hpd_pin >= 0) { 1796 if (tc->have_irq) 1797 tc->connector.polled = DRM_CONNECTOR_POLL_HPD; 1798 else 1799 tc->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 1800 DRM_CONNECTOR_POLL_DISCONNECT; 1801 } 1802 1803 drm_display_info_set_bus_formats(&tc->connector.display_info, 1804 &bus_format, 1); 1805 tc->connector.display_info.bus_flags = 1806 DRM_BUS_FLAG_DE_HIGH | 1807 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE | 1808 DRM_BUS_FLAG_SYNC_DRIVE_NEGEDGE; 1809 drm_connector_attach_encoder(&tc->connector, tc->bridge.encoder); 1810 1811 return 0; 1812 aux_unregister: 1813 drm_dp_aux_unregister(&tc->aux); 1814 return ret; 1815 } 1816 1817 static void tc_edp_bridge_detach(struct drm_bridge *bridge) 1818 { 1819 drm_dp_aux_unregister(&bridge_to_tc(bridge)->aux); 1820 } 1821 1822 #define MAX_INPUT_SEL_FORMATS 1 1823 1824 static u32 * 1825 tc_dpi_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 1826 struct drm_bridge_state *bridge_state, 1827 struct drm_crtc_state *crtc_state, 1828 struct drm_connector_state *conn_state, 1829 u32 output_fmt, 1830 unsigned int *num_input_fmts) 1831 { 1832 u32 *input_fmts; 1833 1834 *num_input_fmts = 0; 1835 1836 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 1837 GFP_KERNEL); 1838 if (!input_fmts) 1839 return NULL; 1840 1841 /* This is the DSI-end bus format */ 1842 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 1843 *num_input_fmts = 1; 1844 1845 return input_fmts; 1846 } 1847 1848 static const struct drm_bridge_funcs tc_dpi_bridge_funcs = { 1849 .attach = tc_dpi_bridge_attach, 1850 .mode_valid = tc_dpi_mode_valid, 1851 .mode_set = tc_bridge_mode_set, 1852 .atomic_check = tc_dpi_atomic_check, 1853 .atomic_enable = tc_dpi_bridge_atomic_enable, 1854 .atomic_disable = tc_dpi_bridge_atomic_disable, 1855 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1856 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1857 .atomic_reset = drm_atomic_helper_bridge_reset, 1858 .atomic_get_input_bus_fmts = tc_dpi_atomic_get_input_bus_fmts, 1859 }; 1860 1861 static const struct drm_bridge_funcs tc_edp_bridge_funcs = { 1862 .attach = tc_edp_bridge_attach, 1863 .detach = tc_edp_bridge_detach, 1864 .mode_valid = tc_edp_mode_valid, 1865 .mode_set = tc_bridge_mode_set, 1866 .atomic_check = tc_edp_atomic_check, 1867 .atomic_enable = tc_edp_bridge_atomic_enable, 1868 .atomic_disable = tc_edp_bridge_atomic_disable, 1869 .detect = tc_bridge_detect, 1870 .edid_read = tc_edid_read, 1871 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1872 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1873 .atomic_reset = drm_atomic_helper_bridge_reset, 1874 }; 1875 1876 static bool tc_readable_reg(struct device *dev, unsigned int reg) 1877 { 1878 switch (reg) { 1879 /* DSI D-PHY Layer */ 1880 case 0x004: 1881 case 0x020: 1882 case 0x024: 1883 case 0x028: 1884 case 0x02c: 1885 case 0x030: 1886 case 0x038: 1887 case 0x040: 1888 case 0x044: 1889 case 0x048: 1890 case 0x04c: 1891 case 0x050: 1892 case 0x054: 1893 /* DSI PPI Layer */ 1894 case PPI_STARTPPI: 1895 case 0x108: 1896 case 0x110: 1897 case PPI_LPTXTIMECNT: 1898 case PPI_LANEENABLE: 1899 case PPI_TX_RX_TA: 1900 case 0x140: 1901 case PPI_D0S_ATMR: 1902 case PPI_D1S_ATMR: 1903 case 0x14c: 1904 case 0x150: 1905 case PPI_D0S_CLRSIPOCOUNT: 1906 case PPI_D1S_CLRSIPOCOUNT: 1907 case PPI_D2S_CLRSIPOCOUNT: 1908 case PPI_D3S_CLRSIPOCOUNT: 1909 case 0x180: 1910 case 0x184: 1911 case 0x188: 1912 case 0x18c: 1913 case 0x190: 1914 case 0x1a0: 1915 case 0x1a4: 1916 case 0x1a8: 1917 case 0x1ac: 1918 case 0x1b0: 1919 case 0x1c0: 1920 case 0x1c4: 1921 case 0x1c8: 1922 case 0x1cc: 1923 case 0x1d0: 1924 case 0x1e0: 1925 case 0x1e4: 1926 case 0x1f0: 1927 case 0x1f4: 1928 /* DSI Protocol Layer */ 1929 case DSI_STARTDSI: 1930 case DSI_BUSYDSI: 1931 case DSI_LANEENABLE: 1932 case DSI_LANESTATUS0: 1933 case DSI_LANESTATUS1: 1934 case DSI_INTSTATUS: 1935 case 0x224: 1936 case 0x228: 1937 case 0x230: 1938 /* DSI General */ 1939 case DSIERRCNT: 1940 /* DSI Application Layer */ 1941 case 0x400: 1942 case 0x404: 1943 /* DPI */ 1944 case DPIPXLFMT: 1945 /* Parallel Output */ 1946 case POCTRL: 1947 /* Video Path0 Configuration */ 1948 case VPCTRL0: 1949 case HTIM01: 1950 case HTIM02: 1951 case VTIM01: 1952 case VTIM02: 1953 case VFUEN0: 1954 /* System */ 1955 case TC_IDREG: 1956 case 0x504: 1957 case SYSSTAT: 1958 case SYSRSTENB: 1959 case SYSCTRL: 1960 /* I2C */ 1961 case 0x520: 1962 /* GPIO */ 1963 case GPIOM: 1964 case GPIOC: 1965 case GPIOO: 1966 case GPIOI: 1967 /* Interrupt */ 1968 case INTCTL_G: 1969 case INTSTS_G: 1970 case 0x570: 1971 case 0x574: 1972 case INT_GP0_LCNT: 1973 case INT_GP1_LCNT: 1974 /* DisplayPort Control */ 1975 case DP0CTL: 1976 /* DisplayPort Clock */ 1977 case DP0_VIDMNGEN0: 1978 case DP0_VIDMNGEN1: 1979 case DP0_VMNGENSTATUS: 1980 case 0x628: 1981 case 0x62c: 1982 case 0x630: 1983 /* DisplayPort Main Channel */ 1984 case DP0_SECSAMPLE: 1985 case DP0_VIDSYNCDELAY: 1986 case DP0_TOTALVAL: 1987 case DP0_STARTVAL: 1988 case DP0_ACTIVEVAL: 1989 case DP0_SYNCVAL: 1990 case DP0_MISC: 1991 /* DisplayPort Aux Channel */ 1992 case DP0_AUXCFG0: 1993 case DP0_AUXCFG1: 1994 case DP0_AUXADDR: 1995 case 0x66c: 1996 case 0x670: 1997 case 0x674: 1998 case 0x678: 1999 case 0x67c: 2000 case 0x680: 2001 case 0x684: 2002 case 0x688: 2003 case DP0_AUXSTATUS: 2004 case DP0_AUXI2CADR: 2005 /* DisplayPort Link Training */ 2006 case DP0_SRCCTRL: 2007 case DP0_LTSTAT: 2008 case DP0_SNKLTCHGREQ: 2009 case DP0_LTLOOPCTRL: 2010 case DP0_SNKLTCTRL: 2011 case 0x6e8: 2012 case 0x6ec: 2013 case 0x6f0: 2014 case 0x6f4: 2015 /* DisplayPort Audio */ 2016 case 0x700: 2017 case 0x704: 2018 case 0x708: 2019 case 0x70c: 2020 case 0x710: 2021 case 0x714: 2022 case 0x718: 2023 case 0x71c: 2024 case 0x720: 2025 /* DisplayPort Source Control */ 2026 case DP1_SRCCTRL: 2027 /* DisplayPort PHY */ 2028 case DP_PHY_CTRL: 2029 case 0x810: 2030 case 0x814: 2031 case 0x820: 2032 case 0x840: 2033 /* I2S */ 2034 case 0x880: 2035 case 0x888: 2036 case 0x88c: 2037 case 0x890: 2038 case 0x894: 2039 case 0x898: 2040 case 0x89c: 2041 case 0x8a0: 2042 case 0x8a4: 2043 case 0x8a8: 2044 case 0x8ac: 2045 case 0x8b0: 2046 case 0x8b4: 2047 /* PLL */ 2048 case DP0_PLLCTRL: 2049 case DP1_PLLCTRL: 2050 case PXL_PLLCTRL: 2051 case PXL_PLLPARAM: 2052 case SYS_PLLPARAM: 2053 /* HDCP */ 2054 case 0x980: 2055 case 0x984: 2056 case 0x988: 2057 case 0x98c: 2058 case 0x990: 2059 case 0x994: 2060 case 0x998: 2061 case 0x99c: 2062 case 0x9a0: 2063 case 0x9a4: 2064 case 0x9a8: 2065 case 0x9ac: 2066 /* Debug */ 2067 case TSTCTL: 2068 case PLL_DBG: 2069 return true; 2070 } 2071 return false; 2072 } 2073 2074 static const struct regmap_range tc_volatile_ranges[] = { 2075 regmap_reg_range(PPI_BUSYPPI, PPI_BUSYPPI), 2076 regmap_reg_range(DSI_BUSYDSI, DSI_BUSYDSI), 2077 regmap_reg_range(DSI_LANESTATUS0, DSI_INTSTATUS), 2078 regmap_reg_range(DSIERRCNT, DSIERRCNT), 2079 regmap_reg_range(VFUEN0, VFUEN0), 2080 regmap_reg_range(SYSSTAT, SYSSTAT), 2081 regmap_reg_range(GPIOI, GPIOI), 2082 regmap_reg_range(INTSTS_G, INTSTS_G), 2083 regmap_reg_range(DP0_VMNGENSTATUS, DP0_VMNGENSTATUS), 2084 regmap_reg_range(DP0_AMNGENSTATUS, DP0_AMNGENSTATUS), 2085 regmap_reg_range(DP0_AUXWDATA(0), DP0_AUXSTATUS), 2086 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ), 2087 regmap_reg_range(DP_PHY_CTRL, DP_PHY_CTRL), 2088 regmap_reg_range(DP0_PLLCTRL, PXL_PLLCTRL), 2089 }; 2090 2091 static const struct regmap_access_table tc_volatile_table = { 2092 .yes_ranges = tc_volatile_ranges, 2093 .n_yes_ranges = ARRAY_SIZE(tc_volatile_ranges), 2094 }; 2095 2096 static const struct regmap_range tc_precious_ranges[] = { 2097 regmap_reg_range(SYSSTAT, SYSSTAT), 2098 }; 2099 2100 static const struct regmap_access_table tc_precious_table = { 2101 .yes_ranges = tc_precious_ranges, 2102 .n_yes_ranges = ARRAY_SIZE(tc_precious_ranges), 2103 }; 2104 2105 static const struct regmap_range tc_non_writeable_ranges[] = { 2106 regmap_reg_range(PPI_BUSYPPI, PPI_BUSYPPI), 2107 regmap_reg_range(DSI_BUSYDSI, DSI_BUSYDSI), 2108 regmap_reg_range(DSI_LANESTATUS0, DSI_INTSTATUS), 2109 regmap_reg_range(TC_IDREG, SYSSTAT), 2110 regmap_reg_range(GPIOI, GPIOI), 2111 regmap_reg_range(DP0_LTSTAT, DP0_SNKLTCHGREQ), 2112 }; 2113 2114 static const struct regmap_access_table tc_writeable_table = { 2115 .no_ranges = tc_non_writeable_ranges, 2116 .n_no_ranges = ARRAY_SIZE(tc_non_writeable_ranges), 2117 }; 2118 2119 static const struct regmap_config tc_regmap_config = { 2120 .name = "tc358767", 2121 .reg_bits = 16, 2122 .val_bits = 32, 2123 .reg_stride = 4, 2124 .max_register = PLL_DBG, 2125 .cache_type = REGCACHE_MAPLE, 2126 .readable_reg = tc_readable_reg, 2127 .volatile_table = &tc_volatile_table, 2128 .precious_table = &tc_precious_table, 2129 .wr_table = &tc_writeable_table, 2130 .reg_format_endian = REGMAP_ENDIAN_BIG, 2131 .val_format_endian = REGMAP_ENDIAN_LITTLE, 2132 }; 2133 2134 static irqreturn_t tc_irq_handler(int irq, void *arg) 2135 { 2136 struct tc_data *tc = arg; 2137 u32 val; 2138 int r; 2139 2140 r = regmap_read(tc->regmap, INTSTS_G, &val); 2141 if (r) 2142 return IRQ_NONE; 2143 2144 if (!val) 2145 return IRQ_NONE; 2146 2147 if (val & INT_SYSERR) { 2148 u32 stat = 0; 2149 2150 regmap_read(tc->regmap, SYSSTAT, &stat); 2151 2152 dev_err(tc->dev, "syserr %x\n", stat); 2153 } 2154 2155 if (tc->hpd_pin >= 0 && tc->bridge.dev && tc->aux.drm_dev) { 2156 /* 2157 * H is triggered when the GPIO goes high. 2158 * 2159 * LC is triggered when the GPIO goes low and stays low for 2160 * the duration of LCNT 2161 */ 2162 bool h = val & INT_GPIO_H(tc->hpd_pin); 2163 bool lc = val & INT_GPIO_LC(tc->hpd_pin); 2164 2165 dev_dbg(tc->dev, "GPIO%d: %s %s\n", tc->hpd_pin, 2166 h ? "H" : "", lc ? "LC" : ""); 2167 2168 if (h || lc) 2169 drm_kms_helper_hotplug_event(tc->bridge.dev); 2170 } 2171 2172 regmap_write(tc->regmap, INTSTS_G, val); 2173 2174 return IRQ_HANDLED; 2175 } 2176 2177 static int tc_mipi_dsi_host_attach(struct tc_data *tc) 2178 { 2179 struct device *dev = tc->dev; 2180 struct device_node *host_node; 2181 struct device_node *endpoint; 2182 struct mipi_dsi_device *dsi; 2183 struct mipi_dsi_host *host; 2184 const struct mipi_dsi_device_info info = { 2185 .type = "tc358767", 2186 .channel = 0, 2187 .node = NULL, 2188 }; 2189 int dsi_lanes, ret; 2190 2191 endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1); 2192 dsi_lanes = drm_of_get_data_lanes_count(endpoint, 1, 4); 2193 host_node = of_graph_get_remote_port_parent(endpoint); 2194 host = of_find_mipi_dsi_host_by_node(host_node); 2195 of_node_put(host_node); 2196 of_node_put(endpoint); 2197 2198 if (!host) 2199 return -EPROBE_DEFER; 2200 2201 if (dsi_lanes < 0) 2202 return dsi_lanes; 2203 2204 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 2205 if (IS_ERR(dsi)) 2206 return dev_err_probe(dev, PTR_ERR(dsi), 2207 "failed to create dsi device\n"); 2208 2209 tc->dsi = dsi; 2210 dsi->lanes = dsi_lanes; 2211 dsi->format = MIPI_DSI_FMT_RGB888; 2212 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 2213 MIPI_DSI_MODE_LPM | MIPI_DSI_CLOCK_NON_CONTINUOUS; 2214 2215 ret = devm_mipi_dsi_attach(dev, dsi); 2216 if (ret < 0) { 2217 dev_err(dev, "failed to attach dsi to host: %d\n", ret); 2218 return ret; 2219 } 2220 2221 return 0; 2222 } 2223 2224 static int tc_probe_dpi_bridge_endpoint(struct tc_data *tc) 2225 { 2226 struct device *dev = tc->dev; 2227 struct drm_bridge *bridge; 2228 struct drm_panel *panel; 2229 int ret; 2230 2231 /* port@1 is the DPI input/output port */ 2232 ret = drm_of_find_panel_or_bridge(dev->of_node, 1, 0, &panel, &bridge); 2233 if (ret && ret != -ENODEV) 2234 return ret; 2235 2236 if (panel) { 2237 bridge = devm_drm_panel_bridge_add(dev, panel); 2238 if (IS_ERR(bridge)) 2239 return PTR_ERR(bridge); 2240 } 2241 2242 if (bridge) { 2243 tc->panel_bridge = bridge; 2244 tc->bridge.type = DRM_MODE_CONNECTOR_DPI; 2245 tc->bridge.funcs = &tc_dpi_bridge_funcs; 2246 2247 return 0; 2248 } 2249 2250 return ret; 2251 } 2252 2253 static int tc_probe_edp_bridge_endpoint(struct tc_data *tc) 2254 { 2255 struct device *dev = tc->dev; 2256 struct drm_panel *panel; 2257 int ret; 2258 2259 /* port@2 is the output port */ 2260 ret = drm_of_find_panel_or_bridge(dev->of_node, 2, 0, &panel, NULL); 2261 if (ret && ret != -ENODEV) 2262 return ret; 2263 2264 if (panel) { 2265 struct drm_bridge *panel_bridge; 2266 2267 panel_bridge = devm_drm_panel_bridge_add(dev, panel); 2268 if (IS_ERR(panel_bridge)) 2269 return PTR_ERR(panel_bridge); 2270 2271 tc->panel_bridge = panel_bridge; 2272 tc->bridge.type = DRM_MODE_CONNECTOR_eDP; 2273 } else { 2274 tc->bridge.type = DRM_MODE_CONNECTOR_DisplayPort; 2275 } 2276 2277 tc->bridge.funcs = &tc_edp_bridge_funcs; 2278 if (tc->hpd_pin >= 0) 2279 tc->bridge.ops |= DRM_BRIDGE_OP_DETECT; 2280 tc->bridge.ops |= DRM_BRIDGE_OP_EDID; 2281 2282 return 0; 2283 } 2284 2285 static int tc_probe_bridge_endpoint(struct tc_data *tc) 2286 { 2287 struct device *dev = tc->dev; 2288 struct of_endpoint endpoint; 2289 struct device_node *node = NULL; 2290 const u8 mode_dpi_to_edp = BIT(1) | BIT(2); 2291 const u8 mode_dpi_to_dp = BIT(1); 2292 const u8 mode_dsi_to_edp = BIT(0) | BIT(2); 2293 const u8 mode_dsi_to_dp = BIT(0); 2294 const u8 mode_dsi_to_dpi = BIT(0) | BIT(1); 2295 u8 mode = 0; 2296 2297 /* 2298 * Determine bridge configuration. 2299 * 2300 * Port allocation: 2301 * port@0 - DSI input 2302 * port@1 - DPI input/output 2303 * port@2 - eDP output 2304 * 2305 * Possible connections: 2306 * DPI -> port@1 -> port@2 -> eDP :: [port@0 is not connected] 2307 * DSI -> port@0 -> port@2 -> eDP :: [port@1 is not connected] 2308 * DSI -> port@0 -> port@1 -> DPI :: [port@2 is not connected] 2309 */ 2310 2311 for_each_endpoint_of_node(dev->of_node, node) { 2312 of_graph_parse_endpoint(node, &endpoint); 2313 if (endpoint.port > 2) { 2314 of_node_put(node); 2315 return -EINVAL; 2316 } 2317 mode |= BIT(endpoint.port); 2318 } 2319 2320 if (mode == mode_dpi_to_edp || mode == mode_dpi_to_dp) { 2321 tc->input_connector_dsi = false; 2322 return tc_probe_edp_bridge_endpoint(tc); 2323 } else if (mode == mode_dsi_to_dpi) { 2324 tc->input_connector_dsi = true; 2325 return tc_probe_dpi_bridge_endpoint(tc); 2326 } else if (mode == mode_dsi_to_edp || mode == mode_dsi_to_dp) { 2327 tc->input_connector_dsi = true; 2328 return tc_probe_edp_bridge_endpoint(tc); 2329 } 2330 2331 dev_warn(dev, "Invalid mode (0x%x) is not supported!\n", mode); 2332 2333 return -EINVAL; 2334 } 2335 2336 static int tc_probe(struct i2c_client *client) 2337 { 2338 struct device *dev = &client->dev; 2339 struct tc_data *tc; 2340 int ret; 2341 2342 tc = devm_kzalloc(dev, sizeof(*tc), GFP_KERNEL); 2343 if (!tc) 2344 return -ENOMEM; 2345 2346 tc->dev = dev; 2347 2348 ret = tc_probe_bridge_endpoint(tc); 2349 if (ret) 2350 return ret; 2351 2352 tc->refclk = devm_clk_get_enabled(dev, "ref"); 2353 if (IS_ERR(tc->refclk)) 2354 return dev_err_probe(dev, PTR_ERR(tc->refclk), 2355 "Failed to get and enable the ref clk\n"); 2356 2357 /* tRSTW = 100 cycles , at 13 MHz that is ~7.69 us */ 2358 usleep_range(10, 15); 2359 2360 /* Shut down GPIO is optional */ 2361 tc->sd_gpio = devm_gpiod_get_optional(dev, "shutdown", GPIOD_OUT_HIGH); 2362 if (IS_ERR(tc->sd_gpio)) 2363 return PTR_ERR(tc->sd_gpio); 2364 2365 if (tc->sd_gpio) { 2366 gpiod_set_value_cansleep(tc->sd_gpio, 0); 2367 usleep_range(5000, 10000); 2368 } 2369 2370 /* Reset GPIO is optional */ 2371 tc->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 2372 if (IS_ERR(tc->reset_gpio)) 2373 return PTR_ERR(tc->reset_gpio); 2374 2375 if (tc->reset_gpio) { 2376 gpiod_set_value_cansleep(tc->reset_gpio, 1); 2377 usleep_range(5000, 10000); 2378 } 2379 2380 tc->regmap = devm_regmap_init_i2c(client, &tc_regmap_config); 2381 if (IS_ERR(tc->regmap)) { 2382 ret = PTR_ERR(tc->regmap); 2383 dev_err(dev, "Failed to initialize regmap: %d\n", ret); 2384 return ret; 2385 } 2386 2387 ret = of_property_read_u32(dev->of_node, "toshiba,hpd-pin", 2388 &tc->hpd_pin); 2389 if (ret) { 2390 tc->hpd_pin = -ENODEV; 2391 } else { 2392 if (tc->hpd_pin < 0 || tc->hpd_pin > 1) { 2393 dev_err(dev, "failed to parse HPD number\n"); 2394 return -EINVAL; 2395 } 2396 } 2397 2398 if (client->irq > 0) { 2399 /* enable SysErr */ 2400 regmap_write(tc->regmap, INTCTL_G, INT_SYSERR); 2401 2402 ret = devm_request_threaded_irq(dev, client->irq, 2403 NULL, tc_irq_handler, 2404 IRQF_ONESHOT, 2405 "tc358767-irq", tc); 2406 if (ret) { 2407 dev_err(dev, "failed to register dp interrupt\n"); 2408 return ret; 2409 } 2410 2411 tc->have_irq = true; 2412 } 2413 2414 ret = regmap_read(tc->regmap, TC_IDREG, &tc->rev); 2415 if (ret) { 2416 dev_err(tc->dev, "can not read device ID: %d\n", ret); 2417 return ret; 2418 } 2419 2420 if ((tc->rev != 0x6601) && (tc->rev != 0x6603)) { 2421 dev_err(tc->dev, "invalid device ID: 0x%08x\n", tc->rev); 2422 return -EINVAL; 2423 } 2424 2425 tc->assr = (tc->rev == 0x6601); /* Enable ASSR for eDP panels */ 2426 2427 if (!tc->reset_gpio) { 2428 /* 2429 * If the reset pin isn't present, do a software reset. It isn't 2430 * as thorough as the hardware reset, as we can't reset the I2C 2431 * communication block for obvious reasons, but it's getting the 2432 * chip into a defined state. 2433 */ 2434 regmap_update_bits(tc->regmap, SYSRSTENB, 2435 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP, 2436 0); 2437 regmap_update_bits(tc->regmap, SYSRSTENB, 2438 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP, 2439 ENBLCD0 | ENBBM | ENBDSIRX | ENBREG | ENBHDCP); 2440 usleep_range(5000, 10000); 2441 } 2442 2443 if (tc->hpd_pin >= 0) { 2444 u32 lcnt_reg = tc->hpd_pin == 0 ? INT_GP0_LCNT : INT_GP1_LCNT; 2445 u32 h_lc = INT_GPIO_H(tc->hpd_pin) | INT_GPIO_LC(tc->hpd_pin); 2446 2447 /* Set LCNT to 2ms */ 2448 regmap_write(tc->regmap, lcnt_reg, 2449 clk_get_rate(tc->refclk) * 2 / 1000); 2450 /* We need the "alternate" mode for HPD */ 2451 regmap_write(tc->regmap, GPIOM, BIT(tc->hpd_pin)); 2452 2453 if (tc->have_irq) { 2454 /* enable H & LC */ 2455 regmap_update_bits(tc->regmap, INTCTL_G, h_lc, h_lc); 2456 } 2457 } 2458 2459 if (tc->bridge.type != DRM_MODE_CONNECTOR_DPI) { /* (e)DP output */ 2460 ret = tc_aux_link_setup(tc); 2461 if (ret) 2462 return ret; 2463 } 2464 2465 tc->bridge.of_node = dev->of_node; 2466 drm_bridge_add(&tc->bridge); 2467 2468 i2c_set_clientdata(client, tc); 2469 2470 if (tc->input_connector_dsi) { /* DSI input */ 2471 ret = tc_mipi_dsi_host_attach(tc); 2472 if (ret) { 2473 drm_bridge_remove(&tc->bridge); 2474 return ret; 2475 } 2476 } 2477 2478 return 0; 2479 } 2480 2481 static void tc_remove(struct i2c_client *client) 2482 { 2483 struct tc_data *tc = i2c_get_clientdata(client); 2484 2485 drm_bridge_remove(&tc->bridge); 2486 } 2487 2488 static const struct i2c_device_id tc358767_i2c_ids[] = { 2489 { "tc358767", 0 }, 2490 { } 2491 }; 2492 MODULE_DEVICE_TABLE(i2c, tc358767_i2c_ids); 2493 2494 static const struct of_device_id tc358767_of_ids[] = { 2495 { .compatible = "toshiba,tc358767", }, 2496 { } 2497 }; 2498 MODULE_DEVICE_TABLE(of, tc358767_of_ids); 2499 2500 static struct i2c_driver tc358767_driver = { 2501 .driver = { 2502 .name = "tc358767", 2503 .of_match_table = tc358767_of_ids, 2504 }, 2505 .id_table = tc358767_i2c_ids, 2506 .probe = tc_probe, 2507 .remove = tc_remove, 2508 }; 2509 module_i2c_driver(tc358767_driver); 2510 2511 MODULE_AUTHOR("Andrey Gusakov <andrey.gusakov@cogentembedded.com>"); 2512 MODULE_DESCRIPTION("tc358767 eDP encoder driver"); 2513 MODULE_LICENSE("GPL"); 2514