1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2024, Fuzhou Rockchip Electronics Co., Ltd 4 * 5 * Modified by Heiko Stuebner <heiko.stuebner@cherry.de> 6 * This generic Synopsys DesignWare MIPI DSI2 host driver is based on the 7 * Rockchip version from rockchip/dw-mipi-dsi2.c converted to use bridge APIs. 8 */ 9 10 #include <linux/bitfield.h> 11 #include <linux/clk.h> 12 #include <linux/iopoll.h> 13 #include <linux/media-bus-format.h> 14 #include <linux/module.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 19 #include <video/mipi_display.h> 20 21 #include <drm/bridge/dw_mipi_dsi2.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_bridge.h> 24 #include <drm/drm_mipi_dsi.h> 25 #include <drm/drm_of.h> 26 #include <drm/drm_print.h> 27 28 #define DSI2_PWR_UP 0x000c 29 #define RESET 0 30 #define POWER_UP BIT(0) 31 #define CMD_TX_MODE(x) FIELD_PREP(BIT(24), x) 32 #define DSI2_SOFT_RESET 0x0010 33 #define SYS_RSTN BIT(2) 34 #define PHY_RSTN BIT(1) 35 #define IPI_RSTN BIT(0) 36 #define INT_ST_MAIN 0x0014 37 #define DSI2_MODE_CTRL 0x0018 38 #define DSI2_MODE_STATUS 0x001c 39 #define DSI2_CORE_STATUS 0x0020 40 #define PRI_RD_DATA_AVAIL BIT(26) 41 #define PRI_FIFOS_NOT_EMPTY BIT(25) 42 #define PRI_BUSY BIT(24) 43 #define CRI_RD_DATA_AVAIL BIT(18) 44 #define CRT_FIFOS_NOT_EMPTY BIT(17) 45 #define CRI_BUSY BIT(16) 46 #define IPI_FIFOS_NOT_EMPTY BIT(9) 47 #define IPI_BUSY BIT(8) 48 #define CORE_FIFOS_NOT_EMPTY BIT(1) 49 #define CORE_BUSY BIT(0) 50 #define MANUAL_MODE_CFG 0x0024 51 #define MANUAL_MODE_EN BIT(0) 52 #define DSI2_TIMEOUT_HSTX_CFG 0x0048 53 #define TO_HSTX(x) FIELD_PREP(GENMASK(15, 0), x) 54 #define DSI2_TIMEOUT_HSTXRDY_CFG 0x004c 55 #define TO_HSTXRDY(x) FIELD_PREP(GENMASK(15, 0), x) 56 #define DSI2_TIMEOUT_LPRX_CFG 0x0050 57 #define TO_LPRXRDY(x) FIELD_PREP(GENMASK(15, 0), x) 58 #define DSI2_TIMEOUT_LPTXRDY_CFG 0x0054 59 #define TO_LPTXRDY(x) FIELD_PREP(GENMASK(15, 0), x) 60 #define DSI2_TIMEOUT_LPTXTRIG_CFG 0x0058 61 #define TO_LPTXTRIG(x) FIELD_PREP(GENMASK(15, 0), x) 62 #define DSI2_TIMEOUT_LPTXULPS_CFG 0x005c 63 #define TO_LPTXULPS(x) FIELD_PREP(GENMASK(15, 0), x) 64 #define DSI2_TIMEOUT_BTA_CFG 0x60 65 #define TO_BTA(x) FIELD_PREP(GENMASK(15, 0), x) 66 67 #define DSI2_PHY_MODE_CFG 0x0100 68 #define PPI_WIDTH(x) FIELD_PREP(GENMASK(9, 8), x) 69 #define PHY_LANES(x) FIELD_PREP(GENMASK(5, 4), (x) - 1) 70 #define PHY_TYPE(x) FIELD_PREP(BIT(0), x) 71 #define DSI2_PHY_CLK_CFG 0X0104 72 #define PHY_LPTX_CLK_DIV(x) FIELD_PREP(GENMASK(12, 8), x) 73 #define CLK_TYPE_MASK BIT(0) 74 #define NON_CONTINUOUS_CLK BIT(0) 75 #define CONTINUOUS_CLK 0 76 #define DSI2_PHY_LP2HS_MAN_CFG 0x010c 77 #define PHY_LP2HS_TIME(x) FIELD_PREP(GENMASK(28, 0), x) 78 #define DSI2_PHY_HS2LP_MAN_CFG 0x0114 79 #define PHY_HS2LP_TIME(x) FIELD_PREP(GENMASK(28, 0), x) 80 #define DSI2_PHY_MAX_RD_T_MAN_CFG 0x011c 81 #define PHY_MAX_RD_TIME(x) FIELD_PREP(GENMASK(26, 0), x) 82 #define DSI2_PHY_ESC_CMD_T_MAN_CFG 0x0124 83 #define PHY_ESC_CMD_TIME(x) FIELD_PREP(GENMASK(28, 0), x) 84 #define DSI2_PHY_ESC_BYTE_T_MAN_CFG 0x012c 85 #define PHY_ESC_BYTE_TIME(x) FIELD_PREP(GENMASK(28, 0), x) 86 87 #define DSI2_PHY_IPI_RATIO_MAN_CFG 0x0134 88 #define PHY_IPI_RATIO(x) FIELD_PREP(GENMASK(21, 0), x) 89 #define DSI2_PHY_SYS_RATIO_MAN_CFG 0x013C 90 #define PHY_SYS_RATIO(x) FIELD_PREP(GENMASK(16, 0), x) 91 92 #define DSI2_DSI_GENERAL_CFG 0x0200 93 #define BTA_EN BIT(1) 94 #define EOTP_TX_EN BIT(0) 95 #define DSI2_DSI_VCID_CFG 0x0204 96 #define TX_VCID(x) FIELD_PREP(GENMASK(1, 0), x) 97 #define DSI2_DSI_SCRAMBLING_CFG 0x0208 98 #define SCRAMBLING_SEED(x) FIELD_PREP(GENMASK(31, 16), x) 99 #define SCRAMBLING_EN BIT(0) 100 #define DSI2_DSI_VID_TX_CFG 0x020c 101 #define LPDT_DISPLAY_CMD_EN BIT(20) 102 #define BLK_VFP_HS_EN BIT(14) 103 #define BLK_VBP_HS_EN BIT(13) 104 #define BLK_VSA_HS_EN BIT(12) 105 #define BLK_HFP_HS_EN BIT(6) 106 #define BLK_HBP_HS_EN BIT(5) 107 #define BLK_HSA_HS_EN BIT(4) 108 #define VID_MODE_TYPE(x) FIELD_PREP(GENMASK(1, 0), x) 109 #define DSI2_CRI_TX_HDR 0x02c0 110 #define CMD_TX_MODE(x) FIELD_PREP(BIT(24), x) 111 #define DSI2_CRI_TX_PLD 0x02c4 112 #define DSI2_CRI_RX_HDR 0x02c8 113 #define DSI2_CRI_RX_PLD 0x02cc 114 115 #define DSI2_IPI_COLOR_MAN_CFG 0x0300 116 #define IPI_DEPTH(x) FIELD_PREP(GENMASK(7, 4), x) 117 #define IPI_DEPTH_5_6_5_BITS 0x02 118 #define IPI_DEPTH_6_BITS 0x03 119 #define IPI_DEPTH_8_BITS 0x05 120 #define IPI_DEPTH_10_BITS 0x06 121 #define IPI_FORMAT(x) FIELD_PREP(GENMASK(3, 0), x) 122 #define IPI_FORMAT_RGB 0x0 123 #define IPI_FORMAT_DSC 0x0b 124 #define DSI2_IPI_VID_HSA_MAN_CFG 0x0304 125 #define VID_HSA_TIME(x) FIELD_PREP(GENMASK(29, 0), x) 126 #define DSI2_IPI_VID_HBP_MAN_CFG 0x030c 127 #define VID_HBP_TIME(x) FIELD_PREP(GENMASK(29, 0), x) 128 #define DSI2_IPI_VID_HACT_MAN_CFG 0x0314 129 #define VID_HACT_TIME(x) FIELD_PREP(GENMASK(29, 0), x) 130 #define DSI2_IPI_VID_HLINE_MAN_CFG 0x031c 131 #define VID_HLINE_TIME(x) FIELD_PREP(GENMASK(29, 0), x) 132 #define DSI2_IPI_VID_VSA_MAN_CFG 0x0324 133 #define VID_VSA_LINES(x) FIELD_PREP(GENMASK(9, 0), x) 134 #define DSI2_IPI_VID_VBP_MAN_CFG 0X032C 135 #define VID_VBP_LINES(x) FIELD_PREP(GENMASK(9, 0), x) 136 #define DSI2_IPI_VID_VACT_MAN_CFG 0X0334 137 #define VID_VACT_LINES(x) FIELD_PREP(GENMASK(13, 0), x) 138 #define DSI2_IPI_VID_VFP_MAN_CFG 0X033C 139 #define VID_VFP_LINES(x) FIELD_PREP(GENMASK(9, 0), x) 140 #define DSI2_IPI_PIX_PKT_CFG 0x0344 141 #define MAX_PIX_PKT(x) FIELD_PREP(GENMASK(15, 0), x) 142 143 #define DSI2_INT_ST_PHY 0x0400 144 #define DSI2_INT_MASK_PHY 0x0404 145 #define DSI2_INT_ST_TO 0x0410 146 #define DSI2_INT_MASK_TO 0x0414 147 #define DSI2_INT_ST_ACK 0x0420 148 #define DSI2_INT_MASK_ACK 0x0424 149 #define DSI2_INT_ST_IPI 0x0430 150 #define DSI2_INT_MASK_IPI 0x0434 151 #define DSI2_INT_ST_FIFO 0x0440 152 #define DSI2_INT_MASK_FIFO 0x0444 153 #define DSI2_INT_ST_PRI 0x0450 154 #define DSI2_INT_MASK_PRI 0x0454 155 #define DSI2_INT_ST_CRI 0x0460 156 #define DSI2_INT_MASK_CRI 0x0464 157 #define DSI2_INT_FORCE_CRI 0x0468 158 #define DSI2_MAX_REGISGER DSI2_INT_FORCE_CRI 159 160 #define MODE_STATUS_TIMEOUT_US 10000 161 #define CMD_PKT_STATUS_TIMEOUT_US 20000 162 163 enum vid_mode_type { 164 VID_MODE_TYPE_NON_BURST_SYNC_PULSES, 165 VID_MODE_TYPE_NON_BURST_SYNC_EVENTS, 166 VID_MODE_TYPE_BURST, 167 }; 168 169 enum mode_ctrl { 170 IDLE_MODE, 171 AUTOCALC_MODE, 172 COMMAND_MODE, 173 VIDEO_MODE, 174 DATA_STREAM_MODE, 175 VIDEO_TEST_MODE, 176 DATA_STREAM_TEST_MODE, 177 }; 178 179 enum ppi_width { 180 PPI_WIDTH_8_BITS, 181 PPI_WIDTH_16_BITS, 182 PPI_WIDTH_32_BITS, 183 }; 184 185 struct cmd_header { 186 u8 cmd_type; 187 u8 delay; 188 u8 payload_length; 189 }; 190 191 struct dw_mipi_dsi2 { 192 struct drm_bridge bridge; 193 struct mipi_dsi_host dsi_host; 194 struct drm_bridge *panel_bridge; 195 struct device *dev; 196 struct regmap *regmap; 197 struct clk *pclk; 198 struct clk *sys_clk; 199 200 unsigned int lane_mbps; /* per lane */ 201 u32 channel; 202 u32 lanes; 203 u32 format; 204 unsigned long mode_flags; 205 206 struct drm_display_mode mode; 207 const struct dw_mipi_dsi2_plat_data *plat_data; 208 }; 209 210 static inline struct dw_mipi_dsi2 *host_to_dsi2(struct mipi_dsi_host *host) 211 { 212 return container_of(host, struct dw_mipi_dsi2, dsi_host); 213 } 214 215 static inline struct dw_mipi_dsi2 *bridge_to_dsi2(struct drm_bridge *bridge) 216 { 217 return container_of(bridge, struct dw_mipi_dsi2, bridge); 218 } 219 220 static int cri_fifos_wait_avail(struct dw_mipi_dsi2 *dsi2) 221 { 222 u32 sts, mask; 223 int ret; 224 225 mask = CRI_BUSY | CRT_FIFOS_NOT_EMPTY; 226 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_CORE_STATUS, sts, 227 !(sts & mask), 0, CMD_PKT_STATUS_TIMEOUT_US); 228 if (ret < 0) { 229 dev_err(dsi2->dev, "command interface is busy\n"); 230 return ret; 231 } 232 233 return 0; 234 } 235 236 static void dw_mipi_dsi2_set_vid_mode(struct dw_mipi_dsi2 *dsi2) 237 { 238 u32 val = 0, mode; 239 int ret; 240 241 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 242 val |= BLK_HFP_HS_EN; 243 244 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 245 val |= BLK_HBP_HS_EN; 246 247 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 248 val |= BLK_HSA_HS_EN; 249 250 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 251 val |= VID_MODE_TYPE_BURST; 252 else if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 253 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 254 else 255 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 256 257 regmap_write(dsi2->regmap, DSI2_DSI_VID_TX_CFG, val); 258 259 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, VIDEO_MODE); 260 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS, 261 mode, mode & VIDEO_MODE, 262 1000, MODE_STATUS_TIMEOUT_US); 263 if (ret < 0) 264 dev_err(dsi2->dev, "failed to enter video mode\n"); 265 } 266 267 static void dw_mipi_dsi2_set_data_stream_mode(struct dw_mipi_dsi2 *dsi2) 268 { 269 u32 mode; 270 int ret; 271 272 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, DATA_STREAM_MODE); 273 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS, 274 mode, mode & DATA_STREAM_MODE, 275 1000, MODE_STATUS_TIMEOUT_US); 276 if (ret < 0) 277 dev_err(dsi2->dev, "failed to enter data stream mode\n"); 278 } 279 280 static void dw_mipi_dsi2_set_cmd_mode(struct dw_mipi_dsi2 *dsi2) 281 { 282 u32 mode; 283 int ret; 284 285 regmap_write(dsi2->regmap, DSI2_MODE_CTRL, COMMAND_MODE); 286 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_MODE_STATUS, 287 mode, mode & COMMAND_MODE, 288 1000, MODE_STATUS_TIMEOUT_US); 289 if (ret < 0) 290 dev_err(dsi2->dev, "failed to enter data stream mode\n"); 291 } 292 293 static void dw_mipi_dsi2_host_softrst(struct dw_mipi_dsi2 *dsi2) 294 { 295 regmap_write(dsi2->regmap, DSI2_SOFT_RESET, 0x0); 296 usleep_range(50, 100); 297 regmap_write(dsi2->regmap, DSI2_SOFT_RESET, 298 SYS_RSTN | PHY_RSTN | IPI_RSTN); 299 } 300 301 static void dw_mipi_dsi2_phy_clk_mode_cfg(struct dw_mipi_dsi2 *dsi2) 302 { 303 u32 sys_clk, esc_clk_div; 304 u32 val = 0; 305 306 /* 307 * clk_type should be NON_CONTINUOUS_CLK before 308 * initial deskew calibration be sent. 309 */ 310 val |= NON_CONTINUOUS_CLK; 311 312 /* The maximum value of the escape clock frequency is 20MHz */ 313 sys_clk = clk_get_rate(dsi2->sys_clk) / USEC_PER_SEC; 314 esc_clk_div = DIV_ROUND_UP(sys_clk, 20 * 2); 315 val |= PHY_LPTX_CLK_DIV(esc_clk_div); 316 317 regmap_write(dsi2->regmap, DSI2_PHY_CLK_CFG, val); 318 } 319 320 static void dw_mipi_dsi2_phy_ratio_cfg(struct dw_mipi_dsi2 *dsi2) 321 { 322 struct drm_display_mode *mode = &dsi2->mode; 323 u64 sys_clk = clk_get_rate(dsi2->sys_clk); 324 u64 pixel_clk, ipi_clk, phy_hsclk; 325 u64 tmp; 326 327 /* 328 * in DPHY mode, the phy_hstx_clk is exactly 1/16 the Lane high-speed 329 * data rate; In CPHY mode, the phy_hstx_clk is exactly 1/7 the trio 330 * high speed symbol rate. 331 */ 332 phy_hsclk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_mbps * USEC_PER_SEC, 16); 333 334 /* IPI_RATIO_MAN_CFG = PHY_HSTX_CLK / IPI_CLK */ 335 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 336 ipi_clk = pixel_clk / 4; 337 338 tmp = DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, ipi_clk); 339 regmap_write(dsi2->regmap, DSI2_PHY_IPI_RATIO_MAN_CFG, 340 PHY_IPI_RATIO(tmp)); 341 342 /* 343 * SYS_RATIO_MAN_CFG = MIPI_DCPHY_HSCLK_Freq / MIPI_DCPHY_HSCLK_Freq 344 */ 345 tmp = DIV_ROUND_CLOSEST_ULL(phy_hsclk << 16, sys_clk); 346 regmap_write(dsi2->regmap, DSI2_PHY_SYS_RATIO_MAN_CFG, 347 PHY_SYS_RATIO(tmp)); 348 } 349 350 static void dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(struct dw_mipi_dsi2 *dsi2) 351 { 352 const struct dw_mipi_dsi2_phy_ops *phy_ops = dsi2->plat_data->phy_ops; 353 struct dw_mipi_dsi2_phy_timing timing; 354 int ret; 355 356 ret = phy_ops->get_timing(dsi2->plat_data->priv_data, 357 dsi2->lane_mbps, &timing); 358 if (ret) 359 dev_err(dsi2->dev, "Retrieving phy timings failed\n"); 360 361 regmap_write(dsi2->regmap, DSI2_PHY_LP2HS_MAN_CFG, PHY_LP2HS_TIME(timing.data_lp2hs)); 362 regmap_write(dsi2->regmap, DSI2_PHY_HS2LP_MAN_CFG, PHY_HS2LP_TIME(timing.data_hs2lp)); 363 } 364 365 static void dw_mipi_dsi2_phy_init(struct dw_mipi_dsi2 *dsi2) 366 { 367 const struct dw_mipi_dsi2_phy_ops *phy_ops = dsi2->plat_data->phy_ops; 368 struct dw_mipi_dsi2_phy_iface iface; 369 u32 val = 0; 370 371 phy_ops->get_interface(dsi2->plat_data->priv_data, &iface); 372 373 switch (iface.ppi_width) { 374 case 8: 375 val |= PPI_WIDTH(PPI_WIDTH_8_BITS); 376 break; 377 case 16: 378 val |= PPI_WIDTH(PPI_WIDTH_16_BITS); 379 break; 380 case 32: 381 val |= PPI_WIDTH(PPI_WIDTH_32_BITS); 382 break; 383 default: 384 /* Caught in probe */ 385 break; 386 } 387 388 val |= PHY_LANES(dsi2->lanes); 389 val |= PHY_TYPE(DW_MIPI_DSI2_DPHY); 390 regmap_write(dsi2->regmap, DSI2_PHY_MODE_CFG, val); 391 392 dw_mipi_dsi2_phy_clk_mode_cfg(dsi2); 393 dw_mipi_dsi2_phy_ratio_cfg(dsi2); 394 dw_mipi_dsi2_lp2hs_or_hs2lp_cfg(dsi2); 395 396 /* phy configuration 8 - 10 */ 397 } 398 399 static void dw_mipi_dsi2_tx_option_set(struct dw_mipi_dsi2 *dsi2) 400 { 401 u32 val; 402 403 val = BTA_EN | EOTP_TX_EN; 404 405 if (dsi2->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 406 val &= ~EOTP_TX_EN; 407 408 regmap_write(dsi2->regmap, DSI2_DSI_GENERAL_CFG, val); 409 regmap_write(dsi2->regmap, DSI2_DSI_VCID_CFG, TX_VCID(dsi2->channel)); 410 } 411 412 static void dw_mipi_dsi2_ipi_color_coding_cfg(struct dw_mipi_dsi2 *dsi2) 413 { 414 u32 val, color_depth; 415 416 switch (dsi2->format) { 417 case MIPI_DSI_FMT_RGB666: 418 case MIPI_DSI_FMT_RGB666_PACKED: 419 color_depth = IPI_DEPTH_6_BITS; 420 break; 421 case MIPI_DSI_FMT_RGB565: 422 color_depth = IPI_DEPTH_5_6_5_BITS; 423 break; 424 case MIPI_DSI_FMT_RGB888: 425 default: 426 color_depth = IPI_DEPTH_8_BITS; 427 break; 428 } 429 430 val = IPI_DEPTH(color_depth) | 431 IPI_FORMAT(IPI_FORMAT_RGB); 432 regmap_write(dsi2->regmap, DSI2_IPI_COLOR_MAN_CFG, val); 433 } 434 435 static void dw_mipi_dsi2_vertical_timing_config(struct dw_mipi_dsi2 *dsi2, 436 const struct drm_display_mode *mode) 437 { 438 u32 vactive, vsa, vfp, vbp; 439 440 vactive = mode->vdisplay; 441 vsa = mode->vsync_end - mode->vsync_start; 442 vfp = mode->vsync_start - mode->vdisplay; 443 vbp = mode->vtotal - mode->vsync_end; 444 445 regmap_write(dsi2->regmap, DSI2_IPI_VID_VSA_MAN_CFG, VID_VSA_LINES(vsa)); 446 regmap_write(dsi2->regmap, DSI2_IPI_VID_VBP_MAN_CFG, VID_VBP_LINES(vbp)); 447 regmap_write(dsi2->regmap, DSI2_IPI_VID_VACT_MAN_CFG, VID_VACT_LINES(vactive)); 448 regmap_write(dsi2->regmap, DSI2_IPI_VID_VFP_MAN_CFG, VID_VFP_LINES(vfp)); 449 } 450 451 static void dw_mipi_dsi2_ipi_set(struct dw_mipi_dsi2 *dsi2) 452 { 453 struct drm_display_mode *mode = &dsi2->mode; 454 u32 hline, hsa, hbp, hact; 455 u64 hline_time, hsa_time, hbp_time, hact_time, tmp; 456 u64 pixel_clk, phy_hs_clk; 457 u16 val; 458 459 val = mode->hdisplay; 460 461 regmap_write(dsi2->regmap, DSI2_IPI_PIX_PKT_CFG, MAX_PIX_PKT(val)); 462 463 dw_mipi_dsi2_ipi_color_coding_cfg(dsi2); 464 465 /* 466 * if the controller is intended to operate in data stream mode, 467 * no more steps are required. 468 */ 469 if (!(dsi2->mode_flags & MIPI_DSI_MODE_VIDEO)) 470 return; 471 472 hact = mode->hdisplay; 473 hsa = mode->hsync_end - mode->hsync_start; 474 hbp = mode->htotal - mode->hsync_end; 475 hline = mode->htotal; 476 477 pixel_clk = mode->crtc_clock * MSEC_PER_SEC; 478 479 phy_hs_clk = DIV_ROUND_CLOSEST_ULL(dsi2->lane_mbps * USEC_PER_SEC, 16); 480 481 tmp = hsa * phy_hs_clk; 482 hsa_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk); 483 regmap_write(dsi2->regmap, DSI2_IPI_VID_HSA_MAN_CFG, VID_HSA_TIME(hsa_time)); 484 485 tmp = hbp * phy_hs_clk; 486 hbp_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk); 487 regmap_write(dsi2->regmap, DSI2_IPI_VID_HBP_MAN_CFG, VID_HBP_TIME(hbp_time)); 488 489 tmp = hact * phy_hs_clk; 490 hact_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk); 491 regmap_write(dsi2->regmap, DSI2_IPI_VID_HACT_MAN_CFG, VID_HACT_TIME(hact_time)); 492 493 tmp = hline * phy_hs_clk; 494 hline_time = DIV_ROUND_CLOSEST_ULL(tmp << 16, pixel_clk); 495 regmap_write(dsi2->regmap, DSI2_IPI_VID_HLINE_MAN_CFG, VID_HLINE_TIME(hline_time)); 496 497 dw_mipi_dsi2_vertical_timing_config(dsi2, mode); 498 } 499 500 static void 501 dw_mipi_dsi2_work_mode(struct dw_mipi_dsi2 *dsi2, u32 mode) 502 { 503 /* 504 * select controller work in Manual mode 505 * Manual: MANUAL_MODE_EN 506 * Automatic: 0 507 */ 508 regmap_write(dsi2->regmap, MANUAL_MODE_CFG, mode); 509 } 510 511 static int dw_mipi_dsi2_host_attach(struct mipi_dsi_host *host, 512 struct mipi_dsi_device *device) 513 { 514 struct dw_mipi_dsi2 *dsi2 = host_to_dsi2(host); 515 const struct dw_mipi_dsi2_plat_data *pdata = dsi2->plat_data; 516 struct drm_bridge *bridge; 517 int ret; 518 519 if (device->lanes > dsi2->plat_data->max_data_lanes) { 520 dev_err(dsi2->dev, "the number of data lanes(%u) is too many\n", 521 device->lanes); 522 return -EINVAL; 523 } 524 525 dsi2->lanes = device->lanes; 526 dsi2->channel = device->channel; 527 dsi2->format = device->format; 528 dsi2->mode_flags = device->mode_flags; 529 530 bridge = devm_drm_of_get_bridge(dsi2->dev, dsi2->dev->of_node, 1, 0); 531 if (IS_ERR(bridge)) 532 return PTR_ERR(bridge); 533 534 bridge->pre_enable_prev_first = true; 535 dsi2->panel_bridge = bridge; 536 537 drm_bridge_add(&dsi2->bridge); 538 539 if (pdata->host_ops && pdata->host_ops->attach) { 540 ret = pdata->host_ops->attach(pdata->priv_data, device); 541 if (ret < 0) 542 return ret; 543 } 544 545 return 0; 546 } 547 548 static int dw_mipi_dsi2_host_detach(struct mipi_dsi_host *host, 549 struct mipi_dsi_device *device) 550 { 551 struct dw_mipi_dsi2 *dsi2 = host_to_dsi2(host); 552 const struct dw_mipi_dsi2_plat_data *pdata = dsi2->plat_data; 553 int ret; 554 555 if (pdata->host_ops && pdata->host_ops->detach) { 556 ret = pdata->host_ops->detach(pdata->priv_data, device); 557 if (ret < 0) 558 return ret; 559 } 560 561 drm_bridge_remove(&dsi2->bridge); 562 563 drm_of_panel_bridge_remove(host->dev->of_node, 1, 0); 564 565 return 0; 566 } 567 568 static int dw_mipi_dsi2_gen_pkt_hdr_write(struct dw_mipi_dsi2 *dsi2, 569 u32 hdr_val, bool lpm) 570 { 571 int ret; 572 573 regmap_write(dsi2->regmap, DSI2_CRI_TX_HDR, hdr_val | CMD_TX_MODE(lpm)); 574 575 ret = cri_fifos_wait_avail(dsi2); 576 if (ret) { 577 dev_err(dsi2->dev, "failed to write command header\n"); 578 return ret; 579 } 580 581 return 0; 582 } 583 584 static int dw_mipi_dsi2_write(struct dw_mipi_dsi2 *dsi2, 585 const struct mipi_dsi_packet *packet, bool lpm) 586 { 587 const u8 *tx_buf = packet->payload; 588 int len = packet->payload_length, pld_data_bytes = sizeof(u32); 589 __le32 word; 590 591 /* Send payload */ 592 while (len) { 593 if (len < pld_data_bytes) { 594 word = 0; 595 memcpy(&word, tx_buf, len); 596 regmap_write(dsi2->regmap, DSI2_CRI_TX_PLD, le32_to_cpu(word)); 597 len = 0; 598 } else { 599 memcpy(&word, tx_buf, pld_data_bytes); 600 regmap_write(dsi2->regmap, DSI2_CRI_TX_PLD, le32_to_cpu(word)); 601 tx_buf += pld_data_bytes; 602 len -= pld_data_bytes; 603 } 604 } 605 606 word = 0; 607 memcpy(&word, packet->header, sizeof(packet->header)); 608 return dw_mipi_dsi2_gen_pkt_hdr_write(dsi2, le32_to_cpu(word), lpm); 609 } 610 611 static int dw_mipi_dsi2_read(struct dw_mipi_dsi2 *dsi2, 612 const struct mipi_dsi_msg *msg) 613 { 614 u8 *payload = msg->rx_buf; 615 int i, j, ret, len = msg->rx_len; 616 u8 data_type; 617 u16 wc; 618 u32 val; 619 620 ret = regmap_read_poll_timeout(dsi2->regmap, DSI2_CORE_STATUS, 621 val, val & CRI_RD_DATA_AVAIL, 622 100, CMD_PKT_STATUS_TIMEOUT_US); 623 if (ret) { 624 dev_err(dsi2->dev, "CRI has no available read data\n"); 625 return ret; 626 } 627 628 regmap_read(dsi2->regmap, DSI2_CRI_RX_HDR, &val); 629 data_type = val & 0x3f; 630 631 if (mipi_dsi_packet_format_is_short(data_type)) { 632 for (i = 0; i < len && i < 2; i++) 633 payload[i] = (val >> (8 * (i + 1))) & 0xff; 634 635 return 0; 636 } 637 638 wc = (val >> 8) & 0xffff; 639 /* Receive payload */ 640 for (i = 0; i < len && i < wc; i += 4) { 641 regmap_read(dsi2->regmap, DSI2_CRI_RX_PLD, &val); 642 for (j = 0; j < 4 && j + i < len && j + i < wc; j++) 643 payload[i + j] = val >> (8 * j); 644 } 645 646 return 0; 647 } 648 649 static ssize_t dw_mipi_dsi2_host_transfer(struct mipi_dsi_host *host, 650 const struct mipi_dsi_msg *msg) 651 { 652 struct dw_mipi_dsi2 *dsi2 = host_to_dsi2(host); 653 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; 654 struct mipi_dsi_packet packet; 655 int ret, nb_bytes; 656 657 regmap_update_bits(dsi2->regmap, DSI2_DSI_VID_TX_CFG, 658 LPDT_DISPLAY_CMD_EN, 659 lpm ? LPDT_DISPLAY_CMD_EN : 0); 660 661 /* create a packet to the DSI protocol */ 662 ret = mipi_dsi_create_packet(&packet, msg); 663 if (ret) { 664 dev_err(dsi2->dev, "failed to create packet: %d\n", ret); 665 return ret; 666 } 667 668 ret = cri_fifos_wait_avail(dsi2); 669 if (ret) 670 return ret; 671 672 ret = dw_mipi_dsi2_write(dsi2, &packet, lpm); 673 if (ret) 674 return ret; 675 676 if (msg->rx_buf && msg->rx_len) { 677 ret = dw_mipi_dsi2_read(dsi2, msg); 678 if (ret < 0) 679 return ret; 680 nb_bytes = msg->rx_len; 681 } else { 682 nb_bytes = packet.size; 683 } 684 685 return nb_bytes; 686 } 687 688 static const struct mipi_dsi_host_ops dw_mipi_dsi2_host_ops = { 689 .attach = dw_mipi_dsi2_host_attach, 690 .detach = dw_mipi_dsi2_host_detach, 691 .transfer = dw_mipi_dsi2_host_transfer, 692 }; 693 694 static u32 * 695 dw_mipi_dsi2_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 696 struct drm_bridge_state *bridge_state, 697 struct drm_crtc_state *crtc_state, 698 struct drm_connector_state *conn_state, 699 u32 output_fmt, 700 unsigned int *num_input_fmts) 701 { 702 struct dw_mipi_dsi2 *dsi2 = bridge_to_dsi2(bridge); 703 const struct dw_mipi_dsi2_plat_data *pdata = dsi2->plat_data; 704 u32 *input_fmts; 705 706 if (pdata->get_input_bus_fmts) 707 return pdata->get_input_bus_fmts(pdata->priv_data, 708 bridge, bridge_state, 709 crtc_state, conn_state, 710 output_fmt, num_input_fmts); 711 712 /* Fall back to MEDIA_BUS_FMT_FIXED as the only input format. */ 713 input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); 714 if (!input_fmts) 715 return NULL; 716 input_fmts[0] = MEDIA_BUS_FMT_FIXED; 717 *num_input_fmts = 1; 718 719 return input_fmts; 720 } 721 722 static int dw_mipi_dsi2_bridge_atomic_check(struct drm_bridge *bridge, 723 struct drm_bridge_state *bridge_state, 724 struct drm_crtc_state *crtc_state, 725 struct drm_connector_state *conn_state) 726 { 727 struct dw_mipi_dsi2 *dsi2 = bridge_to_dsi2(bridge); 728 const struct dw_mipi_dsi2_plat_data *pdata = dsi2->plat_data; 729 bool ret; 730 731 bridge_state->input_bus_cfg.flags = 732 DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE; 733 734 if (pdata->mode_fixup) { 735 ret = pdata->mode_fixup(pdata->priv_data, &crtc_state->mode, 736 &crtc_state->adjusted_mode); 737 if (!ret) { 738 DRM_DEBUG_DRIVER("failed to fixup mode " DRM_MODE_FMT "\n", 739 DRM_MODE_ARG(&crtc_state->mode)); 740 return -EINVAL; 741 } 742 } 743 744 return 0; 745 } 746 747 static void dw_mipi_dsi2_bridge_post_atomic_disable(struct drm_bridge *bridge, 748 struct drm_bridge_state *old_bridge_state) 749 { 750 struct dw_mipi_dsi2 *dsi2 = bridge_to_dsi2(bridge); 751 const struct dw_mipi_dsi2_phy_ops *phy_ops = dsi2->plat_data->phy_ops; 752 753 regmap_write(dsi2->regmap, DSI2_IPI_PIX_PKT_CFG, 0); 754 755 /* 756 * Switch to command mode before panel-bridge post_disable & 757 * panel unprepare. 758 * Note: panel-bridge disable & panel disable has been called 759 * before by the drm framework. 760 */ 761 dw_mipi_dsi2_set_cmd_mode(dsi2); 762 763 regmap_write(dsi2->regmap, DSI2_PWR_UP, RESET); 764 765 if (phy_ops->power_off) 766 phy_ops->power_off(dsi2->plat_data->priv_data); 767 768 clk_disable_unprepare(dsi2->sys_clk); 769 clk_disable_unprepare(dsi2->pclk); 770 pm_runtime_put(dsi2->dev); 771 } 772 773 static unsigned int dw_mipi_dsi2_get_lanes(struct dw_mipi_dsi2 *dsi2) 774 { 775 /* single-dsi, so no other instance to consider */ 776 return dsi2->lanes; 777 } 778 779 static void dw_mipi_dsi2_mode_set(struct dw_mipi_dsi2 *dsi2, 780 const struct drm_display_mode *adjusted_mode) 781 { 782 const struct dw_mipi_dsi2_phy_ops *phy_ops = dsi2->plat_data->phy_ops; 783 void *priv_data = dsi2->plat_data->priv_data; 784 u32 lanes = dw_mipi_dsi2_get_lanes(dsi2); 785 int ret; 786 787 clk_prepare_enable(dsi2->pclk); 788 clk_prepare_enable(dsi2->sys_clk); 789 790 ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi2->mode_flags, 791 lanes, dsi2->format, &dsi2->lane_mbps); 792 if (ret) 793 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n"); 794 795 pm_runtime_get_sync(dsi2->dev); 796 797 dw_mipi_dsi2_host_softrst(dsi2); 798 regmap_write(dsi2->regmap, DSI2_PWR_UP, RESET); 799 800 dw_mipi_dsi2_work_mode(dsi2, MANUAL_MODE_EN); 801 dw_mipi_dsi2_phy_init(dsi2); 802 803 if (phy_ops->power_on) 804 phy_ops->power_on(dsi2->plat_data->priv_data); 805 806 dw_mipi_dsi2_tx_option_set(dsi2); 807 808 /* 809 * initial deskew calibration is send after phy_power_on, 810 * then we can configure clk_type. 811 */ 812 813 regmap_update_bits(dsi2->regmap, DSI2_PHY_CLK_CFG, CLK_TYPE_MASK, 814 dsi2->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS ? NON_CONTINUOUS_CLK : 815 CONTINUOUS_CLK); 816 817 regmap_write(dsi2->regmap, DSI2_PWR_UP, POWER_UP); 818 dw_mipi_dsi2_set_cmd_mode(dsi2); 819 820 dw_mipi_dsi2_ipi_set(dsi2); 821 } 822 823 static void dw_mipi_dsi2_bridge_atomic_pre_enable(struct drm_bridge *bridge, 824 struct drm_bridge_state *old_bridge_state) 825 { 826 struct dw_mipi_dsi2 *dsi2 = bridge_to_dsi2(bridge); 827 828 /* Power up the dsi ctl into a command mode */ 829 dw_mipi_dsi2_mode_set(dsi2, &dsi2->mode); 830 } 831 832 static void dw_mipi_dsi2_bridge_mode_set(struct drm_bridge *bridge, 833 const struct drm_display_mode *mode, 834 const struct drm_display_mode *adjusted_mode) 835 { 836 struct dw_mipi_dsi2 *dsi2 = bridge_to_dsi2(bridge); 837 838 /* Store the display mode for later use in pre_enable callback */ 839 drm_mode_copy(&dsi2->mode, adjusted_mode); 840 } 841 842 static void dw_mipi_dsi2_bridge_atomic_enable(struct drm_bridge *bridge, 843 struct drm_bridge_state *old_bridge_state) 844 { 845 struct dw_mipi_dsi2 *dsi2 = bridge_to_dsi2(bridge); 846 847 /* Switch to video mode for panel-bridge enable & panel enable */ 848 if (dsi2->mode_flags & MIPI_DSI_MODE_VIDEO) 849 dw_mipi_dsi2_set_vid_mode(dsi2); 850 else 851 dw_mipi_dsi2_set_data_stream_mode(dsi2); 852 } 853 854 static enum drm_mode_status 855 dw_mipi_dsi2_bridge_mode_valid(struct drm_bridge *bridge, 856 const struct drm_display_info *info, 857 const struct drm_display_mode *mode) 858 { 859 struct dw_mipi_dsi2 *dsi2 = bridge_to_dsi2(bridge); 860 const struct dw_mipi_dsi2_plat_data *pdata = dsi2->plat_data; 861 enum drm_mode_status mode_status = MODE_OK; 862 863 if (pdata->mode_valid) 864 mode_status = pdata->mode_valid(pdata->priv_data, mode, 865 dsi2->mode_flags, 866 dw_mipi_dsi2_get_lanes(dsi2), 867 dsi2->format); 868 869 return mode_status; 870 } 871 872 static int dw_mipi_dsi2_bridge_attach(struct drm_bridge *bridge, 873 enum drm_bridge_attach_flags flags) 874 { 875 struct dw_mipi_dsi2 *dsi2 = bridge_to_dsi2(bridge); 876 877 /* Set the encoder type as caller does not know it */ 878 bridge->encoder->encoder_type = DRM_MODE_ENCODER_DSI; 879 880 /* Attach the panel-bridge to the dsi bridge */ 881 return drm_bridge_attach(bridge->encoder, dsi2->panel_bridge, bridge, 882 flags); 883 } 884 885 static const struct drm_bridge_funcs dw_mipi_dsi2_bridge_funcs = { 886 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 887 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 888 .atomic_get_input_bus_fmts = dw_mipi_dsi2_bridge_atomic_get_input_bus_fmts, 889 .atomic_check = dw_mipi_dsi2_bridge_atomic_check, 890 .atomic_reset = drm_atomic_helper_bridge_reset, 891 .atomic_pre_enable = dw_mipi_dsi2_bridge_atomic_pre_enable, 892 .atomic_enable = dw_mipi_dsi2_bridge_atomic_enable, 893 .atomic_post_disable = dw_mipi_dsi2_bridge_post_atomic_disable, 894 .mode_set = dw_mipi_dsi2_bridge_mode_set, 895 .mode_valid = dw_mipi_dsi2_bridge_mode_valid, 896 .attach = dw_mipi_dsi2_bridge_attach, 897 }; 898 899 static const struct regmap_config dw_mipi_dsi2_regmap_config = { 900 .name = "dsi2-host", 901 .reg_bits = 32, 902 .val_bits = 32, 903 .reg_stride = 4, 904 .fast_io = true, 905 }; 906 907 static struct dw_mipi_dsi2 * 908 __dw_mipi_dsi2_probe(struct platform_device *pdev, 909 const struct dw_mipi_dsi2_plat_data *plat_data) 910 { 911 struct device *dev = &pdev->dev; 912 struct reset_control *apb_rst; 913 struct dw_mipi_dsi2 *dsi2; 914 int ret; 915 916 dsi2 = devm_kzalloc(dev, sizeof(*dsi2), GFP_KERNEL); 917 if (!dsi2) 918 return ERR_PTR(-ENOMEM); 919 920 dsi2->dev = dev; 921 dsi2->plat_data = plat_data; 922 923 if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps || 924 !plat_data->phy_ops->get_timing) 925 return dev_err_ptr_probe(dev, -ENODEV, "Phy not properly configured\n"); 926 927 if (!plat_data->regmap) { 928 void __iomem *base = devm_platform_ioremap_resource(pdev, 0); 929 930 if (IS_ERR(base)) 931 return dev_err_cast_probe(dev, base, "failed to registers\n"); 932 933 dsi2->regmap = devm_regmap_init_mmio(dev, base, 934 &dw_mipi_dsi2_regmap_config); 935 if (IS_ERR(dsi2->regmap)) 936 return dev_err_cast_probe(dev, dsi2->regmap, "failed to init regmap\n"); 937 } else { 938 dsi2->regmap = plat_data->regmap; 939 } 940 941 dsi2->pclk = devm_clk_get(dev, "pclk"); 942 if (IS_ERR(dsi2->pclk)) 943 return dev_err_cast_probe(dev, dsi2->pclk, "Unable to get pclk\n"); 944 945 dsi2->sys_clk = devm_clk_get(dev, "sys"); 946 if (IS_ERR(dsi2->sys_clk)) 947 return dev_err_cast_probe(dev, dsi2->sys_clk, "Unable to get sys_clk\n"); 948 949 /* 950 * Note that the reset was not defined in the initial device tree, so 951 * we have to be prepared for it not being found. 952 */ 953 apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb"); 954 if (IS_ERR(apb_rst)) 955 return dev_err_cast_probe(dev, apb_rst, "Unable to get reset control\n"); 956 957 if (apb_rst) { 958 ret = clk_prepare_enable(dsi2->pclk); 959 if (ret) { 960 dev_err(dev, "%s: Failed to enable pclk\n", __func__); 961 return ERR_PTR(ret); 962 } 963 964 reset_control_assert(apb_rst); 965 usleep_range(10, 20); 966 reset_control_deassert(apb_rst); 967 968 clk_disable_unprepare(dsi2->pclk); 969 } 970 971 devm_pm_runtime_enable(dev); 972 973 dsi2->dsi_host.ops = &dw_mipi_dsi2_host_ops; 974 dsi2->dsi_host.dev = dev; 975 ret = mipi_dsi_host_register(&dsi2->dsi_host); 976 if (ret) { 977 dev_err(dev, "Failed to register MIPI host: %d\n", ret); 978 pm_runtime_disable(dev); 979 return ERR_PTR(ret); 980 } 981 982 dsi2->bridge.driver_private = dsi2; 983 dsi2->bridge.funcs = &dw_mipi_dsi2_bridge_funcs; 984 dsi2->bridge.of_node = pdev->dev.of_node; 985 986 return dsi2; 987 } 988 989 static void __dw_mipi_dsi2_remove(struct dw_mipi_dsi2 *dsi2) 990 { 991 mipi_dsi_host_unregister(&dsi2->dsi_host); 992 } 993 994 /* 995 * Probe/remove API, used to create the bridge instance. 996 */ 997 struct dw_mipi_dsi2 * 998 dw_mipi_dsi2_probe(struct platform_device *pdev, 999 const struct dw_mipi_dsi2_plat_data *plat_data) 1000 { 1001 return __dw_mipi_dsi2_probe(pdev, plat_data); 1002 } 1003 EXPORT_SYMBOL_GPL(dw_mipi_dsi2_probe); 1004 1005 void dw_mipi_dsi2_remove(struct dw_mipi_dsi2 *dsi2) 1006 { 1007 __dw_mipi_dsi2_remove(dsi2); 1008 } 1009 EXPORT_SYMBOL_GPL(dw_mipi_dsi2_remove); 1010 1011 /* 1012 * Bind/unbind API, used from platforms based on the component framework 1013 * to attach the bridge to an encoder. 1014 */ 1015 int dw_mipi_dsi2_bind(struct dw_mipi_dsi2 *dsi2, struct drm_encoder *encoder) 1016 { 1017 return drm_bridge_attach(encoder, &dsi2->bridge, NULL, 0); 1018 } 1019 EXPORT_SYMBOL_GPL(dw_mipi_dsi2_bind); 1020 1021 void dw_mipi_dsi2_unbind(struct dw_mipi_dsi2 *dsi2) 1022 { 1023 } 1024 EXPORT_SYMBOL_GPL(dw_mipi_dsi2_unbind); 1025 1026 MODULE_AUTHOR("Guochun Huang <hero.huang@rock-chips.com>"); 1027 MODULE_AUTHOR("Heiko Stuebner <heiko.stuebner@cherry.de>"); 1028 MODULE_DESCRIPTION("DW MIPI DSI2 host controller driver"); 1029 MODULE_LICENSE("GPL"); 1030 MODULE_ALIAS("platform:dw-mipi-dsi2"); 1031