1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd 4 * Copyright (C) STMicroelectronics SA 2017 5 * 6 * Modified by Philippe Cornu <philippe.cornu@st.com> 7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the 8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs. 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/debugfs.h> 14 #include <linux/export.h> 15 #include <linux/iopoll.h> 16 #include <linux/math64.h> 17 #include <linux/media-bus-format.h> 18 #include <linux/module.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/reset.h> 22 23 #include <video/mipi_display.h> 24 25 #include <drm/bridge/dw_mipi_dsi.h> 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_bridge.h> 28 #include <drm/drm_connector.h> 29 #include <drm/drm_crtc.h> 30 #include <drm/drm_mipi_dsi.h> 31 #include <drm/drm_modes.h> 32 #include <drm/drm_of.h> 33 #include <drm/drm_print.h> 34 35 #define HWVER_131 0x31333100 /* IP version 1.31 */ 36 37 #define DSI_VERSION 0x00 38 #define VERSION GENMASK(31, 8) 39 40 #define DSI_PWR_UP 0x04 41 #define RESET 0 42 #define POWERUP BIT(0) 43 44 #define DSI_CLKMGR_CFG 0x08 45 #define TO_CLK_DIVISION(div) (((div) & 0xff) << 8) 46 #define TX_ESC_CLK_DIVISION(div) ((div) & 0xff) 47 48 #define DSI_DPI_VCID 0x0c 49 #define DPI_VCID(vcid) ((vcid) & 0x3) 50 51 #define DSI_DPI_COLOR_CODING 0x10 52 #define LOOSELY18_EN BIT(8) 53 #define DPI_COLOR_CODING_16BIT_1 0x0 54 #define DPI_COLOR_CODING_16BIT_2 0x1 55 #define DPI_COLOR_CODING_16BIT_3 0x2 56 #define DPI_COLOR_CODING_18BIT_1 0x3 57 #define DPI_COLOR_CODING_18BIT_2 0x4 58 #define DPI_COLOR_CODING_24BIT 0x5 59 60 #define DSI_DPI_CFG_POL 0x14 61 #define COLORM_ACTIVE_LOW BIT(4) 62 #define SHUTD_ACTIVE_LOW BIT(3) 63 #define HSYNC_ACTIVE_LOW BIT(2) 64 #define VSYNC_ACTIVE_LOW BIT(1) 65 #define DATAEN_ACTIVE_LOW BIT(0) 66 67 #define DSI_DPI_LP_CMD_TIM 0x18 68 #define OUTVACT_LPCMD_TIME(p) (((p) & 0xff) << 16) 69 #define INVACT_LPCMD_TIME(p) ((p) & 0xff) 70 71 #define DSI_DBI_VCID 0x1c 72 #define DSI_DBI_CFG 0x20 73 #define DSI_DBI_PARTITIONING_EN 0x24 74 #define DSI_DBI_CMDSIZE 0x28 75 76 #define DSI_PCKHDL_CFG 0x2c 77 #define CRC_RX_EN BIT(4) 78 #define ECC_RX_EN BIT(3) 79 #define BTA_EN BIT(2) 80 #define EOTP_RX_EN BIT(1) 81 #define EOTP_TX_EN BIT(0) 82 83 #define DSI_GEN_VCID 0x30 84 85 #define DSI_MODE_CFG 0x34 86 #define ENABLE_VIDEO_MODE 0 87 #define ENABLE_CMD_MODE BIT(0) 88 89 #define DSI_VID_MODE_CFG 0x38 90 #define ENABLE_LOW_POWER (0x3f << 8) 91 #define ENABLE_LOW_POWER_MASK (0x3f << 8) 92 #define VID_MODE_TYPE_NON_BURST_SYNC_PULSES 0x0 93 #define VID_MODE_TYPE_NON_BURST_SYNC_EVENTS 0x1 94 #define VID_MODE_TYPE_BURST 0x2 95 #define VID_MODE_TYPE_MASK 0x3 96 #define ENABLE_LOW_POWER_CMD BIT(15) 97 #define VID_MODE_VPG_ENABLE BIT(16) 98 #define VID_MODE_VPG_MODE BIT(20) 99 #define VID_MODE_VPG_HORIZONTAL BIT(24) 100 101 #define DSI_VID_PKT_SIZE 0x3c 102 #define VID_PKT_SIZE(p) ((p) & 0x3fff) 103 104 #define DSI_VID_NUM_CHUNKS 0x40 105 #define VID_NUM_CHUNKS(c) ((c) & 0x1fff) 106 107 #define DSI_VID_NULL_SIZE 0x44 108 #define VID_NULL_SIZE(b) ((b) & 0x1fff) 109 110 #define DSI_VID_HSA_TIME 0x48 111 #define DSI_VID_HBP_TIME 0x4c 112 #define DSI_VID_HLINE_TIME 0x50 113 #define DSI_VID_VSA_LINES 0x54 114 #define DSI_VID_VBP_LINES 0x58 115 #define DSI_VID_VFP_LINES 0x5c 116 #define DSI_VID_VACTIVE_LINES 0x60 117 #define DSI_EDPI_CMD_SIZE 0x64 118 119 #define DSI_CMD_MODE_CFG 0x68 120 #define MAX_RD_PKT_SIZE_LP BIT(24) 121 #define DCS_LW_TX_LP BIT(19) 122 #define DCS_SR_0P_TX_LP BIT(18) 123 #define DCS_SW_1P_TX_LP BIT(17) 124 #define DCS_SW_0P_TX_LP BIT(16) 125 #define GEN_LW_TX_LP BIT(14) 126 #define GEN_SR_2P_TX_LP BIT(13) 127 #define GEN_SR_1P_TX_LP BIT(12) 128 #define GEN_SR_0P_TX_LP BIT(11) 129 #define GEN_SW_2P_TX_LP BIT(10) 130 #define GEN_SW_1P_TX_LP BIT(9) 131 #define GEN_SW_0P_TX_LP BIT(8) 132 #define ACK_RQST_EN BIT(1) 133 #define TEAR_FX_EN BIT(0) 134 135 #define CMD_MODE_ALL_LP (MAX_RD_PKT_SIZE_LP | \ 136 DCS_LW_TX_LP | \ 137 DCS_SR_0P_TX_LP | \ 138 DCS_SW_1P_TX_LP | \ 139 DCS_SW_0P_TX_LP | \ 140 GEN_LW_TX_LP | \ 141 GEN_SR_2P_TX_LP | \ 142 GEN_SR_1P_TX_LP | \ 143 GEN_SR_0P_TX_LP | \ 144 GEN_SW_2P_TX_LP | \ 145 GEN_SW_1P_TX_LP | \ 146 GEN_SW_0P_TX_LP) 147 148 #define DSI_GEN_HDR 0x6c 149 #define DSI_GEN_PLD_DATA 0x70 150 151 #define DSI_CMD_PKT_STATUS 0x74 152 #define GEN_RD_CMD_BUSY BIT(6) 153 #define GEN_PLD_R_FULL BIT(5) 154 #define GEN_PLD_R_EMPTY BIT(4) 155 #define GEN_PLD_W_FULL BIT(3) 156 #define GEN_PLD_W_EMPTY BIT(2) 157 #define GEN_CMD_FULL BIT(1) 158 #define GEN_CMD_EMPTY BIT(0) 159 160 #define DSI_TO_CNT_CFG 0x78 161 #define HSTX_TO_CNT(p) (((p) & 0xffff) << 16) 162 #define LPRX_TO_CNT(p) ((p) & 0xffff) 163 164 #define DSI_HS_RD_TO_CNT 0x7c 165 #define DSI_LP_RD_TO_CNT 0x80 166 #define DSI_HS_WR_TO_CNT 0x84 167 #define DSI_LP_WR_TO_CNT 0x88 168 #define DSI_BTA_TO_CNT 0x8c 169 170 #define DSI_LPCLK_CTRL 0x94 171 #define AUTO_CLKLANE_CTRL BIT(1) 172 #define PHY_TXREQUESTCLKHS BIT(0) 173 174 #define DSI_PHY_TMR_LPCLK_CFG 0x98 175 #define PHY_CLKHS2LP_TIME(lbcc) (((lbcc) & 0x3ff) << 16) 176 #define PHY_CLKLP2HS_TIME(lbcc) ((lbcc) & 0x3ff) 177 178 #define DSI_PHY_TMR_CFG 0x9c 179 #define PHY_HS2LP_TIME(lbcc) (((lbcc) & 0xff) << 24) 180 #define PHY_LP2HS_TIME(lbcc) (((lbcc) & 0xff) << 16) 181 #define MAX_RD_TIME(lbcc) ((lbcc) & 0x7fff) 182 #define PHY_HS2LP_TIME_V131(lbcc) (((lbcc) & 0x3ff) << 16) 183 #define PHY_LP2HS_TIME_V131(lbcc) ((lbcc) & 0x3ff) 184 185 #define DSI_PHY_RSTZ 0xa0 186 #define PHY_DISFORCEPLL 0 187 #define PHY_ENFORCEPLL BIT(3) 188 #define PHY_DISABLECLK 0 189 #define PHY_ENABLECLK BIT(2) 190 #define PHY_RSTZ 0 191 #define PHY_UNRSTZ BIT(1) 192 #define PHY_SHUTDOWNZ 0 193 #define PHY_UNSHUTDOWNZ BIT(0) 194 195 #define DSI_PHY_IF_CFG 0xa4 196 #define PHY_STOP_WAIT_TIME(cycle) (((cycle) & 0xff) << 8) 197 #define N_LANES(n) (((n) - 1) & 0x3) 198 199 #define DSI_PHY_ULPS_CTRL 0xa8 200 #define DSI_PHY_TX_TRIGGERS 0xac 201 202 #define DSI_PHY_STATUS 0xb0 203 #define PHY_STOP_STATE_CLK_LANE BIT(2) 204 #define PHY_LOCK BIT(0) 205 206 #define DSI_PHY_TST_CTRL0 0xb4 207 #define PHY_TESTCLK BIT(1) 208 #define PHY_UNTESTCLK 0 209 #define PHY_TESTCLR BIT(0) 210 #define PHY_UNTESTCLR 0 211 212 #define DSI_PHY_TST_CTRL1 0xb8 213 #define PHY_TESTEN BIT(16) 214 #define PHY_UNTESTEN 0 215 #define PHY_TESTDOUT(n) (((n) & 0xff) << 8) 216 #define PHY_TESTDIN(n) ((n) & 0xff) 217 218 #define DSI_INT_ST0 0xbc 219 #define DSI_INT_ST1 0xc0 220 #define DSI_INT_MSK0 0xc4 221 #define DSI_INT_MSK1 0xc8 222 223 #define DSI_PHY_TMR_RD_CFG 0xf4 224 #define MAX_RD_TIME_V131(lbcc) ((lbcc) & 0x7fff) 225 226 #define PHY_STATUS_TIMEOUT_US 10000 227 #define CMD_PKT_STATUS_TIMEOUT_US 20000 228 229 #ifdef CONFIG_DEBUG_FS 230 #define VPG_DEFS(name, dsi) \ 231 ((void __force *)&((*dsi).vpg_defs.name)) 232 233 #define REGISTER(name, mask, dsi) \ 234 { #name, VPG_DEFS(name, dsi), mask, dsi } 235 236 struct debugfs_entries { 237 const char *name; 238 bool *reg; 239 u32 mask; 240 struct dw_mipi_dsi *dsi; 241 }; 242 #endif /* CONFIG_DEBUG_FS */ 243 244 struct dw_mipi_dsi { 245 struct drm_bridge bridge; 246 struct mipi_dsi_host dsi_host; 247 struct drm_bridge *panel_bridge; 248 struct device *dev; 249 void __iomem *base; 250 251 struct clk *pclk; 252 253 unsigned int lane_mbps; /* per lane */ 254 u32 channel; 255 u32 lanes; 256 u32 format; 257 unsigned long mode_flags; 258 259 #ifdef CONFIG_DEBUG_FS 260 struct dentry *debugfs; 261 struct debugfs_entries *debugfs_vpg; 262 struct { 263 bool vpg; 264 bool vpg_horizontal; 265 bool vpg_ber_pattern; 266 } vpg_defs; 267 #endif /* CONFIG_DEBUG_FS */ 268 269 struct dw_mipi_dsi *master; /* dual-dsi master ptr */ 270 struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */ 271 272 struct drm_display_mode mode; 273 const struct dw_mipi_dsi_plat_data *plat_data; 274 }; 275 276 /* 277 * Check if either a link to a master or slave is present 278 */ 279 static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi) 280 { 281 return dsi->slave || dsi->master; 282 } 283 284 /* 285 * The controller should generate 2 frames before 286 * preparing the peripheral. 287 */ 288 static void dw_mipi_dsi_wait_for_two_frames(const struct drm_display_mode *mode) 289 { 290 int refresh, two_frames; 291 292 refresh = drm_mode_vrefresh(mode); 293 two_frames = DIV_ROUND_UP(MSEC_PER_SEC, refresh) * 2; 294 msleep(two_frames); 295 } 296 297 static inline struct dw_mipi_dsi *host_to_dsi(struct mipi_dsi_host *host) 298 { 299 return container_of(host, struct dw_mipi_dsi, dsi_host); 300 } 301 302 static inline struct dw_mipi_dsi *bridge_to_dsi(struct drm_bridge *bridge) 303 { 304 return container_of(bridge, struct dw_mipi_dsi, bridge); 305 } 306 307 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) 308 { 309 writel(val, dsi->base + reg); 310 } 311 312 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) 313 { 314 return readl(dsi->base + reg); 315 } 316 317 static int dw_mipi_dsi_host_attach(struct mipi_dsi_host *host, 318 struct mipi_dsi_device *device) 319 { 320 struct dw_mipi_dsi *dsi = host_to_dsi(host); 321 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 322 struct drm_bridge *bridge; 323 int ret; 324 325 if (device->lanes > dsi->plat_data->max_data_lanes) { 326 dev_err(dsi->dev, "the number of data lanes(%u) is too many\n", 327 device->lanes); 328 return -EINVAL; 329 } 330 331 dsi->lanes = device->lanes; 332 dsi->channel = device->channel; 333 dsi->format = device->format; 334 dsi->mode_flags = device->mode_flags; 335 336 bridge = devm_drm_of_get_bridge(dsi->dev, dsi->dev->of_node, 1, 0); 337 if (IS_ERR(bridge)) 338 return PTR_ERR(bridge); 339 340 bridge->pre_enable_prev_first = true; 341 dsi->panel_bridge = bridge; 342 343 drm_bridge_add(&dsi->bridge); 344 345 if (pdata->host_ops && pdata->host_ops->attach) { 346 ret = pdata->host_ops->attach(pdata->priv_data, device); 347 if (ret < 0) 348 goto err_remove_bridge; 349 } 350 351 return 0; 352 353 err_remove_bridge: 354 drm_bridge_remove(&dsi->bridge); 355 return ret; 356 } 357 358 static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, 359 struct mipi_dsi_device *device) 360 { 361 struct dw_mipi_dsi *dsi = host_to_dsi(host); 362 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 363 int ret; 364 365 if (pdata->host_ops && pdata->host_ops->detach) { 366 ret = pdata->host_ops->detach(pdata->priv_data, device); 367 if (ret < 0) 368 return ret; 369 } 370 371 drm_of_panel_bridge_remove(host->dev->of_node, 1, 0); 372 373 drm_bridge_remove(&dsi->bridge); 374 375 return 0; 376 } 377 378 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, 379 const struct mipi_dsi_msg *msg) 380 { 381 bool lpm = msg->flags & MIPI_DSI_MSG_USE_LPM; 382 u32 val = 0; 383 384 /* 385 * TODO dw drv improvements 386 * largest packet sizes during hfp or during vsa/vpb/vfp 387 * should be computed according to byte lane, lane number and only 388 * if sending lp cmds in high speed is enable (PHY_TXREQUESTCLKHS) 389 */ 390 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(16) 391 | INVACT_LPCMD_TIME(4)); 392 393 if (msg->flags & MIPI_DSI_MSG_REQ_ACK) 394 val |= ACK_RQST_EN; 395 if (lpm) 396 val |= CMD_MODE_ALL_LP; 397 398 dsi_write(dsi, DSI_CMD_MODE_CFG, val); 399 400 val = dsi_read(dsi, DSI_VID_MODE_CFG); 401 if (lpm) 402 val |= ENABLE_LOW_POWER_CMD; 403 else 404 val &= ~ENABLE_LOW_POWER_CMD; 405 dsi_write(dsi, DSI_VID_MODE_CFG, val); 406 } 407 408 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) 409 { 410 int ret; 411 u32 val, mask; 412 413 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 414 val, !(val & GEN_CMD_FULL), 1000, 415 CMD_PKT_STATUS_TIMEOUT_US); 416 if (ret) { 417 dev_err(dsi->dev, "failed to get available command FIFO\n"); 418 return ret; 419 } 420 421 dsi_write(dsi, DSI_GEN_HDR, hdr_val); 422 423 mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; 424 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 425 val, (val & mask) == mask, 426 1000, CMD_PKT_STATUS_TIMEOUT_US); 427 if (ret) { 428 dev_err(dsi->dev, "failed to write command FIFO\n"); 429 return ret; 430 } 431 432 return 0; 433 } 434 435 static int dw_mipi_dsi_write(struct dw_mipi_dsi *dsi, 436 const struct mipi_dsi_packet *packet) 437 { 438 const u8 *tx_buf = packet->payload; 439 int len = packet->payload_length, pld_data_bytes = sizeof(u32), ret; 440 __le32 word; 441 u32 val; 442 443 while (len) { 444 if (len < pld_data_bytes) { 445 word = 0; 446 memcpy(&word, tx_buf, len); 447 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 448 len = 0; 449 } else { 450 memcpy(&word, tx_buf, pld_data_bytes); 451 dsi_write(dsi, DSI_GEN_PLD_DATA, le32_to_cpu(word)); 452 tx_buf += pld_data_bytes; 453 len -= pld_data_bytes; 454 } 455 456 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 457 val, !(val & GEN_PLD_W_FULL), 1000, 458 CMD_PKT_STATUS_TIMEOUT_US); 459 if (ret) { 460 dev_err(dsi->dev, 461 "failed to get available write payload FIFO\n"); 462 return ret; 463 } 464 } 465 466 word = 0; 467 memcpy(&word, packet->header, sizeof(packet->header)); 468 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, le32_to_cpu(word)); 469 } 470 471 static int dw_mipi_dsi_read(struct dw_mipi_dsi *dsi, 472 const struct mipi_dsi_msg *msg) 473 { 474 int i, j, ret, len = msg->rx_len; 475 u8 *buf = msg->rx_buf; 476 u32 val; 477 478 /* Wait end of the read operation */ 479 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 480 val, !(val & GEN_RD_CMD_BUSY), 481 1000, CMD_PKT_STATUS_TIMEOUT_US); 482 if (ret) { 483 dev_err(dsi->dev, "Timeout during read operation\n"); 484 return ret; 485 } 486 487 for (i = 0; i < len; i += 4) { 488 /* Read fifo must not be empty before all bytes are read */ 489 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, 490 val, !(val & GEN_PLD_R_EMPTY), 491 1000, CMD_PKT_STATUS_TIMEOUT_US); 492 if (ret) { 493 dev_err(dsi->dev, "Read payload FIFO is empty\n"); 494 return ret; 495 } 496 497 val = dsi_read(dsi, DSI_GEN_PLD_DATA); 498 for (j = 0; j < 4 && j + i < len; j++) 499 buf[i + j] = val >> (8 * j); 500 } 501 502 return ret; 503 } 504 505 static ssize_t dw_mipi_dsi_host_transfer(struct mipi_dsi_host *host, 506 const struct mipi_dsi_msg *msg) 507 { 508 struct dw_mipi_dsi *dsi = host_to_dsi(host); 509 struct mipi_dsi_packet packet; 510 int ret, nb_bytes; 511 512 ret = mipi_dsi_create_packet(&packet, msg); 513 if (ret) { 514 dev_err(dsi->dev, "failed to create packet: %d\n", ret); 515 return ret; 516 } 517 518 dw_mipi_message_config(dsi, msg); 519 if (dsi->slave) 520 dw_mipi_message_config(dsi->slave, msg); 521 522 ret = dw_mipi_dsi_write(dsi, &packet); 523 if (ret) 524 return ret; 525 if (dsi->slave) { 526 ret = dw_mipi_dsi_write(dsi->slave, &packet); 527 if (ret) 528 return ret; 529 } 530 531 if (msg->rx_buf && msg->rx_len) { 532 ret = dw_mipi_dsi_read(dsi, msg); 533 if (ret) 534 return ret; 535 nb_bytes = msg->rx_len; 536 } else { 537 nb_bytes = packet.size; 538 } 539 540 return nb_bytes; 541 } 542 543 static const struct mipi_dsi_host_ops dw_mipi_dsi_host_ops = { 544 .attach = dw_mipi_dsi_host_attach, 545 .detach = dw_mipi_dsi_host_detach, 546 .transfer = dw_mipi_dsi_host_transfer, 547 }; 548 549 static u32 * 550 dw_mipi_dsi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 551 struct drm_bridge_state *bridge_state, 552 struct drm_crtc_state *crtc_state, 553 struct drm_connector_state *conn_state, 554 u32 output_fmt, 555 unsigned int *num_input_fmts) 556 { 557 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 558 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 559 u32 *input_fmts; 560 561 if (pdata->get_input_bus_fmts) 562 return pdata->get_input_bus_fmts(pdata->priv_data, 563 bridge, bridge_state, 564 crtc_state, conn_state, 565 output_fmt, num_input_fmts); 566 567 /* Fall back to MEDIA_BUS_FMT_FIXED as the only input format. */ 568 input_fmts = kmalloc_obj(*input_fmts); 569 if (!input_fmts) 570 return NULL; 571 input_fmts[0] = MEDIA_BUS_FMT_FIXED; 572 *num_input_fmts = 1; 573 574 return input_fmts; 575 } 576 577 static int dw_mipi_dsi_bridge_atomic_check(struct drm_bridge *bridge, 578 struct drm_bridge_state *bridge_state, 579 struct drm_crtc_state *crtc_state, 580 struct drm_connector_state *conn_state) 581 { 582 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 583 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 584 bool ret; 585 586 bridge_state->input_bus_cfg.flags = 587 DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE; 588 589 if (pdata->mode_fixup) { 590 ret = pdata->mode_fixup(pdata->priv_data, &crtc_state->mode, 591 &crtc_state->adjusted_mode); 592 if (!ret) { 593 DRM_DEBUG_DRIVER("failed to fixup mode " DRM_MODE_FMT "\n", 594 DRM_MODE_ARG(&crtc_state->mode)); 595 return -EINVAL; 596 } 597 } 598 599 return 0; 600 } 601 602 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) 603 { 604 u32 val; 605 606 /* 607 * TODO dw drv improvements 608 * enabling low power is panel-dependent, we should use the 609 * panel configuration here... 610 */ 611 val = ENABLE_LOW_POWER; 612 613 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 614 val |= VID_MODE_TYPE_BURST; 615 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 616 val |= VID_MODE_TYPE_NON_BURST_SYNC_PULSES; 617 else 618 val |= VID_MODE_TYPE_NON_BURST_SYNC_EVENTS; 619 620 #ifdef CONFIG_DEBUG_FS 621 if (dsi->vpg_defs.vpg) { 622 val |= VID_MODE_VPG_ENABLE; 623 val |= dsi->vpg_defs.vpg_horizontal ? 624 VID_MODE_VPG_HORIZONTAL : 0; 625 val |= dsi->vpg_defs.vpg_ber_pattern ? VID_MODE_VPG_MODE : 0; 626 } 627 #endif /* CONFIG_DEBUG_FS */ 628 629 dsi_write(dsi, DSI_VID_MODE_CFG, val); 630 } 631 632 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, 633 unsigned long mode_flags) 634 { 635 u32 val; 636 637 dsi_write(dsi, DSI_PWR_UP, RESET); 638 639 if (mode_flags & MIPI_DSI_MODE_VIDEO) { 640 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); 641 dw_mipi_dsi_video_mode_config(dsi); 642 } else { 643 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 644 } 645 646 val = PHY_TXREQUESTCLKHS; 647 if (dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 648 val |= AUTO_CLKLANE_CTRL; 649 dsi_write(dsi, DSI_LPCLK_CTRL, val); 650 651 dsi_write(dsi, DSI_PWR_UP, POWERUP); 652 } 653 654 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) 655 { 656 dsi_write(dsi, DSI_PWR_UP, RESET); 657 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); 658 } 659 660 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) 661 { 662 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 663 unsigned int esc_rate; /* in MHz */ 664 u32 esc_clk_division; 665 int ret; 666 667 /* 668 * The maximum permitted escape clock is 20MHz and it is derived from 669 * lanebyteclk, which is running at "lane_mbps / 8". 670 */ 671 if (phy_ops->get_esc_clk_rate) { 672 ret = phy_ops->get_esc_clk_rate(dsi->plat_data->priv_data, 673 &esc_rate); 674 if (ret) 675 DRM_DEBUG_DRIVER("Phy get_esc_clk_rate() failed\n"); 676 } else 677 esc_rate = 20; /* Default to 20MHz */ 678 679 /* 680 * We want : 681 * (lane_mbps >> 3) / esc_clk_division < X 682 * which is: 683 * (lane_mbps >> 3) / X > esc_clk_division 684 */ 685 esc_clk_division = (dsi->lane_mbps >> 3) / esc_rate + 1; 686 687 dsi_write(dsi, DSI_PWR_UP, RESET); 688 689 /* 690 * TODO dw drv improvements 691 * timeout clock division should be computed with the 692 * high speed transmission counter timeout and byte lane... 693 */ 694 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVISION(0) | 695 TX_ESC_CLK_DIVISION(esc_clk_division)); 696 } 697 698 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, 699 const struct drm_display_mode *mode) 700 { 701 u32 val = 0, color = 0; 702 703 switch (dsi->format) { 704 case MIPI_DSI_FMT_RGB888: 705 color = DPI_COLOR_CODING_24BIT; 706 break; 707 case MIPI_DSI_FMT_RGB666: 708 color = DPI_COLOR_CODING_18BIT_2 | LOOSELY18_EN; 709 break; 710 case MIPI_DSI_FMT_RGB666_PACKED: 711 color = DPI_COLOR_CODING_18BIT_1; 712 break; 713 case MIPI_DSI_FMT_RGB565: 714 color = DPI_COLOR_CODING_16BIT_1; 715 break; 716 } 717 718 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 719 val |= VSYNC_ACTIVE_LOW; 720 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 721 val |= HSYNC_ACTIVE_LOW; 722 723 dsi_write(dsi, DSI_DPI_VCID, DPI_VCID(dsi->channel)); 724 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); 725 dsi_write(dsi, DSI_DPI_CFG_POL, val); 726 } 727 728 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) 729 { 730 u32 val = CRC_RX_EN | ECC_RX_EN | BTA_EN | EOTP_TX_EN; 731 732 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 733 val &= ~EOTP_TX_EN; 734 735 dsi_write(dsi, DSI_PCKHDL_CFG, val); 736 } 737 738 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, 739 const struct drm_display_mode *mode) 740 { 741 /* 742 * TODO dw drv improvements 743 * only burst mode is supported here. For non-burst video modes, 744 * we should compute DSI_VID_PKT_SIZE, DSI_VCCR.NUMC & 745 * DSI_VNPCR.NPSIZE... especially because this driver supports 746 * non-burst video modes, see dw_mipi_dsi_video_mode_config()... 747 */ 748 749 dsi_write(dsi, DSI_VID_PKT_SIZE, 750 dw_mipi_is_dual_mode(dsi) ? 751 VID_PKT_SIZE(mode->hdisplay / 2) : 752 VID_PKT_SIZE(mode->hdisplay)); 753 } 754 755 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) 756 { 757 /* 758 * TODO dw drv improvements 759 * compute high speed transmission counter timeout according 760 * to the timeout clock division (TO_CLK_DIVISION) and byte lane... 761 */ 762 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(0) | LPRX_TO_CNT(0)); 763 /* 764 * TODO dw drv improvements 765 * the Bus-Turn-Around Timeout Counter should be computed 766 * according to byte lane... 767 */ 768 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); 769 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); 770 } 771 772 static const u32 minimum_lbccs[] = {10, 5, 4, 3}; 773 774 static inline u32 dw_mipi_dsi_get_minimum_lbcc(struct dw_mipi_dsi *dsi) 775 { 776 return minimum_lbccs[dsi->lanes - 1]; 777 } 778 779 /* Get lane byte clock cycles. */ 780 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, 781 const struct drm_display_mode *mode, 782 u32 hcomponent) 783 { 784 u32 frac, lbcc, minimum_lbcc; 785 int bpp; 786 787 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 788 /* lbcc based on lane_mbps */ 789 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; 790 } else { 791 /* lbcc based on pixel clock rate */ 792 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 793 if (bpp < 0) { 794 dev_err(dsi->dev, "failed to get bpp\n"); 795 return 0; 796 } 797 798 lbcc = div_u64((u64)hcomponent * mode->clock * bpp, dsi->lanes * 8); 799 } 800 801 frac = lbcc % mode->clock; 802 lbcc = lbcc / mode->clock; 803 if (frac) 804 lbcc++; 805 806 minimum_lbcc = dw_mipi_dsi_get_minimum_lbcc(dsi); 807 808 if (lbcc < minimum_lbcc) 809 lbcc = minimum_lbcc; 810 811 return lbcc; 812 } 813 814 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, 815 const struct drm_display_mode *mode) 816 { 817 u32 htotal, hsa, hbp, lbcc; 818 819 htotal = mode->htotal; 820 hsa = mode->hsync_end - mode->hsync_start; 821 hbp = mode->htotal - mode->hsync_end; 822 823 /* 824 * TODO dw drv improvements 825 * computations below may be improved... 826 */ 827 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal); 828 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); 829 830 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); 831 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); 832 833 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); 834 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); 835 } 836 837 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, 838 const struct drm_display_mode *mode) 839 { 840 u32 vactive, vsa, vfp, vbp; 841 842 vactive = mode->vdisplay; 843 vsa = mode->vsync_end - mode->vsync_start; 844 vfp = mode->vsync_start - mode->vdisplay; 845 vbp = mode->vtotal - mode->vsync_end; 846 847 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); 848 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); 849 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); 850 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); 851 } 852 853 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) 854 { 855 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 856 struct dw_mipi_dsi_dphy_timing timing; 857 u32 hw_version; 858 int ret; 859 860 ret = phy_ops->get_timing(dsi->plat_data->priv_data, 861 dsi->lane_mbps, &timing); 862 if (ret) 863 DRM_DEV_ERROR(dsi->dev, "Retrieving phy timings failed\n"); 864 865 /* 866 * TODO dw drv improvements 867 * data & clock lane timers should be computed according to panel 868 * blankings and to the automatic clock lane control mode... 869 * note: DSI_PHY_TMR_CFG.MAX_RD_TIME should be in line with 870 * DSI_CMD_MODE_CFG.MAX_RD_PKT_SIZE_LP (see CMD_MODE_ALL_LP) 871 */ 872 873 hw_version = dsi_read(dsi, DSI_VERSION) & VERSION; 874 875 if (hw_version >= HWVER_131) { 876 dsi_write(dsi, DSI_PHY_TMR_CFG, 877 PHY_HS2LP_TIME_V131(timing.data_hs2lp) | 878 PHY_LP2HS_TIME_V131(timing.data_lp2hs)); 879 dsi_write(dsi, DSI_PHY_TMR_RD_CFG, MAX_RD_TIME_V131(10000)); 880 } else { 881 dsi_write(dsi, DSI_PHY_TMR_CFG, 882 PHY_HS2LP_TIME(timing.data_hs2lp) | 883 PHY_LP2HS_TIME(timing.data_lp2hs) | 884 MAX_RD_TIME(10000)); 885 } 886 887 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, 888 PHY_CLKHS2LP_TIME(timing.clk_hs2lp) | 889 PHY_CLKLP2HS_TIME(timing.clk_lp2hs)); 890 } 891 892 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) 893 { 894 /* 895 * TODO dw drv improvements 896 * stop wait time should be the maximum between host dsi 897 * and panel stop wait times 898 */ 899 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | 900 N_LANES(dsi->lanes)); 901 } 902 903 static void dw_mipi_dsi_dphy_init(struct dw_mipi_dsi *dsi) 904 { 905 /* Clear PHY state */ 906 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK 907 | PHY_RSTZ | PHY_SHUTDOWNZ); 908 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 909 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); 910 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); 911 } 912 913 static void dw_mipi_dsi_dphy_enable(struct dw_mipi_dsi *dsi) 914 { 915 u32 val; 916 int ret; 917 918 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | 919 PHY_UNRSTZ | PHY_UNSHUTDOWNZ); 920 921 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, val, 922 val & PHY_LOCK, 1000, PHY_STATUS_TIMEOUT_US); 923 if (ret) 924 DRM_DEBUG_DRIVER("failed to wait phy lock state\n"); 925 926 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, 927 val, val & PHY_STOP_STATE_CLK_LANE, 1000, 928 PHY_STATUS_TIMEOUT_US); 929 if (ret) 930 DRM_DEBUG_DRIVER("failed to wait phy clk lane stop state\n"); 931 } 932 933 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) 934 { 935 dsi_read(dsi, DSI_INT_ST0); 936 dsi_read(dsi, DSI_INT_ST1); 937 dsi_write(dsi, DSI_INT_MSK0, 0); 938 dsi_write(dsi, DSI_INT_MSK1, 0); 939 } 940 941 static void dw_mipi_dsi_bridge_post_atomic_disable(struct drm_bridge *bridge, 942 struct drm_atomic_state *state) 943 { 944 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 945 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 946 947 /* 948 * Switch to command mode before panel-bridge post_disable & 949 * panel unprepare. 950 * Note: panel-bridge disable & panel disable has been called 951 * before by the drm framework. 952 */ 953 dw_mipi_dsi_set_mode(dsi, 0); 954 955 if (phy_ops->power_off) 956 phy_ops->power_off(dsi->plat_data->priv_data); 957 958 if (dsi->slave) { 959 dw_mipi_dsi_disable(dsi->slave); 960 clk_disable_unprepare(dsi->slave->pclk); 961 pm_runtime_put(dsi->slave->dev); 962 } 963 dw_mipi_dsi_disable(dsi); 964 965 clk_disable_unprepare(dsi->pclk); 966 pm_runtime_put(dsi->dev); 967 } 968 969 static unsigned int dw_mipi_dsi_get_lanes(struct dw_mipi_dsi *dsi) 970 { 971 /* this instance is the slave, so add the master's lanes */ 972 if (dsi->master) 973 return dsi->master->lanes + dsi->lanes; 974 975 /* this instance is the master, so add the slave's lanes */ 976 if (dsi->slave) 977 return dsi->lanes + dsi->slave->lanes; 978 979 /* single-dsi, so no other instance to consider */ 980 return dsi->lanes; 981 } 982 983 static void dw_mipi_dsi_mode_set(struct dw_mipi_dsi *dsi, 984 const struct drm_display_mode *adjusted_mode) 985 { 986 const struct dw_mipi_dsi_phy_ops *phy_ops = dsi->plat_data->phy_ops; 987 void *priv_data = dsi->plat_data->priv_data; 988 int ret; 989 u32 lanes = dw_mipi_dsi_get_lanes(dsi); 990 991 clk_prepare_enable(dsi->pclk); 992 993 ret = phy_ops->get_lane_mbps(priv_data, adjusted_mode, dsi->mode_flags, 994 lanes, dsi->format, &dsi->lane_mbps); 995 if (ret) 996 DRM_DEBUG_DRIVER("Phy get_lane_mbps() failed\n"); 997 998 pm_runtime_get_sync(dsi->dev); 999 dw_mipi_dsi_init(dsi); 1000 dw_mipi_dsi_dpi_config(dsi, adjusted_mode); 1001 dw_mipi_dsi_packet_handler_config(dsi); 1002 dw_mipi_dsi_video_mode_config(dsi); 1003 dw_mipi_dsi_video_packet_config(dsi, adjusted_mode); 1004 dw_mipi_dsi_command_mode_config(dsi); 1005 dw_mipi_dsi_line_timer_config(dsi, adjusted_mode); 1006 dw_mipi_dsi_vertical_timing_config(dsi, adjusted_mode); 1007 1008 dw_mipi_dsi_dphy_init(dsi); 1009 dw_mipi_dsi_dphy_timing_config(dsi); 1010 dw_mipi_dsi_dphy_interface_config(dsi); 1011 1012 dw_mipi_dsi_clear_err(dsi); 1013 1014 ret = phy_ops->init(priv_data); 1015 if (ret) 1016 DRM_DEBUG_DRIVER("Phy init() failed\n"); 1017 1018 dw_mipi_dsi_dphy_enable(dsi); 1019 1020 dw_mipi_dsi_wait_for_two_frames(adjusted_mode); 1021 1022 /* Switch to cmd mode for panel-bridge pre_enable & panel prepare */ 1023 dw_mipi_dsi_set_mode(dsi, 0); 1024 1025 if (phy_ops->power_on) 1026 phy_ops->power_on(dsi->plat_data->priv_data); 1027 } 1028 1029 static void dw_mipi_dsi_bridge_atomic_pre_enable(struct drm_bridge *bridge, 1030 struct drm_atomic_state *state) 1031 { 1032 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 1033 1034 /* Power up the dsi ctl into a command mode */ 1035 dw_mipi_dsi_mode_set(dsi, &dsi->mode); 1036 if (dsi->slave) 1037 dw_mipi_dsi_mode_set(dsi->slave, &dsi->mode); 1038 } 1039 1040 static void dw_mipi_dsi_bridge_mode_set(struct drm_bridge *bridge, 1041 const struct drm_display_mode *mode, 1042 const struct drm_display_mode *adjusted_mode) 1043 { 1044 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 1045 1046 /* Store the display mode for later use in pre_enable callback */ 1047 drm_mode_copy(&dsi->mode, adjusted_mode); 1048 } 1049 1050 static void dw_mipi_dsi_bridge_atomic_enable(struct drm_bridge *bridge, 1051 struct drm_atomic_state *state) 1052 { 1053 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 1054 1055 /* Switch to video mode for panel-bridge enable & panel enable */ 1056 dw_mipi_dsi_set_mode(dsi, MIPI_DSI_MODE_VIDEO); 1057 if (dsi->slave) 1058 dw_mipi_dsi_set_mode(dsi->slave, MIPI_DSI_MODE_VIDEO); 1059 } 1060 1061 static enum drm_mode_status 1062 dw_mipi_dsi_bridge_mode_valid(struct drm_bridge *bridge, 1063 const struct drm_display_info *info, 1064 const struct drm_display_mode *mode) 1065 { 1066 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 1067 const struct dw_mipi_dsi_plat_data *pdata = dsi->plat_data; 1068 enum drm_mode_status mode_status = MODE_OK; 1069 1070 if (pdata->mode_valid) 1071 mode_status = pdata->mode_valid(pdata->priv_data, mode, 1072 dsi->mode_flags, 1073 dw_mipi_dsi_get_lanes(dsi), 1074 dsi->format); 1075 1076 return mode_status; 1077 } 1078 1079 static int dw_mipi_dsi_bridge_attach(struct drm_bridge *bridge, 1080 struct drm_encoder *encoder, 1081 enum drm_bridge_attach_flags flags) 1082 { 1083 struct dw_mipi_dsi *dsi = bridge_to_dsi(bridge); 1084 1085 /* Set the encoder type as caller does not know it */ 1086 encoder->encoder_type = DRM_MODE_ENCODER_DSI; 1087 1088 /* Attach the panel-bridge to the dsi bridge */ 1089 return drm_bridge_attach(encoder, dsi->panel_bridge, bridge, 1090 flags); 1091 } 1092 1093 static const struct drm_bridge_funcs dw_mipi_dsi_bridge_funcs = { 1094 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1095 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1096 .atomic_get_input_bus_fmts = dw_mipi_dsi_bridge_atomic_get_input_bus_fmts, 1097 .atomic_check = dw_mipi_dsi_bridge_atomic_check, 1098 .atomic_reset = drm_atomic_helper_bridge_reset, 1099 .atomic_pre_enable = dw_mipi_dsi_bridge_atomic_pre_enable, 1100 .atomic_enable = dw_mipi_dsi_bridge_atomic_enable, 1101 .atomic_post_disable = dw_mipi_dsi_bridge_post_atomic_disable, 1102 .mode_set = dw_mipi_dsi_bridge_mode_set, 1103 .mode_valid = dw_mipi_dsi_bridge_mode_valid, 1104 .attach = dw_mipi_dsi_bridge_attach, 1105 }; 1106 1107 #ifdef CONFIG_DEBUG_FS 1108 1109 static int dw_mipi_dsi_debugfs_write(void *data, u64 val) 1110 { 1111 struct debugfs_entries *vpg = data; 1112 struct dw_mipi_dsi *dsi; 1113 u32 mode_cfg; 1114 1115 if (!vpg) 1116 return -ENODEV; 1117 1118 dsi = vpg->dsi; 1119 1120 *vpg->reg = (bool)val; 1121 1122 mode_cfg = dsi_read(dsi, DSI_VID_MODE_CFG); 1123 1124 if (*vpg->reg) 1125 mode_cfg |= vpg->mask; 1126 else 1127 mode_cfg &= ~vpg->mask; 1128 1129 dsi_write(dsi, DSI_VID_MODE_CFG, mode_cfg); 1130 1131 return 0; 1132 } 1133 1134 static int dw_mipi_dsi_debugfs_show(void *data, u64 *val) 1135 { 1136 struct debugfs_entries *vpg = data; 1137 1138 if (!vpg) 1139 return -ENODEV; 1140 1141 *val = *vpg->reg; 1142 1143 return 0; 1144 } 1145 1146 DEFINE_DEBUGFS_ATTRIBUTE(fops_x32, dw_mipi_dsi_debugfs_show, 1147 dw_mipi_dsi_debugfs_write, "%llu\n"); 1148 1149 static void debugfs_create_files(void *data) 1150 { 1151 struct dw_mipi_dsi *dsi = data; 1152 struct debugfs_entries debugfs[] = { 1153 REGISTER(vpg, VID_MODE_VPG_ENABLE, dsi), 1154 REGISTER(vpg_horizontal, VID_MODE_VPG_HORIZONTAL, dsi), 1155 REGISTER(vpg_ber_pattern, VID_MODE_VPG_MODE, dsi), 1156 }; 1157 int i; 1158 1159 dsi->debugfs_vpg = kmemdup(debugfs, sizeof(debugfs), GFP_KERNEL); 1160 if (!dsi->debugfs_vpg) 1161 return; 1162 1163 for (i = 0; i < ARRAY_SIZE(debugfs); i++) 1164 debugfs_create_file(dsi->debugfs_vpg[i].name, 0644, 1165 dsi->debugfs, &dsi->debugfs_vpg[i], 1166 &fops_x32); 1167 } 1168 1169 static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) 1170 { 1171 dsi->debugfs = debugfs_create_dir(dev_name(dsi->dev), NULL); 1172 if (IS_ERR(dsi->debugfs)) { 1173 dev_err(dsi->dev, "failed to create debugfs root\n"); 1174 return; 1175 } 1176 1177 debugfs_create_files(dsi); 1178 } 1179 1180 static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) 1181 { 1182 debugfs_remove_recursive(dsi->debugfs); 1183 kfree(dsi->debugfs_vpg); 1184 } 1185 1186 #else 1187 1188 static void dw_mipi_dsi_debugfs_init(struct dw_mipi_dsi *dsi) { } 1189 static void dw_mipi_dsi_debugfs_remove(struct dw_mipi_dsi *dsi) { } 1190 1191 #endif /* CONFIG_DEBUG_FS */ 1192 1193 static struct dw_mipi_dsi * 1194 __dw_mipi_dsi_probe(struct platform_device *pdev, 1195 const struct dw_mipi_dsi_plat_data *plat_data) 1196 { 1197 struct device *dev = &pdev->dev; 1198 struct reset_control *apb_rst; 1199 struct dw_mipi_dsi *dsi; 1200 int ret; 1201 1202 dsi = devm_drm_bridge_alloc(dev, struct dw_mipi_dsi, bridge, 1203 &dw_mipi_dsi_bridge_funcs); 1204 if (IS_ERR(dsi)) 1205 return ERR_CAST(dsi); 1206 1207 dsi->dev = dev; 1208 dsi->plat_data = plat_data; 1209 1210 if (!plat_data->phy_ops->init || !plat_data->phy_ops->get_lane_mbps || 1211 !plat_data->phy_ops->get_timing) { 1212 DRM_ERROR("Phy not properly configured\n"); 1213 return ERR_PTR(-ENODEV); 1214 } 1215 1216 if (!plat_data->base) { 1217 dsi->base = devm_platform_ioremap_resource(pdev, 0); 1218 if (IS_ERR(dsi->base)) 1219 return ERR_PTR(-ENODEV); 1220 1221 } else { 1222 dsi->base = plat_data->base; 1223 } 1224 1225 dsi->pclk = devm_clk_get(dev, "pclk"); 1226 if (IS_ERR(dsi->pclk)) { 1227 ret = PTR_ERR(dsi->pclk); 1228 dev_err(dev, "Unable to get pclk: %d\n", ret); 1229 return ERR_PTR(ret); 1230 } 1231 1232 /* 1233 * Note that the reset was not defined in the initial device tree, so 1234 * we have to be prepared for it not being found. 1235 */ 1236 apb_rst = devm_reset_control_get_optional_exclusive(dev, "apb"); 1237 if (IS_ERR(apb_rst)) { 1238 ret = PTR_ERR(apb_rst); 1239 1240 if (ret != -EPROBE_DEFER) 1241 dev_err(dev, "Unable to get reset control: %d\n", ret); 1242 1243 return ERR_PTR(ret); 1244 } 1245 1246 if (apb_rst) { 1247 ret = clk_prepare_enable(dsi->pclk); 1248 if (ret) { 1249 dev_err(dev, "%s: Failed to enable pclk\n", __func__); 1250 return ERR_PTR(ret); 1251 } 1252 1253 reset_control_assert(apb_rst); 1254 usleep_range(10, 20); 1255 reset_control_deassert(apb_rst); 1256 1257 clk_disable_unprepare(dsi->pclk); 1258 } 1259 1260 dw_mipi_dsi_debugfs_init(dsi); 1261 pm_runtime_enable(dev); 1262 1263 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; 1264 dsi->dsi_host.dev = dev; 1265 ret = mipi_dsi_host_register(&dsi->dsi_host); 1266 if (ret) { 1267 dev_err(dev, "Failed to register MIPI host: %d\n", ret); 1268 pm_runtime_disable(dev); 1269 dw_mipi_dsi_debugfs_remove(dsi); 1270 return ERR_PTR(ret); 1271 } 1272 1273 dsi->bridge.driver_private = dsi; 1274 dsi->bridge.of_node = pdev->dev.of_node; 1275 1276 return dsi; 1277 } 1278 1279 static void __dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 1280 { 1281 mipi_dsi_host_unregister(&dsi->dsi_host); 1282 1283 pm_runtime_disable(dsi->dev); 1284 dw_mipi_dsi_debugfs_remove(dsi); 1285 } 1286 1287 void dw_mipi_dsi_set_slave(struct dw_mipi_dsi *dsi, struct dw_mipi_dsi *slave) 1288 { 1289 /* introduce controllers to each other */ 1290 dsi->slave = slave; 1291 dsi->slave->master = dsi; 1292 1293 /* migrate settings for already attached displays */ 1294 dsi->slave->lanes = dsi->lanes; 1295 dsi->slave->channel = dsi->channel; 1296 dsi->slave->format = dsi->format; 1297 dsi->slave->mode_flags = dsi->mode_flags; 1298 } 1299 EXPORT_SYMBOL_GPL(dw_mipi_dsi_set_slave); 1300 1301 struct drm_bridge *dw_mipi_dsi_get_bridge(struct dw_mipi_dsi *dsi) 1302 { 1303 return &dsi->bridge; 1304 } 1305 EXPORT_SYMBOL_GPL(dw_mipi_dsi_get_bridge); 1306 1307 /* 1308 * Probe/remove API, used from platforms based on the DRM bridge API. 1309 */ 1310 struct dw_mipi_dsi * 1311 dw_mipi_dsi_probe(struct platform_device *pdev, 1312 const struct dw_mipi_dsi_plat_data *plat_data) 1313 { 1314 return __dw_mipi_dsi_probe(pdev, plat_data); 1315 } 1316 EXPORT_SYMBOL_GPL(dw_mipi_dsi_probe); 1317 1318 void dw_mipi_dsi_remove(struct dw_mipi_dsi *dsi) 1319 { 1320 __dw_mipi_dsi_remove(dsi); 1321 } 1322 EXPORT_SYMBOL_GPL(dw_mipi_dsi_remove); 1323 1324 /* 1325 * Bind/unbind API, used from platforms based on the component framework. 1326 */ 1327 int dw_mipi_dsi_bind(struct dw_mipi_dsi *dsi, struct drm_encoder *encoder) 1328 { 1329 return drm_bridge_attach(encoder, &dsi->bridge, NULL, 0); 1330 } 1331 EXPORT_SYMBOL_GPL(dw_mipi_dsi_bind); 1332 1333 void dw_mipi_dsi_unbind(struct dw_mipi_dsi *dsi) 1334 { 1335 } 1336 EXPORT_SYMBOL_GPL(dw_mipi_dsi_unbind); 1337 1338 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>"); 1339 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1340 MODULE_DESCRIPTION("DW MIPI DSI host controller driver"); 1341 MODULE_LICENSE("GPL"); 1342 MODULE_ALIAS("platform:dw-mipi-dsi"); 1343