1 /* 2 * DesignWare High-Definition Multimedia Interface (HDMI) driver 3 * 4 * Copyright (C) 2013-2015 Mentor Graphics Inc. 5 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 6 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 */ 14 #include <linux/module.h> 15 #include <linux/irq.h> 16 #include <linux/delay.h> 17 #include <linux/err.h> 18 #include <linux/clk.h> 19 #include <linux/hdmi.h> 20 #include <linux/mutex.h> 21 #include <linux/of_device.h> 22 #include <linux/regmap.h> 23 #include <linux/spinlock.h> 24 25 #include <drm/drm_of.h> 26 #include <drm/drmP.h> 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_crtc_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_encoder_slave.h> 31 #include <drm/bridge/dw_hdmi.h> 32 33 #include <uapi/linux/media-bus-format.h> 34 #include <uapi/linux/videodev2.h> 35 36 #include "dw-hdmi.h" 37 #include "dw-hdmi-audio.h" 38 39 #define DDC_SEGMENT_ADDR 0x30 40 #define HDMI_EDID_LEN 512 41 42 enum hdmi_datamap { 43 RGB444_8B = 0x01, 44 RGB444_10B = 0x03, 45 RGB444_12B = 0x05, 46 RGB444_16B = 0x07, 47 YCbCr444_8B = 0x09, 48 YCbCr444_10B = 0x0B, 49 YCbCr444_12B = 0x0D, 50 YCbCr444_16B = 0x0F, 51 YCbCr422_8B = 0x16, 52 YCbCr422_10B = 0x14, 53 YCbCr422_12B = 0x12, 54 }; 55 56 static const u16 csc_coeff_default[3][4] = { 57 { 0x2000, 0x0000, 0x0000, 0x0000 }, 58 { 0x0000, 0x2000, 0x0000, 0x0000 }, 59 { 0x0000, 0x0000, 0x2000, 0x0000 } 60 }; 61 62 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 63 { 0x2000, 0x6926, 0x74fd, 0x010e }, 64 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 65 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 66 }; 67 68 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 69 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 70 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 71 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 72 }; 73 74 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 75 { 0x2591, 0x1322, 0x074b, 0x0000 }, 76 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 77 { 0x6acd, 0x7534, 0x2000, 0x0200 } 78 }; 79 80 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 81 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 82 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 83 { 0x6756, 0x78ab, 0x2000, 0x0200 } 84 }; 85 86 struct hdmi_vmode { 87 bool mdataenablepolarity; 88 89 unsigned int mpixelclock; 90 unsigned int mpixelrepetitioninput; 91 unsigned int mpixelrepetitionoutput; 92 }; 93 94 struct hdmi_data_info { 95 unsigned int enc_in_bus_format; 96 unsigned int enc_out_bus_format; 97 unsigned int enc_in_encoding; 98 unsigned int enc_out_encoding; 99 unsigned int pix_repet_factor; 100 unsigned int hdcp_enable; 101 struct hdmi_vmode video_mode; 102 }; 103 104 struct dw_hdmi_i2c { 105 struct i2c_adapter adap; 106 107 struct mutex lock; /* used to serialize data transfers */ 108 struct completion cmp; 109 u8 stat; 110 111 u8 slave_reg; 112 bool is_regaddr; 113 bool is_segment; 114 }; 115 116 struct dw_hdmi_phy_data { 117 enum dw_hdmi_phy_type type; 118 const char *name; 119 unsigned int gen; 120 bool has_svsret; 121 int (*configure)(struct dw_hdmi *hdmi, 122 const struct dw_hdmi_plat_data *pdata, 123 unsigned long mpixelclock); 124 }; 125 126 struct dw_hdmi { 127 struct drm_connector connector; 128 struct drm_bridge bridge; 129 130 unsigned int version; 131 132 struct platform_device *audio; 133 struct device *dev; 134 struct clk *isfr_clk; 135 struct clk *iahb_clk; 136 struct dw_hdmi_i2c *i2c; 137 138 struct hdmi_data_info hdmi_data; 139 const struct dw_hdmi_plat_data *plat_data; 140 141 int vic; 142 143 u8 edid[HDMI_EDID_LEN]; 144 bool cable_plugin; 145 146 struct { 147 const struct dw_hdmi_phy_ops *ops; 148 const char *name; 149 void *data; 150 bool enabled; 151 } phy; 152 153 struct drm_display_mode previous_mode; 154 155 struct i2c_adapter *ddc; 156 void __iomem *regs; 157 bool sink_is_hdmi; 158 bool sink_has_audio; 159 160 struct mutex mutex; /* for state below and previous_mode */ 161 enum drm_connector_force force; /* mutex-protected force state */ 162 bool disabled; /* DRM has disabled our bridge */ 163 bool bridge_is_on; /* indicates the bridge is on */ 164 bool rxsense; /* rxsense state */ 165 u8 phy_mask; /* desired phy int mask settings */ 166 167 spinlock_t audio_lock; 168 struct mutex audio_mutex; 169 unsigned int sample_rate; 170 unsigned int audio_cts; 171 unsigned int audio_n; 172 bool audio_enable; 173 174 unsigned int reg_shift; 175 struct regmap *regm; 176 }; 177 178 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 179 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 180 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 181 182 #define HDMI_PHY_RX_SENSE \ 183 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 184 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 185 186 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 187 { 188 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 189 } 190 191 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 192 { 193 unsigned int val = 0; 194 195 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 196 197 return val; 198 } 199 200 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 201 { 202 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 203 } 204 205 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 206 u8 shift, u8 mask) 207 { 208 hdmi_modb(hdmi, data << shift, mask, reg); 209 } 210 211 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 212 { 213 /* Software reset */ 214 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 215 216 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 217 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 218 219 /* Set done, not acknowledged and arbitration interrupt polarities */ 220 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 221 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 222 HDMI_I2CM_CTLINT); 223 224 /* Clear DONE and ERROR interrupts */ 225 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 226 HDMI_IH_I2CM_STAT0); 227 228 /* Mute DONE and ERROR interrupts */ 229 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 230 HDMI_IH_MUTE_I2CM_STAT0); 231 } 232 233 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 234 unsigned char *buf, unsigned int length) 235 { 236 struct dw_hdmi_i2c *i2c = hdmi->i2c; 237 int stat; 238 239 if (!i2c->is_regaddr) { 240 dev_dbg(hdmi->dev, "set read register address to 0\n"); 241 i2c->slave_reg = 0x00; 242 i2c->is_regaddr = true; 243 } 244 245 while (length--) { 246 reinit_completion(&i2c->cmp); 247 248 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 249 if (i2c->is_segment) 250 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 251 HDMI_I2CM_OPERATION); 252 else 253 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 254 HDMI_I2CM_OPERATION); 255 256 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 257 if (!stat) 258 return -EAGAIN; 259 260 /* Check for error condition on the bus */ 261 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 262 return -EIO; 263 264 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 265 } 266 i2c->is_segment = false; 267 268 return 0; 269 } 270 271 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 272 unsigned char *buf, unsigned int length) 273 { 274 struct dw_hdmi_i2c *i2c = hdmi->i2c; 275 int stat; 276 277 if (!i2c->is_regaddr) { 278 /* Use the first write byte as register address */ 279 i2c->slave_reg = buf[0]; 280 length--; 281 buf++; 282 i2c->is_regaddr = true; 283 } 284 285 while (length--) { 286 reinit_completion(&i2c->cmp); 287 288 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 289 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 290 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 291 HDMI_I2CM_OPERATION); 292 293 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 294 if (!stat) 295 return -EAGAIN; 296 297 /* Check for error condition on the bus */ 298 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 299 return -EIO; 300 } 301 302 return 0; 303 } 304 305 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 306 struct i2c_msg *msgs, int num) 307 { 308 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 309 struct dw_hdmi_i2c *i2c = hdmi->i2c; 310 u8 addr = msgs[0].addr; 311 int i, ret = 0; 312 313 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 314 315 for (i = 0; i < num; i++) { 316 if (msgs[i].len == 0) { 317 dev_dbg(hdmi->dev, 318 "unsupported transfer %d/%d, no data\n", 319 i + 1, num); 320 return -EOPNOTSUPP; 321 } 322 } 323 324 mutex_lock(&i2c->lock); 325 326 /* Unmute DONE and ERROR interrupts */ 327 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 328 329 /* Set slave device address taken from the first I2C message */ 330 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 331 332 /* Set slave device register address on transfer */ 333 i2c->is_regaddr = false; 334 335 /* Set segment pointer for I2C extended read mode operation */ 336 i2c->is_segment = false; 337 338 for (i = 0; i < num; i++) { 339 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 340 i + 1, num, msgs[i].len, msgs[i].flags); 341 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 342 i2c->is_segment = true; 343 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 344 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 345 } else { 346 if (msgs[i].flags & I2C_M_RD) 347 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 348 msgs[i].len); 349 else 350 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 351 msgs[i].len); 352 } 353 if (ret < 0) 354 break; 355 } 356 357 if (!ret) 358 ret = num; 359 360 /* Mute DONE and ERROR interrupts */ 361 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 362 HDMI_IH_MUTE_I2CM_STAT0); 363 364 mutex_unlock(&i2c->lock); 365 366 return ret; 367 } 368 369 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 370 { 371 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 372 } 373 374 static const struct i2c_algorithm dw_hdmi_algorithm = { 375 .master_xfer = dw_hdmi_i2c_xfer, 376 .functionality = dw_hdmi_i2c_func, 377 }; 378 379 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 380 { 381 struct i2c_adapter *adap; 382 struct dw_hdmi_i2c *i2c; 383 int ret; 384 385 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 386 if (!i2c) 387 return ERR_PTR(-ENOMEM); 388 389 mutex_init(&i2c->lock); 390 init_completion(&i2c->cmp); 391 392 adap = &i2c->adap; 393 adap->class = I2C_CLASS_DDC; 394 adap->owner = THIS_MODULE; 395 adap->dev.parent = hdmi->dev; 396 adap->algo = &dw_hdmi_algorithm; 397 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 398 i2c_set_adapdata(adap, hdmi); 399 400 ret = i2c_add_adapter(adap); 401 if (ret) { 402 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 403 devm_kfree(hdmi->dev, i2c); 404 return ERR_PTR(ret); 405 } 406 407 hdmi->i2c = i2c; 408 409 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 410 411 return adap; 412 } 413 414 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 415 unsigned int n) 416 { 417 /* Must be set/cleared first */ 418 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 419 420 /* nshift factor = 0 */ 421 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 422 423 hdmi_writeb(hdmi, ((cts >> 16) & HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 424 HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 425 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 426 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 427 428 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 429 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 430 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 431 } 432 433 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 434 { 435 unsigned int n = (128 * freq) / 1000; 436 unsigned int mult = 1; 437 438 while (freq > 48000) { 439 mult *= 2; 440 freq /= 2; 441 } 442 443 switch (freq) { 444 case 32000: 445 if (pixel_clk == 25175000) 446 n = 4576; 447 else if (pixel_clk == 27027000) 448 n = 4096; 449 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 450 n = 11648; 451 else 452 n = 4096; 453 n *= mult; 454 break; 455 456 case 44100: 457 if (pixel_clk == 25175000) 458 n = 7007; 459 else if (pixel_clk == 74176000) 460 n = 17836; 461 else if (pixel_clk == 148352000) 462 n = 8918; 463 else 464 n = 6272; 465 n *= mult; 466 break; 467 468 case 48000: 469 if (pixel_clk == 25175000) 470 n = 6864; 471 else if (pixel_clk == 27027000) 472 n = 6144; 473 else if (pixel_clk == 74176000) 474 n = 11648; 475 else if (pixel_clk == 148352000) 476 n = 5824; 477 else 478 n = 6144; 479 n *= mult; 480 break; 481 482 default: 483 break; 484 } 485 486 return n; 487 } 488 489 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 490 unsigned long pixel_clk, unsigned int sample_rate) 491 { 492 unsigned long ftdms = pixel_clk; 493 unsigned int n, cts; 494 u64 tmp; 495 496 n = hdmi_compute_n(sample_rate, pixel_clk); 497 498 /* 499 * Compute the CTS value from the N value. Note that CTS and N 500 * can be up to 20 bits in total, so we need 64-bit math. Also 501 * note that our TDMS clock is not fully accurate; it is accurate 502 * to kHz. This can introduce an unnecessary remainder in the 503 * calculation below, so we don't try to warn about that. 504 */ 505 tmp = (u64)ftdms * n; 506 do_div(tmp, 128 * sample_rate); 507 cts = tmp; 508 509 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 510 __func__, sample_rate, ftdms / 1000000, (ftdms / 1000) % 1000, 511 n, cts); 512 513 spin_lock_irq(&hdmi->audio_lock); 514 hdmi->audio_n = n; 515 hdmi->audio_cts = cts; 516 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 517 spin_unlock_irq(&hdmi->audio_lock); 518 } 519 520 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 521 { 522 mutex_lock(&hdmi->audio_mutex); 523 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 524 mutex_unlock(&hdmi->audio_mutex); 525 } 526 527 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 528 { 529 mutex_lock(&hdmi->audio_mutex); 530 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock, 531 hdmi->sample_rate); 532 mutex_unlock(&hdmi->audio_mutex); 533 } 534 535 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 536 { 537 mutex_lock(&hdmi->audio_mutex); 538 hdmi->sample_rate = rate; 539 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mpixelclock, 540 hdmi->sample_rate); 541 mutex_unlock(&hdmi->audio_mutex); 542 } 543 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 544 545 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 546 { 547 unsigned long flags; 548 549 spin_lock_irqsave(&hdmi->audio_lock, flags); 550 hdmi->audio_enable = true; 551 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 552 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 553 } 554 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 555 556 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 557 { 558 unsigned long flags; 559 560 spin_lock_irqsave(&hdmi->audio_lock, flags); 561 hdmi->audio_enable = false; 562 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 563 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 564 } 565 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 566 567 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 568 { 569 switch (bus_format) { 570 case MEDIA_BUS_FMT_RGB888_1X24: 571 case MEDIA_BUS_FMT_RGB101010_1X30: 572 case MEDIA_BUS_FMT_RGB121212_1X36: 573 case MEDIA_BUS_FMT_RGB161616_1X48: 574 return true; 575 576 default: 577 return false; 578 } 579 } 580 581 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 582 { 583 switch (bus_format) { 584 case MEDIA_BUS_FMT_YUV8_1X24: 585 case MEDIA_BUS_FMT_YUV10_1X30: 586 case MEDIA_BUS_FMT_YUV12_1X36: 587 case MEDIA_BUS_FMT_YUV16_1X48: 588 return true; 589 590 default: 591 return false; 592 } 593 } 594 595 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 596 { 597 switch (bus_format) { 598 case MEDIA_BUS_FMT_UYVY8_1X16: 599 case MEDIA_BUS_FMT_UYVY10_1X20: 600 case MEDIA_BUS_FMT_UYVY12_1X24: 601 return true; 602 603 default: 604 return false; 605 } 606 } 607 608 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 609 { 610 switch (bus_format) { 611 case MEDIA_BUS_FMT_RGB888_1X24: 612 case MEDIA_BUS_FMT_YUV8_1X24: 613 case MEDIA_BUS_FMT_UYVY8_1X16: 614 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 615 return 8; 616 617 case MEDIA_BUS_FMT_RGB101010_1X30: 618 case MEDIA_BUS_FMT_YUV10_1X30: 619 case MEDIA_BUS_FMT_UYVY10_1X20: 620 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 621 return 10; 622 623 case MEDIA_BUS_FMT_RGB121212_1X36: 624 case MEDIA_BUS_FMT_YUV12_1X36: 625 case MEDIA_BUS_FMT_UYVY12_1X24: 626 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 627 return 12; 628 629 case MEDIA_BUS_FMT_RGB161616_1X48: 630 case MEDIA_BUS_FMT_YUV16_1X48: 631 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 632 return 16; 633 634 default: 635 return 0; 636 } 637 } 638 639 /* 640 * this submodule is responsible for the video data synchronization. 641 * for example, for RGB 4:4:4 input, the data map is defined as 642 * pin{47~40} <==> R[7:0] 643 * pin{31~24} <==> G[7:0] 644 * pin{15~8} <==> B[7:0] 645 */ 646 static void hdmi_video_sample(struct dw_hdmi *hdmi) 647 { 648 int color_format = 0; 649 u8 val; 650 651 switch (hdmi->hdmi_data.enc_in_bus_format) { 652 case MEDIA_BUS_FMT_RGB888_1X24: 653 color_format = 0x01; 654 break; 655 case MEDIA_BUS_FMT_RGB101010_1X30: 656 color_format = 0x03; 657 break; 658 case MEDIA_BUS_FMT_RGB121212_1X36: 659 color_format = 0x05; 660 break; 661 case MEDIA_BUS_FMT_RGB161616_1X48: 662 color_format = 0x07; 663 break; 664 665 case MEDIA_BUS_FMT_YUV8_1X24: 666 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 667 color_format = 0x09; 668 break; 669 case MEDIA_BUS_FMT_YUV10_1X30: 670 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 671 color_format = 0x0B; 672 break; 673 case MEDIA_BUS_FMT_YUV12_1X36: 674 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 675 color_format = 0x0D; 676 break; 677 case MEDIA_BUS_FMT_YUV16_1X48: 678 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 679 color_format = 0x0F; 680 break; 681 682 case MEDIA_BUS_FMT_UYVY8_1X16: 683 color_format = 0x16; 684 break; 685 case MEDIA_BUS_FMT_UYVY10_1X20: 686 color_format = 0x14; 687 break; 688 case MEDIA_BUS_FMT_UYVY12_1X24: 689 color_format = 0x12; 690 break; 691 692 default: 693 return; 694 } 695 696 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 697 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 698 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 699 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 700 701 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 702 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 703 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 704 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 705 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 706 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 707 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 708 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 709 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 710 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 711 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 712 } 713 714 static int is_color_space_conversion(struct dw_hdmi *hdmi) 715 { 716 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format; 717 } 718 719 static int is_color_space_decimation(struct dw_hdmi *hdmi) 720 { 721 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 722 return 0; 723 724 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 725 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 726 return 1; 727 728 return 0; 729 } 730 731 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 732 { 733 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 734 return 0; 735 736 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 737 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 738 return 1; 739 740 return 0; 741 } 742 743 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 744 { 745 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 746 unsigned i; 747 u32 csc_scale = 1; 748 749 if (is_color_space_conversion(hdmi)) { 750 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 751 if (hdmi->hdmi_data.enc_out_encoding == 752 V4L2_YCBCR_ENC_601) 753 csc_coeff = &csc_coeff_rgb_out_eitu601; 754 else 755 csc_coeff = &csc_coeff_rgb_out_eitu709; 756 } else if (hdmi_bus_fmt_is_rgb( 757 hdmi->hdmi_data.enc_in_bus_format)) { 758 if (hdmi->hdmi_data.enc_out_encoding == 759 V4L2_YCBCR_ENC_601) 760 csc_coeff = &csc_coeff_rgb_in_eitu601; 761 else 762 csc_coeff = &csc_coeff_rgb_in_eitu709; 763 csc_scale = 0; 764 } 765 } 766 767 /* The CSC registers are sequential, alternating MSB then LSB */ 768 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 769 u16 coeff_a = (*csc_coeff)[0][i]; 770 u16 coeff_b = (*csc_coeff)[1][i]; 771 u16 coeff_c = (*csc_coeff)[2][i]; 772 773 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 774 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 775 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 776 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 777 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 778 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 779 } 780 781 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 782 HDMI_CSC_SCALE); 783 } 784 785 static void hdmi_video_csc(struct dw_hdmi *hdmi) 786 { 787 int color_depth = 0; 788 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 789 int decimation = 0; 790 791 /* YCC422 interpolation to 444 mode */ 792 if (is_color_space_interpolation(hdmi)) 793 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 794 else if (is_color_space_decimation(hdmi)) 795 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 796 797 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 798 case 8: 799 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 800 break; 801 case 10: 802 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 803 break; 804 case 12: 805 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 806 break; 807 case 16: 808 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 809 break; 810 811 default: 812 return; 813 } 814 815 /* Configure the CSC registers */ 816 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 817 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 818 HDMI_CSC_SCALE); 819 820 dw_hdmi_update_csc_coeffs(hdmi); 821 } 822 823 /* 824 * HDMI video packetizer is used to packetize the data. 825 * for example, if input is YCC422 mode or repeater is used, 826 * data should be repacked this module can be bypassed. 827 */ 828 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 829 { 830 unsigned int color_depth = 0; 831 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 832 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 833 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 834 u8 val, vp_conf; 835 836 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 837 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) { 838 switch (hdmi_bus_fmt_color_depth( 839 hdmi->hdmi_data.enc_out_bus_format)) { 840 case 8: 841 color_depth = 4; 842 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 843 break; 844 case 10: 845 color_depth = 5; 846 break; 847 case 12: 848 color_depth = 6; 849 break; 850 case 16: 851 color_depth = 7; 852 break; 853 default: 854 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 855 } 856 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 857 switch (hdmi_bus_fmt_color_depth( 858 hdmi->hdmi_data.enc_out_bus_format)) { 859 case 0: 860 case 8: 861 remap_size = HDMI_VP_REMAP_YCC422_16bit; 862 break; 863 case 10: 864 remap_size = HDMI_VP_REMAP_YCC422_20bit; 865 break; 866 case 12: 867 remap_size = HDMI_VP_REMAP_YCC422_24bit; 868 break; 869 870 default: 871 return; 872 } 873 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 874 } else { 875 return; 876 } 877 878 /* set the packetizer registers */ 879 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 880 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 881 ((hdmi_data->pix_repet_factor << 882 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 883 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 884 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 885 886 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 887 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 888 889 /* Data from pixel repeater block */ 890 if (hdmi_data->pix_repet_factor > 1) { 891 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 892 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 893 } else { /* data from packetizer block */ 894 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 895 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 896 } 897 898 hdmi_modb(hdmi, vp_conf, 899 HDMI_VP_CONF_PR_EN_MASK | 900 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 901 902 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 903 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 904 905 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 906 907 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 908 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 909 HDMI_VP_CONF_PP_EN_ENABLE | 910 HDMI_VP_CONF_YCC422_EN_DISABLE; 911 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 912 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 913 HDMI_VP_CONF_PP_EN_DISABLE | 914 HDMI_VP_CONF_YCC422_EN_ENABLE; 915 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 916 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 917 HDMI_VP_CONF_PP_EN_DISABLE | 918 HDMI_VP_CONF_YCC422_EN_DISABLE; 919 } else { 920 return; 921 } 922 923 hdmi_modb(hdmi, vp_conf, 924 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 925 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 926 927 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 928 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 929 HDMI_VP_STUFF_PP_STUFFING_MASK | 930 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 931 932 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 933 HDMI_VP_CONF); 934 } 935 936 /* ----------------------------------------------------------------------------- 937 * Synopsys PHY Handling 938 */ 939 940 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 941 unsigned char bit) 942 { 943 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 944 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 945 } 946 947 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 948 { 949 u32 val; 950 951 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 952 if (msec-- == 0) 953 return false; 954 udelay(1000); 955 } 956 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 957 958 return true; 959 } 960 961 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 962 unsigned char addr) 963 { 964 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 965 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 966 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 967 HDMI_PHY_I2CM_DATAO_1_ADDR); 968 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 969 HDMI_PHY_I2CM_DATAO_0_ADDR); 970 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 971 HDMI_PHY_I2CM_OPERATION_ADDR); 972 hdmi_phy_wait_i2c_done(hdmi, 1000); 973 } 974 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 975 976 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 977 { 978 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 979 HDMI_PHY_CONF0_PDZ_OFFSET, 980 HDMI_PHY_CONF0_PDZ_MASK); 981 } 982 983 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 984 { 985 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 986 HDMI_PHY_CONF0_ENTMDS_OFFSET, 987 HDMI_PHY_CONF0_ENTMDS_MASK); 988 } 989 990 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 991 { 992 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 993 HDMI_PHY_CONF0_SVSRET_OFFSET, 994 HDMI_PHY_CONF0_SVSRET_MASK); 995 } 996 997 static void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 998 { 999 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1000 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1001 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1002 } 1003 1004 static void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1005 { 1006 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1007 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1008 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1009 } 1010 1011 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1012 { 1013 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1014 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1015 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1016 } 1017 1018 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1019 { 1020 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1021 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1022 HDMI_PHY_CONF0_SELDIPIF_MASK); 1023 } 1024 1025 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1026 { 1027 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1028 unsigned int i; 1029 u16 val; 1030 1031 if (phy->gen == 1) { 1032 dw_hdmi_phy_enable_tmds(hdmi, 0); 1033 dw_hdmi_phy_enable_powerdown(hdmi, true); 1034 return; 1035 } 1036 1037 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1038 1039 /* 1040 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1041 * to low power mode. 1042 */ 1043 for (i = 0; i < 5; ++i) { 1044 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1045 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1046 break; 1047 1048 usleep_range(1000, 2000); 1049 } 1050 1051 if (val & HDMI_PHY_TX_PHY_LOCK) 1052 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1053 else 1054 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1055 1056 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1057 } 1058 1059 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1060 { 1061 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1062 unsigned int i; 1063 u8 val; 1064 1065 if (phy->gen == 1) { 1066 dw_hdmi_phy_enable_powerdown(hdmi, false); 1067 1068 /* Toggle TMDS enable. */ 1069 dw_hdmi_phy_enable_tmds(hdmi, 0); 1070 dw_hdmi_phy_enable_tmds(hdmi, 1); 1071 return 0; 1072 } 1073 1074 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1075 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1076 1077 /* Wait for PHY PLL lock */ 1078 for (i = 0; i < 5; ++i) { 1079 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1080 if (val) 1081 break; 1082 1083 usleep_range(1000, 2000); 1084 } 1085 1086 if (!val) { 1087 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1088 return -ETIMEDOUT; 1089 } 1090 1091 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1092 return 0; 1093 } 1094 1095 /* 1096 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1097 * information the DWC MHL PHY has the same register layout and is thus also 1098 * supported by this function. 1099 */ 1100 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1101 const struct dw_hdmi_plat_data *pdata, 1102 unsigned long mpixelclock) 1103 { 1104 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1105 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1106 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1107 1108 /* PLL/MPLL Cfg - always match on final entry */ 1109 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1110 if (mpixelclock <= mpll_config->mpixelclock) 1111 break; 1112 1113 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1114 if (mpixelclock <= curr_ctrl->mpixelclock) 1115 break; 1116 1117 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1118 if (mpixelclock <= phy_config->mpixelclock) 1119 break; 1120 1121 if (mpll_config->mpixelclock == ~0UL || 1122 curr_ctrl->mpixelclock == ~0UL || 1123 phy_config->mpixelclock == ~0UL) 1124 return -EINVAL; 1125 1126 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1127 HDMI_3D_TX_PHY_CPCE_CTRL); 1128 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1129 HDMI_3D_TX_PHY_GMPCTRL); 1130 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1131 HDMI_3D_TX_PHY_CURRCTRL); 1132 1133 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1134 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1135 HDMI_3D_TX_PHY_MSM_CTRL); 1136 1137 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1138 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1139 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1140 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1141 HDMI_3D_TX_PHY_VLEVCTRL); 1142 1143 /* Override and disable clock termination. */ 1144 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1145 HDMI_3D_TX_PHY_CKCALCTRL); 1146 1147 return 0; 1148 } 1149 1150 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 1151 { 1152 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1153 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1154 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1155 int ret; 1156 1157 dw_hdmi_phy_power_off(hdmi); 1158 1159 /* Leave low power consumption mode by asserting SVSRET. */ 1160 if (phy->has_svsret) 1161 dw_hdmi_phy_enable_svsret(hdmi, 1); 1162 1163 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1164 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1165 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1166 1167 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1168 1169 hdmi_phy_test_clear(hdmi, 1); 1170 hdmi_writeb(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2, 1171 HDMI_PHY_I2CM_SLAVE_ADDR); 1172 hdmi_phy_test_clear(hdmi, 0); 1173 1174 /* Write to the PHY as configured by the platform */ 1175 if (pdata->configure_phy) 1176 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 1177 else 1178 ret = phy->configure(hdmi, pdata, mpixelclock); 1179 if (ret) { 1180 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1181 mpixelclock); 1182 return ret; 1183 } 1184 1185 return dw_hdmi_phy_power_on(hdmi); 1186 } 1187 1188 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1189 struct drm_display_mode *mode) 1190 { 1191 int i, ret; 1192 1193 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1194 for (i = 0; i < 2; i++) { 1195 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1196 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1197 1198 ret = hdmi_phy_configure(hdmi); 1199 if (ret) 1200 return ret; 1201 } 1202 1203 return 0; 1204 } 1205 1206 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1207 { 1208 dw_hdmi_phy_power_off(hdmi); 1209 } 1210 1211 static enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1212 void *data) 1213 { 1214 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1215 connector_status_connected : connector_status_disconnected; 1216 } 1217 1218 static void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1219 bool force, bool disabled, bool rxsense) 1220 { 1221 u8 old_mask = hdmi->phy_mask; 1222 1223 if (force || disabled || !rxsense) 1224 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1225 else 1226 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1227 1228 if (old_mask != hdmi->phy_mask) 1229 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1230 } 1231 1232 static void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1233 { 1234 /* 1235 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1236 * any pending interrupt. 1237 */ 1238 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1239 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1240 HDMI_IH_PHY_STAT0); 1241 1242 /* Enable cable hot plug irq. */ 1243 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1244 1245 /* Clear and unmute interrupts. */ 1246 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1247 HDMI_IH_PHY_STAT0); 1248 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1249 HDMI_IH_MUTE_PHY_STAT0); 1250 } 1251 1252 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1253 .init = dw_hdmi_phy_init, 1254 .disable = dw_hdmi_phy_disable, 1255 .read_hpd = dw_hdmi_phy_read_hpd, 1256 .update_hpd = dw_hdmi_phy_update_hpd, 1257 .setup_hpd = dw_hdmi_phy_setup_hpd, 1258 }; 1259 1260 /* ----------------------------------------------------------------------------- 1261 * HDMI TX Setup 1262 */ 1263 1264 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1265 { 1266 u8 de; 1267 1268 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1269 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1270 else 1271 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1272 1273 /* disable rx detect */ 1274 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1275 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1276 1277 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1278 1279 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1280 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1281 } 1282 1283 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1284 { 1285 struct hdmi_avi_infoframe frame; 1286 u8 val; 1287 1288 /* Initialise info frame from DRM mode */ 1289 drm_hdmi_avi_infoframe_from_display_mode(&frame, mode); 1290 1291 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1292 frame.colorspace = HDMI_COLORSPACE_YUV444; 1293 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1294 frame.colorspace = HDMI_COLORSPACE_YUV422; 1295 else 1296 frame.colorspace = HDMI_COLORSPACE_RGB; 1297 1298 /* Set up colorimetry */ 1299 switch (hdmi->hdmi_data.enc_out_encoding) { 1300 case V4L2_YCBCR_ENC_601: 1301 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1302 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1303 else 1304 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1305 frame.extended_colorimetry = 1306 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1307 break; 1308 case V4L2_YCBCR_ENC_709: 1309 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1310 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1311 else 1312 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1313 frame.extended_colorimetry = 1314 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1315 break; 1316 default: /* Carries no data */ 1317 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1318 frame.extended_colorimetry = 1319 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1320 break; 1321 } 1322 1323 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1324 1325 /* 1326 * The Designware IP uses a different byte format from standard 1327 * AVI info frames, though generally the bits are in the correct 1328 * bytes. 1329 */ 1330 1331 /* 1332 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1333 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1334 * bit 6 rather than 4. 1335 */ 1336 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1337 if (frame.active_aspect & 15) 1338 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1339 if (frame.top_bar || frame.bottom_bar) 1340 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1341 if (frame.left_bar || frame.right_bar) 1342 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1343 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1344 1345 /* AVI data byte 2 differences: none */ 1346 val = ((frame.colorimetry & 0x3) << 6) | 1347 ((frame.picture_aspect & 0x3) << 4) | 1348 (frame.active_aspect & 0xf); 1349 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1350 1351 /* AVI data byte 3 differences: none */ 1352 val = ((frame.extended_colorimetry & 0x7) << 4) | 1353 ((frame.quantization_range & 0x3) << 2) | 1354 (frame.nups & 0x3); 1355 if (frame.itc) 1356 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1357 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1358 1359 /* AVI data byte 4 differences: none */ 1360 val = frame.video_code & 0x7f; 1361 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1362 1363 /* AVI Data Byte 5- set up input and output pixel repetition */ 1364 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1365 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1366 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1367 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1368 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1369 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1370 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1371 1372 /* 1373 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1374 * ycc range in bits 2,3 rather than 6,7 1375 */ 1376 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1377 (frame.content_type & 0x3); 1378 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1379 1380 /* AVI Data Bytes 6-13 */ 1381 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1382 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1383 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1384 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1385 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1386 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1387 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1388 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1389 } 1390 1391 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1392 struct drm_display_mode *mode) 1393 { 1394 struct hdmi_vendor_infoframe frame; 1395 u8 buffer[10]; 1396 ssize_t err; 1397 1398 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, mode); 1399 if (err < 0) 1400 /* 1401 * Going into that statement does not means vendor infoframe 1402 * fails. It just informed us that vendor infoframe is not 1403 * needed for the selected mode. Only 4k or stereoscopic 3D 1404 * mode requires vendor infoframe. So just simply return. 1405 */ 1406 return; 1407 1408 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1409 if (err < 0) { 1410 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1411 err); 1412 return; 1413 } 1414 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1415 HDMI_FC_DATAUTO0_VSD_MASK); 1416 1417 /* Set the length of HDMI vendor specific InfoFrame payload */ 1418 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1419 1420 /* Set 24bit IEEE Registration Identifier */ 1421 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1422 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1423 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1424 1425 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1426 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1427 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1428 1429 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1430 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1431 1432 /* Packet frame interpolation */ 1433 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1434 1435 /* Auto packets per frame and line spacing */ 1436 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1437 1438 /* Configures the Frame Composer On RDRB mode */ 1439 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1440 HDMI_FC_DATAUTO0_VSD_MASK); 1441 } 1442 1443 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1444 const struct drm_display_mode *mode) 1445 { 1446 u8 inv_val; 1447 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1448 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1449 unsigned int vdisplay; 1450 1451 vmode->mpixelclock = mode->clock * 1000; 1452 1453 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1454 1455 /* Set up HDMI_FC_INVIDCONF */ 1456 inv_val = (hdmi->hdmi_data.hdcp_enable ? 1457 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1458 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1459 1460 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1461 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1462 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1463 1464 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1465 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1466 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1467 1468 inv_val |= (vmode->mdataenablepolarity ? 1469 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1470 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1471 1472 if (hdmi->vic == 39) 1473 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1474 else 1475 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1476 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1477 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1478 1479 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1480 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1481 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1482 1483 inv_val |= hdmi->sink_is_hdmi ? 1484 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1485 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1486 1487 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1488 1489 vdisplay = mode->vdisplay; 1490 vblank = mode->vtotal - mode->vdisplay; 1491 v_de_vs = mode->vsync_start - mode->vdisplay; 1492 vsync_len = mode->vsync_end - mode->vsync_start; 1493 1494 /* 1495 * When we're setting an interlaced mode, we need 1496 * to adjust the vertical timing to suit. 1497 */ 1498 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1499 vdisplay /= 2; 1500 vblank /= 2; 1501 v_de_vs /= 2; 1502 vsync_len /= 2; 1503 } 1504 1505 /* Set up horizontal active pixel width */ 1506 hdmi_writeb(hdmi, mode->hdisplay >> 8, HDMI_FC_INHACTV1); 1507 hdmi_writeb(hdmi, mode->hdisplay, HDMI_FC_INHACTV0); 1508 1509 /* Set up vertical active lines */ 1510 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1511 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1512 1513 /* Set up horizontal blanking pixel region width */ 1514 hblank = mode->htotal - mode->hdisplay; 1515 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1516 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1517 1518 /* Set up vertical blanking pixel region width */ 1519 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1520 1521 /* Set up HSYNC active edge delay width (in pixel clks) */ 1522 h_de_hs = mode->hsync_start - mode->hdisplay; 1523 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1524 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1525 1526 /* Set up VSYNC active edge delay (in lines) */ 1527 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1528 1529 /* Set up HSYNC active pulse width (in pixel clks) */ 1530 hsync_len = mode->hsync_end - mode->hsync_start; 1531 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1532 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1533 1534 /* Set up VSYNC active edge delay (in lines) */ 1535 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1536 } 1537 1538 /* HDMI Initialization Step B.4 */ 1539 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1540 { 1541 u8 clkdis; 1542 1543 /* control period minimum duration */ 1544 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1545 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1546 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1547 1548 /* Set to fill TMDS data channels */ 1549 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1550 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1551 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1552 1553 /* Enable pixel clock and tmds data path */ 1554 clkdis = 0x7F; 1555 clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1556 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1557 1558 clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1559 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1560 1561 /* Enable csc path */ 1562 if (is_color_space_conversion(hdmi)) { 1563 clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1564 hdmi_writeb(hdmi, clkdis, HDMI_MC_CLKDIS); 1565 } 1566 1567 /* Enable color space conversion if needed */ 1568 if (is_color_space_conversion(hdmi)) 1569 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1570 HDMI_MC_FLOWCTRL); 1571 else 1572 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1573 HDMI_MC_FLOWCTRL); 1574 } 1575 1576 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi) 1577 { 1578 hdmi_modb(hdmi, 0, HDMI_MC_CLKDIS_AUDCLK_DISABLE, HDMI_MC_CLKDIS); 1579 } 1580 1581 /* Workaround to clear the overflow condition */ 1582 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1583 { 1584 unsigned int count; 1585 unsigned int i; 1586 u8 val; 1587 1588 /* 1589 * Under some circumstances the Frame Composer arithmetic unit can miss 1590 * an FC register write due to being busy processing the previous one. 1591 * The issue can be worked around by issuing a TMDS software reset and 1592 * then write one of the FC registers several times. 1593 * 1594 * The number of iterations matters and depends on the HDMI TX revision 1595 * (and possibly on the platform). So far only i.MX6Q (v1.30a) and 1596 * i.MX6DL (v1.31a) have been identified as needing the workaround, with 1597 * 4 and 1 iterations respectively. 1598 */ 1599 1600 switch (hdmi->version) { 1601 case 0x130a: 1602 count = 4; 1603 break; 1604 case 0x131a: 1605 count = 1; 1606 break; 1607 default: 1608 return; 1609 } 1610 1611 /* TMDS software reset */ 1612 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1613 1614 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1615 for (i = 0; i < count; i++) 1616 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1617 } 1618 1619 static void hdmi_enable_overflow_interrupts(struct dw_hdmi *hdmi) 1620 { 1621 hdmi_writeb(hdmi, 0, HDMI_FC_MASK2); 1622 hdmi_writeb(hdmi, 0, HDMI_IH_MUTE_FC_STAT2); 1623 } 1624 1625 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1626 { 1627 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1628 HDMI_IH_MUTE_FC_STAT2); 1629 } 1630 1631 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1632 { 1633 int ret; 1634 1635 hdmi_disable_overflow_interrupts(hdmi); 1636 1637 hdmi->vic = drm_match_cea_mode(mode); 1638 1639 if (!hdmi->vic) { 1640 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 1641 } else { 1642 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 1643 } 1644 1645 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 1646 (hdmi->vic == 21) || (hdmi->vic == 22) || 1647 (hdmi->vic == 2) || (hdmi->vic == 3) || 1648 (hdmi->vic == 17) || (hdmi->vic == 18)) 1649 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 1650 else 1651 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 1652 1653 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 1654 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 1655 1656 /* TOFIX: Get input format from plat data or fallback to RGB888 */ 1657 if (hdmi->plat_data->input_bus_format) 1658 hdmi->hdmi_data.enc_in_bus_format = 1659 hdmi->plat_data->input_bus_format; 1660 else 1661 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1662 1663 /* TOFIX: Get input encoding from plat data or fallback to none */ 1664 if (hdmi->plat_data->input_bus_encoding) 1665 hdmi->hdmi_data.enc_in_encoding = 1666 hdmi->plat_data->input_bus_encoding; 1667 else 1668 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 1669 1670 /* TOFIX: Default to RGB888 output format */ 1671 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1672 1673 hdmi->hdmi_data.pix_repet_factor = 0; 1674 hdmi->hdmi_data.hdcp_enable = 0; 1675 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 1676 1677 /* HDMI Initialization Step B.1 */ 1678 hdmi_av_composer(hdmi, mode); 1679 1680 /* HDMI Initializateion Step B.2 */ 1681 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); 1682 if (ret) 1683 return ret; 1684 hdmi->phy.enabled = true; 1685 1686 /* HDMI Initialization Step B.3 */ 1687 dw_hdmi_enable_video_path(hdmi); 1688 1689 if (hdmi->sink_has_audio) { 1690 dev_dbg(hdmi->dev, "sink has audio support\n"); 1691 1692 /* HDMI Initialization Step E - Configure audio */ 1693 hdmi_clk_regenerator_update_pixel_clock(hdmi); 1694 hdmi_enable_audio_clk(hdmi); 1695 } 1696 1697 /* not for DVI mode */ 1698 if (hdmi->sink_is_hdmi) { 1699 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 1700 1701 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 1702 hdmi_config_AVI(hdmi, mode); 1703 hdmi_config_vendor_specific_infoframe(hdmi, mode); 1704 } else { 1705 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 1706 } 1707 1708 hdmi_video_packetize(hdmi); 1709 hdmi_video_csc(hdmi); 1710 hdmi_video_sample(hdmi); 1711 hdmi_tx_hdcp_config(hdmi); 1712 1713 dw_hdmi_clear_overflow(hdmi); 1714 if (hdmi->cable_plugin && hdmi->sink_is_hdmi) 1715 hdmi_enable_overflow_interrupts(hdmi); 1716 1717 return 0; 1718 } 1719 1720 static void dw_hdmi_setup_i2c(struct dw_hdmi *hdmi) 1721 { 1722 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 1723 HDMI_PHY_I2CM_INT_ADDR); 1724 1725 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 1726 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 1727 HDMI_PHY_I2CM_CTLINT_ADDR); 1728 } 1729 1730 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 1731 { 1732 u8 ih_mute; 1733 1734 /* 1735 * Boot up defaults are: 1736 * HDMI_IH_MUTE = 0x03 (disabled) 1737 * HDMI_IH_MUTE_* = 0x00 (enabled) 1738 * 1739 * Disable top level interrupt bits in HDMI block 1740 */ 1741 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 1742 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 1743 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 1744 1745 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 1746 1747 /* by default mask all interrupts */ 1748 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 1749 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 1750 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 1751 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 1752 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 1753 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 1754 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 1755 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 1756 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 1757 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 1758 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 1759 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 1760 hdmi_writeb(hdmi, 0xff, HDMI_CEC_MASK); 1761 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 1762 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 1763 1764 /* Disable interrupts in the IH_MUTE_* registers */ 1765 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 1766 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 1767 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 1768 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 1769 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 1770 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 1771 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 1772 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 1773 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 1774 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 1775 1776 /* Enable top level interrupt bits in HDMI block */ 1777 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 1778 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 1779 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 1780 } 1781 1782 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 1783 { 1784 hdmi->bridge_is_on = true; 1785 dw_hdmi_setup(hdmi, &hdmi->previous_mode); 1786 } 1787 1788 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 1789 { 1790 if (hdmi->phy.enabled) { 1791 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 1792 hdmi->phy.enabled = false; 1793 } 1794 1795 hdmi->bridge_is_on = false; 1796 } 1797 1798 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 1799 { 1800 int force = hdmi->force; 1801 1802 if (hdmi->disabled) { 1803 force = DRM_FORCE_OFF; 1804 } else if (force == DRM_FORCE_UNSPECIFIED) { 1805 if (hdmi->rxsense) 1806 force = DRM_FORCE_ON; 1807 else 1808 force = DRM_FORCE_OFF; 1809 } 1810 1811 if (force == DRM_FORCE_OFF) { 1812 if (hdmi->bridge_is_on) 1813 dw_hdmi_poweroff(hdmi); 1814 } else { 1815 if (!hdmi->bridge_is_on) 1816 dw_hdmi_poweron(hdmi); 1817 } 1818 } 1819 1820 /* 1821 * Adjust the detection of RXSENSE according to whether we have a forced 1822 * connection mode enabled, or whether we have been disabled. There is 1823 * no point processing RXSENSE interrupts if we have a forced connection 1824 * state, or DRM has us disabled. 1825 * 1826 * We also disable rxsense interrupts when we think we're disconnected 1827 * to avoid floating TDMS signals giving false rxsense interrupts. 1828 * 1829 * Note: we still need to listen for HPD interrupts even when DRM has us 1830 * disabled so that we can detect a connect event. 1831 */ 1832 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 1833 { 1834 if (hdmi->phy.ops->update_hpd) 1835 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 1836 hdmi->force, hdmi->disabled, 1837 hdmi->rxsense); 1838 } 1839 1840 static enum drm_connector_status 1841 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 1842 { 1843 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 1844 connector); 1845 1846 mutex_lock(&hdmi->mutex); 1847 hdmi->force = DRM_FORCE_UNSPECIFIED; 1848 dw_hdmi_update_power(hdmi); 1849 dw_hdmi_update_phy_mask(hdmi); 1850 mutex_unlock(&hdmi->mutex); 1851 1852 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 1853 } 1854 1855 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 1856 { 1857 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 1858 connector); 1859 struct edid *edid; 1860 int ret = 0; 1861 1862 if (!hdmi->ddc) 1863 return 0; 1864 1865 edid = drm_get_edid(connector, hdmi->ddc); 1866 if (edid) { 1867 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 1868 edid->width_cm, edid->height_cm); 1869 1870 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 1871 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 1872 drm_mode_connector_update_edid_property(connector, edid); 1873 ret = drm_add_edid_modes(connector, edid); 1874 /* Store the ELD */ 1875 drm_edid_to_eld(connector, edid); 1876 kfree(edid); 1877 } else { 1878 dev_dbg(hdmi->dev, "failed to get edid\n"); 1879 } 1880 1881 return ret; 1882 } 1883 1884 static enum drm_mode_status 1885 dw_hdmi_connector_mode_valid(struct drm_connector *connector, 1886 struct drm_display_mode *mode) 1887 { 1888 struct dw_hdmi *hdmi = container_of(connector, 1889 struct dw_hdmi, connector); 1890 enum drm_mode_status mode_status = MODE_OK; 1891 1892 /* We don't support double-clocked modes */ 1893 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 1894 return MODE_BAD; 1895 1896 if (hdmi->plat_data->mode_valid) 1897 mode_status = hdmi->plat_data->mode_valid(connector, mode); 1898 1899 return mode_status; 1900 } 1901 1902 static void dw_hdmi_connector_force(struct drm_connector *connector) 1903 { 1904 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 1905 connector); 1906 1907 mutex_lock(&hdmi->mutex); 1908 hdmi->force = connector->force; 1909 dw_hdmi_update_power(hdmi); 1910 dw_hdmi_update_phy_mask(hdmi); 1911 mutex_unlock(&hdmi->mutex); 1912 } 1913 1914 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 1915 .dpms = drm_atomic_helper_connector_dpms, 1916 .fill_modes = drm_helper_probe_single_connector_modes, 1917 .detect = dw_hdmi_connector_detect, 1918 .destroy = drm_connector_cleanup, 1919 .force = dw_hdmi_connector_force, 1920 .reset = drm_atomic_helper_connector_reset, 1921 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 1922 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 1923 }; 1924 1925 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 1926 .get_modes = dw_hdmi_connector_get_modes, 1927 .mode_valid = dw_hdmi_connector_mode_valid, 1928 .best_encoder = drm_atomic_helper_best_encoder, 1929 }; 1930 1931 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) 1932 { 1933 struct dw_hdmi *hdmi = bridge->driver_private; 1934 struct drm_encoder *encoder = bridge->encoder; 1935 struct drm_connector *connector = &hdmi->connector; 1936 1937 connector->interlace_allowed = 1; 1938 connector->polled = DRM_CONNECTOR_POLL_HPD; 1939 1940 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 1941 1942 drm_connector_init(bridge->dev, connector, &dw_hdmi_connector_funcs, 1943 DRM_MODE_CONNECTOR_HDMIA); 1944 1945 drm_mode_connector_attach_encoder(connector, encoder); 1946 1947 return 0; 1948 } 1949 1950 static bool dw_hdmi_bridge_mode_fixup(struct drm_bridge *bridge, 1951 const struct drm_display_mode *orig_mode, 1952 struct drm_display_mode *mode) 1953 { 1954 struct dw_hdmi *hdmi = bridge->driver_private; 1955 struct drm_connector *connector = &hdmi->connector; 1956 enum drm_mode_status status; 1957 1958 status = dw_hdmi_connector_mode_valid(connector, mode); 1959 if (status != MODE_OK) 1960 return false; 1961 return true; 1962 } 1963 1964 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 1965 struct drm_display_mode *orig_mode, 1966 struct drm_display_mode *mode) 1967 { 1968 struct dw_hdmi *hdmi = bridge->driver_private; 1969 1970 mutex_lock(&hdmi->mutex); 1971 1972 /* Store the display mode for plugin/DKMS poweron events */ 1973 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 1974 1975 mutex_unlock(&hdmi->mutex); 1976 } 1977 1978 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) 1979 { 1980 struct dw_hdmi *hdmi = bridge->driver_private; 1981 1982 mutex_lock(&hdmi->mutex); 1983 hdmi->disabled = true; 1984 dw_hdmi_update_power(hdmi); 1985 dw_hdmi_update_phy_mask(hdmi); 1986 mutex_unlock(&hdmi->mutex); 1987 } 1988 1989 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) 1990 { 1991 struct dw_hdmi *hdmi = bridge->driver_private; 1992 1993 mutex_lock(&hdmi->mutex); 1994 hdmi->disabled = false; 1995 dw_hdmi_update_power(hdmi); 1996 dw_hdmi_update_phy_mask(hdmi); 1997 mutex_unlock(&hdmi->mutex); 1998 } 1999 2000 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 2001 .attach = dw_hdmi_bridge_attach, 2002 .enable = dw_hdmi_bridge_enable, 2003 .disable = dw_hdmi_bridge_disable, 2004 .mode_set = dw_hdmi_bridge_mode_set, 2005 .mode_fixup = dw_hdmi_bridge_mode_fixup, 2006 }; 2007 2008 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 2009 { 2010 struct dw_hdmi_i2c *i2c = hdmi->i2c; 2011 unsigned int stat; 2012 2013 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 2014 if (!stat) 2015 return IRQ_NONE; 2016 2017 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 2018 2019 i2c->stat = stat; 2020 2021 complete(&i2c->cmp); 2022 2023 return IRQ_HANDLED; 2024 } 2025 2026 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 2027 { 2028 struct dw_hdmi *hdmi = dev_id; 2029 u8 intr_stat; 2030 irqreturn_t ret = IRQ_NONE; 2031 2032 if (hdmi->i2c) 2033 ret = dw_hdmi_i2c_irq(hdmi); 2034 2035 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2036 if (intr_stat) { 2037 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2038 return IRQ_WAKE_THREAD; 2039 } 2040 2041 return ret; 2042 } 2043 2044 void __dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 2045 { 2046 mutex_lock(&hdmi->mutex); 2047 2048 if (!hdmi->force) { 2049 /* 2050 * If the RX sense status indicates we're disconnected, 2051 * clear the software rxsense status. 2052 */ 2053 if (!rx_sense) 2054 hdmi->rxsense = false; 2055 2056 /* 2057 * Only set the software rxsense status when both 2058 * rxsense and hpd indicates we're connected. 2059 * This avoids what seems to be bad behaviour in 2060 * at least iMX6S versions of the phy. 2061 */ 2062 if (hpd) 2063 hdmi->rxsense = true; 2064 2065 dw_hdmi_update_power(hdmi); 2066 dw_hdmi_update_phy_mask(hdmi); 2067 } 2068 mutex_unlock(&hdmi->mutex); 2069 } 2070 2071 void dw_hdmi_setup_rx_sense(struct device *dev, bool hpd, bool rx_sense) 2072 { 2073 struct dw_hdmi *hdmi = dev_get_drvdata(dev); 2074 2075 __dw_hdmi_setup_rx_sense(hdmi, hpd, rx_sense); 2076 } 2077 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 2078 2079 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 2080 { 2081 struct dw_hdmi *hdmi = dev_id; 2082 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 2083 2084 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2085 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 2086 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 2087 2088 phy_pol_mask = 0; 2089 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 2090 phy_pol_mask |= HDMI_PHY_HPD; 2091 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 2092 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 2093 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 2094 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 2095 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 2096 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 2097 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 2098 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 2099 2100 if (phy_pol_mask) 2101 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 2102 2103 /* 2104 * RX sense tells us whether the TDMS transmitters are detecting 2105 * load - in other words, there's something listening on the 2106 * other end of the link. Use this to decide whether we should 2107 * power on the phy as HPD may be toggled by the sink to merely 2108 * ask the source to re-read the EDID. 2109 */ 2110 if (intr_stat & 2111 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) 2112 __dw_hdmi_setup_rx_sense(hdmi, 2113 phy_stat & HDMI_PHY_HPD, 2114 phy_stat & HDMI_PHY_RX_SENSE); 2115 2116 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { 2117 dev_dbg(hdmi->dev, "EVENT=%s\n", 2118 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); 2119 if (hdmi->bridge.dev) 2120 drm_helper_hpd_irq_event(hdmi->bridge.dev); 2121 } 2122 2123 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 2124 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 2125 HDMI_IH_MUTE_PHY_STAT0); 2126 2127 return IRQ_HANDLED; 2128 } 2129 2130 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 2131 { 2132 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 2133 .name = "DWC HDMI TX PHY", 2134 .gen = 1, 2135 }, { 2136 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 2137 .name = "DWC MHL PHY + HEAC PHY", 2138 .gen = 2, 2139 .has_svsret = true, 2140 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2141 }, { 2142 .type = DW_HDMI_PHY_DWC_MHL_PHY, 2143 .name = "DWC MHL PHY", 2144 .gen = 2, 2145 .has_svsret = true, 2146 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2147 }, { 2148 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 2149 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 2150 .gen = 2, 2151 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2152 }, { 2153 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 2154 .name = "DWC HDMI 3D TX PHY", 2155 .gen = 2, 2156 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2157 }, { 2158 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 2159 .name = "DWC HDMI 2.0 TX PHY", 2160 .gen = 2, 2161 .has_svsret = true, 2162 }, { 2163 .type = DW_HDMI_PHY_VENDOR_PHY, 2164 .name = "Vendor PHY", 2165 } 2166 }; 2167 2168 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 2169 { 2170 unsigned int i; 2171 u8 phy_type; 2172 2173 phy_type = hdmi_readb(hdmi, HDMI_CONFIG2_ID); 2174 2175 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 2176 /* Vendor PHYs require support from the glue layer. */ 2177 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 2178 dev_err(hdmi->dev, 2179 "Vendor HDMI PHY not supported by glue layer\n"); 2180 return -ENODEV; 2181 } 2182 2183 hdmi->phy.ops = hdmi->plat_data->phy_ops; 2184 hdmi->phy.data = hdmi->plat_data->phy_data; 2185 hdmi->phy.name = hdmi->plat_data->phy_name; 2186 return 0; 2187 } 2188 2189 /* Synopsys PHYs are handled internally. */ 2190 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 2191 if (dw_hdmi_phys[i].type == phy_type) { 2192 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 2193 hdmi->phy.name = dw_hdmi_phys[i].name; 2194 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 2195 2196 if (!dw_hdmi_phys[i].configure && 2197 !hdmi->plat_data->configure_phy) { 2198 dev_err(hdmi->dev, "%s requires platform support\n", 2199 hdmi->phy.name); 2200 return -ENODEV; 2201 } 2202 2203 return 0; 2204 } 2205 } 2206 2207 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 2208 return -ENODEV; 2209 } 2210 2211 static const struct regmap_config hdmi_regmap_8bit_config = { 2212 .reg_bits = 32, 2213 .val_bits = 8, 2214 .reg_stride = 1, 2215 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 2216 }; 2217 2218 static const struct regmap_config hdmi_regmap_32bit_config = { 2219 .reg_bits = 32, 2220 .val_bits = 32, 2221 .reg_stride = 4, 2222 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 2223 }; 2224 2225 static struct dw_hdmi * 2226 __dw_hdmi_probe(struct platform_device *pdev, 2227 const struct dw_hdmi_plat_data *plat_data) 2228 { 2229 struct device *dev = &pdev->dev; 2230 struct device_node *np = dev->of_node; 2231 struct platform_device_info pdevinfo; 2232 struct device_node *ddc_node; 2233 struct dw_hdmi *hdmi; 2234 struct resource *iores = NULL; 2235 int irq; 2236 int ret; 2237 u32 val = 1; 2238 u8 prod_id0; 2239 u8 prod_id1; 2240 u8 config0; 2241 u8 config3; 2242 2243 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 2244 if (!hdmi) 2245 return ERR_PTR(-ENOMEM); 2246 2247 hdmi->plat_data = plat_data; 2248 hdmi->dev = dev; 2249 hdmi->sample_rate = 48000; 2250 hdmi->disabled = true; 2251 hdmi->rxsense = true; 2252 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 2253 2254 mutex_init(&hdmi->mutex); 2255 mutex_init(&hdmi->audio_mutex); 2256 spin_lock_init(&hdmi->audio_lock); 2257 2258 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 2259 if (ddc_node) { 2260 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 2261 of_node_put(ddc_node); 2262 if (!hdmi->ddc) { 2263 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 2264 return ERR_PTR(-EPROBE_DEFER); 2265 } 2266 2267 } else { 2268 dev_dbg(hdmi->dev, "no ddc property found\n"); 2269 } 2270 2271 if (!plat_data->regm) { 2272 const struct regmap_config *reg_config; 2273 2274 of_property_read_u32(np, "reg-io-width", &val); 2275 switch (val) { 2276 case 4: 2277 reg_config = &hdmi_regmap_32bit_config; 2278 hdmi->reg_shift = 2; 2279 break; 2280 case 1: 2281 reg_config = &hdmi_regmap_8bit_config; 2282 break; 2283 default: 2284 dev_err(dev, "reg-io-width must be 1 or 4\n"); 2285 return ERR_PTR(-EINVAL); 2286 } 2287 2288 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2289 hdmi->regs = devm_ioremap_resource(dev, iores); 2290 if (IS_ERR(hdmi->regs)) { 2291 ret = PTR_ERR(hdmi->regs); 2292 goto err_res; 2293 } 2294 2295 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 2296 if (IS_ERR(hdmi->regm)) { 2297 dev_err(dev, "Failed to configure regmap\n"); 2298 ret = PTR_ERR(hdmi->regm); 2299 goto err_res; 2300 } 2301 } else { 2302 hdmi->regm = plat_data->regm; 2303 } 2304 2305 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 2306 if (IS_ERR(hdmi->isfr_clk)) { 2307 ret = PTR_ERR(hdmi->isfr_clk); 2308 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 2309 goto err_res; 2310 } 2311 2312 ret = clk_prepare_enable(hdmi->isfr_clk); 2313 if (ret) { 2314 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 2315 goto err_res; 2316 } 2317 2318 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 2319 if (IS_ERR(hdmi->iahb_clk)) { 2320 ret = PTR_ERR(hdmi->iahb_clk); 2321 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 2322 goto err_isfr; 2323 } 2324 2325 ret = clk_prepare_enable(hdmi->iahb_clk); 2326 if (ret) { 2327 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 2328 goto err_isfr; 2329 } 2330 2331 /* Product and revision IDs */ 2332 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2333 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2334 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 2335 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 2336 2337 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 2338 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 2339 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 2340 hdmi->version, prod_id0, prod_id1); 2341 ret = -ENODEV; 2342 goto err_iahb; 2343 } 2344 2345 ret = dw_hdmi_detect_phy(hdmi); 2346 if (ret < 0) 2347 goto err_iahb; 2348 2349 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 2350 hdmi->version >> 12, hdmi->version & 0xfff, 2351 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 2352 hdmi->phy.name); 2353 2354 initialize_hdmi_ih_mutes(hdmi); 2355 2356 irq = platform_get_irq(pdev, 0); 2357 if (irq < 0) { 2358 ret = irq; 2359 goto err_iahb; 2360 } 2361 2362 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 2363 dw_hdmi_irq, IRQF_SHARED, 2364 dev_name(dev), hdmi); 2365 if (ret) 2366 goto err_iahb; 2367 2368 /* 2369 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 2370 * N and cts values before enabling phy 2371 */ 2372 hdmi_init_clk_regenerator(hdmi); 2373 2374 /* If DDC bus is not specified, try to register HDMI I2C bus */ 2375 if (!hdmi->ddc) { 2376 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 2377 if (IS_ERR(hdmi->ddc)) 2378 hdmi->ddc = NULL; 2379 } 2380 2381 hdmi->bridge.driver_private = hdmi; 2382 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 2383 #ifdef CONFIG_OF 2384 hdmi->bridge.of_node = pdev->dev.of_node; 2385 #endif 2386 2387 dw_hdmi_setup_i2c(hdmi); 2388 if (hdmi->phy.ops->setup_hpd) 2389 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 2390 2391 memset(&pdevinfo, 0, sizeof(pdevinfo)); 2392 pdevinfo.parent = dev; 2393 pdevinfo.id = PLATFORM_DEVID_AUTO; 2394 2395 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 2396 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 2397 2398 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 2399 struct dw_hdmi_audio_data audio; 2400 2401 audio.phys = iores->start; 2402 audio.base = hdmi->regs; 2403 audio.irq = irq; 2404 audio.hdmi = hdmi; 2405 audio.eld = hdmi->connector.eld; 2406 2407 pdevinfo.name = "dw-hdmi-ahb-audio"; 2408 pdevinfo.data = &audio; 2409 pdevinfo.size_data = sizeof(audio); 2410 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2411 hdmi->audio = platform_device_register_full(&pdevinfo); 2412 } else if (config0 & HDMI_CONFIG0_I2S) { 2413 struct dw_hdmi_i2s_audio_data audio; 2414 2415 audio.hdmi = hdmi; 2416 audio.write = hdmi_writeb; 2417 audio.read = hdmi_readb; 2418 2419 pdevinfo.name = "dw-hdmi-i2s-audio"; 2420 pdevinfo.data = &audio; 2421 pdevinfo.size_data = sizeof(audio); 2422 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2423 hdmi->audio = platform_device_register_full(&pdevinfo); 2424 } 2425 2426 /* Reset HDMI DDC I2C master controller and mute I2CM interrupts */ 2427 if (hdmi->i2c) 2428 dw_hdmi_i2c_init(hdmi); 2429 2430 platform_set_drvdata(pdev, hdmi); 2431 2432 return hdmi; 2433 2434 err_iahb: 2435 if (hdmi->i2c) { 2436 i2c_del_adapter(&hdmi->i2c->adap); 2437 hdmi->ddc = NULL; 2438 } 2439 2440 clk_disable_unprepare(hdmi->iahb_clk); 2441 err_isfr: 2442 clk_disable_unprepare(hdmi->isfr_clk); 2443 err_res: 2444 i2c_put_adapter(hdmi->ddc); 2445 2446 return ERR_PTR(ret); 2447 } 2448 2449 static void __dw_hdmi_remove(struct dw_hdmi *hdmi) 2450 { 2451 if (hdmi->audio && !IS_ERR(hdmi->audio)) 2452 platform_device_unregister(hdmi->audio); 2453 2454 /* Disable all interrupts */ 2455 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2456 2457 clk_disable_unprepare(hdmi->iahb_clk); 2458 clk_disable_unprepare(hdmi->isfr_clk); 2459 2460 if (hdmi->i2c) 2461 i2c_del_adapter(&hdmi->i2c->adap); 2462 else 2463 i2c_put_adapter(hdmi->ddc); 2464 } 2465 2466 /* ----------------------------------------------------------------------------- 2467 * Probe/remove API, used from platforms based on the DRM bridge API. 2468 */ 2469 int dw_hdmi_probe(struct platform_device *pdev, 2470 const struct dw_hdmi_plat_data *plat_data) 2471 { 2472 struct dw_hdmi *hdmi; 2473 int ret; 2474 2475 hdmi = __dw_hdmi_probe(pdev, plat_data); 2476 if (IS_ERR(hdmi)) 2477 return PTR_ERR(hdmi); 2478 2479 ret = drm_bridge_add(&hdmi->bridge); 2480 if (ret < 0) { 2481 __dw_hdmi_remove(hdmi); 2482 return ret; 2483 } 2484 2485 return 0; 2486 } 2487 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 2488 2489 void dw_hdmi_remove(struct platform_device *pdev) 2490 { 2491 struct dw_hdmi *hdmi = platform_get_drvdata(pdev); 2492 2493 drm_bridge_remove(&hdmi->bridge); 2494 2495 __dw_hdmi_remove(hdmi); 2496 } 2497 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 2498 2499 /* ----------------------------------------------------------------------------- 2500 * Bind/unbind API, used from platforms based on the component framework. 2501 */ 2502 int dw_hdmi_bind(struct platform_device *pdev, struct drm_encoder *encoder, 2503 const struct dw_hdmi_plat_data *plat_data) 2504 { 2505 struct dw_hdmi *hdmi; 2506 int ret; 2507 2508 hdmi = __dw_hdmi_probe(pdev, plat_data); 2509 if (IS_ERR(hdmi)) 2510 return PTR_ERR(hdmi); 2511 2512 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL); 2513 if (ret) { 2514 dw_hdmi_remove(pdev); 2515 DRM_ERROR("Failed to initialize bridge with drm\n"); 2516 return ret; 2517 } 2518 2519 return 0; 2520 } 2521 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 2522 2523 void dw_hdmi_unbind(struct device *dev) 2524 { 2525 struct dw_hdmi *hdmi = dev_get_drvdata(dev); 2526 2527 __dw_hdmi_remove(hdmi); 2528 } 2529 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 2530 2531 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 2532 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 2533 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 2534 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 2535 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 2536 MODULE_LICENSE("GPL"); 2537 MODULE_ALIAS("platform:dw-hdmi"); 2538