1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver 4 * 5 * Copyright (C) 2013-2015 Mentor Graphics Inc. 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/hdmi.h> 13 #include <linux/irq.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/regmap.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/spinlock.h> 21 22 #include <media/cec-notifier.h> 23 24 #include <uapi/linux/media-bus-format.h> 25 #include <uapi/linux/videodev2.h> 26 27 #include <drm/bridge/dw_hdmi.h> 28 #include <drm/display/drm_hdmi_helper.h> 29 #include <drm/display/drm_scdc_helper.h> 30 #include <drm/drm_atomic.h> 31 #include <drm/drm_atomic_helper.h> 32 #include <drm/drm_bridge.h> 33 #include <drm/drm_of.h> 34 #include <drm/drm_print.h> 35 #include <drm/drm_probe_helper.h> 36 37 #include "dw-hdmi-audio.h" 38 #include "dw-hdmi-cec.h" 39 #include "dw-hdmi.h" 40 41 #define DDC_CI_ADDR 0x37 42 #define DDC_SEGMENT_ADDR 0x30 43 44 #define HDMI_EDID_LEN 512 45 46 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 47 #define SCDC_MIN_SOURCE_VERSION 0x1 48 49 #define HDMI14_MAX_TMDSCLK 340000000 50 51 enum hdmi_datamap { 52 RGB444_8B = 0x01, 53 RGB444_10B = 0x03, 54 RGB444_12B = 0x05, 55 RGB444_16B = 0x07, 56 YCbCr444_8B = 0x09, 57 YCbCr444_10B = 0x0B, 58 YCbCr444_12B = 0x0D, 59 YCbCr444_16B = 0x0F, 60 YCbCr422_8B = 0x16, 61 YCbCr422_10B = 0x14, 62 YCbCr422_12B = 0x12, 63 }; 64 65 static const u16 csc_coeff_default[3][4] = { 66 { 0x2000, 0x0000, 0x0000, 0x0000 }, 67 { 0x0000, 0x2000, 0x0000, 0x0000 }, 68 { 0x0000, 0x0000, 0x2000, 0x0000 } 69 }; 70 71 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 72 { 0x2000, 0x6926, 0x74fd, 0x010e }, 73 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 74 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 75 }; 76 77 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 78 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 79 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 80 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 81 }; 82 83 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 84 { 0x2591, 0x1322, 0x074b, 0x0000 }, 85 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 86 { 0x6acd, 0x7534, 0x2000, 0x0200 } 87 }; 88 89 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 90 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 91 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 92 { 0x6756, 0x78ab, 0x2000, 0x0200 } 93 }; 94 95 static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = { 96 { 0x1b7c, 0x0000, 0x0000, 0x0020 }, 97 { 0x0000, 0x1b7c, 0x0000, 0x0020 }, 98 { 0x0000, 0x0000, 0x1b7c, 0x0020 } 99 }; 100 101 struct hdmi_vmode { 102 bool mdataenablepolarity; 103 104 unsigned int mpixelclock; 105 unsigned int mpixelrepetitioninput; 106 unsigned int mpixelrepetitionoutput; 107 unsigned int mtmdsclock; 108 }; 109 110 struct hdmi_data_info { 111 unsigned int enc_in_bus_format; 112 unsigned int enc_out_bus_format; 113 unsigned int enc_in_encoding; 114 unsigned int enc_out_encoding; 115 unsigned int pix_repet_factor; 116 unsigned int hdcp_enable; 117 struct hdmi_vmode video_mode; 118 bool rgb_limited_range; 119 }; 120 121 struct dw_hdmi_i2c { 122 struct i2c_adapter adap; 123 124 struct mutex lock; /* used to serialize data transfers */ 125 struct completion cmp; 126 u8 stat; 127 128 u8 slave_reg; 129 bool is_regaddr; 130 bool is_segment; 131 }; 132 133 struct dw_hdmi_phy_data { 134 enum dw_hdmi_phy_type type; 135 const char *name; 136 unsigned int gen; 137 bool has_svsret; 138 int (*configure)(struct dw_hdmi *hdmi, 139 const struct dw_hdmi_plat_data *pdata, 140 unsigned long mpixelclock); 141 }; 142 143 struct dw_hdmi { 144 struct drm_connector connector; 145 struct drm_bridge bridge; 146 struct drm_bridge *next_bridge; 147 148 unsigned int version; 149 150 struct platform_device *audio; 151 struct platform_device *cec; 152 struct device *dev; 153 struct clk *isfr_clk; 154 struct clk *iahb_clk; 155 struct clk *cec_clk; 156 struct dw_hdmi_i2c *i2c; 157 158 struct hdmi_data_info hdmi_data; 159 const struct dw_hdmi_plat_data *plat_data; 160 161 int vic; 162 163 u8 edid[HDMI_EDID_LEN]; 164 165 struct { 166 const struct dw_hdmi_phy_ops *ops; 167 const char *name; 168 void *data; 169 bool enabled; 170 } phy; 171 172 struct drm_display_mode previous_mode; 173 174 struct i2c_adapter *ddc; 175 void __iomem *regs; 176 bool sink_is_hdmi; 177 bool sink_has_audio; 178 179 struct pinctrl *pinctrl; 180 struct pinctrl_state *default_state; 181 struct pinctrl_state *unwedge_state; 182 183 struct mutex mutex; /* for state below and previous_mode */ 184 enum drm_connector_force force; /* mutex-protected force state */ 185 struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */ 186 bool disabled; /* DRM has disabled our bridge */ 187 bool bridge_is_on; /* indicates the bridge is on */ 188 bool rxsense; /* rxsense state */ 189 u8 phy_mask; /* desired phy int mask settings */ 190 u8 mc_clkdis; /* clock disable register */ 191 192 spinlock_t audio_lock; 193 struct mutex audio_mutex; 194 unsigned int sample_non_pcm; 195 unsigned int sample_width; 196 unsigned int sample_rate; 197 unsigned int channels; 198 unsigned int audio_cts; 199 unsigned int audio_n; 200 bool audio_enable; 201 202 unsigned int reg_shift; 203 struct regmap *regm; 204 void (*enable_audio)(struct dw_hdmi *hdmi); 205 void (*disable_audio)(struct dw_hdmi *hdmi); 206 207 struct mutex cec_notifier_mutex; 208 struct cec_notifier *cec_notifier; 209 210 hdmi_codec_plugged_cb plugged_cb; 211 struct device *codec_dev; 212 enum drm_connector_status last_connector_result; 213 }; 214 215 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 216 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 217 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 218 219 #define HDMI_PHY_RX_SENSE \ 220 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 221 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 222 223 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 224 { 225 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 226 } 227 228 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 229 { 230 unsigned int val = 0; 231 232 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 233 234 return val; 235 } 236 237 static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged) 238 { 239 if (hdmi->plugged_cb && hdmi->codec_dev) 240 hdmi->plugged_cb(hdmi->codec_dev, plugged); 241 } 242 243 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn, 244 struct device *codec_dev) 245 { 246 bool plugged; 247 248 mutex_lock(&hdmi->mutex); 249 hdmi->plugged_cb = fn; 250 hdmi->codec_dev = codec_dev; 251 plugged = hdmi->last_connector_result == connector_status_connected; 252 handle_plugged_change(hdmi, plugged); 253 mutex_unlock(&hdmi->mutex); 254 255 return 0; 256 } 257 EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb); 258 259 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 260 { 261 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 262 } 263 264 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 265 u8 shift, u8 mask) 266 { 267 hdmi_modb(hdmi, data << shift, mask, reg); 268 } 269 270 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 271 { 272 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 273 HDMI_PHY_I2CM_INT_ADDR); 274 275 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 276 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 277 HDMI_PHY_I2CM_CTLINT_ADDR); 278 279 /* Software reset */ 280 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 281 282 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 283 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 284 285 /* Set done, not acknowledged and arbitration interrupt polarities */ 286 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 287 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 288 HDMI_I2CM_CTLINT); 289 290 /* Clear DONE and ERROR interrupts */ 291 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 292 HDMI_IH_I2CM_STAT0); 293 294 /* Mute DONE and ERROR interrupts */ 295 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 296 HDMI_IH_MUTE_I2CM_STAT0); 297 } 298 299 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi) 300 { 301 /* If no unwedge state then give up */ 302 if (!hdmi->unwedge_state) 303 return false; 304 305 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n"); 306 307 /* 308 * This is a huge hack to workaround a problem where the dw_hdmi i2c 309 * bus could sometimes get wedged. Once wedged there doesn't appear 310 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ) 311 * other than pulsing the SDA line. 312 * 313 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi) 314 * by: 315 * 1. Remux the pin as a GPIO output, driven low. 316 * 2. Wait a little while. 1 ms seems to work, but we'll do 10. 317 * 3. Immediately jump to remux the pin as dw_hdmi i2c again. 318 * 319 * At the moment of remuxing, the line will still be low due to its 320 * recent stint as an output, but then it will be pulled high by the 321 * (presumed) external pullup. dw_hdmi seems to see this as a rising 322 * edge and that seems to get it out of its jam. 323 * 324 * This wedging was only ever seen on one TV, and only on one of 325 * its HDMI ports. It happened when the TV was powered on while the 326 * device was plugged in. A scope trace shows the TV bringing both SDA 327 * and SCL low, then bringing them both back up at roughly the same 328 * time. Presumably this confuses dw_hdmi because it saw activity but 329 * no real STOP (maybe it thinks there's another master on the bus?). 330 * Giving it a clean rising edge of SDA while SCL is already high 331 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out 332 * of its stupor. 333 * 334 * Note that after coming back alive, transfers seem to immediately 335 * resume, so if we unwedge due to a timeout we should wait a little 336 * longer for our transfer to finish, since it might have just started 337 * now. 338 */ 339 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state); 340 msleep(10); 341 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state); 342 343 return true; 344 } 345 346 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi) 347 { 348 struct dw_hdmi_i2c *i2c = hdmi->i2c; 349 int stat; 350 351 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 352 if (!stat) { 353 /* If we can't unwedge, return timeout */ 354 if (!dw_hdmi_i2c_unwedge(hdmi)) 355 return -EAGAIN; 356 357 /* We tried to unwedge; give it another chance */ 358 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 359 if (!stat) 360 return -EAGAIN; 361 } 362 363 /* Check for error condition on the bus */ 364 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 365 return -EIO; 366 367 return 0; 368 } 369 370 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 371 unsigned char *buf, unsigned int length) 372 { 373 struct dw_hdmi_i2c *i2c = hdmi->i2c; 374 int ret; 375 376 if (!i2c->is_regaddr) { 377 dev_dbg(hdmi->dev, "set read register address to 0\n"); 378 i2c->slave_reg = 0x00; 379 i2c->is_regaddr = true; 380 } 381 382 while (length--) { 383 reinit_completion(&i2c->cmp); 384 385 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 386 if (i2c->is_segment) 387 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 388 HDMI_I2CM_OPERATION); 389 else 390 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 391 HDMI_I2CM_OPERATION); 392 393 ret = dw_hdmi_i2c_wait(hdmi); 394 if (ret) 395 return ret; 396 397 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 398 } 399 i2c->is_segment = false; 400 401 return 0; 402 } 403 404 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 405 unsigned char *buf, unsigned int length) 406 { 407 struct dw_hdmi_i2c *i2c = hdmi->i2c; 408 int ret; 409 410 if (!i2c->is_regaddr) { 411 /* Use the first write byte as register address */ 412 i2c->slave_reg = buf[0]; 413 length--; 414 buf++; 415 i2c->is_regaddr = true; 416 } 417 418 while (length--) { 419 reinit_completion(&i2c->cmp); 420 421 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 422 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 423 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 424 HDMI_I2CM_OPERATION); 425 426 ret = dw_hdmi_i2c_wait(hdmi); 427 if (ret) 428 return ret; 429 } 430 431 return 0; 432 } 433 434 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 435 struct i2c_msg *msgs, int num) 436 { 437 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 438 struct dw_hdmi_i2c *i2c = hdmi->i2c; 439 u8 addr = msgs[0].addr; 440 int i, ret = 0; 441 442 if (addr == DDC_CI_ADDR) 443 /* 444 * The internal I2C controller does not support the multi-byte 445 * read and write operations needed for DDC/CI. 446 * TOFIX: Blacklist the DDC/CI address until we filter out 447 * unsupported I2C operations. 448 */ 449 return -EOPNOTSUPP; 450 451 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 452 453 for (i = 0; i < num; i++) { 454 if (msgs[i].len == 0) { 455 dev_dbg(hdmi->dev, 456 "unsupported transfer %d/%d, no data\n", 457 i + 1, num); 458 return -EOPNOTSUPP; 459 } 460 } 461 462 mutex_lock(&i2c->lock); 463 464 /* Unmute DONE and ERROR interrupts */ 465 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 466 467 /* Set slave device address taken from the first I2C message */ 468 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 469 470 /* Set slave device register address on transfer */ 471 i2c->is_regaddr = false; 472 473 /* Set segment pointer for I2C extended read mode operation */ 474 i2c->is_segment = false; 475 476 for (i = 0; i < num; i++) { 477 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 478 i + 1, num, msgs[i].len, msgs[i].flags); 479 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 480 i2c->is_segment = true; 481 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 482 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 483 } else { 484 if (msgs[i].flags & I2C_M_RD) 485 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 486 msgs[i].len); 487 else 488 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 489 msgs[i].len); 490 } 491 if (ret < 0) 492 break; 493 } 494 495 if (!ret) 496 ret = num; 497 498 /* Mute DONE and ERROR interrupts */ 499 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 500 HDMI_IH_MUTE_I2CM_STAT0); 501 502 mutex_unlock(&i2c->lock); 503 504 return ret; 505 } 506 507 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 508 { 509 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 510 } 511 512 static const struct i2c_algorithm dw_hdmi_algorithm = { 513 .master_xfer = dw_hdmi_i2c_xfer, 514 .functionality = dw_hdmi_i2c_func, 515 }; 516 517 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 518 { 519 struct i2c_adapter *adap; 520 struct dw_hdmi_i2c *i2c; 521 int ret; 522 523 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 524 if (!i2c) 525 return ERR_PTR(-ENOMEM); 526 527 mutex_init(&i2c->lock); 528 init_completion(&i2c->cmp); 529 530 adap = &i2c->adap; 531 adap->class = I2C_CLASS_DDC; 532 adap->owner = THIS_MODULE; 533 adap->dev.parent = hdmi->dev; 534 adap->algo = &dw_hdmi_algorithm; 535 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 536 i2c_set_adapdata(adap, hdmi); 537 538 ret = i2c_add_adapter(adap); 539 if (ret) { 540 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 541 devm_kfree(hdmi->dev, i2c); 542 return ERR_PTR(ret); 543 } 544 545 hdmi->i2c = i2c; 546 547 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 548 549 return adap; 550 } 551 552 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 553 unsigned int n) 554 { 555 /* Must be set/cleared first */ 556 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 557 558 /* nshift factor = 0 */ 559 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 560 561 /* Use automatic CTS generation mode when CTS is not set */ 562 if (cts) 563 hdmi_writeb(hdmi, ((cts >> 16) & 564 HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 565 HDMI_AUD_CTS3_CTS_MANUAL, 566 HDMI_AUD_CTS3); 567 else 568 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); 569 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 570 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 571 572 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 573 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 574 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 575 } 576 577 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 578 { 579 unsigned int n = (128 * freq) / 1000; 580 unsigned int mult = 1; 581 582 while (freq > 48000) { 583 mult *= 2; 584 freq /= 2; 585 } 586 587 switch (freq) { 588 case 32000: 589 if (pixel_clk == 25175000) 590 n = 4576; 591 else if (pixel_clk == 27027000) 592 n = 4096; 593 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 594 n = 11648; 595 else if (pixel_clk == 297000000) 596 n = 3072; 597 else 598 n = 4096; 599 n *= mult; 600 break; 601 602 case 44100: 603 if (pixel_clk == 25175000) 604 n = 7007; 605 else if (pixel_clk == 74176000) 606 n = 17836; 607 else if (pixel_clk == 148352000) 608 n = 8918; 609 else if (pixel_clk == 297000000) 610 n = 4704; 611 else 612 n = 6272; 613 n *= mult; 614 break; 615 616 case 48000: 617 if (pixel_clk == 25175000) 618 n = 6864; 619 else if (pixel_clk == 27027000) 620 n = 6144; 621 else if (pixel_clk == 74176000) 622 n = 11648; 623 else if (pixel_clk == 148352000) 624 n = 5824; 625 else if (pixel_clk == 297000000) 626 n = 5120; 627 else 628 n = 6144; 629 n *= mult; 630 break; 631 632 default: 633 break; 634 } 635 636 return n; 637 } 638 639 /* 640 * When transmitting IEC60958 linear PCM audio, these registers allow to 641 * configure the channel status information of all the channel status 642 * bits in the IEC60958 frame. For the moment this configuration is only 643 * used when the I2S audio interface, General Purpose Audio (GPA), 644 * or AHB audio DMA (AHBAUDDMA) interface is active 645 * (for S/PDIF interface this information comes from the stream). 646 */ 647 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, 648 u8 *channel_status) 649 { 650 /* 651 * Set channel status register for frequency and word length. 652 * Use default values for other registers. 653 */ 654 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7); 655 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8); 656 } 657 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status); 658 659 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 660 unsigned long pixel_clk, unsigned int sample_rate) 661 { 662 unsigned long ftdms = pixel_clk; 663 unsigned int n, cts; 664 u8 config3; 665 u64 tmp; 666 667 n = hdmi_compute_n(sample_rate, pixel_clk); 668 669 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 670 671 /* Compute CTS when using internal AHB audio or General Parallel audio*/ 672 if ((config3 & HDMI_CONFIG3_AHBAUDDMA) || (config3 & HDMI_CONFIG3_GPAUD)) { 673 /* 674 * Compute the CTS value from the N value. Note that CTS and N 675 * can be up to 20 bits in total, so we need 64-bit math. Also 676 * note that our TDMS clock is not fully accurate; it is 677 * accurate to kHz. This can introduce an unnecessary remainder 678 * in the calculation below, so we don't try to warn about that. 679 */ 680 tmp = (u64)ftdms * n; 681 do_div(tmp, 128 * sample_rate); 682 cts = tmp; 683 684 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 685 __func__, sample_rate, 686 ftdms / 1000000, (ftdms / 1000) % 1000, 687 n, cts); 688 } else { 689 cts = 0; 690 } 691 692 spin_lock_irq(&hdmi->audio_lock); 693 hdmi->audio_n = n; 694 hdmi->audio_cts = cts; 695 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 696 spin_unlock_irq(&hdmi->audio_lock); 697 } 698 699 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 700 { 701 mutex_lock(&hdmi->audio_mutex); 702 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 703 mutex_unlock(&hdmi->audio_mutex); 704 } 705 706 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 707 { 708 mutex_lock(&hdmi->audio_mutex); 709 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 710 hdmi->sample_rate); 711 mutex_unlock(&hdmi->audio_mutex); 712 } 713 714 void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width) 715 { 716 mutex_lock(&hdmi->audio_mutex); 717 hdmi->sample_width = width; 718 mutex_unlock(&hdmi->audio_mutex); 719 } 720 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_width); 721 722 void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm) 723 { 724 mutex_lock(&hdmi->audio_mutex); 725 hdmi->sample_non_pcm = non_pcm; 726 mutex_unlock(&hdmi->audio_mutex); 727 } 728 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_non_pcm); 729 730 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 731 { 732 mutex_lock(&hdmi->audio_mutex); 733 hdmi->sample_rate = rate; 734 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 735 hdmi->sample_rate); 736 mutex_unlock(&hdmi->audio_mutex); 737 } 738 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 739 740 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt) 741 { 742 u8 layout; 743 744 mutex_lock(&hdmi->audio_mutex); 745 hdmi->channels = cnt; 746 747 /* 748 * For >2 channel PCM audio, we need to select layout 1 749 * and set an appropriate channel map. 750 */ 751 if (cnt > 2) 752 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1; 753 else 754 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0; 755 756 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, 757 HDMI_FC_AUDSCONF); 758 759 /* Set the audio infoframes channel count */ 760 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, 761 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0); 762 763 mutex_unlock(&hdmi->audio_mutex); 764 } 765 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count); 766 767 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca) 768 { 769 mutex_lock(&hdmi->audio_mutex); 770 771 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2); 772 773 mutex_unlock(&hdmi->audio_mutex); 774 } 775 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation); 776 777 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 778 { 779 if (enable) 780 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 781 else 782 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 783 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 784 } 785 786 static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi) 787 { 788 if (!hdmi->curr_conn) 789 return NULL; 790 791 return hdmi->curr_conn->eld; 792 } 793 794 static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi) 795 { 796 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 797 int sample_freq = 0x2, org_sample_freq = 0xD; 798 int ch_mask = BIT(hdmi->channels) - 1; 799 800 switch (hdmi->sample_rate) { 801 case 32000: 802 sample_freq = 0x03; 803 org_sample_freq = 0x0C; 804 break; 805 case 44100: 806 sample_freq = 0x00; 807 org_sample_freq = 0x0F; 808 break; 809 case 48000: 810 sample_freq = 0x02; 811 org_sample_freq = 0x0D; 812 break; 813 case 88200: 814 sample_freq = 0x08; 815 org_sample_freq = 0x07; 816 break; 817 case 96000: 818 sample_freq = 0x0A; 819 org_sample_freq = 0x05; 820 break; 821 case 176400: 822 sample_freq = 0x0C; 823 org_sample_freq = 0x03; 824 break; 825 case 192000: 826 sample_freq = 0x0E; 827 org_sample_freq = 0x01; 828 break; 829 default: 830 break; 831 } 832 833 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 834 hdmi_enable_audio_clk(hdmi, true); 835 836 hdmi_writeb(hdmi, 0x1, HDMI_FC_AUDSCHNLS0); 837 hdmi_writeb(hdmi, hdmi->channels, HDMI_FC_AUDSCHNLS2); 838 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS3); 839 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS4); 840 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS5); 841 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS6); 842 hdmi_writeb(hdmi, (0x3 << 4) | sample_freq, HDMI_FC_AUDSCHNLS7); 843 hdmi_writeb(hdmi, (org_sample_freq << 4) | 0xb, HDMI_FC_AUDSCHNLS8); 844 845 hdmi_writeb(hdmi, ch_mask, HDMI_GP_CONF1); 846 hdmi_writeb(hdmi, 0x02, HDMI_GP_CONF2); 847 hdmi_writeb(hdmi, 0x01, HDMI_GP_CONF0); 848 849 hdmi_modb(hdmi, 0x3, 0x3, HDMI_FC_DATAUTO3); 850 851 /* hbr */ 852 if (hdmi->sample_rate == 192000 && hdmi->channels == 8 && 853 hdmi->sample_width == 32 && hdmi->sample_non_pcm) 854 hdmi_modb(hdmi, 0x01, 0x01, HDMI_GP_CONF2); 855 856 if (pdata->enable_audio) 857 pdata->enable_audio(hdmi, 858 hdmi->channels, 859 hdmi->sample_width, 860 hdmi->sample_rate, 861 hdmi->sample_non_pcm); 862 } 863 864 static void dw_hdmi_gp_audio_disable(struct dw_hdmi *hdmi) 865 { 866 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 867 868 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 869 870 hdmi_modb(hdmi, 0, 0x3, HDMI_FC_DATAUTO3); 871 if (pdata->disable_audio) 872 pdata->disable_audio(hdmi); 873 874 hdmi_enable_audio_clk(hdmi, false); 875 } 876 877 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 878 { 879 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 880 } 881 882 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 883 { 884 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 885 } 886 887 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 888 { 889 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 890 hdmi_enable_audio_clk(hdmi, true); 891 } 892 893 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 894 { 895 hdmi_enable_audio_clk(hdmi, false); 896 } 897 898 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 899 { 900 unsigned long flags; 901 902 spin_lock_irqsave(&hdmi->audio_lock, flags); 903 hdmi->audio_enable = true; 904 if (hdmi->enable_audio) 905 hdmi->enable_audio(hdmi); 906 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 907 } 908 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 909 910 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 911 { 912 unsigned long flags; 913 914 spin_lock_irqsave(&hdmi->audio_lock, flags); 915 hdmi->audio_enable = false; 916 if (hdmi->disable_audio) 917 hdmi->disable_audio(hdmi); 918 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 919 } 920 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 921 922 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 923 { 924 switch (bus_format) { 925 case MEDIA_BUS_FMT_RGB888_1X24: 926 case MEDIA_BUS_FMT_RGB101010_1X30: 927 case MEDIA_BUS_FMT_RGB121212_1X36: 928 case MEDIA_BUS_FMT_RGB161616_1X48: 929 return true; 930 931 default: 932 return false; 933 } 934 } 935 936 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 937 { 938 switch (bus_format) { 939 case MEDIA_BUS_FMT_YUV8_1X24: 940 case MEDIA_BUS_FMT_YUV10_1X30: 941 case MEDIA_BUS_FMT_YUV12_1X36: 942 case MEDIA_BUS_FMT_YUV16_1X48: 943 return true; 944 945 default: 946 return false; 947 } 948 } 949 950 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 951 { 952 switch (bus_format) { 953 case MEDIA_BUS_FMT_UYVY8_1X16: 954 case MEDIA_BUS_FMT_UYVY10_1X20: 955 case MEDIA_BUS_FMT_UYVY12_1X24: 956 return true; 957 958 default: 959 return false; 960 } 961 } 962 963 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 964 { 965 switch (bus_format) { 966 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 967 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 968 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 969 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 970 return true; 971 972 default: 973 return false; 974 } 975 } 976 977 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 978 { 979 switch (bus_format) { 980 case MEDIA_BUS_FMT_RGB888_1X24: 981 case MEDIA_BUS_FMT_YUV8_1X24: 982 case MEDIA_BUS_FMT_UYVY8_1X16: 983 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 984 return 8; 985 986 case MEDIA_BUS_FMT_RGB101010_1X30: 987 case MEDIA_BUS_FMT_YUV10_1X30: 988 case MEDIA_BUS_FMT_UYVY10_1X20: 989 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 990 return 10; 991 992 case MEDIA_BUS_FMT_RGB121212_1X36: 993 case MEDIA_BUS_FMT_YUV12_1X36: 994 case MEDIA_BUS_FMT_UYVY12_1X24: 995 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 996 return 12; 997 998 case MEDIA_BUS_FMT_RGB161616_1X48: 999 case MEDIA_BUS_FMT_YUV16_1X48: 1000 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1001 return 16; 1002 1003 default: 1004 return 0; 1005 } 1006 } 1007 1008 /* 1009 * this submodule is responsible for the video data synchronization. 1010 * for example, for RGB 4:4:4 input, the data map is defined as 1011 * pin{47~40} <==> R[7:0] 1012 * pin{31~24} <==> G[7:0] 1013 * pin{15~8} <==> B[7:0] 1014 */ 1015 static void hdmi_video_sample(struct dw_hdmi *hdmi) 1016 { 1017 int color_format = 0; 1018 u8 val; 1019 1020 switch (hdmi->hdmi_data.enc_in_bus_format) { 1021 case MEDIA_BUS_FMT_RGB888_1X24: 1022 color_format = 0x01; 1023 break; 1024 case MEDIA_BUS_FMT_RGB101010_1X30: 1025 color_format = 0x03; 1026 break; 1027 case MEDIA_BUS_FMT_RGB121212_1X36: 1028 color_format = 0x05; 1029 break; 1030 case MEDIA_BUS_FMT_RGB161616_1X48: 1031 color_format = 0x07; 1032 break; 1033 1034 case MEDIA_BUS_FMT_YUV8_1X24: 1035 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1036 color_format = 0x09; 1037 break; 1038 case MEDIA_BUS_FMT_YUV10_1X30: 1039 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1040 color_format = 0x0B; 1041 break; 1042 case MEDIA_BUS_FMT_YUV12_1X36: 1043 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 1044 color_format = 0x0D; 1045 break; 1046 case MEDIA_BUS_FMT_YUV16_1X48: 1047 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1048 color_format = 0x0F; 1049 break; 1050 1051 case MEDIA_BUS_FMT_UYVY8_1X16: 1052 color_format = 0x16; 1053 break; 1054 case MEDIA_BUS_FMT_UYVY10_1X20: 1055 color_format = 0x14; 1056 break; 1057 case MEDIA_BUS_FMT_UYVY12_1X24: 1058 color_format = 0x12; 1059 break; 1060 1061 default: 1062 return; 1063 } 1064 1065 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 1066 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 1067 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 1068 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 1069 1070 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 1071 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 1072 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 1073 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 1074 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 1075 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 1076 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 1077 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 1078 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 1079 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 1080 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 1081 } 1082 1083 static int is_color_space_conversion(struct dw_hdmi *hdmi) 1084 { 1085 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1086 bool is_input_rgb, is_output_rgb; 1087 1088 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format); 1089 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format); 1090 1091 return (is_input_rgb != is_output_rgb) || 1092 (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range); 1093 } 1094 1095 static int is_color_space_decimation(struct dw_hdmi *hdmi) 1096 { 1097 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1098 return 0; 1099 1100 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 1101 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 1102 return 1; 1103 1104 return 0; 1105 } 1106 1107 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 1108 { 1109 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 1110 return 0; 1111 1112 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1113 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1114 return 1; 1115 1116 return 0; 1117 } 1118 1119 static bool is_csc_needed(struct dw_hdmi *hdmi) 1120 { 1121 return is_color_space_conversion(hdmi) || 1122 is_color_space_decimation(hdmi) || 1123 is_color_space_interpolation(hdmi); 1124 } 1125 1126 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 1127 { 1128 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 1129 bool is_input_rgb, is_output_rgb; 1130 unsigned i; 1131 u32 csc_scale = 1; 1132 1133 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); 1134 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); 1135 1136 if (!is_input_rgb && is_output_rgb) { 1137 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) 1138 csc_coeff = &csc_coeff_rgb_out_eitu601; 1139 else 1140 csc_coeff = &csc_coeff_rgb_out_eitu709; 1141 } else if (is_input_rgb && !is_output_rgb) { 1142 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) 1143 csc_coeff = &csc_coeff_rgb_in_eitu601; 1144 else 1145 csc_coeff = &csc_coeff_rgb_in_eitu709; 1146 csc_scale = 0; 1147 } else if (is_input_rgb && is_output_rgb && 1148 hdmi->hdmi_data.rgb_limited_range) { 1149 csc_coeff = &csc_coeff_rgb_full_to_rgb_limited; 1150 } 1151 1152 /* The CSC registers are sequential, alternating MSB then LSB */ 1153 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 1154 u16 coeff_a = (*csc_coeff)[0][i]; 1155 u16 coeff_b = (*csc_coeff)[1][i]; 1156 u16 coeff_c = (*csc_coeff)[2][i]; 1157 1158 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 1159 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 1160 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 1161 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 1162 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 1163 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 1164 } 1165 1166 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 1167 HDMI_CSC_SCALE); 1168 } 1169 1170 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1171 { 1172 int color_depth = 0; 1173 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1174 int decimation = 0; 1175 1176 /* YCC422 interpolation to 444 mode */ 1177 if (is_color_space_interpolation(hdmi)) 1178 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1179 else if (is_color_space_decimation(hdmi)) 1180 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1181 1182 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1183 case 8: 1184 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1185 break; 1186 case 10: 1187 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1188 break; 1189 case 12: 1190 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1191 break; 1192 case 16: 1193 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1194 break; 1195 1196 default: 1197 return; 1198 } 1199 1200 /* Configure the CSC registers */ 1201 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1202 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1203 HDMI_CSC_SCALE); 1204 1205 dw_hdmi_update_csc_coeffs(hdmi); 1206 } 1207 1208 /* 1209 * HDMI video packetizer is used to packetize the data. 1210 * for example, if input is YCC422 mode or repeater is used, 1211 * data should be repacked this module can be bypassed. 1212 */ 1213 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1214 { 1215 unsigned int color_depth = 0; 1216 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1217 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1218 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1219 u8 val, vp_conf; 1220 u8 clear_gcp_auto = 0; 1221 1222 1223 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1224 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1225 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1226 switch (hdmi_bus_fmt_color_depth( 1227 hdmi->hdmi_data.enc_out_bus_format)) { 1228 case 8: 1229 color_depth = 4; 1230 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1231 clear_gcp_auto = 1; 1232 break; 1233 case 10: 1234 color_depth = 5; 1235 break; 1236 case 12: 1237 color_depth = 6; 1238 break; 1239 case 16: 1240 color_depth = 7; 1241 break; 1242 default: 1243 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1244 } 1245 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1246 switch (hdmi_bus_fmt_color_depth( 1247 hdmi->hdmi_data.enc_out_bus_format)) { 1248 case 0: 1249 case 8: 1250 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1251 clear_gcp_auto = 1; 1252 break; 1253 case 10: 1254 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1255 break; 1256 case 12: 1257 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1258 break; 1259 1260 default: 1261 return; 1262 } 1263 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1264 } else { 1265 return; 1266 } 1267 1268 /* set the packetizer registers */ 1269 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1270 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 1271 ((hdmi_data->pix_repet_factor << 1272 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 1273 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 1274 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1275 1276 /* HDMI1.4b specification section 6.5.3: 1277 * Source shall only send GCPs with non-zero CD to sinks 1278 * that indicate support for Deep Color. 1279 * GCP only transmit CD and do not handle AVMUTE, PP norDefault_Phase (yet). 1280 * Disable Auto GCP when 24-bit color for sinks that not support Deep Color. 1281 */ 1282 val = hdmi_readb(hdmi, HDMI_FC_DATAUTO3); 1283 if (clear_gcp_auto == 1) 1284 val &= ~HDMI_FC_DATAUTO3_GCP_AUTO; 1285 else 1286 val |= HDMI_FC_DATAUTO3_GCP_AUTO; 1287 hdmi_writeb(hdmi, val, HDMI_FC_DATAUTO3); 1288 1289 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1290 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1291 1292 /* Data from pixel repeater block */ 1293 if (hdmi_data->pix_repet_factor > 1) { 1294 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1295 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1296 } else { /* data from packetizer block */ 1297 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1298 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1299 } 1300 1301 hdmi_modb(hdmi, vp_conf, 1302 HDMI_VP_CONF_PR_EN_MASK | 1303 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1304 1305 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1306 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1307 1308 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1309 1310 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1311 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1312 HDMI_VP_CONF_PP_EN_ENABLE | 1313 HDMI_VP_CONF_YCC422_EN_DISABLE; 1314 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1315 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1316 HDMI_VP_CONF_PP_EN_DISABLE | 1317 HDMI_VP_CONF_YCC422_EN_ENABLE; 1318 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1319 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1320 HDMI_VP_CONF_PP_EN_DISABLE | 1321 HDMI_VP_CONF_YCC422_EN_DISABLE; 1322 } else { 1323 return; 1324 } 1325 1326 hdmi_modb(hdmi, vp_conf, 1327 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1328 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1329 1330 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1331 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1332 HDMI_VP_STUFF_PP_STUFFING_MASK | 1333 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1334 1335 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1336 HDMI_VP_CONF); 1337 } 1338 1339 /* ----------------------------------------------------------------------------- 1340 * Synopsys PHY Handling 1341 */ 1342 1343 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 1344 unsigned char bit) 1345 { 1346 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 1347 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 1348 } 1349 1350 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 1351 { 1352 u32 val; 1353 1354 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 1355 if (msec-- == 0) 1356 return false; 1357 udelay(1000); 1358 } 1359 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1360 1361 return true; 1362 } 1363 1364 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1365 unsigned char addr) 1366 { 1367 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1368 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1369 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1370 HDMI_PHY_I2CM_DATAO_1_ADDR); 1371 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1372 HDMI_PHY_I2CM_DATAO_0_ADDR); 1373 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1374 HDMI_PHY_I2CM_OPERATION_ADDR); 1375 hdmi_phy_wait_i2c_done(hdmi, 1000); 1376 } 1377 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1378 1379 /* Filter out invalid setups to avoid configuring SCDC and scrambling */ 1380 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi, 1381 const struct drm_display_info *display) 1382 { 1383 /* Completely disable SCDC support for older controllers */ 1384 if (hdmi->version < 0x200a) 1385 return false; 1386 1387 /* Disable if no DDC bus */ 1388 if (!hdmi->ddc) 1389 return false; 1390 1391 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ 1392 if (!display->hdmi.scdc.supported || 1393 !display->hdmi.scdc.scrambling.supported) 1394 return false; 1395 1396 /* 1397 * Disable if display only support low TMDS rates and scrambling 1398 * for low rates is not supported either 1399 */ 1400 if (!display->hdmi.scdc.scrambling.low_rates && 1401 display->max_tmds_clock <= 340000) 1402 return false; 1403 1404 return true; 1405 } 1406 1407 /* 1408 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: 1409 * - The Source shall suspend transmission of the TMDS clock and data 1410 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it 1411 * from a 0 to a 1 or from a 1 to a 0 1412 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from 1413 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming 1414 * transmission of TMDS clock and data 1415 * 1416 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() 1417 * helper should called right before enabling the TMDS Clock and Data in 1418 * the PHY configuration callback. 1419 */ 1420 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi, 1421 const struct drm_display_info *display) 1422 { 1423 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1424 1425 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 1426 if (dw_hdmi_support_scdc(hdmi, display)) { 1427 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1428 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1); 1429 else 1430 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0); 1431 } 1432 } 1433 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); 1434 1435 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1436 { 1437 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1438 HDMI_PHY_CONF0_PDZ_OFFSET, 1439 HDMI_PHY_CONF0_PDZ_MASK); 1440 } 1441 1442 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1443 { 1444 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1445 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1446 HDMI_PHY_CONF0_ENTMDS_MASK); 1447 } 1448 1449 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1450 { 1451 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1452 HDMI_PHY_CONF0_SVSRET_OFFSET, 1453 HDMI_PHY_CONF0_SVSRET_MASK); 1454 } 1455 1456 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1457 { 1458 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1459 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1460 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1461 } 1462 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1463 1464 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1465 { 1466 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1467 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1468 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1469 } 1470 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1471 1472 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1473 { 1474 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1475 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1476 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1477 } 1478 1479 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1480 { 1481 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1482 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1483 HDMI_PHY_CONF0_SELDIPIF_MASK); 1484 } 1485 1486 void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi) 1487 { 1488 /* PHY reset. The reset signal is active low on Gen1 PHYs. */ 1489 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1490 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1491 } 1492 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset); 1493 1494 void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi) 1495 { 1496 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1497 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1498 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1499 } 1500 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset); 1501 1502 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1503 { 1504 hdmi_phy_test_clear(hdmi, 1); 1505 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1506 hdmi_phy_test_clear(hdmi, 0); 1507 } 1508 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1509 1510 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1511 { 1512 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1513 unsigned int i; 1514 u16 val; 1515 1516 if (phy->gen == 1) { 1517 dw_hdmi_phy_enable_tmds(hdmi, 0); 1518 dw_hdmi_phy_enable_powerdown(hdmi, true); 1519 return; 1520 } 1521 1522 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1523 1524 /* 1525 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1526 * to low power mode. 1527 */ 1528 for (i = 0; i < 5; ++i) { 1529 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1530 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1531 break; 1532 1533 usleep_range(1000, 2000); 1534 } 1535 1536 if (val & HDMI_PHY_TX_PHY_LOCK) 1537 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1538 else 1539 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1540 1541 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1542 } 1543 1544 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1545 { 1546 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1547 unsigned int i; 1548 u8 val; 1549 1550 if (phy->gen == 1) { 1551 dw_hdmi_phy_enable_powerdown(hdmi, false); 1552 1553 /* Toggle TMDS enable. */ 1554 dw_hdmi_phy_enable_tmds(hdmi, 0); 1555 dw_hdmi_phy_enable_tmds(hdmi, 1); 1556 return 0; 1557 } 1558 1559 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1560 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1561 1562 /* Wait for PHY PLL lock */ 1563 for (i = 0; i < 5; ++i) { 1564 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1565 if (val) 1566 break; 1567 1568 usleep_range(1000, 2000); 1569 } 1570 1571 if (!val) { 1572 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1573 return -ETIMEDOUT; 1574 } 1575 1576 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1577 return 0; 1578 } 1579 1580 /* 1581 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1582 * information the DWC MHL PHY has the same register layout and is thus also 1583 * supported by this function. 1584 */ 1585 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1586 const struct dw_hdmi_plat_data *pdata, 1587 unsigned long mpixelclock) 1588 { 1589 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1590 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1591 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1592 1593 /* TOFIX Will need 420 specific PHY configuration tables */ 1594 1595 /* PLL/MPLL Cfg - always match on final entry */ 1596 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1597 if (mpixelclock <= mpll_config->mpixelclock) 1598 break; 1599 1600 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1601 if (mpixelclock <= curr_ctrl->mpixelclock) 1602 break; 1603 1604 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1605 if (mpixelclock <= phy_config->mpixelclock) 1606 break; 1607 1608 if (mpll_config->mpixelclock == ~0UL || 1609 curr_ctrl->mpixelclock == ~0UL || 1610 phy_config->mpixelclock == ~0UL) 1611 return -EINVAL; 1612 1613 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1614 HDMI_3D_TX_PHY_CPCE_CTRL); 1615 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1616 HDMI_3D_TX_PHY_GMPCTRL); 1617 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1618 HDMI_3D_TX_PHY_CURRCTRL); 1619 1620 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1621 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1622 HDMI_3D_TX_PHY_MSM_CTRL); 1623 1624 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1625 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1626 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1627 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1628 HDMI_3D_TX_PHY_VLEVCTRL); 1629 1630 /* Override and disable clock termination. */ 1631 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1632 HDMI_3D_TX_PHY_CKCALCTRL); 1633 1634 return 0; 1635 } 1636 1637 static int hdmi_phy_configure(struct dw_hdmi *hdmi, 1638 const struct drm_display_info *display) 1639 { 1640 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1641 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1642 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1643 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1644 int ret; 1645 1646 dw_hdmi_phy_power_off(hdmi); 1647 1648 dw_hdmi_set_high_tmds_clock_ratio(hdmi, display); 1649 1650 /* Leave low power consumption mode by asserting SVSRET. */ 1651 if (phy->has_svsret) 1652 dw_hdmi_phy_enable_svsret(hdmi, 1); 1653 1654 dw_hdmi_phy_gen2_reset(hdmi); 1655 1656 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1657 1658 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1659 1660 /* Write to the PHY as configured by the platform */ 1661 if (pdata->configure_phy) 1662 ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock); 1663 else 1664 ret = phy->configure(hdmi, pdata, mpixelclock); 1665 if (ret) { 1666 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1667 mpixelclock); 1668 return ret; 1669 } 1670 1671 /* Wait for resuming transmission of TMDS clock and data */ 1672 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1673 msleep(100); 1674 1675 return dw_hdmi_phy_power_on(hdmi); 1676 } 1677 1678 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1679 const struct drm_display_info *display, 1680 const struct drm_display_mode *mode) 1681 { 1682 int i, ret; 1683 1684 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1685 for (i = 0; i < 2; i++) { 1686 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1687 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1688 1689 ret = hdmi_phy_configure(hdmi, display); 1690 if (ret) 1691 return ret; 1692 } 1693 1694 return 0; 1695 } 1696 1697 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1698 { 1699 dw_hdmi_phy_power_off(hdmi); 1700 } 1701 1702 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1703 void *data) 1704 { 1705 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1706 connector_status_connected : connector_status_disconnected; 1707 } 1708 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1709 1710 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1711 bool force, bool disabled, bool rxsense) 1712 { 1713 u8 old_mask = hdmi->phy_mask; 1714 1715 if (force || disabled || !rxsense) 1716 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1717 else 1718 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1719 1720 if (old_mask != hdmi->phy_mask) 1721 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1722 } 1723 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1724 1725 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1726 { 1727 /* 1728 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1729 * any pending interrupt. 1730 */ 1731 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1732 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1733 HDMI_IH_PHY_STAT0); 1734 1735 /* Enable cable hot plug irq. */ 1736 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1737 1738 /* Clear and unmute interrupts. */ 1739 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1740 HDMI_IH_PHY_STAT0); 1741 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1742 HDMI_IH_MUTE_PHY_STAT0); 1743 } 1744 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1745 1746 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1747 .init = dw_hdmi_phy_init, 1748 .disable = dw_hdmi_phy_disable, 1749 .read_hpd = dw_hdmi_phy_read_hpd, 1750 .update_hpd = dw_hdmi_phy_update_hpd, 1751 .setup_hpd = dw_hdmi_phy_setup_hpd, 1752 }; 1753 1754 /* ----------------------------------------------------------------------------- 1755 * HDMI TX Setup 1756 */ 1757 1758 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1759 { 1760 u8 de; 1761 1762 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1763 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1764 else 1765 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1766 1767 /* disable rx detect */ 1768 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1769 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1770 1771 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1772 1773 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1774 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1775 } 1776 1777 static void hdmi_config_AVI(struct dw_hdmi *hdmi, 1778 const struct drm_connector *connector, 1779 const struct drm_display_mode *mode) 1780 { 1781 struct hdmi_avi_infoframe frame; 1782 u8 val; 1783 1784 /* Initialise info frame from DRM mode */ 1785 drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1786 1787 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 1788 drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode, 1789 hdmi->hdmi_data.rgb_limited_range ? 1790 HDMI_QUANTIZATION_RANGE_LIMITED : 1791 HDMI_QUANTIZATION_RANGE_FULL); 1792 } else { 1793 frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 1794 frame.ycc_quantization_range = 1795 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 1796 } 1797 1798 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1799 frame.colorspace = HDMI_COLORSPACE_YUV444; 1800 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1801 frame.colorspace = HDMI_COLORSPACE_YUV422; 1802 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1803 frame.colorspace = HDMI_COLORSPACE_YUV420; 1804 else 1805 frame.colorspace = HDMI_COLORSPACE_RGB; 1806 1807 /* Set up colorimetry */ 1808 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 1809 switch (hdmi->hdmi_data.enc_out_encoding) { 1810 case V4L2_YCBCR_ENC_601: 1811 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1812 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1813 else 1814 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1815 frame.extended_colorimetry = 1816 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1817 break; 1818 case V4L2_YCBCR_ENC_709: 1819 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1820 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1821 else 1822 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1823 frame.extended_colorimetry = 1824 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1825 break; 1826 default: /* Carries no data */ 1827 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1828 frame.extended_colorimetry = 1829 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1830 break; 1831 } 1832 } else { 1833 frame.colorimetry = HDMI_COLORIMETRY_NONE; 1834 frame.extended_colorimetry = 1835 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1836 } 1837 1838 /* 1839 * The Designware IP uses a different byte format from standard 1840 * AVI info frames, though generally the bits are in the correct 1841 * bytes. 1842 */ 1843 1844 /* 1845 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1846 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1847 * bit 6 rather than 4. 1848 */ 1849 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1850 if (frame.active_aspect & 15) 1851 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1852 if (frame.top_bar || frame.bottom_bar) 1853 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1854 if (frame.left_bar || frame.right_bar) 1855 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1856 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1857 1858 /* AVI data byte 2 differences: none */ 1859 val = ((frame.colorimetry & 0x3) << 6) | 1860 ((frame.picture_aspect & 0x3) << 4) | 1861 (frame.active_aspect & 0xf); 1862 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1863 1864 /* AVI data byte 3 differences: none */ 1865 val = ((frame.extended_colorimetry & 0x7) << 4) | 1866 ((frame.quantization_range & 0x3) << 2) | 1867 (frame.nups & 0x3); 1868 if (frame.itc) 1869 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1870 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1871 1872 /* AVI data byte 4 differences: none */ 1873 val = frame.video_code & 0x7f; 1874 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1875 1876 /* AVI Data Byte 5- set up input and output pixel repetition */ 1877 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1878 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1879 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1880 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1881 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1882 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1883 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1884 1885 /* 1886 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1887 * ycc range in bits 2,3 rather than 6,7 1888 */ 1889 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1890 (frame.content_type & 0x3); 1891 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1892 1893 /* AVI Data Bytes 6-13 */ 1894 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1895 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1896 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1897 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1898 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1899 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1900 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1901 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1902 } 1903 1904 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1905 const struct drm_connector *connector, 1906 const struct drm_display_mode *mode) 1907 { 1908 struct hdmi_vendor_infoframe frame; 1909 u8 buffer[10]; 1910 ssize_t err; 1911 1912 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, connector, 1913 mode); 1914 if (err < 0) 1915 /* 1916 * Going into that statement does not means vendor infoframe 1917 * fails. It just informed us that vendor infoframe is not 1918 * needed for the selected mode. Only 4k or stereoscopic 3D 1919 * mode requires vendor infoframe. So just simply return. 1920 */ 1921 return; 1922 1923 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1924 if (err < 0) { 1925 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1926 err); 1927 return; 1928 } 1929 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1930 HDMI_FC_DATAUTO0_VSD_MASK); 1931 1932 /* Set the length of HDMI vendor specific InfoFrame payload */ 1933 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1934 1935 /* Set 24bit IEEE Registration Identifier */ 1936 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1937 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1938 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1939 1940 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1941 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1942 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1943 1944 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1945 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1946 1947 /* Packet frame interpolation */ 1948 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1949 1950 /* Auto packets per frame and line spacing */ 1951 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1952 1953 /* Configures the Frame Composer On RDRB mode */ 1954 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1955 HDMI_FC_DATAUTO0_VSD_MASK); 1956 } 1957 1958 static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, 1959 const struct drm_connector *connector) 1960 { 1961 const struct drm_connector_state *conn_state = connector->state; 1962 struct hdmi_drm_infoframe frame; 1963 u8 buffer[30]; 1964 ssize_t err; 1965 int i; 1966 1967 if (!hdmi->plat_data->use_drm_infoframe) 1968 return; 1969 1970 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE, 1971 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1972 1973 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state); 1974 if (err < 0) 1975 return; 1976 1977 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer)); 1978 if (err < 0) { 1979 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err); 1980 return; 1981 } 1982 1983 hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0); 1984 hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1); 1985 1986 for (i = 0; i < frame.length; i++) 1987 hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i); 1988 1989 hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP); 1990 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE, 1991 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1992 } 1993 1994 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1995 const struct drm_display_info *display, 1996 const struct drm_display_mode *mode) 1997 { 1998 u8 inv_val, bytes; 1999 const struct drm_hdmi_info *hdmi_info = &display->hdmi; 2000 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 2001 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 2002 unsigned int vdisplay, hdisplay; 2003 2004 vmode->mpixelclock = mode->clock * 1000; 2005 2006 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 2007 2008 vmode->mtmdsclock = vmode->mpixelclock; 2009 2010 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 2011 switch (hdmi_bus_fmt_color_depth( 2012 hdmi->hdmi_data.enc_out_bus_format)) { 2013 case 16: 2014 vmode->mtmdsclock = vmode->mpixelclock * 2; 2015 break; 2016 case 12: 2017 vmode->mtmdsclock = vmode->mpixelclock * 3 / 2; 2018 break; 2019 case 10: 2020 vmode->mtmdsclock = vmode->mpixelclock * 5 / 4; 2021 break; 2022 } 2023 } 2024 2025 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 2026 vmode->mtmdsclock /= 2; 2027 2028 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock); 2029 2030 /* Set up HDMI_FC_INVIDCONF */ 2031 inv_val = (hdmi->hdmi_data.hdcp_enable || 2032 (dw_hdmi_support_scdc(hdmi, display) && 2033 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 2034 hdmi_info->scdc.scrambling.low_rates)) ? 2035 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 2036 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 2037 2038 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 2039 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 2040 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 2041 2042 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 2043 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 2044 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 2045 2046 inv_val |= (vmode->mdataenablepolarity ? 2047 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 2048 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 2049 2050 if (hdmi->vic == 39) 2051 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 2052 else 2053 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 2054 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 2055 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 2056 2057 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 2058 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 2059 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 2060 2061 inv_val |= hdmi->sink_is_hdmi ? 2062 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 2063 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 2064 2065 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 2066 2067 hdisplay = mode->hdisplay; 2068 hblank = mode->htotal - mode->hdisplay; 2069 h_de_hs = mode->hsync_start - mode->hdisplay; 2070 hsync_len = mode->hsync_end - mode->hsync_start; 2071 2072 /* 2073 * When we're setting a YCbCr420 mode, we need 2074 * to adjust the horizontal timing to suit. 2075 */ 2076 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 2077 hdisplay /= 2; 2078 hblank /= 2; 2079 h_de_hs /= 2; 2080 hsync_len /= 2; 2081 } 2082 2083 vdisplay = mode->vdisplay; 2084 vblank = mode->vtotal - mode->vdisplay; 2085 v_de_vs = mode->vsync_start - mode->vdisplay; 2086 vsync_len = mode->vsync_end - mode->vsync_start; 2087 2088 /* 2089 * When we're setting an interlaced mode, we need 2090 * to adjust the vertical timing to suit. 2091 */ 2092 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 2093 vdisplay /= 2; 2094 vblank /= 2; 2095 v_de_vs /= 2; 2096 vsync_len /= 2; 2097 } 2098 2099 /* Scrambling Control */ 2100 if (dw_hdmi_support_scdc(hdmi, display)) { 2101 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 2102 hdmi_info->scdc.scrambling.low_rates) { 2103 /* 2104 * HDMI2.0 Specifies the following procedure: 2105 * After the Source Device has determined that 2106 * SCDC_Present is set (=1), the Source Device should 2107 * write the accurate Version of the Source Device 2108 * to the Source Version field in the SCDCS. 2109 * Source Devices compliant shall set the 2110 * Source Version = 1. 2111 */ 2112 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, 2113 &bytes); 2114 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, 2115 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 2116 2117 /* Enabled Scrambling in the Sink */ 2118 drm_scdc_set_scrambling(hdmi->ddc, 1); 2119 2120 /* 2121 * To activate the scrambler feature, you must ensure 2122 * that the quasi-static configuration bit 2123 * fc_invidconf.HDCP_keepout is set at configuration 2124 * time, before the required mc_swrstzreq.tmdsswrst_req 2125 * reset request is issued. 2126 */ 2127 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 2128 HDMI_MC_SWRSTZ); 2129 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 2130 } else { 2131 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 2132 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 2133 HDMI_MC_SWRSTZ); 2134 drm_scdc_set_scrambling(hdmi->ddc, 0); 2135 } 2136 } 2137 2138 /* Set up horizontal active pixel width */ 2139 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 2140 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 2141 2142 /* Set up vertical active lines */ 2143 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 2144 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 2145 2146 /* Set up horizontal blanking pixel region width */ 2147 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 2148 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 2149 2150 /* Set up vertical blanking pixel region width */ 2151 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 2152 2153 /* Set up HSYNC active edge delay width (in pixel clks) */ 2154 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 2155 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 2156 2157 /* Set up VSYNC active edge delay (in lines) */ 2158 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 2159 2160 /* Set up HSYNC active pulse width (in pixel clks) */ 2161 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 2162 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 2163 2164 /* Set up VSYNC active edge delay (in lines) */ 2165 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 2166 } 2167 2168 /* HDMI Initialization Step B.4 */ 2169 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 2170 { 2171 /* control period minimum duration */ 2172 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 2173 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 2174 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 2175 2176 /* Set to fill TMDS data channels */ 2177 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 2178 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 2179 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 2180 2181 /* Enable pixel clock and tmds data path */ 2182 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 2183 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 2184 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 2185 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 2186 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 2187 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 2188 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2189 2190 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 2191 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2192 2193 /* Enable csc path */ 2194 if (is_csc_needed(hdmi)) { 2195 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 2196 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2197 2198 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 2199 HDMI_MC_FLOWCTRL); 2200 } else { 2201 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE; 2202 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2203 2204 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 2205 HDMI_MC_FLOWCTRL); 2206 } 2207 } 2208 2209 /* Workaround to clear the overflow condition */ 2210 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 2211 { 2212 unsigned int count; 2213 unsigned int i; 2214 u8 val; 2215 2216 /* 2217 * Under some circumstances the Frame Composer arithmetic unit can miss 2218 * an FC register write due to being busy processing the previous one. 2219 * The issue can be worked around by issuing a TMDS software reset and 2220 * then write one of the FC registers several times. 2221 * 2222 * The number of iterations matters and depends on the HDMI TX revision 2223 * (and possibly on the platform). 2224 * 4 iterations for i.MX6Q(v1.30a) and 1 iteration for others. 2225 * i.MX6DL (v1.31a), Allwinner SoCs (v1.32a), Rockchip RK3288 SoC (v2.00a), 2226 * Amlogic Meson GX SoCs (v2.01a), RK3328/RK3399 SoCs (v2.11a) 2227 * and i.MX8MPlus (v2.13a) have been identified as needing the workaround 2228 * with a single iteration. 2229 */ 2230 2231 switch (hdmi->version) { 2232 case 0x130a: 2233 count = 4; 2234 break; 2235 default: 2236 count = 1; 2237 break; 2238 } 2239 2240 /* TMDS software reset */ 2241 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 2242 2243 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 2244 for (i = 0; i < count; i++) 2245 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 2246 } 2247 2248 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 2249 { 2250 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 2251 HDMI_IH_MUTE_FC_STAT2); 2252 } 2253 2254 static int dw_hdmi_setup(struct dw_hdmi *hdmi, 2255 const struct drm_connector *connector, 2256 const struct drm_display_mode *mode) 2257 { 2258 int ret; 2259 2260 hdmi_disable_overflow_interrupts(hdmi); 2261 2262 hdmi->vic = drm_match_cea_mode(mode); 2263 2264 if (!hdmi->vic) { 2265 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 2266 } else { 2267 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 2268 } 2269 2270 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 2271 (hdmi->vic == 21) || (hdmi->vic == 22) || 2272 (hdmi->vic == 2) || (hdmi->vic == 3) || 2273 (hdmi->vic == 17) || (hdmi->vic == 18)) 2274 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2275 else 2276 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2277 2278 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2279 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2280 2281 if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED) 2282 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2283 2284 /* TOFIX: Get input encoding from plat data or fallback to none */ 2285 if (hdmi->plat_data->input_bus_encoding) 2286 hdmi->hdmi_data.enc_in_encoding = 2287 hdmi->plat_data->input_bus_encoding; 2288 else 2289 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2290 2291 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED) 2292 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2293 2294 hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi && 2295 drm_default_rgb_quant_range(mode) == 2296 HDMI_QUANTIZATION_RANGE_LIMITED; 2297 2298 hdmi->hdmi_data.pix_repet_factor = 0; 2299 hdmi->hdmi_data.hdcp_enable = 0; 2300 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2301 2302 /* HDMI Initialization Step B.1 */ 2303 hdmi_av_composer(hdmi, &connector->display_info, mode); 2304 2305 /* HDMI Initializateion Step B.2 */ 2306 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, 2307 &connector->display_info, 2308 &hdmi->previous_mode); 2309 if (ret) 2310 return ret; 2311 hdmi->phy.enabled = true; 2312 2313 /* HDMI Initialization Step B.3 */ 2314 dw_hdmi_enable_video_path(hdmi); 2315 2316 if (hdmi->sink_has_audio) { 2317 dev_dbg(hdmi->dev, "sink has audio support\n"); 2318 2319 /* HDMI Initialization Step E - Configure audio */ 2320 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2321 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable); 2322 } 2323 2324 /* not for DVI mode */ 2325 if (hdmi->sink_is_hdmi) { 2326 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 2327 2328 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2329 hdmi_config_AVI(hdmi, connector, mode); 2330 hdmi_config_vendor_specific_infoframe(hdmi, connector, mode); 2331 hdmi_config_drm_infoframe(hdmi, connector); 2332 } else { 2333 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 2334 } 2335 2336 hdmi_video_packetize(hdmi); 2337 hdmi_video_csc(hdmi); 2338 hdmi_video_sample(hdmi); 2339 hdmi_tx_hdcp_config(hdmi); 2340 2341 dw_hdmi_clear_overflow(hdmi); 2342 2343 return 0; 2344 } 2345 2346 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 2347 { 2348 u8 ih_mute; 2349 2350 /* 2351 * Boot up defaults are: 2352 * HDMI_IH_MUTE = 0x03 (disabled) 2353 * HDMI_IH_MUTE_* = 0x00 (enabled) 2354 * 2355 * Disable top level interrupt bits in HDMI block 2356 */ 2357 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 2358 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2359 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 2360 2361 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2362 2363 /* by default mask all interrupts */ 2364 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 2365 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2366 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2367 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2368 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 2369 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 2370 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 2371 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 2372 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 2373 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 2374 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 2375 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 2376 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 2377 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 2378 2379 /* Disable interrupts in the IH_MUTE_* registers */ 2380 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2381 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2382 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2383 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2384 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 2385 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2386 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2387 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2388 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2389 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2390 2391 /* Enable top level interrupt bits in HDMI block */ 2392 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2393 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 2394 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2395 } 2396 2397 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 2398 { 2399 hdmi->bridge_is_on = true; 2400 2401 /* 2402 * The curr_conn field is guaranteed to be valid here, as this function 2403 * is only be called when !hdmi->disabled. 2404 */ 2405 dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); 2406 } 2407 2408 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 2409 { 2410 if (hdmi->phy.enabled) { 2411 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 2412 hdmi->phy.enabled = false; 2413 } 2414 2415 hdmi->bridge_is_on = false; 2416 } 2417 2418 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 2419 { 2420 int force = hdmi->force; 2421 2422 if (hdmi->disabled) { 2423 force = DRM_FORCE_OFF; 2424 } else if (force == DRM_FORCE_UNSPECIFIED) { 2425 if (hdmi->rxsense) 2426 force = DRM_FORCE_ON; 2427 else 2428 force = DRM_FORCE_OFF; 2429 } 2430 2431 if (force == DRM_FORCE_OFF) { 2432 if (hdmi->bridge_is_on) 2433 dw_hdmi_poweroff(hdmi); 2434 } else { 2435 if (!hdmi->bridge_is_on) 2436 dw_hdmi_poweron(hdmi); 2437 } 2438 } 2439 2440 /* 2441 * Adjust the detection of RXSENSE according to whether we have a forced 2442 * connection mode enabled, or whether we have been disabled. There is 2443 * no point processing RXSENSE interrupts if we have a forced connection 2444 * state, or DRM has us disabled. 2445 * 2446 * We also disable rxsense interrupts when we think we're disconnected 2447 * to avoid floating TDMS signals giving false rxsense interrupts. 2448 * 2449 * Note: we still need to listen for HPD interrupts even when DRM has us 2450 * disabled so that we can detect a connect event. 2451 */ 2452 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 2453 { 2454 if (hdmi->phy.ops->update_hpd) 2455 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 2456 hdmi->force, hdmi->disabled, 2457 hdmi->rxsense); 2458 } 2459 2460 static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi) 2461 { 2462 enum drm_connector_status result; 2463 2464 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 2465 2466 mutex_lock(&hdmi->mutex); 2467 if (result != hdmi->last_connector_result) { 2468 dev_dbg(hdmi->dev, "read_hpd result: %d", result); 2469 handle_plugged_change(hdmi, 2470 result == connector_status_connected); 2471 hdmi->last_connector_result = result; 2472 } 2473 mutex_unlock(&hdmi->mutex); 2474 2475 return result; 2476 } 2477 2478 static struct edid *dw_hdmi_get_edid(struct dw_hdmi *hdmi, 2479 struct drm_connector *connector) 2480 { 2481 struct edid *edid; 2482 2483 if (!hdmi->ddc) 2484 return NULL; 2485 2486 edid = drm_get_edid(connector, hdmi->ddc); 2487 if (!edid) { 2488 dev_dbg(hdmi->dev, "failed to get edid\n"); 2489 return NULL; 2490 } 2491 2492 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 2493 edid->width_cm, edid->height_cm); 2494 2495 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 2496 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2497 2498 return edid; 2499 } 2500 2501 /* ----------------------------------------------------------------------------- 2502 * DRM Connector Operations 2503 */ 2504 2505 static enum drm_connector_status 2506 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 2507 { 2508 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2509 connector); 2510 return dw_hdmi_detect(hdmi); 2511 } 2512 2513 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 2514 { 2515 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2516 connector); 2517 struct edid *edid; 2518 int ret; 2519 2520 edid = dw_hdmi_get_edid(hdmi, connector); 2521 if (!edid) 2522 return 0; 2523 2524 drm_connector_update_edid_property(connector, edid); 2525 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); 2526 ret = drm_add_edid_modes(connector, edid); 2527 kfree(edid); 2528 2529 return ret; 2530 } 2531 2532 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, 2533 struct drm_atomic_state *state) 2534 { 2535 struct drm_connector_state *old_state = 2536 drm_atomic_get_old_connector_state(state, connector); 2537 struct drm_connector_state *new_state = 2538 drm_atomic_get_new_connector_state(state, connector); 2539 struct drm_crtc *crtc = new_state->crtc; 2540 struct drm_crtc_state *crtc_state; 2541 2542 if (!crtc) 2543 return 0; 2544 2545 if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 2546 crtc_state = drm_atomic_get_crtc_state(state, crtc); 2547 if (IS_ERR(crtc_state)) 2548 return PTR_ERR(crtc_state); 2549 2550 crtc_state->mode_changed = true; 2551 } 2552 2553 return 0; 2554 } 2555 2556 static void dw_hdmi_connector_force(struct drm_connector *connector) 2557 { 2558 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2559 connector); 2560 2561 mutex_lock(&hdmi->mutex); 2562 hdmi->force = connector->force; 2563 dw_hdmi_update_power(hdmi); 2564 dw_hdmi_update_phy_mask(hdmi); 2565 mutex_unlock(&hdmi->mutex); 2566 } 2567 2568 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 2569 .fill_modes = drm_helper_probe_single_connector_modes, 2570 .detect = dw_hdmi_connector_detect, 2571 .destroy = drm_connector_cleanup, 2572 .force = dw_hdmi_connector_force, 2573 .reset = drm_atomic_helper_connector_reset, 2574 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2575 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2576 }; 2577 2578 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 2579 .get_modes = dw_hdmi_connector_get_modes, 2580 .atomic_check = dw_hdmi_connector_atomic_check, 2581 }; 2582 2583 static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) 2584 { 2585 struct drm_connector *connector = &hdmi->connector; 2586 struct cec_connector_info conn_info; 2587 struct cec_notifier *notifier; 2588 2589 if (hdmi->version >= 0x200a) 2590 connector->ycbcr_420_allowed = 2591 hdmi->plat_data->ycbcr_420_allowed; 2592 else 2593 connector->ycbcr_420_allowed = false; 2594 2595 connector->interlace_allowed = 1; 2596 connector->polled = DRM_CONNECTOR_POLL_HPD; 2597 2598 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 2599 2600 drm_connector_init_with_ddc(hdmi->bridge.dev, connector, 2601 &dw_hdmi_connector_funcs, 2602 DRM_MODE_CONNECTOR_HDMIA, 2603 hdmi->ddc); 2604 2605 /* 2606 * drm_connector_attach_max_bpc_property() requires the 2607 * connector to have a state. 2608 */ 2609 drm_atomic_helper_connector_reset(connector); 2610 2611 drm_connector_attach_max_bpc_property(connector, 8, 16); 2612 2613 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) 2614 drm_connector_attach_hdr_output_metadata_property(connector); 2615 2616 drm_connector_attach_encoder(connector, hdmi->bridge.encoder); 2617 2618 cec_fill_conn_info_from_drm(&conn_info, connector); 2619 2620 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info); 2621 if (!notifier) 2622 return -ENOMEM; 2623 2624 mutex_lock(&hdmi->cec_notifier_mutex); 2625 hdmi->cec_notifier = notifier; 2626 mutex_unlock(&hdmi->cec_notifier_mutex); 2627 2628 return 0; 2629 } 2630 2631 /* ----------------------------------------------------------------------------- 2632 * DRM Bridge Operations 2633 */ 2634 2635 /* 2636 * Possible output formats : 2637 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48, 2638 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36, 2639 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30, 2640 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24, 2641 * - MEDIA_BUS_FMT_YUV16_1X48, 2642 * - MEDIA_BUS_FMT_RGB161616_1X48, 2643 * - MEDIA_BUS_FMT_UYVY12_1X24, 2644 * - MEDIA_BUS_FMT_YUV12_1X36, 2645 * - MEDIA_BUS_FMT_RGB121212_1X36, 2646 * - MEDIA_BUS_FMT_UYVY10_1X20, 2647 * - MEDIA_BUS_FMT_YUV10_1X30, 2648 * - MEDIA_BUS_FMT_RGB101010_1X30, 2649 * - MEDIA_BUS_FMT_UYVY8_1X16, 2650 * - MEDIA_BUS_FMT_YUV8_1X24, 2651 * - MEDIA_BUS_FMT_RGB888_1X24, 2652 */ 2653 2654 /* Can return a maximum of 11 possible output formats for a mode/connector */ 2655 #define MAX_OUTPUT_SEL_FORMATS 11 2656 2657 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 2658 struct drm_bridge_state *bridge_state, 2659 struct drm_crtc_state *crtc_state, 2660 struct drm_connector_state *conn_state, 2661 unsigned int *num_output_fmts) 2662 { 2663 struct drm_connector *conn = conn_state->connector; 2664 struct drm_display_info *info = &conn->display_info; 2665 struct drm_display_mode *mode = &crtc_state->mode; 2666 u8 max_bpc = conn_state->max_requested_bpc; 2667 bool is_hdmi2_sink = info->hdmi.scdc.supported || 2668 (info->color_formats & DRM_COLOR_FORMAT_YCBCR420); 2669 u32 *output_fmts; 2670 unsigned int i = 0; 2671 2672 *num_output_fmts = 0; 2673 2674 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), 2675 GFP_KERNEL); 2676 if (!output_fmts) 2677 return NULL; 2678 2679 /* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */ 2680 if (list_is_singular(&bridge->encoder->bridge_chain) || 2681 list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) { 2682 *num_output_fmts = 1; 2683 output_fmts[0] = MEDIA_BUS_FMT_FIXED; 2684 2685 return output_fmts; 2686 } 2687 2688 /* 2689 * If the current mode enforces 4:2:0, force the output but format 2690 * to 4:2:0 and do not add the YUV422/444/RGB formats 2691 */ 2692 if (conn->ycbcr_420_allowed && 2693 (drm_mode_is_420_only(info, mode) || 2694 (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) { 2695 2696 /* Order bus formats from 16bit to 8bit if supported */ 2697 if (max_bpc >= 16 && info->bpc == 16 && 2698 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)) 2699 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48; 2700 2701 if (max_bpc >= 12 && info->bpc >= 12 && 2702 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) 2703 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36; 2704 2705 if (max_bpc >= 10 && info->bpc >= 10 && 2706 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)) 2707 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30; 2708 2709 /* Default 8bit fallback */ 2710 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; 2711 2712 *num_output_fmts = i; 2713 2714 return output_fmts; 2715 } 2716 2717 /* 2718 * Order bus formats from 16bit to 8bit and from YUV422 to RGB 2719 * if supported. In any case the default RGB888 format is added 2720 */ 2721 2722 if (max_bpc >= 16 && info->bpc == 16) { 2723 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2724 output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2725 2726 output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2727 } 2728 2729 if (max_bpc >= 12 && info->bpc >= 12) { 2730 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) 2731 output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2732 2733 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2734 output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2735 2736 output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2737 } 2738 2739 if (max_bpc >= 10 && info->bpc >= 10) { 2740 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) 2741 output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2742 2743 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2744 output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2745 2746 output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2747 } 2748 2749 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) 2750 output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2751 2752 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2753 output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2754 2755 /* Default 8bit RGB fallback */ 2756 output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2757 2758 *num_output_fmts = i; 2759 2760 return output_fmts; 2761 } 2762 2763 /* 2764 * Possible input formats : 2765 * - MEDIA_BUS_FMT_RGB888_1X24 2766 * - MEDIA_BUS_FMT_YUV8_1X24 2767 * - MEDIA_BUS_FMT_UYVY8_1X16 2768 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24 2769 * - MEDIA_BUS_FMT_RGB101010_1X30 2770 * - MEDIA_BUS_FMT_YUV10_1X30 2771 * - MEDIA_BUS_FMT_UYVY10_1X20 2772 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30 2773 * - MEDIA_BUS_FMT_RGB121212_1X36 2774 * - MEDIA_BUS_FMT_YUV12_1X36 2775 * - MEDIA_BUS_FMT_UYVY12_1X24 2776 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36 2777 * - MEDIA_BUS_FMT_RGB161616_1X48 2778 * - MEDIA_BUS_FMT_YUV16_1X48 2779 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48 2780 */ 2781 2782 /* Can return a maximum of 3 possible input formats for an output format */ 2783 #define MAX_INPUT_SEL_FORMATS 3 2784 2785 static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 2786 struct drm_bridge_state *bridge_state, 2787 struct drm_crtc_state *crtc_state, 2788 struct drm_connector_state *conn_state, 2789 u32 output_fmt, 2790 unsigned int *num_input_fmts) 2791 { 2792 u32 *input_fmts; 2793 unsigned int i = 0; 2794 2795 *num_input_fmts = 0; 2796 2797 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 2798 GFP_KERNEL); 2799 if (!input_fmts) 2800 return NULL; 2801 2802 switch (output_fmt) { 2803 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */ 2804 case MEDIA_BUS_FMT_FIXED: 2805 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2806 break; 2807 /* 8bit */ 2808 case MEDIA_BUS_FMT_RGB888_1X24: 2809 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2810 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2811 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2812 break; 2813 case MEDIA_BUS_FMT_YUV8_1X24: 2814 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2815 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2816 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2817 break; 2818 case MEDIA_BUS_FMT_UYVY8_1X16: 2819 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2820 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2821 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2822 break; 2823 2824 /* 10bit */ 2825 case MEDIA_BUS_FMT_RGB101010_1X30: 2826 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2827 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2828 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2829 break; 2830 case MEDIA_BUS_FMT_YUV10_1X30: 2831 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2832 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2833 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2834 break; 2835 case MEDIA_BUS_FMT_UYVY10_1X20: 2836 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2837 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2838 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2839 break; 2840 2841 /* 12bit */ 2842 case MEDIA_BUS_FMT_RGB121212_1X36: 2843 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2844 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2845 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2846 break; 2847 case MEDIA_BUS_FMT_YUV12_1X36: 2848 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2849 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2850 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2851 break; 2852 case MEDIA_BUS_FMT_UYVY12_1X24: 2853 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2854 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2855 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2856 break; 2857 2858 /* 16bit */ 2859 case MEDIA_BUS_FMT_RGB161616_1X48: 2860 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2861 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2862 break; 2863 case MEDIA_BUS_FMT_YUV16_1X48: 2864 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2865 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2866 break; 2867 2868 /*YUV 4:2:0 */ 2869 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2870 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2871 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 2872 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 2873 input_fmts[i++] = output_fmt; 2874 break; 2875 } 2876 2877 *num_input_fmts = i; 2878 2879 if (*num_input_fmts == 0) { 2880 kfree(input_fmts); 2881 input_fmts = NULL; 2882 } 2883 2884 return input_fmts; 2885 } 2886 2887 static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge, 2888 struct drm_bridge_state *bridge_state, 2889 struct drm_crtc_state *crtc_state, 2890 struct drm_connector_state *conn_state) 2891 { 2892 struct dw_hdmi *hdmi = bridge->driver_private; 2893 2894 hdmi->hdmi_data.enc_out_bus_format = 2895 bridge_state->output_bus_cfg.format; 2896 2897 hdmi->hdmi_data.enc_in_bus_format = 2898 bridge_state->input_bus_cfg.format; 2899 2900 dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n", 2901 bridge_state->input_bus_cfg.format, 2902 bridge_state->output_bus_cfg.format); 2903 2904 return 0; 2905 } 2906 2907 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge, 2908 enum drm_bridge_attach_flags flags) 2909 { 2910 struct dw_hdmi *hdmi = bridge->driver_private; 2911 2912 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 2913 return drm_bridge_attach(bridge->encoder, hdmi->next_bridge, 2914 bridge, flags); 2915 2916 return dw_hdmi_connector_create(hdmi); 2917 } 2918 2919 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge) 2920 { 2921 struct dw_hdmi *hdmi = bridge->driver_private; 2922 2923 mutex_lock(&hdmi->cec_notifier_mutex); 2924 cec_notifier_conn_unregister(hdmi->cec_notifier); 2925 hdmi->cec_notifier = NULL; 2926 mutex_unlock(&hdmi->cec_notifier_mutex); 2927 } 2928 2929 static enum drm_mode_status 2930 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 2931 const struct drm_display_info *info, 2932 const struct drm_display_mode *mode) 2933 { 2934 struct dw_hdmi *hdmi = bridge->driver_private; 2935 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 2936 enum drm_mode_status mode_status = MODE_OK; 2937 2938 /* We don't support double-clocked modes */ 2939 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2940 return MODE_BAD; 2941 2942 if (pdata->mode_valid) 2943 mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info, 2944 mode); 2945 2946 return mode_status; 2947 } 2948 2949 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2950 const struct drm_display_mode *orig_mode, 2951 const struct drm_display_mode *mode) 2952 { 2953 struct dw_hdmi *hdmi = bridge->driver_private; 2954 2955 mutex_lock(&hdmi->mutex); 2956 2957 /* Store the display mode for plugin/DKMS poweron events */ 2958 drm_mode_copy(&hdmi->previous_mode, mode); 2959 2960 mutex_unlock(&hdmi->mutex); 2961 } 2962 2963 static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, 2964 struct drm_bridge_state *old_state) 2965 { 2966 struct dw_hdmi *hdmi = bridge->driver_private; 2967 2968 mutex_lock(&hdmi->mutex); 2969 hdmi->disabled = true; 2970 hdmi->curr_conn = NULL; 2971 dw_hdmi_update_power(hdmi); 2972 dw_hdmi_update_phy_mask(hdmi); 2973 mutex_unlock(&hdmi->mutex); 2974 } 2975 2976 static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, 2977 struct drm_bridge_state *old_state) 2978 { 2979 struct dw_hdmi *hdmi = bridge->driver_private; 2980 struct drm_atomic_state *state = old_state->base.state; 2981 struct drm_connector *connector; 2982 2983 connector = drm_atomic_get_new_connector_for_encoder(state, 2984 bridge->encoder); 2985 2986 mutex_lock(&hdmi->mutex); 2987 hdmi->disabled = false; 2988 hdmi->curr_conn = connector; 2989 dw_hdmi_update_power(hdmi); 2990 dw_hdmi_update_phy_mask(hdmi); 2991 mutex_unlock(&hdmi->mutex); 2992 } 2993 2994 static enum drm_connector_status dw_hdmi_bridge_detect(struct drm_bridge *bridge) 2995 { 2996 struct dw_hdmi *hdmi = bridge->driver_private; 2997 2998 return dw_hdmi_detect(hdmi); 2999 } 3000 3001 static struct edid *dw_hdmi_bridge_get_edid(struct drm_bridge *bridge, 3002 struct drm_connector *connector) 3003 { 3004 struct dw_hdmi *hdmi = bridge->driver_private; 3005 3006 return dw_hdmi_get_edid(hdmi, connector); 3007 } 3008 3009 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 3010 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 3011 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 3012 .atomic_reset = drm_atomic_helper_bridge_reset, 3013 .attach = dw_hdmi_bridge_attach, 3014 .detach = dw_hdmi_bridge_detach, 3015 .atomic_check = dw_hdmi_bridge_atomic_check, 3016 .atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts, 3017 .atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts, 3018 .atomic_enable = dw_hdmi_bridge_atomic_enable, 3019 .atomic_disable = dw_hdmi_bridge_atomic_disable, 3020 .mode_set = dw_hdmi_bridge_mode_set, 3021 .mode_valid = dw_hdmi_bridge_mode_valid, 3022 .detect = dw_hdmi_bridge_detect, 3023 .get_edid = dw_hdmi_bridge_get_edid, 3024 }; 3025 3026 /* ----------------------------------------------------------------------------- 3027 * IRQ Handling 3028 */ 3029 3030 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 3031 { 3032 struct dw_hdmi_i2c *i2c = hdmi->i2c; 3033 unsigned int stat; 3034 3035 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 3036 if (!stat) 3037 return IRQ_NONE; 3038 3039 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 3040 3041 i2c->stat = stat; 3042 3043 complete(&i2c->cmp); 3044 3045 return IRQ_HANDLED; 3046 } 3047 3048 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 3049 { 3050 struct dw_hdmi *hdmi = dev_id; 3051 u8 intr_stat; 3052 irqreturn_t ret = IRQ_NONE; 3053 3054 if (hdmi->i2c) 3055 ret = dw_hdmi_i2c_irq(hdmi); 3056 3057 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 3058 if (intr_stat) { 3059 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 3060 return IRQ_WAKE_THREAD; 3061 } 3062 3063 return ret; 3064 } 3065 3066 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 3067 { 3068 mutex_lock(&hdmi->mutex); 3069 3070 if (!hdmi->force) { 3071 /* 3072 * If the RX sense status indicates we're disconnected, 3073 * clear the software rxsense status. 3074 */ 3075 if (!rx_sense) 3076 hdmi->rxsense = false; 3077 3078 /* 3079 * Only set the software rxsense status when both 3080 * rxsense and hpd indicates we're connected. 3081 * This avoids what seems to be bad behaviour in 3082 * at least iMX6S versions of the phy. 3083 */ 3084 if (hpd) 3085 hdmi->rxsense = true; 3086 3087 dw_hdmi_update_power(hdmi); 3088 dw_hdmi_update_phy_mask(hdmi); 3089 } 3090 mutex_unlock(&hdmi->mutex); 3091 } 3092 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 3093 3094 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 3095 { 3096 struct dw_hdmi *hdmi = dev_id; 3097 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 3098 3099 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 3100 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 3101 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 3102 3103 phy_pol_mask = 0; 3104 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 3105 phy_pol_mask |= HDMI_PHY_HPD; 3106 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 3107 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 3108 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 3109 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 3110 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 3111 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 3112 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 3113 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 3114 3115 if (phy_pol_mask) 3116 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 3117 3118 /* 3119 * RX sense tells us whether the TDMS transmitters are detecting 3120 * load - in other words, there's something listening on the 3121 * other end of the link. Use this to decide whether we should 3122 * power on the phy as HPD may be toggled by the sink to merely 3123 * ask the source to re-read the EDID. 3124 */ 3125 if (intr_stat & 3126 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 3127 dw_hdmi_setup_rx_sense(hdmi, 3128 phy_stat & HDMI_PHY_HPD, 3129 phy_stat & HDMI_PHY_RX_SENSE); 3130 3131 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { 3132 mutex_lock(&hdmi->cec_notifier_mutex); 3133 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); 3134 mutex_unlock(&hdmi->cec_notifier_mutex); 3135 } 3136 } 3137 3138 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { 3139 enum drm_connector_status status = phy_int_pol & HDMI_PHY_HPD 3140 ? connector_status_connected 3141 : connector_status_disconnected; 3142 3143 dev_dbg(hdmi->dev, "EVENT=%s\n", 3144 status == connector_status_connected ? 3145 "plugin" : "plugout"); 3146 3147 if (hdmi->bridge.dev) { 3148 drm_helper_hpd_irq_event(hdmi->bridge.dev); 3149 drm_bridge_hpd_notify(&hdmi->bridge, status); 3150 } 3151 } 3152 3153 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 3154 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 3155 HDMI_IH_MUTE_PHY_STAT0); 3156 3157 return IRQ_HANDLED; 3158 } 3159 3160 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 3161 { 3162 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 3163 .name = "DWC HDMI TX PHY", 3164 .gen = 1, 3165 }, { 3166 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 3167 .name = "DWC MHL PHY + HEAC PHY", 3168 .gen = 2, 3169 .has_svsret = true, 3170 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3171 }, { 3172 .type = DW_HDMI_PHY_DWC_MHL_PHY, 3173 .name = "DWC MHL PHY", 3174 .gen = 2, 3175 .has_svsret = true, 3176 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3177 }, { 3178 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 3179 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 3180 .gen = 2, 3181 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3182 }, { 3183 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 3184 .name = "DWC HDMI 3D TX PHY", 3185 .gen = 2, 3186 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3187 }, { 3188 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 3189 .name = "DWC HDMI 2.0 TX PHY", 3190 .gen = 2, 3191 .has_svsret = true, 3192 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3193 }, { 3194 .type = DW_HDMI_PHY_VENDOR_PHY, 3195 .name = "Vendor PHY", 3196 } 3197 }; 3198 3199 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 3200 { 3201 unsigned int i; 3202 u8 phy_type; 3203 3204 phy_type = hdmi->plat_data->phy_force_vendor ? 3205 DW_HDMI_PHY_VENDOR_PHY : 3206 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 3207 3208 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 3209 /* Vendor PHYs require support from the glue layer. */ 3210 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 3211 dev_err(hdmi->dev, 3212 "Vendor HDMI PHY not supported by glue layer\n"); 3213 return -ENODEV; 3214 } 3215 3216 hdmi->phy.ops = hdmi->plat_data->phy_ops; 3217 hdmi->phy.data = hdmi->plat_data->phy_data; 3218 hdmi->phy.name = hdmi->plat_data->phy_name; 3219 return 0; 3220 } 3221 3222 /* Synopsys PHYs are handled internally. */ 3223 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 3224 if (dw_hdmi_phys[i].type == phy_type) { 3225 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 3226 hdmi->phy.name = dw_hdmi_phys[i].name; 3227 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 3228 3229 if (!dw_hdmi_phys[i].configure && 3230 !hdmi->plat_data->configure_phy) { 3231 dev_err(hdmi->dev, "%s requires platform support\n", 3232 hdmi->phy.name); 3233 return -ENODEV; 3234 } 3235 3236 return 0; 3237 } 3238 } 3239 3240 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 3241 return -ENODEV; 3242 } 3243 3244 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 3245 { 3246 mutex_lock(&hdmi->mutex); 3247 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 3248 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 3249 mutex_unlock(&hdmi->mutex); 3250 } 3251 3252 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 3253 { 3254 mutex_lock(&hdmi->mutex); 3255 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 3256 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 3257 mutex_unlock(&hdmi->mutex); 3258 } 3259 3260 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 3261 .write = hdmi_writeb, 3262 .read = hdmi_readb, 3263 .enable = dw_hdmi_cec_enable, 3264 .disable = dw_hdmi_cec_disable, 3265 }; 3266 3267 static const struct regmap_config hdmi_regmap_8bit_config = { 3268 .reg_bits = 32, 3269 .val_bits = 8, 3270 .reg_stride = 1, 3271 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 3272 }; 3273 3274 static const struct regmap_config hdmi_regmap_32bit_config = { 3275 .reg_bits = 32, 3276 .val_bits = 32, 3277 .reg_stride = 4, 3278 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 3279 }; 3280 3281 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi) 3282 { 3283 initialize_hdmi_ih_mutes(hdmi); 3284 3285 /* 3286 * Reset HDMI DDC I2C master controller and mute I2CM interrupts. 3287 * Even if we are using a separate i2c adapter doing this doesn't 3288 * hurt. 3289 */ 3290 dw_hdmi_i2c_init(hdmi); 3291 3292 if (hdmi->phy.ops->setup_hpd) 3293 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 3294 } 3295 3296 /* ----------------------------------------------------------------------------- 3297 * Probe/remove API, used from platforms based on the DRM bridge API. 3298 */ 3299 3300 static int dw_hdmi_parse_dt(struct dw_hdmi *hdmi) 3301 { 3302 struct device_node *endpoint; 3303 struct device_node *remote; 3304 3305 if (!hdmi->plat_data->output_port) 3306 return 0; 3307 3308 endpoint = of_graph_get_endpoint_by_regs(hdmi->dev->of_node, 3309 hdmi->plat_data->output_port, 3310 -1); 3311 if (!endpoint) { 3312 /* 3313 * On platforms whose bindings don't make the output port 3314 * mandatory (such as Rockchip) the plat_data->output_port 3315 * field isn't set, so it's safe to make this a fatal error. 3316 */ 3317 dev_err(hdmi->dev, "Missing endpoint in port@%u\n", 3318 hdmi->plat_data->output_port); 3319 return -ENODEV; 3320 } 3321 3322 remote = of_graph_get_remote_port_parent(endpoint); 3323 of_node_put(endpoint); 3324 if (!remote) { 3325 dev_err(hdmi->dev, "Endpoint in port@%u unconnected\n", 3326 hdmi->plat_data->output_port); 3327 return -ENODEV; 3328 } 3329 3330 if (!of_device_is_available(remote)) { 3331 dev_err(hdmi->dev, "port@%u remote device is disabled\n", 3332 hdmi->plat_data->output_port); 3333 of_node_put(remote); 3334 return -ENODEV; 3335 } 3336 3337 hdmi->next_bridge = of_drm_find_bridge(remote); 3338 of_node_put(remote); 3339 if (!hdmi->next_bridge) 3340 return -EPROBE_DEFER; 3341 3342 return 0; 3343 } 3344 3345 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 3346 const struct dw_hdmi_plat_data *plat_data) 3347 { 3348 struct device *dev = &pdev->dev; 3349 struct device_node *np = dev->of_node; 3350 struct platform_device_info pdevinfo; 3351 struct device_node *ddc_node; 3352 struct dw_hdmi_cec_data cec; 3353 struct dw_hdmi *hdmi; 3354 struct resource *iores = NULL; 3355 int irq; 3356 int ret; 3357 u32 val = 1; 3358 u8 prod_id0; 3359 u8 prod_id1; 3360 u8 config0; 3361 u8 config3; 3362 3363 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 3364 if (!hdmi) 3365 return ERR_PTR(-ENOMEM); 3366 3367 hdmi->plat_data = plat_data; 3368 hdmi->dev = dev; 3369 hdmi->sample_rate = 48000; 3370 hdmi->channels = 2; 3371 hdmi->disabled = true; 3372 hdmi->rxsense = true; 3373 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 3374 hdmi->mc_clkdis = 0x7f; 3375 hdmi->last_connector_result = connector_status_disconnected; 3376 3377 mutex_init(&hdmi->mutex); 3378 mutex_init(&hdmi->audio_mutex); 3379 mutex_init(&hdmi->cec_notifier_mutex); 3380 spin_lock_init(&hdmi->audio_lock); 3381 3382 ret = dw_hdmi_parse_dt(hdmi); 3383 if (ret < 0) 3384 return ERR_PTR(ret); 3385 3386 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 3387 if (ddc_node) { 3388 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 3389 of_node_put(ddc_node); 3390 if (!hdmi->ddc) { 3391 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 3392 return ERR_PTR(-EPROBE_DEFER); 3393 } 3394 3395 } else { 3396 dev_dbg(hdmi->dev, "no ddc property found\n"); 3397 } 3398 3399 if (!plat_data->regm) { 3400 const struct regmap_config *reg_config; 3401 3402 of_property_read_u32(np, "reg-io-width", &val); 3403 switch (val) { 3404 case 4: 3405 reg_config = &hdmi_regmap_32bit_config; 3406 hdmi->reg_shift = 2; 3407 break; 3408 case 1: 3409 reg_config = &hdmi_regmap_8bit_config; 3410 break; 3411 default: 3412 dev_err(dev, "reg-io-width must be 1 or 4\n"); 3413 return ERR_PTR(-EINVAL); 3414 } 3415 3416 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3417 hdmi->regs = devm_ioremap_resource(dev, iores); 3418 if (IS_ERR(hdmi->regs)) { 3419 ret = PTR_ERR(hdmi->regs); 3420 goto err_res; 3421 } 3422 3423 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 3424 if (IS_ERR(hdmi->regm)) { 3425 dev_err(dev, "Failed to configure regmap\n"); 3426 ret = PTR_ERR(hdmi->regm); 3427 goto err_res; 3428 } 3429 } else { 3430 hdmi->regm = plat_data->regm; 3431 } 3432 3433 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 3434 if (IS_ERR(hdmi->isfr_clk)) { 3435 ret = PTR_ERR(hdmi->isfr_clk); 3436 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 3437 goto err_res; 3438 } 3439 3440 ret = clk_prepare_enable(hdmi->isfr_clk); 3441 if (ret) { 3442 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 3443 goto err_res; 3444 } 3445 3446 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 3447 if (IS_ERR(hdmi->iahb_clk)) { 3448 ret = PTR_ERR(hdmi->iahb_clk); 3449 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 3450 goto err_isfr; 3451 } 3452 3453 ret = clk_prepare_enable(hdmi->iahb_clk); 3454 if (ret) { 3455 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 3456 goto err_isfr; 3457 } 3458 3459 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec"); 3460 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) { 3461 hdmi->cec_clk = NULL; 3462 } else if (IS_ERR(hdmi->cec_clk)) { 3463 ret = PTR_ERR(hdmi->cec_clk); 3464 if (ret != -EPROBE_DEFER) 3465 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 3466 ret); 3467 3468 hdmi->cec_clk = NULL; 3469 goto err_iahb; 3470 } else { 3471 ret = clk_prepare_enable(hdmi->cec_clk); 3472 if (ret) { 3473 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", 3474 ret); 3475 goto err_iahb; 3476 } 3477 } 3478 3479 /* Product and revision IDs */ 3480 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 3481 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 3482 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 3483 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 3484 3485 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 3486 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 3487 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 3488 hdmi->version, prod_id0, prod_id1); 3489 ret = -ENODEV; 3490 goto err_iahb; 3491 } 3492 3493 ret = dw_hdmi_detect_phy(hdmi); 3494 if (ret < 0) 3495 goto err_iahb; 3496 3497 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 3498 hdmi->version >> 12, hdmi->version & 0xfff, 3499 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 3500 hdmi->phy.name); 3501 3502 dw_hdmi_init_hw(hdmi); 3503 3504 irq = platform_get_irq(pdev, 0); 3505 if (irq < 0) { 3506 ret = irq; 3507 goto err_iahb; 3508 } 3509 3510 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 3511 dw_hdmi_irq, IRQF_SHARED, 3512 dev_name(dev), hdmi); 3513 if (ret) 3514 goto err_iahb; 3515 3516 /* 3517 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 3518 * N and cts values before enabling phy 3519 */ 3520 hdmi_init_clk_regenerator(hdmi); 3521 3522 /* If DDC bus is not specified, try to register HDMI I2C bus */ 3523 if (!hdmi->ddc) { 3524 /* Look for (optional) stuff related to unwedging */ 3525 hdmi->pinctrl = devm_pinctrl_get(dev); 3526 if (!IS_ERR(hdmi->pinctrl)) { 3527 hdmi->unwedge_state = 3528 pinctrl_lookup_state(hdmi->pinctrl, "unwedge"); 3529 hdmi->default_state = 3530 pinctrl_lookup_state(hdmi->pinctrl, "default"); 3531 3532 if (IS_ERR(hdmi->default_state) || 3533 IS_ERR(hdmi->unwedge_state)) { 3534 if (!IS_ERR(hdmi->unwedge_state)) 3535 dev_warn(dev, 3536 "Unwedge requires default pinctrl\n"); 3537 hdmi->default_state = NULL; 3538 hdmi->unwedge_state = NULL; 3539 } 3540 } 3541 3542 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 3543 if (IS_ERR(hdmi->ddc)) 3544 hdmi->ddc = NULL; 3545 } 3546 3547 hdmi->bridge.driver_private = hdmi; 3548 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 3549 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID 3550 | DRM_BRIDGE_OP_HPD; 3551 hdmi->bridge.interlace_allowed = true; 3552 #ifdef CONFIG_OF 3553 hdmi->bridge.of_node = pdev->dev.of_node; 3554 #endif 3555 3556 memset(&pdevinfo, 0, sizeof(pdevinfo)); 3557 pdevinfo.parent = dev; 3558 pdevinfo.id = PLATFORM_DEVID_AUTO; 3559 3560 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 3561 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 3562 3563 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 3564 struct dw_hdmi_audio_data audio; 3565 3566 audio.phys = iores->start; 3567 audio.base = hdmi->regs; 3568 audio.irq = irq; 3569 audio.hdmi = hdmi; 3570 audio.get_eld = hdmi_audio_get_eld; 3571 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 3572 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 3573 3574 pdevinfo.name = "dw-hdmi-ahb-audio"; 3575 pdevinfo.data = &audio; 3576 pdevinfo.size_data = sizeof(audio); 3577 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3578 hdmi->audio = platform_device_register_full(&pdevinfo); 3579 } else if (config0 & HDMI_CONFIG0_I2S) { 3580 struct dw_hdmi_i2s_audio_data audio; 3581 3582 audio.hdmi = hdmi; 3583 audio.get_eld = hdmi_audio_get_eld; 3584 audio.write = hdmi_writeb; 3585 audio.read = hdmi_readb; 3586 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 3587 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 3588 3589 pdevinfo.name = "dw-hdmi-i2s-audio"; 3590 pdevinfo.data = &audio; 3591 pdevinfo.size_data = sizeof(audio); 3592 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3593 hdmi->audio = platform_device_register_full(&pdevinfo); 3594 } else if (iores && config3 & HDMI_CONFIG3_GPAUD) { 3595 struct dw_hdmi_audio_data audio; 3596 3597 audio.phys = iores->start; 3598 audio.base = hdmi->regs; 3599 audio.irq = irq; 3600 audio.hdmi = hdmi; 3601 audio.get_eld = hdmi_audio_get_eld; 3602 3603 hdmi->enable_audio = dw_hdmi_gp_audio_enable; 3604 hdmi->disable_audio = dw_hdmi_gp_audio_disable; 3605 3606 pdevinfo.name = "dw-hdmi-gp-audio"; 3607 pdevinfo.id = PLATFORM_DEVID_NONE; 3608 pdevinfo.data = &audio; 3609 pdevinfo.size_data = sizeof(audio); 3610 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3611 hdmi->audio = platform_device_register_full(&pdevinfo); 3612 } 3613 3614 if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) { 3615 cec.hdmi = hdmi; 3616 cec.ops = &dw_hdmi_cec_ops; 3617 cec.irq = irq; 3618 3619 pdevinfo.name = "dw-hdmi-cec"; 3620 pdevinfo.data = &cec; 3621 pdevinfo.size_data = sizeof(cec); 3622 pdevinfo.dma_mask = 0; 3623 3624 hdmi->cec = platform_device_register_full(&pdevinfo); 3625 } 3626 3627 drm_bridge_add(&hdmi->bridge); 3628 3629 return hdmi; 3630 3631 err_iahb: 3632 clk_disable_unprepare(hdmi->iahb_clk); 3633 clk_disable_unprepare(hdmi->cec_clk); 3634 err_isfr: 3635 clk_disable_unprepare(hdmi->isfr_clk); 3636 err_res: 3637 i2c_put_adapter(hdmi->ddc); 3638 3639 return ERR_PTR(ret); 3640 } 3641 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 3642 3643 void dw_hdmi_remove(struct dw_hdmi *hdmi) 3644 { 3645 drm_bridge_remove(&hdmi->bridge); 3646 3647 if (hdmi->audio && !IS_ERR(hdmi->audio)) 3648 platform_device_unregister(hdmi->audio); 3649 if (!IS_ERR(hdmi->cec)) 3650 platform_device_unregister(hdmi->cec); 3651 3652 /* Disable all interrupts */ 3653 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 3654 3655 clk_disable_unprepare(hdmi->iahb_clk); 3656 clk_disable_unprepare(hdmi->isfr_clk); 3657 clk_disable_unprepare(hdmi->cec_clk); 3658 3659 if (hdmi->i2c) 3660 i2c_del_adapter(&hdmi->i2c->adap); 3661 else 3662 i2c_put_adapter(hdmi->ddc); 3663 } 3664 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 3665 3666 /* ----------------------------------------------------------------------------- 3667 * Bind/unbind API, used from platforms based on the component framework. 3668 */ 3669 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 3670 struct drm_encoder *encoder, 3671 const struct dw_hdmi_plat_data *plat_data) 3672 { 3673 struct dw_hdmi *hdmi; 3674 int ret; 3675 3676 hdmi = dw_hdmi_probe(pdev, plat_data); 3677 if (IS_ERR(hdmi)) 3678 return hdmi; 3679 3680 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0); 3681 if (ret) { 3682 dw_hdmi_remove(hdmi); 3683 return ERR_PTR(ret); 3684 } 3685 3686 return hdmi; 3687 } 3688 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 3689 3690 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 3691 { 3692 dw_hdmi_remove(hdmi); 3693 } 3694 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 3695 3696 void dw_hdmi_resume(struct dw_hdmi *hdmi) 3697 { 3698 dw_hdmi_init_hw(hdmi); 3699 } 3700 EXPORT_SYMBOL_GPL(dw_hdmi_resume); 3701 3702 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 3703 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 3704 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 3705 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 3706 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 3707 MODULE_LICENSE("GPL"); 3708 MODULE_ALIAS("platform:dw-hdmi"); 3709