1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver 4 * 5 * Copyright (C) 2013-2015 Mentor Graphics Inc. 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 */ 9 10 #include <linux/cleanup.h> 11 #include <linux/clk.h> 12 #include <linux/delay.h> 13 #include <linux/err.h> 14 #include <linux/export.h> 15 #include <linux/hdmi.h> 16 #include <linux/i2c.h> 17 #include <linux/irq.h> 18 #include <linux/module.h> 19 #include <linux/mutex.h> 20 #include <linux/of.h> 21 #include <linux/pinctrl/consumer.h> 22 #include <linux/regmap.h> 23 #include <linux/dma-mapping.h> 24 #include <linux/spinlock.h> 25 26 #include <media/cec-notifier.h> 27 28 #include <linux/media-bus-format.h> 29 #include <linux/videodev2.h> 30 31 #include <drm/bridge/dw_hdmi.h> 32 #include <drm/display/drm_hdmi_helper.h> 33 #include <drm/display/drm_scdc_helper.h> 34 #include <drm/drm_atomic.h> 35 #include <drm/drm_atomic_helper.h> 36 #include <drm/drm_bridge.h> 37 #include <drm/drm_edid.h> 38 #include <drm/drm_of.h> 39 #include <drm/drm_print.h> 40 #include <drm/drm_probe_helper.h> 41 42 #include "dw-hdmi-audio.h" 43 #include "dw-hdmi-cec.h" 44 #include "dw-hdmi.h" 45 46 #define DDC_CI_ADDR 0x37 47 #define DDC_SEGMENT_ADDR 0x30 48 49 #define HDMI_EDID_LEN 512 50 51 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 52 #define SCDC_MIN_SOURCE_VERSION 0x1 53 54 #define HDMI14_MAX_TMDSCLK 340000000 55 56 static const u16 csc_coeff_default[3][4] = { 57 { 0x2000, 0x0000, 0x0000, 0x0000 }, 58 { 0x0000, 0x2000, 0x0000, 0x0000 }, 59 { 0x0000, 0x0000, 0x2000, 0x0000 } 60 }; 61 62 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 63 { 0x2000, 0x6926, 0x74fd, 0x010e }, 64 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 65 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 66 }; 67 68 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 69 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 70 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 71 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 72 }; 73 74 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 75 { 0x2591, 0x1322, 0x074b, 0x0000 }, 76 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 77 { 0x6acd, 0x7534, 0x2000, 0x0200 } 78 }; 79 80 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 81 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 82 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 83 { 0x6756, 0x78ab, 0x2000, 0x0200 } 84 }; 85 86 static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = { 87 { 0x1b7c, 0x0000, 0x0000, 0x0020 }, 88 { 0x0000, 0x1b7c, 0x0000, 0x0020 }, 89 { 0x0000, 0x0000, 0x1b7c, 0x0020 } 90 }; 91 92 struct hdmi_vmode { 93 bool mdataenablepolarity; 94 95 unsigned int mpixelclock; 96 unsigned int mpixelrepetitioninput; 97 unsigned int mpixelrepetitionoutput; 98 unsigned int mtmdsclock; 99 }; 100 101 struct hdmi_data_info { 102 unsigned int enc_in_bus_format; 103 unsigned int enc_out_bus_format; 104 unsigned int enc_in_encoding; 105 unsigned int enc_out_encoding; 106 unsigned int pix_repet_factor; 107 unsigned int hdcp_enable; 108 struct hdmi_vmode video_mode; 109 bool rgb_limited_range; 110 }; 111 112 struct dw_hdmi_i2c { 113 struct i2c_adapter adap; 114 115 struct mutex lock; /* used to serialize data transfers */ 116 struct completion cmp; 117 u8 stat; 118 119 u8 slave_reg; 120 bool is_regaddr; 121 bool is_segment; 122 }; 123 124 struct dw_hdmi_phy_data { 125 enum dw_hdmi_phy_type type; 126 const char *name; 127 unsigned int gen; 128 bool has_svsret; 129 int (*configure)(struct dw_hdmi *hdmi, 130 const struct dw_hdmi_plat_data *pdata, 131 unsigned long mpixelclock); 132 }; 133 134 struct dw_hdmi { 135 struct drm_connector connector; 136 struct drm_bridge bridge; 137 138 unsigned int version; 139 140 struct platform_device *audio; 141 struct platform_device *cec; 142 struct device *dev; 143 struct dw_hdmi_i2c *i2c; 144 145 struct hdmi_data_info hdmi_data; 146 const struct dw_hdmi_plat_data *plat_data; 147 148 int vic; 149 150 u8 edid[HDMI_EDID_LEN]; 151 152 struct { 153 const struct dw_hdmi_phy_ops *ops; 154 const char *name; 155 void *data; 156 bool enabled; 157 } phy; 158 159 struct drm_display_mode previous_mode; 160 161 struct i2c_adapter *ddc; 162 void __iomem *regs; 163 bool sink_is_hdmi; 164 bool sink_has_audio; 165 166 struct pinctrl *pinctrl; 167 struct pinctrl_state *default_state; 168 struct pinctrl_state *unwedge_state; 169 170 struct mutex mutex; /* for state below and previous_mode */ 171 enum drm_connector_force force; /* mutex-protected force state */ 172 struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */ 173 bool disabled; /* DRM has disabled our bridge */ 174 bool bridge_is_on; /* indicates the bridge is on */ 175 bool rxsense; /* rxsense state */ 176 u8 phy_mask; /* desired phy int mask settings */ 177 u8 mc_clkdis; /* clock disable register */ 178 179 spinlock_t audio_lock; 180 struct mutex audio_mutex; 181 unsigned int sample_iec958; 182 unsigned int sample_non_pcm; 183 unsigned int sample_width; 184 unsigned int sample_rate; 185 unsigned int channels; 186 unsigned int audio_cts; 187 unsigned int audio_n; 188 bool audio_enable; 189 190 unsigned int reg_shift; 191 struct regmap *regm; 192 void (*enable_audio)(struct dw_hdmi *hdmi); 193 void (*disable_audio)(struct dw_hdmi *hdmi); 194 195 struct mutex cec_notifier_mutex; 196 struct cec_notifier *cec_notifier; 197 198 hdmi_codec_plugged_cb plugged_cb; 199 struct device *codec_dev; 200 enum drm_connector_status last_connector_result; 201 }; 202 203 const struct dw_hdmi_plat_data *dw_hdmi_to_plat_data(struct dw_hdmi *hdmi) 204 { 205 return hdmi->plat_data; 206 } 207 EXPORT_SYMBOL_GPL(dw_hdmi_to_plat_data); 208 209 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 210 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 211 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 212 213 #define HDMI_PHY_RX_SENSE \ 214 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 215 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 216 217 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 218 { 219 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 220 } 221 222 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 223 { 224 unsigned int val = 0; 225 226 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 227 228 return val; 229 } 230 231 static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged) 232 { 233 if (hdmi->plugged_cb && hdmi->codec_dev) 234 hdmi->plugged_cb(hdmi->codec_dev, plugged); 235 } 236 237 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn, 238 struct device *codec_dev) 239 { 240 bool plugged; 241 242 mutex_lock(&hdmi->mutex); 243 hdmi->plugged_cb = fn; 244 hdmi->codec_dev = codec_dev; 245 plugged = hdmi->last_connector_result == connector_status_connected; 246 handle_plugged_change(hdmi, plugged); 247 mutex_unlock(&hdmi->mutex); 248 249 return 0; 250 } 251 EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb); 252 253 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 254 { 255 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 256 } 257 258 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 259 u8 shift, u8 mask) 260 { 261 hdmi_modb(hdmi, data << shift, mask, reg); 262 } 263 264 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 265 { 266 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 267 HDMI_PHY_I2CM_INT_ADDR); 268 269 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 270 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 271 HDMI_PHY_I2CM_CTLINT_ADDR); 272 273 /* Software reset */ 274 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 275 276 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 277 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 278 279 /* Set done, not acknowledged and arbitration interrupt polarities */ 280 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 281 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 282 HDMI_I2CM_CTLINT); 283 284 /* Clear DONE and ERROR interrupts */ 285 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 286 HDMI_IH_I2CM_STAT0); 287 288 /* Mute DONE and ERROR interrupts */ 289 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 290 HDMI_IH_MUTE_I2CM_STAT0); 291 } 292 293 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi) 294 { 295 /* If no unwedge state then give up */ 296 if (!hdmi->unwedge_state) 297 return false; 298 299 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n"); 300 301 /* 302 * This is a huge hack to workaround a problem where the dw_hdmi i2c 303 * bus could sometimes get wedged. Once wedged there doesn't appear 304 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ) 305 * other than pulsing the SDA line. 306 * 307 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi) 308 * by: 309 * 1. Remux the pin as a GPIO output, driven low. 310 * 2. Wait a little while. 1 ms seems to work, but we'll do 10. 311 * 3. Immediately jump to remux the pin as dw_hdmi i2c again. 312 * 313 * At the moment of remuxing, the line will still be low due to its 314 * recent stint as an output, but then it will be pulled high by the 315 * (presumed) external pullup. dw_hdmi seems to see this as a rising 316 * edge and that seems to get it out of its jam. 317 * 318 * This wedging was only ever seen on one TV, and only on one of 319 * its HDMI ports. It happened when the TV was powered on while the 320 * device was plugged in. A scope trace shows the TV bringing both SDA 321 * and SCL low, then bringing them both back up at roughly the same 322 * time. Presumably this confuses dw_hdmi because it saw activity but 323 * no real STOP (maybe it thinks there's another master on the bus?). 324 * Giving it a clean rising edge of SDA while SCL is already high 325 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out 326 * of its stupor. 327 * 328 * Note that after coming back alive, transfers seem to immediately 329 * resume, so if we unwedge due to a timeout we should wait a little 330 * longer for our transfer to finish, since it might have just started 331 * now. 332 */ 333 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state); 334 msleep(10); 335 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state); 336 337 return true; 338 } 339 340 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi) 341 { 342 struct dw_hdmi_i2c *i2c = hdmi->i2c; 343 int stat; 344 345 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 346 if (!stat) { 347 /* If we can't unwedge, return timeout */ 348 if (!dw_hdmi_i2c_unwedge(hdmi)) 349 return -EAGAIN; 350 351 /* We tried to unwedge; give it another chance */ 352 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 353 if (!stat) 354 return -EAGAIN; 355 } 356 357 /* Check for error condition on the bus */ 358 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 359 return -EIO; 360 361 return 0; 362 } 363 364 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 365 unsigned char *buf, unsigned int length) 366 { 367 struct dw_hdmi_i2c *i2c = hdmi->i2c; 368 int ret; 369 370 if (!i2c->is_regaddr) { 371 dev_dbg(hdmi->dev, "set read register address to 0\n"); 372 i2c->slave_reg = 0x00; 373 i2c->is_regaddr = true; 374 } 375 376 while (length--) { 377 reinit_completion(&i2c->cmp); 378 379 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 380 if (i2c->is_segment) 381 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 382 HDMI_I2CM_OPERATION); 383 else 384 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 385 HDMI_I2CM_OPERATION); 386 387 ret = dw_hdmi_i2c_wait(hdmi); 388 if (ret) 389 return ret; 390 391 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 392 } 393 i2c->is_segment = false; 394 395 return 0; 396 } 397 398 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 399 unsigned char *buf, unsigned int length) 400 { 401 struct dw_hdmi_i2c *i2c = hdmi->i2c; 402 int ret; 403 404 if (!i2c->is_regaddr) { 405 /* Use the first write byte as register address */ 406 i2c->slave_reg = buf[0]; 407 length--; 408 buf++; 409 i2c->is_regaddr = true; 410 } 411 412 while (length--) { 413 reinit_completion(&i2c->cmp); 414 415 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 416 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 417 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 418 HDMI_I2CM_OPERATION); 419 420 ret = dw_hdmi_i2c_wait(hdmi); 421 if (ret) 422 return ret; 423 } 424 425 return 0; 426 } 427 428 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 429 struct i2c_msg *msgs, int num) 430 { 431 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 432 struct dw_hdmi_i2c *i2c = hdmi->i2c; 433 u8 addr = msgs[0].addr; 434 int i, ret = 0; 435 436 if (addr == DDC_CI_ADDR) 437 /* 438 * The internal I2C controller does not support the multi-byte 439 * read and write operations needed for DDC/CI. 440 * TOFIX: Blacklist the DDC/CI address until we filter out 441 * unsupported I2C operations. 442 */ 443 return -EOPNOTSUPP; 444 445 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 446 447 for (i = 0; i < num; i++) { 448 if (msgs[i].len == 0) { 449 dev_dbg(hdmi->dev, 450 "unsupported transfer %d/%d, no data\n", 451 i + 1, num); 452 return -EOPNOTSUPP; 453 } 454 } 455 456 mutex_lock(&i2c->lock); 457 458 /* Unmute DONE and ERROR interrupts */ 459 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 460 461 /* Set slave device address taken from the first I2C message */ 462 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 463 464 /* Set slave device register address on transfer */ 465 i2c->is_regaddr = false; 466 467 /* Set segment pointer for I2C extended read mode operation */ 468 i2c->is_segment = false; 469 470 for (i = 0; i < num; i++) { 471 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 472 i + 1, num, msgs[i].len, msgs[i].flags); 473 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 474 i2c->is_segment = true; 475 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 476 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 477 } else { 478 if (msgs[i].flags & I2C_M_RD) 479 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 480 msgs[i].len); 481 else 482 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 483 msgs[i].len); 484 } 485 if (ret < 0) 486 break; 487 } 488 489 if (!ret) 490 ret = num; 491 492 /* Mute DONE and ERROR interrupts */ 493 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 494 HDMI_IH_MUTE_I2CM_STAT0); 495 496 mutex_unlock(&i2c->lock); 497 498 return ret; 499 } 500 501 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 502 { 503 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 504 } 505 506 static const struct i2c_algorithm dw_hdmi_algorithm = { 507 .master_xfer = dw_hdmi_i2c_xfer, 508 .functionality = dw_hdmi_i2c_func, 509 }; 510 511 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 512 { 513 struct i2c_adapter *adap; 514 struct dw_hdmi_i2c *i2c; 515 int ret; 516 517 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 518 if (!i2c) 519 return ERR_PTR(-ENOMEM); 520 521 mutex_init(&i2c->lock); 522 init_completion(&i2c->cmp); 523 524 adap = &i2c->adap; 525 adap->owner = THIS_MODULE; 526 adap->dev.parent = hdmi->dev; 527 adap->algo = &dw_hdmi_algorithm; 528 strscpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 529 i2c_set_adapdata(adap, hdmi); 530 531 ret = i2c_add_adapter(adap); 532 if (ret) { 533 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 534 devm_kfree(hdmi->dev, i2c); 535 return ERR_PTR(ret); 536 } 537 538 hdmi->i2c = i2c; 539 540 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 541 542 return adap; 543 } 544 545 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 546 unsigned int n) 547 { 548 /* Must be set/cleared first */ 549 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 550 551 /* nshift factor = 0 */ 552 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 553 554 /* Use automatic CTS generation mode when CTS is not set */ 555 if (cts) 556 hdmi_writeb(hdmi, ((cts >> 16) & 557 HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 558 HDMI_AUD_CTS3_CTS_MANUAL, 559 HDMI_AUD_CTS3); 560 else 561 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); 562 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 563 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 564 565 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 566 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 567 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 568 } 569 570 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 571 { 572 unsigned int n = (128 * freq) / 1000; 573 unsigned int mult = 1; 574 575 while (freq > 48000) { 576 mult *= 2; 577 freq /= 2; 578 } 579 580 switch (freq) { 581 case 32000: 582 if (pixel_clk == 25175000) 583 n = 4576; 584 else if (pixel_clk == 27027000) 585 n = 4096; 586 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 587 n = 11648; 588 else if (pixel_clk == 297000000) 589 n = 3072; 590 else 591 n = 4096; 592 n *= mult; 593 break; 594 595 case 44100: 596 if (pixel_clk == 25175000) 597 n = 7007; 598 else if (pixel_clk == 74176000) 599 n = 17836; 600 else if (pixel_clk == 148352000) 601 n = 8918; 602 else if (pixel_clk == 297000000) 603 n = 4704; 604 else 605 n = 6272; 606 n *= mult; 607 break; 608 609 case 48000: 610 if (pixel_clk == 25175000) 611 n = 6864; 612 else if (pixel_clk == 27027000) 613 n = 6144; 614 else if (pixel_clk == 74176000) 615 n = 11648; 616 else if (pixel_clk == 148352000) 617 n = 5824; 618 else if (pixel_clk == 297000000) 619 n = 5120; 620 else 621 n = 6144; 622 n *= mult; 623 break; 624 625 default: 626 break; 627 } 628 629 return n; 630 } 631 632 /* 633 * When transmitting IEC60958 linear PCM audio, these registers allow to 634 * configure the channel status information of all the channel status 635 * bits in the IEC60958 frame. For the moment this configuration is only 636 * used when the I2S audio interface, General Purpose Audio (GPA), 637 * or AHB audio DMA (AHBAUDDMA) interface is active 638 * (for S/PDIF interface this information comes from the stream). 639 */ 640 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, 641 u8 *channel_status) 642 { 643 /* 644 * Set channel status register for frequency and word length. 645 * Use default values for other registers. 646 */ 647 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7); 648 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8); 649 } 650 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status); 651 652 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 653 unsigned long pixel_clk, unsigned int sample_rate) 654 { 655 unsigned long ftdms = pixel_clk; 656 unsigned int n, cts; 657 u8 config3; 658 u64 tmp; 659 660 n = hdmi_compute_n(sample_rate, pixel_clk); 661 662 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 663 664 /* Compute CTS when using internal AHB audio or General Parallel audio*/ 665 if ((config3 & HDMI_CONFIG3_AHBAUDDMA) || (config3 & HDMI_CONFIG3_GPAUD)) { 666 /* 667 * Compute the CTS value from the N value. Note that CTS and N 668 * can be up to 20 bits in total, so we need 64-bit math. Also 669 * note that our TDMS clock is not fully accurate; it is 670 * accurate to kHz. This can introduce an unnecessary remainder 671 * in the calculation below, so we don't try to warn about that. 672 */ 673 tmp = (u64)ftdms * n; 674 do_div(tmp, 128 * sample_rate); 675 cts = tmp; 676 677 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 678 __func__, sample_rate, 679 ftdms / 1000000, (ftdms / 1000) % 1000, 680 n, cts); 681 } else { 682 cts = 0; 683 } 684 685 spin_lock_irq(&hdmi->audio_lock); 686 hdmi->audio_n = n; 687 hdmi->audio_cts = cts; 688 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 689 spin_unlock_irq(&hdmi->audio_lock); 690 } 691 692 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 693 { 694 mutex_lock(&hdmi->audio_mutex); 695 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 696 mutex_unlock(&hdmi->audio_mutex); 697 } 698 699 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 700 { 701 mutex_lock(&hdmi->audio_mutex); 702 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 703 hdmi->sample_rate); 704 mutex_unlock(&hdmi->audio_mutex); 705 } 706 707 void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width) 708 { 709 mutex_lock(&hdmi->audio_mutex); 710 hdmi->sample_width = width; 711 mutex_unlock(&hdmi->audio_mutex); 712 } 713 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_width); 714 715 void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm) 716 { 717 mutex_lock(&hdmi->audio_mutex); 718 hdmi->sample_non_pcm = non_pcm; 719 mutex_unlock(&hdmi->audio_mutex); 720 } 721 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_non_pcm); 722 723 void dw_hdmi_set_sample_iec958(struct dw_hdmi *hdmi, unsigned int iec958) 724 { 725 mutex_lock(&hdmi->audio_mutex); 726 hdmi->sample_iec958 = iec958; 727 mutex_unlock(&hdmi->audio_mutex); 728 } 729 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_iec958); 730 731 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 732 { 733 mutex_lock(&hdmi->audio_mutex); 734 hdmi->sample_rate = rate; 735 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 736 hdmi->sample_rate); 737 mutex_unlock(&hdmi->audio_mutex); 738 } 739 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 740 741 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt) 742 { 743 u8 layout; 744 745 mutex_lock(&hdmi->audio_mutex); 746 hdmi->channels = cnt; 747 748 /* 749 * For >2 channel PCM audio, we need to select layout 1 750 * and set an appropriate channel map. 751 */ 752 if (cnt > 2) 753 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1; 754 else 755 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0; 756 757 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, 758 HDMI_FC_AUDSCONF); 759 760 /* Set the audio infoframes channel count */ 761 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, 762 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0); 763 764 mutex_unlock(&hdmi->audio_mutex); 765 } 766 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count); 767 768 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca) 769 { 770 mutex_lock(&hdmi->audio_mutex); 771 772 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2); 773 774 mutex_unlock(&hdmi->audio_mutex); 775 } 776 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation); 777 778 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 779 { 780 if (enable) 781 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 782 else 783 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 784 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 785 } 786 787 static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi) 788 { 789 if (!hdmi->curr_conn) 790 return NULL; 791 792 return hdmi->curr_conn->eld; 793 } 794 795 static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi) 796 { 797 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 798 int sample_freq = 0x2, org_sample_freq = 0xD; 799 int ch_mask = BIT(hdmi->channels) - 1; 800 801 switch (hdmi->sample_rate) { 802 case 32000: 803 sample_freq = 0x03; 804 org_sample_freq = 0x0C; 805 break; 806 case 44100: 807 sample_freq = 0x00; 808 org_sample_freq = 0x0F; 809 break; 810 case 48000: 811 sample_freq = 0x02; 812 org_sample_freq = 0x0D; 813 break; 814 case 88200: 815 sample_freq = 0x08; 816 org_sample_freq = 0x07; 817 break; 818 case 96000: 819 sample_freq = 0x0A; 820 org_sample_freq = 0x05; 821 break; 822 case 176400: 823 sample_freq = 0x0C; 824 org_sample_freq = 0x03; 825 break; 826 case 192000: 827 sample_freq = 0x0E; 828 org_sample_freq = 0x01; 829 break; 830 default: 831 break; 832 } 833 834 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 835 hdmi_enable_audio_clk(hdmi, true); 836 837 hdmi_writeb(hdmi, 0x1, HDMI_FC_AUDSCHNLS0); 838 hdmi_writeb(hdmi, hdmi->channels, HDMI_FC_AUDSCHNLS2); 839 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS3); 840 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS4); 841 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS5); 842 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS6); 843 hdmi_writeb(hdmi, (0x3 << 4) | sample_freq, HDMI_FC_AUDSCHNLS7); 844 hdmi_writeb(hdmi, (org_sample_freq << 4) | 0xb, HDMI_FC_AUDSCHNLS8); 845 846 hdmi_writeb(hdmi, ch_mask, HDMI_GP_CONF1); 847 hdmi_writeb(hdmi, 0x02, HDMI_GP_CONF2); 848 hdmi_writeb(hdmi, 0x01, HDMI_GP_CONF0); 849 850 hdmi_modb(hdmi, 0x3, 0x3, HDMI_FC_DATAUTO3); 851 852 /* hbr */ 853 if (hdmi->sample_rate == 192000 && hdmi->channels == 8 && 854 hdmi->sample_width == 32 && hdmi->sample_non_pcm) 855 hdmi_modb(hdmi, 0x01, 0x01, HDMI_GP_CONF2); 856 857 if (pdata->enable_audio) 858 pdata->enable_audio(hdmi, 859 hdmi->channels, 860 hdmi->sample_width, 861 hdmi->sample_rate, 862 hdmi->sample_non_pcm, 863 hdmi->sample_iec958); 864 } 865 866 static void dw_hdmi_gp_audio_disable(struct dw_hdmi *hdmi) 867 { 868 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 869 870 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 871 872 hdmi_modb(hdmi, 0, 0x3, HDMI_FC_DATAUTO3); 873 if (pdata->disable_audio) 874 pdata->disable_audio(hdmi); 875 876 hdmi_enable_audio_clk(hdmi, false); 877 } 878 879 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 880 { 881 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 882 } 883 884 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 885 { 886 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 887 } 888 889 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 890 { 891 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 892 hdmi_enable_audio_clk(hdmi, true); 893 } 894 895 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 896 { 897 hdmi_enable_audio_clk(hdmi, false); 898 } 899 900 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 901 { 902 unsigned long flags; 903 904 spin_lock_irqsave(&hdmi->audio_lock, flags); 905 hdmi->audio_enable = true; 906 if (hdmi->enable_audio) 907 hdmi->enable_audio(hdmi); 908 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 909 } 910 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 911 912 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 913 { 914 unsigned long flags; 915 916 spin_lock_irqsave(&hdmi->audio_lock, flags); 917 hdmi->audio_enable = false; 918 if (hdmi->disable_audio) 919 hdmi->disable_audio(hdmi); 920 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 921 } 922 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 923 924 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 925 { 926 switch (bus_format) { 927 case MEDIA_BUS_FMT_RGB888_1X24: 928 case MEDIA_BUS_FMT_RGB101010_1X30: 929 case MEDIA_BUS_FMT_RGB121212_1X36: 930 case MEDIA_BUS_FMT_RGB161616_1X48: 931 return true; 932 933 default: 934 return false; 935 } 936 } 937 938 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 939 { 940 switch (bus_format) { 941 case MEDIA_BUS_FMT_YUV8_1X24: 942 case MEDIA_BUS_FMT_YUV10_1X30: 943 case MEDIA_BUS_FMT_YUV12_1X36: 944 case MEDIA_BUS_FMT_YUV16_1X48: 945 return true; 946 947 default: 948 return false; 949 } 950 } 951 952 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 953 { 954 switch (bus_format) { 955 case MEDIA_BUS_FMT_UYVY8_1X16: 956 case MEDIA_BUS_FMT_UYVY10_1X20: 957 case MEDIA_BUS_FMT_UYVY12_1X24: 958 return true; 959 960 default: 961 return false; 962 } 963 } 964 965 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 966 { 967 switch (bus_format) { 968 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 969 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 970 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 971 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 972 return true; 973 974 default: 975 return false; 976 } 977 } 978 979 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 980 { 981 switch (bus_format) { 982 case MEDIA_BUS_FMT_RGB888_1X24: 983 case MEDIA_BUS_FMT_YUV8_1X24: 984 case MEDIA_BUS_FMT_UYVY8_1X16: 985 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 986 return 8; 987 988 case MEDIA_BUS_FMT_RGB101010_1X30: 989 case MEDIA_BUS_FMT_YUV10_1X30: 990 case MEDIA_BUS_FMT_UYVY10_1X20: 991 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 992 return 10; 993 994 case MEDIA_BUS_FMT_RGB121212_1X36: 995 case MEDIA_BUS_FMT_YUV12_1X36: 996 case MEDIA_BUS_FMT_UYVY12_1X24: 997 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 998 return 12; 999 1000 case MEDIA_BUS_FMT_RGB161616_1X48: 1001 case MEDIA_BUS_FMT_YUV16_1X48: 1002 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1003 return 16; 1004 1005 default: 1006 return 0; 1007 } 1008 } 1009 1010 /* 1011 * this submodule is responsible for the video data synchronization. 1012 * for example, for RGB 4:4:4 input, the data map is defined as 1013 * pin{47~40} <==> R[7:0] 1014 * pin{31~24} <==> G[7:0] 1015 * pin{15~8} <==> B[7:0] 1016 */ 1017 static void hdmi_video_sample(struct dw_hdmi *hdmi) 1018 { 1019 int color_format = 0; 1020 u8 val; 1021 1022 switch (hdmi->hdmi_data.enc_in_bus_format) { 1023 case MEDIA_BUS_FMT_RGB888_1X24: 1024 color_format = 0x01; 1025 break; 1026 case MEDIA_BUS_FMT_RGB101010_1X30: 1027 color_format = 0x03; 1028 break; 1029 case MEDIA_BUS_FMT_RGB121212_1X36: 1030 color_format = 0x05; 1031 break; 1032 case MEDIA_BUS_FMT_RGB161616_1X48: 1033 color_format = 0x07; 1034 break; 1035 1036 case MEDIA_BUS_FMT_YUV8_1X24: 1037 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1038 color_format = 0x09; 1039 break; 1040 case MEDIA_BUS_FMT_YUV10_1X30: 1041 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1042 color_format = 0x0B; 1043 break; 1044 case MEDIA_BUS_FMT_YUV12_1X36: 1045 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 1046 color_format = 0x0D; 1047 break; 1048 case MEDIA_BUS_FMT_YUV16_1X48: 1049 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1050 color_format = 0x0F; 1051 break; 1052 1053 case MEDIA_BUS_FMT_UYVY8_1X16: 1054 color_format = 0x16; 1055 break; 1056 case MEDIA_BUS_FMT_UYVY10_1X20: 1057 color_format = 0x14; 1058 break; 1059 case MEDIA_BUS_FMT_UYVY12_1X24: 1060 color_format = 0x12; 1061 break; 1062 1063 default: 1064 return; 1065 } 1066 1067 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 1068 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 1069 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 1070 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 1071 1072 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 1073 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 1074 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 1075 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 1076 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 1077 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 1078 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 1079 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 1080 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 1081 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 1082 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 1083 } 1084 1085 static int is_color_space_conversion(struct dw_hdmi *hdmi) 1086 { 1087 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1088 bool is_input_rgb, is_output_rgb; 1089 1090 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format); 1091 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format); 1092 1093 return (is_input_rgb != is_output_rgb) || 1094 (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range); 1095 } 1096 1097 static int is_color_space_decimation(struct dw_hdmi *hdmi) 1098 { 1099 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1100 return 0; 1101 1102 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 1103 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 1104 return 1; 1105 1106 return 0; 1107 } 1108 1109 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 1110 { 1111 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 1112 return 0; 1113 1114 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1115 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1116 return 1; 1117 1118 return 0; 1119 } 1120 1121 static bool is_csc_needed(struct dw_hdmi *hdmi) 1122 { 1123 return is_color_space_conversion(hdmi) || 1124 is_color_space_decimation(hdmi) || 1125 is_color_space_interpolation(hdmi); 1126 } 1127 1128 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 1129 { 1130 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 1131 bool is_input_rgb, is_output_rgb; 1132 unsigned i; 1133 u32 csc_scale = 1; 1134 1135 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); 1136 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); 1137 1138 if (!is_input_rgb && is_output_rgb) { 1139 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) 1140 csc_coeff = &csc_coeff_rgb_out_eitu601; 1141 else 1142 csc_coeff = &csc_coeff_rgb_out_eitu709; 1143 } else if (is_input_rgb && !is_output_rgb) { 1144 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) 1145 csc_coeff = &csc_coeff_rgb_in_eitu601; 1146 else 1147 csc_coeff = &csc_coeff_rgb_in_eitu709; 1148 csc_scale = 0; 1149 } else if (is_input_rgb && is_output_rgb && 1150 hdmi->hdmi_data.rgb_limited_range) { 1151 csc_coeff = &csc_coeff_rgb_full_to_rgb_limited; 1152 } 1153 1154 /* The CSC registers are sequential, alternating MSB then LSB */ 1155 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 1156 u16 coeff_a = (*csc_coeff)[0][i]; 1157 u16 coeff_b = (*csc_coeff)[1][i]; 1158 u16 coeff_c = (*csc_coeff)[2][i]; 1159 1160 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 1161 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 1162 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 1163 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 1164 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 1165 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 1166 } 1167 1168 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 1169 HDMI_CSC_SCALE); 1170 } 1171 1172 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1173 { 1174 int color_depth = 0; 1175 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1176 int decimation = 0; 1177 1178 /* YCC422 interpolation to 444 mode */ 1179 if (is_color_space_interpolation(hdmi)) 1180 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1181 else if (is_color_space_decimation(hdmi)) 1182 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1183 1184 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1185 case 8: 1186 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1187 break; 1188 case 10: 1189 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1190 break; 1191 case 12: 1192 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1193 break; 1194 case 16: 1195 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1196 break; 1197 1198 default: 1199 return; 1200 } 1201 1202 /* Configure the CSC registers */ 1203 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1204 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1205 HDMI_CSC_SCALE); 1206 1207 dw_hdmi_update_csc_coeffs(hdmi); 1208 } 1209 1210 /* 1211 * HDMI video packetizer is used to packetize the data. 1212 * for example, if input is YCC422 mode or repeater is used, 1213 * data should be repacked this module can be bypassed. 1214 */ 1215 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1216 { 1217 unsigned int color_depth = 0; 1218 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1219 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1220 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1221 u8 val, vp_conf; 1222 u8 clear_gcp_auto = 0; 1223 1224 1225 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1226 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1227 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1228 switch (hdmi_bus_fmt_color_depth( 1229 hdmi->hdmi_data.enc_out_bus_format)) { 1230 case 8: 1231 color_depth = 4; 1232 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1233 clear_gcp_auto = 1; 1234 break; 1235 case 10: 1236 color_depth = 5; 1237 break; 1238 case 12: 1239 color_depth = 6; 1240 break; 1241 case 16: 1242 color_depth = 7; 1243 break; 1244 default: 1245 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1246 } 1247 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1248 switch (hdmi_bus_fmt_color_depth( 1249 hdmi->hdmi_data.enc_out_bus_format)) { 1250 case 0: 1251 case 8: 1252 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1253 clear_gcp_auto = 1; 1254 break; 1255 case 10: 1256 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1257 break; 1258 case 12: 1259 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1260 break; 1261 1262 default: 1263 return; 1264 } 1265 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1266 } else { 1267 return; 1268 } 1269 1270 /* set the packetizer registers */ 1271 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1272 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 1273 ((hdmi_data->pix_repet_factor << 1274 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 1275 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 1276 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1277 1278 /* HDMI1.4b specification section 6.5.3: 1279 * Source shall only send GCPs with non-zero CD to sinks 1280 * that indicate support for Deep Color. 1281 * GCP only transmit CD and do not handle AVMUTE, PP norDefault_Phase (yet). 1282 * Disable Auto GCP when 24-bit color for sinks that not support Deep Color. 1283 */ 1284 val = hdmi_readb(hdmi, HDMI_FC_DATAUTO3); 1285 if (clear_gcp_auto == 1) 1286 val &= ~HDMI_FC_DATAUTO3_GCP_AUTO; 1287 else 1288 val |= HDMI_FC_DATAUTO3_GCP_AUTO; 1289 hdmi_writeb(hdmi, val, HDMI_FC_DATAUTO3); 1290 1291 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1292 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1293 1294 /* Data from pixel repeater block */ 1295 if (hdmi_data->pix_repet_factor > 1) { 1296 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1297 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1298 } else { /* data from packetizer block */ 1299 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1300 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1301 } 1302 1303 hdmi_modb(hdmi, vp_conf, 1304 HDMI_VP_CONF_PR_EN_MASK | 1305 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1306 1307 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1308 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1309 1310 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1311 1312 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1313 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1314 HDMI_VP_CONF_PP_EN_ENABLE | 1315 HDMI_VP_CONF_YCC422_EN_DISABLE; 1316 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1317 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1318 HDMI_VP_CONF_PP_EN_DISABLE | 1319 HDMI_VP_CONF_YCC422_EN_ENABLE; 1320 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1321 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1322 HDMI_VP_CONF_PP_EN_DISABLE | 1323 HDMI_VP_CONF_YCC422_EN_DISABLE; 1324 } else { 1325 return; 1326 } 1327 1328 hdmi_modb(hdmi, vp_conf, 1329 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1330 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1331 1332 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1333 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1334 HDMI_VP_STUFF_PP_STUFFING_MASK | 1335 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1336 1337 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1338 HDMI_VP_CONF); 1339 } 1340 1341 /* ----------------------------------------------------------------------------- 1342 * Synopsys PHY Handling 1343 */ 1344 1345 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 1346 unsigned char bit) 1347 { 1348 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 1349 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 1350 } 1351 1352 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 1353 { 1354 u32 val; 1355 1356 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 1357 if (msec-- == 0) 1358 return false; 1359 udelay(1000); 1360 } 1361 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1362 1363 return true; 1364 } 1365 1366 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1367 unsigned char addr) 1368 { 1369 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1370 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1371 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1372 HDMI_PHY_I2CM_DATAO_1_ADDR); 1373 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1374 HDMI_PHY_I2CM_DATAO_0_ADDR); 1375 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1376 HDMI_PHY_I2CM_OPERATION_ADDR); 1377 hdmi_phy_wait_i2c_done(hdmi, 1000); 1378 } 1379 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1380 1381 /* Filter out invalid setups to avoid configuring SCDC and scrambling */ 1382 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi, 1383 const struct drm_display_info *display) 1384 { 1385 /* Completely disable SCDC support for older controllers */ 1386 if (hdmi->version < 0x200a) 1387 return false; 1388 1389 /* Disable if no DDC bus */ 1390 if (!hdmi->ddc) 1391 return false; 1392 1393 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ 1394 if (!display->hdmi.scdc.supported || 1395 !display->hdmi.scdc.scrambling.supported) 1396 return false; 1397 1398 /* 1399 * Disable if display only support low TMDS rates and scrambling 1400 * for low rates is not supported either 1401 */ 1402 if (!display->hdmi.scdc.scrambling.low_rates && 1403 display->max_tmds_clock <= 340000) 1404 return false; 1405 1406 return true; 1407 } 1408 1409 /* 1410 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: 1411 * - The Source shall suspend transmission of the TMDS clock and data 1412 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it 1413 * from a 0 to a 1 or from a 1 to a 0 1414 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from 1415 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming 1416 * transmission of TMDS clock and data 1417 * 1418 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() 1419 * helper should called right before enabling the TMDS Clock and Data in 1420 * the PHY configuration callback. 1421 */ 1422 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi, 1423 const struct drm_display_info *display) 1424 { 1425 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1426 1427 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 1428 if (dw_hdmi_support_scdc(hdmi, display)) { 1429 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1430 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 1); 1431 else 1432 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 0); 1433 } 1434 } 1435 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); 1436 1437 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1438 { 1439 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1440 HDMI_PHY_CONF0_PDZ_OFFSET, 1441 HDMI_PHY_CONF0_PDZ_MASK); 1442 } 1443 1444 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1445 { 1446 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1447 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1448 HDMI_PHY_CONF0_ENTMDS_MASK); 1449 } 1450 1451 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1452 { 1453 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1454 HDMI_PHY_CONF0_SVSRET_OFFSET, 1455 HDMI_PHY_CONF0_SVSRET_MASK); 1456 } 1457 1458 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1459 { 1460 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1461 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1462 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1463 } 1464 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1465 1466 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1467 { 1468 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1469 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1470 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1471 } 1472 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1473 1474 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1475 { 1476 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1477 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1478 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1479 } 1480 1481 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1482 { 1483 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1484 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1485 HDMI_PHY_CONF0_SELDIPIF_MASK); 1486 } 1487 1488 void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi) 1489 { 1490 /* PHY reset. The reset signal is active low on Gen1 PHYs. */ 1491 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1492 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1493 } 1494 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset); 1495 1496 void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi) 1497 { 1498 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1499 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1500 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1501 } 1502 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset); 1503 1504 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1505 { 1506 hdmi_phy_test_clear(hdmi, 1); 1507 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1508 hdmi_phy_test_clear(hdmi, 0); 1509 } 1510 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1511 1512 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1513 { 1514 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1515 unsigned int i; 1516 u16 val; 1517 1518 if (phy->gen == 1) { 1519 dw_hdmi_phy_enable_tmds(hdmi, 0); 1520 dw_hdmi_phy_enable_powerdown(hdmi, true); 1521 return; 1522 } 1523 1524 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1525 1526 /* 1527 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1528 * to low power mode. 1529 */ 1530 for (i = 0; i < 5; ++i) { 1531 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1532 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1533 break; 1534 1535 usleep_range(1000, 2000); 1536 } 1537 1538 if (val & HDMI_PHY_TX_PHY_LOCK) 1539 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1540 else 1541 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1542 1543 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1544 } 1545 1546 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1547 { 1548 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1549 unsigned int i; 1550 u8 val; 1551 1552 if (phy->gen == 1) { 1553 dw_hdmi_phy_enable_powerdown(hdmi, false); 1554 1555 /* Toggle TMDS enable. */ 1556 dw_hdmi_phy_enable_tmds(hdmi, 0); 1557 dw_hdmi_phy_enable_tmds(hdmi, 1); 1558 return 0; 1559 } 1560 1561 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1562 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1563 1564 /* Wait for PHY PLL lock */ 1565 for (i = 0; i < 5; ++i) { 1566 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1567 if (val) 1568 break; 1569 1570 usleep_range(1000, 2000); 1571 } 1572 1573 if (!val) { 1574 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1575 return -ETIMEDOUT; 1576 } 1577 1578 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1579 return 0; 1580 } 1581 1582 /* 1583 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1584 * information the DWC MHL PHY has the same register layout and is thus also 1585 * supported by this function. 1586 */ 1587 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1588 const struct dw_hdmi_plat_data *pdata, 1589 unsigned long mpixelclock) 1590 { 1591 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1592 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1593 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1594 1595 /* TOFIX Will need 420 specific PHY configuration tables */ 1596 1597 /* PLL/MPLL Cfg - always match on final entry */ 1598 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1599 if (mpixelclock <= mpll_config->mpixelclock) 1600 break; 1601 1602 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1603 if (mpixelclock <= curr_ctrl->mpixelclock) 1604 break; 1605 1606 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1607 if (mpixelclock <= phy_config->mpixelclock) 1608 break; 1609 1610 if (mpll_config->mpixelclock == ~0UL || 1611 curr_ctrl->mpixelclock == ~0UL || 1612 phy_config->mpixelclock == ~0UL) 1613 return -EINVAL; 1614 1615 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1616 HDMI_3D_TX_PHY_CPCE_CTRL); 1617 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1618 HDMI_3D_TX_PHY_GMPCTRL); 1619 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1620 HDMI_3D_TX_PHY_CURRCTRL); 1621 1622 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1623 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1624 HDMI_3D_TX_PHY_MSM_CTRL); 1625 1626 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1627 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1628 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1629 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1630 HDMI_3D_TX_PHY_VLEVCTRL); 1631 1632 /* Override and disable clock termination. */ 1633 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1634 HDMI_3D_TX_PHY_CKCALCTRL); 1635 1636 return 0; 1637 } 1638 1639 static int hdmi_phy_configure(struct dw_hdmi *hdmi, 1640 const struct drm_display_info *display) 1641 { 1642 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1643 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1644 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1645 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1646 int ret; 1647 1648 dw_hdmi_phy_power_off(hdmi); 1649 1650 dw_hdmi_set_high_tmds_clock_ratio(hdmi, display); 1651 1652 /* Leave low power consumption mode by asserting SVSRET. */ 1653 if (phy->has_svsret) 1654 dw_hdmi_phy_enable_svsret(hdmi, 1); 1655 1656 dw_hdmi_phy_gen2_reset(hdmi); 1657 1658 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1659 1660 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1661 1662 /* Write to the PHY as configured by the platform */ 1663 if (pdata->configure_phy) 1664 ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock); 1665 else 1666 ret = phy->configure(hdmi, pdata, mpixelclock); 1667 if (ret) { 1668 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1669 mpixelclock); 1670 return ret; 1671 } 1672 1673 /* Wait for resuming transmission of TMDS clock and data */ 1674 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1675 msleep(100); 1676 1677 return dw_hdmi_phy_power_on(hdmi); 1678 } 1679 1680 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1681 const struct drm_display_info *display, 1682 const struct drm_display_mode *mode) 1683 { 1684 int i, ret; 1685 1686 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1687 for (i = 0; i < 2; i++) { 1688 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1689 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1690 1691 ret = hdmi_phy_configure(hdmi, display); 1692 if (ret) 1693 return ret; 1694 } 1695 1696 return 0; 1697 } 1698 1699 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1700 { 1701 dw_hdmi_phy_power_off(hdmi); 1702 } 1703 1704 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1705 void *data) 1706 { 1707 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1708 connector_status_connected : connector_status_disconnected; 1709 } 1710 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1711 1712 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1713 bool force, bool disabled, bool rxsense) 1714 { 1715 u8 old_mask = hdmi->phy_mask; 1716 1717 if (force || disabled || !rxsense) 1718 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1719 else 1720 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1721 1722 if (old_mask != hdmi->phy_mask) 1723 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1724 } 1725 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1726 1727 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1728 { 1729 /* 1730 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1731 * any pending interrupt. 1732 */ 1733 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1734 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1735 HDMI_IH_PHY_STAT0); 1736 1737 /* Enable cable hot plug irq. */ 1738 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1739 1740 /* Clear and unmute interrupts. */ 1741 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1742 HDMI_IH_PHY_STAT0); 1743 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1744 HDMI_IH_MUTE_PHY_STAT0); 1745 } 1746 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1747 1748 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1749 .init = dw_hdmi_phy_init, 1750 .disable = dw_hdmi_phy_disable, 1751 .read_hpd = dw_hdmi_phy_read_hpd, 1752 .update_hpd = dw_hdmi_phy_update_hpd, 1753 .setup_hpd = dw_hdmi_phy_setup_hpd, 1754 }; 1755 1756 /* ----------------------------------------------------------------------------- 1757 * HDMI TX Setup 1758 */ 1759 1760 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1761 { 1762 u8 de; 1763 1764 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1765 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1766 else 1767 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1768 1769 /* disable rx detect */ 1770 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1771 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1772 1773 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1774 1775 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1776 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1777 } 1778 1779 static void hdmi_config_AVI(struct dw_hdmi *hdmi, 1780 const struct drm_connector *connector, 1781 const struct drm_display_mode *mode) 1782 { 1783 struct hdmi_avi_infoframe frame; 1784 u8 val; 1785 1786 /* Initialise info frame from DRM mode */ 1787 drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1788 1789 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 1790 drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode, 1791 hdmi->hdmi_data.rgb_limited_range ? 1792 HDMI_QUANTIZATION_RANGE_LIMITED : 1793 HDMI_QUANTIZATION_RANGE_FULL); 1794 } else { 1795 frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 1796 frame.ycc_quantization_range = 1797 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 1798 } 1799 1800 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1801 frame.colorspace = HDMI_COLORSPACE_YUV444; 1802 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1803 frame.colorspace = HDMI_COLORSPACE_YUV422; 1804 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1805 frame.colorspace = HDMI_COLORSPACE_YUV420; 1806 else 1807 frame.colorspace = HDMI_COLORSPACE_RGB; 1808 1809 /* Set up colorimetry */ 1810 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 1811 switch (hdmi->hdmi_data.enc_out_encoding) { 1812 case V4L2_YCBCR_ENC_601: 1813 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1814 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1815 else 1816 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1817 frame.extended_colorimetry = 1818 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1819 break; 1820 case V4L2_YCBCR_ENC_709: 1821 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1822 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1823 else 1824 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1825 frame.extended_colorimetry = 1826 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1827 break; 1828 default: /* Carries no data */ 1829 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1830 frame.extended_colorimetry = 1831 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1832 break; 1833 } 1834 } else { 1835 frame.colorimetry = HDMI_COLORIMETRY_NONE; 1836 frame.extended_colorimetry = 1837 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1838 } 1839 1840 /* 1841 * The Designware IP uses a different byte format from standard 1842 * AVI info frames, though generally the bits are in the correct 1843 * bytes. 1844 */ 1845 1846 /* 1847 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1848 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1849 * bit 6 rather than 4. 1850 */ 1851 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1852 if (frame.active_aspect & 15) 1853 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1854 if (frame.top_bar || frame.bottom_bar) 1855 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1856 if (frame.left_bar || frame.right_bar) 1857 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1858 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1859 1860 /* AVI data byte 2 differences: none */ 1861 val = ((frame.colorimetry & 0x3) << 6) | 1862 ((frame.picture_aspect & 0x3) << 4) | 1863 (frame.active_aspect & 0xf); 1864 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1865 1866 /* AVI data byte 3 differences: none */ 1867 val = ((frame.extended_colorimetry & 0x7) << 4) | 1868 ((frame.quantization_range & 0x3) << 2) | 1869 (frame.nups & 0x3); 1870 if (frame.itc) 1871 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1872 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1873 1874 /* AVI data byte 4 differences: none */ 1875 val = frame.video_code & 0x7f; 1876 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1877 1878 /* AVI Data Byte 5- set up input and output pixel repetition */ 1879 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1880 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1881 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1882 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1883 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1884 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1885 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1886 1887 /* 1888 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1889 * ycc range in bits 2,3 rather than 6,7 1890 */ 1891 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1892 (frame.content_type & 0x3); 1893 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1894 1895 /* AVI Data Bytes 6-13 */ 1896 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1897 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1898 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1899 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1900 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1901 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1902 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1903 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1904 } 1905 1906 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1907 const struct drm_connector *connector, 1908 const struct drm_display_mode *mode) 1909 { 1910 struct hdmi_vendor_infoframe frame; 1911 u8 buffer[10]; 1912 ssize_t err; 1913 1914 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, connector, 1915 mode); 1916 if (err < 0) 1917 /* 1918 * Going into that statement does not means vendor infoframe 1919 * fails. It just informed us that vendor infoframe is not 1920 * needed for the selected mode. Only 4k or stereoscopic 3D 1921 * mode requires vendor infoframe. So just simply return. 1922 */ 1923 return; 1924 1925 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1926 if (err < 0) { 1927 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1928 err); 1929 return; 1930 } 1931 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1932 HDMI_FC_DATAUTO0_VSD_MASK); 1933 1934 /* Set the length of HDMI vendor specific InfoFrame payload */ 1935 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1936 1937 /* Set 24bit IEEE Registration Identifier */ 1938 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1939 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1940 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1941 1942 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1943 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1944 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1945 1946 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1947 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1948 1949 /* Packet frame interpolation */ 1950 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1951 1952 /* Auto packets per frame and line spacing */ 1953 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1954 1955 /* Configures the Frame Composer On RDRB mode */ 1956 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1957 HDMI_FC_DATAUTO0_VSD_MASK); 1958 } 1959 1960 static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, 1961 const struct drm_connector *connector) 1962 { 1963 const struct drm_connector_state *conn_state = connector->state; 1964 struct hdmi_drm_infoframe frame; 1965 u8 buffer[30]; 1966 ssize_t err; 1967 int i; 1968 1969 if (!hdmi->plat_data->use_drm_infoframe) 1970 return; 1971 1972 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE, 1973 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1974 1975 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state); 1976 if (err < 0) 1977 return; 1978 1979 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer)); 1980 if (err < 0) { 1981 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err); 1982 return; 1983 } 1984 1985 hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0); 1986 hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1); 1987 1988 for (i = 0; i < frame.length; i++) 1989 hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i); 1990 1991 hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP); 1992 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE, 1993 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1994 } 1995 1996 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1997 const struct drm_display_info *display, 1998 const struct drm_display_mode *mode) 1999 { 2000 u8 inv_val, bytes; 2001 const struct drm_hdmi_info *hdmi_info = &display->hdmi; 2002 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 2003 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 2004 unsigned int vdisplay, hdisplay; 2005 2006 vmode->mpixelclock = mode->clock * 1000; 2007 2008 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 2009 2010 vmode->mtmdsclock = vmode->mpixelclock; 2011 2012 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 2013 switch (hdmi_bus_fmt_color_depth( 2014 hdmi->hdmi_data.enc_out_bus_format)) { 2015 case 16: 2016 vmode->mtmdsclock = vmode->mpixelclock * 2; 2017 break; 2018 case 12: 2019 vmode->mtmdsclock = vmode->mpixelclock * 3 / 2; 2020 break; 2021 case 10: 2022 vmode->mtmdsclock = vmode->mpixelclock * 5 / 4; 2023 break; 2024 } 2025 } 2026 2027 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 2028 vmode->mtmdsclock /= 2; 2029 2030 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock); 2031 2032 /* Set up HDMI_FC_INVIDCONF */ 2033 inv_val = (hdmi->hdmi_data.hdcp_enable || 2034 (dw_hdmi_support_scdc(hdmi, display) && 2035 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 2036 hdmi_info->scdc.scrambling.low_rates)) ? 2037 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 2038 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 2039 2040 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 2041 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 2042 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 2043 2044 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 2045 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 2046 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 2047 2048 inv_val |= (vmode->mdataenablepolarity ? 2049 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 2050 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 2051 2052 if (hdmi->vic == 39) 2053 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 2054 else 2055 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 2056 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 2057 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 2058 2059 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 2060 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 2061 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 2062 2063 inv_val |= hdmi->sink_is_hdmi ? 2064 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 2065 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 2066 2067 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 2068 2069 hdisplay = mode->hdisplay; 2070 hblank = mode->htotal - mode->hdisplay; 2071 h_de_hs = mode->hsync_start - mode->hdisplay; 2072 hsync_len = mode->hsync_end - mode->hsync_start; 2073 2074 /* 2075 * When we're setting a YCbCr420 mode, we need 2076 * to adjust the horizontal timing to suit. 2077 */ 2078 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 2079 hdisplay /= 2; 2080 hblank /= 2; 2081 h_de_hs /= 2; 2082 hsync_len /= 2; 2083 } 2084 2085 vdisplay = mode->vdisplay; 2086 vblank = mode->vtotal - mode->vdisplay; 2087 v_de_vs = mode->vsync_start - mode->vdisplay; 2088 vsync_len = mode->vsync_end - mode->vsync_start; 2089 2090 /* 2091 * When we're setting an interlaced mode, we need 2092 * to adjust the vertical timing to suit. 2093 */ 2094 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 2095 vdisplay /= 2; 2096 vblank /= 2; 2097 v_de_vs /= 2; 2098 vsync_len /= 2; 2099 } 2100 2101 /* Scrambling Control */ 2102 if (dw_hdmi_support_scdc(hdmi, display)) { 2103 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 2104 hdmi_info->scdc.scrambling.low_rates) { 2105 /* 2106 * HDMI2.0 Specifies the following procedure: 2107 * After the Source Device has determined that 2108 * SCDC_Present is set (=1), the Source Device should 2109 * write the accurate Version of the Source Device 2110 * to the Source Version field in the SCDCS. 2111 * Source Devices compliant shall set the 2112 * Source Version = 1. 2113 */ 2114 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, 2115 &bytes); 2116 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, 2117 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 2118 2119 /* Enabled Scrambling in the Sink */ 2120 drm_scdc_set_scrambling(hdmi->curr_conn, 1); 2121 2122 /* 2123 * To activate the scrambler feature, you must ensure 2124 * that the quasi-static configuration bit 2125 * fc_invidconf.HDCP_keepout is set at configuration 2126 * time, before the required mc_swrstzreq.tmdsswrst_req 2127 * reset request is issued. 2128 */ 2129 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 2130 HDMI_MC_SWRSTZ); 2131 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 2132 } else { 2133 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 2134 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 2135 HDMI_MC_SWRSTZ); 2136 drm_scdc_set_scrambling(hdmi->curr_conn, 0); 2137 } 2138 } 2139 2140 /* Set up horizontal active pixel width */ 2141 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 2142 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 2143 2144 /* Set up vertical active lines */ 2145 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 2146 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 2147 2148 /* Set up horizontal blanking pixel region width */ 2149 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 2150 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 2151 2152 /* Set up vertical blanking pixel region width */ 2153 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 2154 2155 /* Set up HSYNC active edge delay width (in pixel clks) */ 2156 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 2157 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 2158 2159 /* Set up VSYNC active edge delay (in lines) */ 2160 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 2161 2162 /* Set up HSYNC active pulse width (in pixel clks) */ 2163 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 2164 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 2165 2166 /* Set up VSYNC active edge delay (in lines) */ 2167 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 2168 } 2169 2170 /* HDMI Initialization Step B.4 */ 2171 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 2172 { 2173 /* control period minimum duration */ 2174 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 2175 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 2176 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 2177 2178 /* Set to fill TMDS data channels */ 2179 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 2180 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 2181 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 2182 2183 /* Enable pixel clock and tmds data path */ 2184 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 2185 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 2186 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 2187 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 2188 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 2189 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 2190 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2191 2192 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 2193 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2194 2195 /* Enable csc path */ 2196 if (is_csc_needed(hdmi)) { 2197 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 2198 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2199 2200 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 2201 HDMI_MC_FLOWCTRL); 2202 } else { 2203 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE; 2204 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2205 2206 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 2207 HDMI_MC_FLOWCTRL); 2208 } 2209 } 2210 2211 /* Workaround to clear the overflow condition */ 2212 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 2213 { 2214 unsigned int count; 2215 unsigned int i; 2216 u8 val; 2217 2218 /* 2219 * Under some circumstances the Frame Composer arithmetic unit can miss 2220 * an FC register write due to being busy processing the previous one. 2221 * The issue can be worked around by issuing a TMDS software reset and 2222 * then write one of the FC registers several times. 2223 * 2224 * The number of iterations matters and depends on the HDMI TX revision 2225 * (and possibly on the platform). 2226 * 4 iterations for i.MX6Q(v1.30a) and 1 iteration for others. 2227 * i.MX6DL (v1.31a), Allwinner SoCs (v1.32a), Rockchip RK3288 SoC (v2.00a), 2228 * Amlogic Meson GX SoCs (v2.01a), RK3328/RK3399 SoCs (v2.11a) 2229 * and i.MX8MPlus (v2.13a) have been identified as needing the workaround 2230 * with a single iteration. 2231 */ 2232 2233 switch (hdmi->version) { 2234 case 0x130a: 2235 count = 4; 2236 break; 2237 default: 2238 count = 1; 2239 break; 2240 } 2241 2242 /* TMDS software reset */ 2243 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 2244 2245 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 2246 for (i = 0; i < count; i++) 2247 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 2248 } 2249 2250 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 2251 { 2252 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 2253 HDMI_IH_MUTE_FC_STAT2); 2254 } 2255 2256 static int dw_hdmi_setup(struct dw_hdmi *hdmi, 2257 const struct drm_connector *connector, 2258 const struct drm_display_mode *mode) 2259 { 2260 int ret; 2261 2262 hdmi_disable_overflow_interrupts(hdmi); 2263 2264 hdmi->vic = drm_match_cea_mode(mode); 2265 2266 if (!hdmi->vic) { 2267 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 2268 } else { 2269 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 2270 } 2271 2272 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 2273 (hdmi->vic == 21) || (hdmi->vic == 22) || 2274 (hdmi->vic == 2) || (hdmi->vic == 3) || 2275 (hdmi->vic == 17) || (hdmi->vic == 18)) 2276 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2277 else 2278 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2279 2280 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2281 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2282 2283 if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED) 2284 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2285 2286 /* TOFIX: Get input encoding from plat data or fallback to none */ 2287 if (hdmi->plat_data->input_bus_encoding) 2288 hdmi->hdmi_data.enc_in_encoding = 2289 hdmi->plat_data->input_bus_encoding; 2290 else 2291 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2292 2293 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED) 2294 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2295 2296 hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi && 2297 drm_default_rgb_quant_range(mode) == 2298 HDMI_QUANTIZATION_RANGE_LIMITED; 2299 2300 hdmi->hdmi_data.pix_repet_factor = 0; 2301 hdmi->hdmi_data.hdcp_enable = 0; 2302 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2303 2304 /* HDMI Initialization Step B.1 */ 2305 hdmi_av_composer(hdmi, &connector->display_info, mode); 2306 2307 /* HDMI Initializateion Step B.2 */ 2308 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, 2309 &connector->display_info, 2310 &hdmi->previous_mode); 2311 if (ret) 2312 return ret; 2313 hdmi->phy.enabled = true; 2314 2315 /* HDMI Initialization Step B.3 */ 2316 dw_hdmi_enable_video_path(hdmi); 2317 2318 if (hdmi->sink_has_audio) { 2319 dev_dbg(hdmi->dev, "sink has audio support\n"); 2320 2321 /* HDMI Initialization Step E - Configure audio */ 2322 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2323 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable); 2324 } 2325 2326 /* not for DVI mode */ 2327 if (hdmi->sink_is_hdmi) { 2328 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 2329 2330 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2331 hdmi_config_AVI(hdmi, connector, mode); 2332 hdmi_config_vendor_specific_infoframe(hdmi, connector, mode); 2333 hdmi_config_drm_infoframe(hdmi, connector); 2334 } else { 2335 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 2336 } 2337 2338 hdmi_video_packetize(hdmi); 2339 hdmi_video_csc(hdmi); 2340 hdmi_video_sample(hdmi); 2341 hdmi_tx_hdcp_config(hdmi); 2342 2343 dw_hdmi_clear_overflow(hdmi); 2344 2345 return 0; 2346 } 2347 2348 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 2349 { 2350 u8 ih_mute; 2351 2352 /* 2353 * Boot up defaults are: 2354 * HDMI_IH_MUTE = 0x03 (disabled) 2355 * HDMI_IH_MUTE_* = 0x00 (enabled) 2356 * 2357 * Disable top level interrupt bits in HDMI block 2358 */ 2359 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 2360 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2361 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 2362 2363 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2364 2365 /* by default mask all interrupts */ 2366 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 2367 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2368 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2369 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2370 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 2371 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 2372 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 2373 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 2374 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 2375 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 2376 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 2377 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 2378 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 2379 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 2380 2381 /* Disable interrupts in the IH_MUTE_* registers */ 2382 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2383 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2384 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2385 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2386 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 2387 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2388 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2389 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2390 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2391 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2392 2393 /* Enable top level interrupt bits in HDMI block */ 2394 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2395 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 2396 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2397 } 2398 2399 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 2400 { 2401 hdmi->bridge_is_on = true; 2402 2403 /* 2404 * The curr_conn field is guaranteed to be valid here, as this function 2405 * is only be called when !hdmi->disabled. 2406 */ 2407 dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); 2408 } 2409 2410 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 2411 { 2412 if (hdmi->phy.enabled) { 2413 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 2414 hdmi->phy.enabled = false; 2415 } 2416 2417 hdmi->bridge_is_on = false; 2418 } 2419 2420 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 2421 { 2422 int force = hdmi->force; 2423 2424 if (hdmi->disabled) { 2425 force = DRM_FORCE_OFF; 2426 } else if (force == DRM_FORCE_UNSPECIFIED) { 2427 if (hdmi->rxsense) 2428 force = DRM_FORCE_ON; 2429 else 2430 force = DRM_FORCE_OFF; 2431 } 2432 2433 if (force == DRM_FORCE_OFF) { 2434 if (hdmi->bridge_is_on) 2435 dw_hdmi_poweroff(hdmi); 2436 } else { 2437 if (!hdmi->bridge_is_on) 2438 dw_hdmi_poweron(hdmi); 2439 } 2440 } 2441 2442 /* 2443 * Adjust the detection of RXSENSE according to whether we have a forced 2444 * connection mode enabled, or whether we have been disabled. There is 2445 * no point processing RXSENSE interrupts if we have a forced connection 2446 * state, or DRM has us disabled. 2447 * 2448 * We also disable rxsense interrupts when we think we're disconnected 2449 * to avoid floating TDMS signals giving false rxsense interrupts. 2450 * 2451 * Note: we still need to listen for HPD interrupts even when DRM has us 2452 * disabled so that we can detect a connect event. 2453 */ 2454 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 2455 { 2456 if (hdmi->phy.ops->update_hpd) 2457 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 2458 hdmi->force, hdmi->disabled, 2459 hdmi->rxsense); 2460 } 2461 2462 static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi) 2463 { 2464 enum drm_connector_status result; 2465 2466 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 2467 hdmi->last_connector_result = result; 2468 2469 return result; 2470 } 2471 2472 static const struct drm_edid *dw_hdmi_edid_read(struct dw_hdmi *hdmi, 2473 struct drm_connector *connector) 2474 { 2475 const struct drm_edid *drm_edid; 2476 const struct edid *edid; 2477 2478 if (!hdmi->ddc) 2479 return NULL; 2480 2481 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc); 2482 if (!drm_edid) { 2483 dev_dbg(hdmi->dev, "failed to get edid\n"); 2484 return NULL; 2485 } 2486 2487 /* 2488 * FIXME: This should use connector->display_info.is_hdmi and 2489 * connector->display_info.has_audio from a path that has read the EDID 2490 * and called drm_edid_connector_update(). 2491 */ 2492 edid = drm_edid_raw(drm_edid); 2493 2494 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 2495 edid->width_cm, edid->height_cm); 2496 2497 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 2498 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2499 2500 return drm_edid; 2501 } 2502 2503 /* ----------------------------------------------------------------------------- 2504 * DRM Connector Operations 2505 */ 2506 2507 static enum drm_connector_status 2508 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 2509 { 2510 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2511 connector); 2512 return dw_hdmi_detect(hdmi); 2513 } 2514 2515 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 2516 { 2517 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2518 connector); 2519 const struct drm_edid *drm_edid; 2520 int ret; 2521 2522 drm_edid = dw_hdmi_edid_read(hdmi, connector); 2523 2524 drm_edid_connector_update(connector, drm_edid); 2525 cec_notifier_set_phys_addr(hdmi->cec_notifier, 2526 connector->display_info.source_physical_address); 2527 ret = drm_edid_connector_add_modes(connector); 2528 drm_edid_free(drm_edid); 2529 2530 return ret; 2531 } 2532 2533 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, 2534 struct drm_atomic_commit *state) 2535 { 2536 struct drm_connector_state *old_state = 2537 drm_atomic_get_old_connector_state(state, connector); 2538 struct drm_connector_state *new_state = 2539 drm_atomic_get_new_connector_state(state, connector); 2540 struct drm_crtc *crtc = new_state->crtc; 2541 struct drm_crtc_state *crtc_state; 2542 2543 if (!crtc) 2544 return 0; 2545 2546 if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 2547 crtc_state = drm_atomic_get_crtc_state(state, crtc); 2548 if (IS_ERR(crtc_state)) 2549 return PTR_ERR(crtc_state); 2550 2551 crtc_state->mode_changed = true; 2552 } 2553 2554 return 0; 2555 } 2556 2557 static void dw_hdmi_connector_force(struct drm_connector *connector) 2558 { 2559 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2560 connector); 2561 2562 mutex_lock(&hdmi->mutex); 2563 hdmi->force = connector->force; 2564 dw_hdmi_update_power(hdmi); 2565 dw_hdmi_update_phy_mask(hdmi); 2566 mutex_unlock(&hdmi->mutex); 2567 } 2568 2569 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 2570 .fill_modes = drm_helper_probe_single_connector_modes, 2571 .detect = dw_hdmi_connector_detect, 2572 .destroy = drm_connector_cleanup, 2573 .force = dw_hdmi_connector_force, 2574 .reset = drm_atomic_helper_connector_reset, 2575 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2576 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2577 }; 2578 2579 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 2580 .get_modes = dw_hdmi_connector_get_modes, 2581 .atomic_check = dw_hdmi_connector_atomic_check, 2582 }; 2583 2584 static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) 2585 { 2586 struct drm_connector *connector = &hdmi->connector; 2587 struct cec_connector_info conn_info; 2588 struct cec_notifier *notifier; 2589 2590 if (hdmi->version >= 0x200a) 2591 connector->ycbcr_420_allowed = 2592 hdmi->plat_data->ycbcr_420_allowed; 2593 else 2594 connector->ycbcr_420_allowed = false; 2595 2596 connector->interlace_allowed = 1; 2597 connector->polled = DRM_CONNECTOR_POLL_HPD; 2598 2599 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 2600 2601 drm_connector_init_with_ddc(hdmi->bridge.dev, connector, 2602 &dw_hdmi_connector_funcs, 2603 DRM_MODE_CONNECTOR_HDMIA, 2604 hdmi->ddc); 2605 2606 /* 2607 * drm_connector_attach_max_bpc_property() requires the 2608 * connector to have a state. 2609 */ 2610 drm_atomic_helper_connector_reset(connector); 2611 2612 drm_connector_attach_max_bpc_property(connector, 8, 16); 2613 2614 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) 2615 drm_connector_attach_hdr_output_metadata_property(connector); 2616 2617 drm_connector_attach_encoder(connector, hdmi->bridge.encoder); 2618 2619 cec_fill_conn_info_from_drm(&conn_info, connector); 2620 2621 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info); 2622 if (!notifier) 2623 return -ENOMEM; 2624 2625 mutex_lock(&hdmi->cec_notifier_mutex); 2626 hdmi->cec_notifier = notifier; 2627 mutex_unlock(&hdmi->cec_notifier_mutex); 2628 2629 return 0; 2630 } 2631 2632 /* ----------------------------------------------------------------------------- 2633 * DRM Bridge Operations 2634 */ 2635 2636 /* 2637 * Possible output formats : 2638 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48, 2639 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36, 2640 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30, 2641 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24, 2642 * - MEDIA_BUS_FMT_RGB888_1X24, 2643 * - MEDIA_BUS_FMT_YUV16_1X48, 2644 * - MEDIA_BUS_FMT_RGB161616_1X48, 2645 * - MEDIA_BUS_FMT_UYVY12_1X24, 2646 * - MEDIA_BUS_FMT_YUV12_1X36, 2647 * - MEDIA_BUS_FMT_RGB121212_1X36, 2648 * - MEDIA_BUS_FMT_UYVY10_1X20, 2649 * - MEDIA_BUS_FMT_YUV10_1X30, 2650 * - MEDIA_BUS_FMT_RGB101010_1X30, 2651 * - MEDIA_BUS_FMT_UYVY8_1X16, 2652 * - MEDIA_BUS_FMT_YUV8_1X24, 2653 */ 2654 2655 /* Can return a maximum of 11 possible output formats for a mode/connector */ 2656 #define MAX_OUTPUT_SEL_FORMATS 11 2657 2658 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 2659 struct drm_bridge_state *bridge_state, 2660 struct drm_crtc_state *crtc_state, 2661 struct drm_connector_state *conn_state, 2662 unsigned int *num_output_fmts) 2663 { 2664 struct drm_connector *conn = conn_state->connector; 2665 struct drm_display_info *info = &conn->display_info; 2666 struct drm_display_mode *mode = &crtc_state->mode; 2667 u8 max_bpc = conn_state->max_requested_bpc; 2668 bool is_hdmi2_sink = info->hdmi.scdc.supported || 2669 (info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR420)); 2670 u32 *output_fmts; 2671 unsigned int i = 0; 2672 2673 *num_output_fmts = 0; 2674 2675 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), 2676 GFP_KERNEL); 2677 if (!output_fmts) 2678 return NULL; 2679 2680 /* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */ 2681 if (list_is_singular(&bridge->encoder->bridge_chain) || 2682 list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) { 2683 *num_output_fmts = 1; 2684 output_fmts[0] = MEDIA_BUS_FMT_FIXED; 2685 2686 return output_fmts; 2687 } 2688 2689 /* 2690 * If the current mode enforces 4:2:0, force the output bus format 2691 * to 4:2:0 and do not add the YUV422/444/RGB formats 2692 */ 2693 if (conn->ycbcr_420_allowed && 2694 (drm_mode_is_420_only(info, mode) || 2695 (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) { 2696 2697 /* Order bus formats from 16bit to 8bit if supported */ 2698 if (max_bpc >= 16 && info->bpc == 16 && 2699 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)) 2700 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48; 2701 2702 if (max_bpc >= 12 && info->bpc >= 12 && 2703 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) 2704 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36; 2705 2706 if (max_bpc >= 10 && info->bpc >= 10 && 2707 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)) 2708 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30; 2709 2710 /* Default 8bit fallback */ 2711 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; 2712 2713 if (drm_mode_is_420_only(info, mode)) { 2714 *num_output_fmts = i; 2715 return output_fmts; 2716 } 2717 } 2718 2719 /* 2720 * Order bus formats from 16bit to 8bit and from YUV422 to RGB 2721 * if supported. In any case the default RGB888 format is added 2722 */ 2723 2724 /* Default 8bit RGB fallback */ 2725 output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2726 2727 if (max_bpc >= 16 && info->bpc == 16) { 2728 if (info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444)) 2729 output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2730 2731 output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2732 } 2733 2734 if (max_bpc >= 12 && info->bpc >= 12) { 2735 if (info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422)) 2736 output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2737 2738 if (info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444)) 2739 output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2740 2741 output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2742 } 2743 2744 if (max_bpc >= 10 && info->bpc >= 10) { 2745 if (info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422)) 2746 output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2747 2748 if (info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444)) 2749 output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2750 2751 output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2752 } 2753 2754 if (info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR422)) 2755 output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2756 2757 if (info->color_formats & BIT(DRM_OUTPUT_COLOR_FORMAT_YCBCR444)) 2758 output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2759 2760 *num_output_fmts = i; 2761 2762 return output_fmts; 2763 } 2764 2765 /* 2766 * Possible input formats : 2767 * - MEDIA_BUS_FMT_RGB888_1X24 2768 * - MEDIA_BUS_FMT_YUV8_1X24 2769 * - MEDIA_BUS_FMT_UYVY8_1X16 2770 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24 2771 * - MEDIA_BUS_FMT_RGB101010_1X30 2772 * - MEDIA_BUS_FMT_YUV10_1X30 2773 * - MEDIA_BUS_FMT_UYVY10_1X20 2774 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30 2775 * - MEDIA_BUS_FMT_RGB121212_1X36 2776 * - MEDIA_BUS_FMT_YUV12_1X36 2777 * - MEDIA_BUS_FMT_UYVY12_1X24 2778 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36 2779 * - MEDIA_BUS_FMT_RGB161616_1X48 2780 * - MEDIA_BUS_FMT_YUV16_1X48 2781 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48 2782 */ 2783 2784 /* Can return a maximum of 3 possible input formats for an output format */ 2785 #define MAX_INPUT_SEL_FORMATS 3 2786 2787 static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 2788 struct drm_bridge_state *bridge_state, 2789 struct drm_crtc_state *crtc_state, 2790 struct drm_connector_state *conn_state, 2791 u32 output_fmt, 2792 unsigned int *num_input_fmts) 2793 { 2794 u32 *input_fmts; 2795 unsigned int i = 0; 2796 2797 *num_input_fmts = 0; 2798 2799 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 2800 GFP_KERNEL); 2801 if (!input_fmts) 2802 return NULL; 2803 2804 switch (output_fmt) { 2805 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */ 2806 case MEDIA_BUS_FMT_FIXED: 2807 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2808 break; 2809 /* 8bit */ 2810 case MEDIA_BUS_FMT_RGB888_1X24: 2811 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2812 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2813 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2814 break; 2815 case MEDIA_BUS_FMT_YUV8_1X24: 2816 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2817 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2818 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2819 break; 2820 case MEDIA_BUS_FMT_UYVY8_1X16: 2821 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2822 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2823 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2824 break; 2825 2826 /* 10bit */ 2827 case MEDIA_BUS_FMT_RGB101010_1X30: 2828 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2829 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2830 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2831 break; 2832 case MEDIA_BUS_FMT_YUV10_1X30: 2833 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2834 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2835 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2836 break; 2837 case MEDIA_BUS_FMT_UYVY10_1X20: 2838 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2839 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2840 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2841 break; 2842 2843 /* 12bit */ 2844 case MEDIA_BUS_FMT_RGB121212_1X36: 2845 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2846 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2847 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2848 break; 2849 case MEDIA_BUS_FMT_YUV12_1X36: 2850 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2851 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2852 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2853 break; 2854 case MEDIA_BUS_FMT_UYVY12_1X24: 2855 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2856 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2857 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2858 break; 2859 2860 /* 16bit */ 2861 case MEDIA_BUS_FMT_RGB161616_1X48: 2862 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2863 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2864 break; 2865 case MEDIA_BUS_FMT_YUV16_1X48: 2866 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2867 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2868 break; 2869 2870 /*YUV 4:2:0 */ 2871 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2872 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2873 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 2874 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 2875 input_fmts[i++] = output_fmt; 2876 break; 2877 } 2878 2879 *num_input_fmts = i; 2880 2881 if (*num_input_fmts == 0) { 2882 kfree(input_fmts); 2883 input_fmts = NULL; 2884 } 2885 2886 return input_fmts; 2887 } 2888 2889 static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge, 2890 struct drm_bridge_state *bridge_state, 2891 struct drm_crtc_state *crtc_state, 2892 struct drm_connector_state *conn_state) 2893 { 2894 struct dw_hdmi *hdmi = bridge->driver_private; 2895 2896 hdmi->hdmi_data.enc_out_bus_format = 2897 bridge_state->output_bus_cfg.format; 2898 2899 hdmi->hdmi_data.enc_in_bus_format = 2900 bridge_state->input_bus_cfg.format; 2901 2902 dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n", 2903 bridge_state->input_bus_cfg.format, 2904 bridge_state->output_bus_cfg.format); 2905 2906 return 0; 2907 } 2908 2909 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge, 2910 struct drm_encoder *encoder, 2911 enum drm_bridge_attach_flags flags) 2912 { 2913 struct dw_hdmi *hdmi = bridge->driver_private; 2914 2915 /* DRM_BRIDGE_ATTACH_NO_CONNECTOR requires a remote-endpoint to the next bridge */ 2916 if (WARN_ON((flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) && !hdmi->plat_data->output_port)) 2917 return -EINVAL; 2918 2919 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) { 2920 struct device_node *remote __free(device_node) = 2921 of_graph_get_remote_node(hdmi->dev->of_node, 2922 hdmi->plat_data->output_port, -1); 2923 if (!remote) 2924 return -ENODEV; 2925 2926 struct drm_bridge *next_bridge __free(drm_bridge_put) = 2927 of_drm_find_and_get_bridge(remote); 2928 if (!next_bridge) 2929 return -EPROBE_DEFER; 2930 2931 return drm_bridge_attach(encoder, next_bridge, bridge, flags); 2932 } 2933 2934 return dw_hdmi_connector_create(hdmi); 2935 } 2936 2937 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge) 2938 { 2939 struct dw_hdmi *hdmi = bridge->driver_private; 2940 2941 mutex_lock(&hdmi->cec_notifier_mutex); 2942 cec_notifier_conn_unregister(hdmi->cec_notifier); 2943 hdmi->cec_notifier = NULL; 2944 mutex_unlock(&hdmi->cec_notifier_mutex); 2945 } 2946 2947 static enum drm_mode_status 2948 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 2949 const struct drm_display_info *info, 2950 const struct drm_display_mode *mode) 2951 { 2952 struct dw_hdmi *hdmi = bridge->driver_private; 2953 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 2954 enum drm_mode_status mode_status = MODE_OK; 2955 2956 /* We don't support double-clocked modes */ 2957 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2958 return MODE_BAD; 2959 2960 if (pdata->mode_valid) 2961 mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info, 2962 mode); 2963 2964 return mode_status; 2965 } 2966 2967 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2968 const struct drm_display_mode *orig_mode, 2969 const struct drm_display_mode *mode) 2970 { 2971 struct dw_hdmi *hdmi = bridge->driver_private; 2972 2973 mutex_lock(&hdmi->mutex); 2974 2975 /* Store the display mode for plugin/DKMS poweron events */ 2976 drm_mode_copy(&hdmi->previous_mode, mode); 2977 2978 mutex_unlock(&hdmi->mutex); 2979 } 2980 2981 static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, 2982 struct drm_atomic_commit *state) 2983 { 2984 struct dw_hdmi *hdmi = bridge->driver_private; 2985 2986 mutex_lock(&hdmi->mutex); 2987 hdmi->disabled = true; 2988 hdmi->curr_conn = NULL; 2989 dw_hdmi_update_power(hdmi); 2990 dw_hdmi_update_phy_mask(hdmi); 2991 handle_plugged_change(hdmi, false); 2992 mutex_unlock(&hdmi->mutex); 2993 } 2994 2995 static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, 2996 struct drm_atomic_commit *state) 2997 { 2998 struct dw_hdmi *hdmi = bridge->driver_private; 2999 struct drm_connector *connector; 3000 3001 connector = drm_atomic_get_new_connector_for_encoder(state, 3002 bridge->encoder); 3003 3004 mutex_lock(&hdmi->mutex); 3005 hdmi->disabled = false; 3006 hdmi->curr_conn = connector; 3007 dw_hdmi_update_power(hdmi); 3008 dw_hdmi_update_phy_mask(hdmi); 3009 handle_plugged_change(hdmi, true); 3010 mutex_unlock(&hdmi->mutex); 3011 } 3012 3013 static enum drm_connector_status 3014 dw_hdmi_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 3015 { 3016 struct dw_hdmi *hdmi = bridge->driver_private; 3017 3018 return dw_hdmi_detect(hdmi); 3019 } 3020 3021 static const struct drm_edid *dw_hdmi_bridge_edid_read(struct drm_bridge *bridge, 3022 struct drm_connector *connector) 3023 { 3024 struct dw_hdmi *hdmi = bridge->driver_private; 3025 3026 return dw_hdmi_edid_read(hdmi, connector); 3027 } 3028 3029 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 3030 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 3031 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 3032 .atomic_reset = drm_atomic_helper_bridge_reset, 3033 .attach = dw_hdmi_bridge_attach, 3034 .detach = dw_hdmi_bridge_detach, 3035 .atomic_check = dw_hdmi_bridge_atomic_check, 3036 .atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts, 3037 .atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts, 3038 .atomic_enable = dw_hdmi_bridge_atomic_enable, 3039 .atomic_disable = dw_hdmi_bridge_atomic_disable, 3040 .mode_set = dw_hdmi_bridge_mode_set, 3041 .mode_valid = dw_hdmi_bridge_mode_valid, 3042 .detect = dw_hdmi_bridge_detect, 3043 .edid_read = dw_hdmi_bridge_edid_read, 3044 }; 3045 3046 /* ----------------------------------------------------------------------------- 3047 * IRQ Handling 3048 */ 3049 3050 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 3051 { 3052 struct dw_hdmi_i2c *i2c = hdmi->i2c; 3053 unsigned int stat; 3054 3055 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 3056 if (!stat) 3057 return IRQ_NONE; 3058 3059 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 3060 3061 i2c->stat = stat; 3062 3063 complete(&i2c->cmp); 3064 3065 return IRQ_HANDLED; 3066 } 3067 3068 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 3069 { 3070 struct dw_hdmi *hdmi = dev_id; 3071 u8 intr_stat; 3072 irqreturn_t ret = IRQ_NONE; 3073 3074 if (hdmi->i2c) 3075 ret = dw_hdmi_i2c_irq(hdmi); 3076 3077 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 3078 if (intr_stat) { 3079 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 3080 return IRQ_WAKE_THREAD; 3081 } 3082 3083 return ret; 3084 } 3085 3086 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 3087 { 3088 mutex_lock(&hdmi->mutex); 3089 3090 if (!hdmi->force) { 3091 /* 3092 * If the RX sense status indicates we're disconnected, 3093 * clear the software rxsense status. 3094 */ 3095 if (!rx_sense) 3096 hdmi->rxsense = false; 3097 3098 /* 3099 * Only set the software rxsense status when both 3100 * rxsense and hpd indicates we're connected. 3101 * This avoids what seems to be bad behaviour in 3102 * at least iMX6S versions of the phy. 3103 */ 3104 if (hpd) 3105 hdmi->rxsense = true; 3106 3107 dw_hdmi_update_power(hdmi); 3108 dw_hdmi_update_phy_mask(hdmi); 3109 } 3110 mutex_unlock(&hdmi->mutex); 3111 } 3112 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 3113 3114 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 3115 { 3116 struct dw_hdmi *hdmi = dev_id; 3117 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 3118 enum drm_connector_status status = connector_status_unknown; 3119 3120 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 3121 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 3122 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 3123 3124 phy_pol_mask = 0; 3125 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 3126 phy_pol_mask |= HDMI_PHY_HPD; 3127 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 3128 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 3129 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 3130 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 3131 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 3132 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 3133 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 3134 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 3135 3136 if (phy_pol_mask) 3137 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 3138 3139 /* 3140 * RX sense tells us whether the TDMS transmitters are detecting 3141 * load - in other words, there's something listening on the 3142 * other end of the link. Use this to decide whether we should 3143 * power on the phy as HPD may be toggled by the sink to merely 3144 * ask the source to re-read the EDID. 3145 */ 3146 if (intr_stat & 3147 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 3148 dw_hdmi_setup_rx_sense(hdmi, 3149 phy_stat & HDMI_PHY_HPD, 3150 phy_stat & HDMI_PHY_RX_SENSE); 3151 3152 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { 3153 mutex_lock(&hdmi->cec_notifier_mutex); 3154 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); 3155 mutex_unlock(&hdmi->cec_notifier_mutex); 3156 } 3157 3158 if (phy_stat & HDMI_PHY_HPD) 3159 status = connector_status_connected; 3160 3161 if (!(phy_stat & (HDMI_PHY_HPD | HDMI_PHY_RX_SENSE))) 3162 status = connector_status_disconnected; 3163 } 3164 3165 if (status != connector_status_unknown) { 3166 dev_dbg(hdmi->dev, "EVENT=%s\n", 3167 status == connector_status_connected ? 3168 "plugin" : "plugout"); 3169 3170 if (hdmi->bridge.dev) { 3171 drm_helper_hpd_irq_event(hdmi->bridge.dev); 3172 drm_bridge_hpd_notify(&hdmi->bridge, status); 3173 } 3174 } 3175 3176 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 3177 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 3178 HDMI_IH_MUTE_PHY_STAT0); 3179 3180 return IRQ_HANDLED; 3181 } 3182 3183 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 3184 { 3185 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 3186 .name = "DWC HDMI TX PHY", 3187 .gen = 1, 3188 }, { 3189 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 3190 .name = "DWC MHL PHY + HEAC PHY", 3191 .gen = 2, 3192 .has_svsret = true, 3193 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3194 }, { 3195 .type = DW_HDMI_PHY_DWC_MHL_PHY, 3196 .name = "DWC MHL PHY", 3197 .gen = 2, 3198 .has_svsret = true, 3199 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3200 }, { 3201 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 3202 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 3203 .gen = 2, 3204 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3205 }, { 3206 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 3207 .name = "DWC HDMI 3D TX PHY", 3208 .gen = 2, 3209 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3210 }, { 3211 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 3212 .name = "DWC HDMI 2.0 TX PHY", 3213 .gen = 2, 3214 .has_svsret = true, 3215 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3216 }, { 3217 .type = DW_HDMI_PHY_VENDOR_PHY, 3218 .name = "Vendor PHY", 3219 } 3220 }; 3221 3222 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 3223 { 3224 unsigned int i; 3225 u8 phy_type; 3226 3227 phy_type = hdmi->plat_data->phy_force_vendor ? 3228 DW_HDMI_PHY_VENDOR_PHY : 3229 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 3230 3231 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 3232 /* Vendor PHYs require support from the glue layer. */ 3233 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 3234 dev_err(hdmi->dev, 3235 "Vendor HDMI PHY not supported by glue layer\n"); 3236 return -ENODEV; 3237 } 3238 3239 hdmi->phy.ops = hdmi->plat_data->phy_ops; 3240 hdmi->phy.data = hdmi->plat_data->phy_data; 3241 hdmi->phy.name = hdmi->plat_data->phy_name; 3242 return 0; 3243 } 3244 3245 /* Synopsys PHYs are handled internally. */ 3246 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 3247 if (dw_hdmi_phys[i].type == phy_type) { 3248 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 3249 hdmi->phy.name = dw_hdmi_phys[i].name; 3250 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 3251 3252 if (!dw_hdmi_phys[i].configure && 3253 !hdmi->plat_data->configure_phy) { 3254 dev_err(hdmi->dev, "%s requires platform support\n", 3255 hdmi->phy.name); 3256 return -ENODEV; 3257 } 3258 3259 return 0; 3260 } 3261 } 3262 3263 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 3264 return -ENODEV; 3265 } 3266 3267 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 3268 { 3269 mutex_lock(&hdmi->mutex); 3270 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 3271 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 3272 mutex_unlock(&hdmi->mutex); 3273 } 3274 3275 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 3276 { 3277 mutex_lock(&hdmi->mutex); 3278 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 3279 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 3280 mutex_unlock(&hdmi->mutex); 3281 } 3282 3283 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 3284 .write = hdmi_writeb, 3285 .read = hdmi_readb, 3286 .enable = dw_hdmi_cec_enable, 3287 .disable = dw_hdmi_cec_disable, 3288 }; 3289 3290 static const struct regmap_config hdmi_regmap_8bit_config = { 3291 .reg_bits = 32, 3292 .val_bits = 8, 3293 .reg_stride = 1, 3294 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 3295 }; 3296 3297 static const struct regmap_config hdmi_regmap_32bit_config = { 3298 .reg_bits = 32, 3299 .val_bits = 32, 3300 .reg_stride = 4, 3301 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 3302 }; 3303 3304 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi) 3305 { 3306 initialize_hdmi_ih_mutes(hdmi); 3307 3308 /* 3309 * Reset HDMI DDC I2C master controller and mute I2CM interrupts. 3310 * Even if we are using a separate i2c adapter doing this doesn't 3311 * hurt. 3312 */ 3313 dw_hdmi_i2c_init(hdmi); 3314 3315 if (hdmi->phy.ops->setup_hpd) 3316 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 3317 } 3318 3319 /* ----------------------------------------------------------------------------- 3320 * Probe/remove API, used from platforms based on the DRM bridge API. 3321 */ 3322 3323 bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi) 3324 { 3325 return hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format); 3326 } 3327 EXPORT_SYMBOL_GPL(dw_hdmi_bus_fmt_is_420); 3328 3329 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 3330 const struct dw_hdmi_plat_data *plat_data) 3331 { 3332 struct device *dev = &pdev->dev; 3333 struct device_node *np = dev->of_node; 3334 struct platform_device_info pdevinfo; 3335 struct device_node *ddc_node; 3336 struct dw_hdmi_cec_data cec; 3337 struct dw_hdmi *hdmi; 3338 struct clk *clk; 3339 struct resource *iores = NULL; 3340 int irq; 3341 int ret; 3342 u32 val = 1; 3343 u8 prod_id0; 3344 u8 prod_id1; 3345 u8 config0; 3346 u8 config3; 3347 3348 hdmi = devm_drm_bridge_alloc(dev, struct dw_hdmi, bridge, &dw_hdmi_bridge_funcs); 3349 if (IS_ERR(hdmi)) 3350 return hdmi; 3351 3352 hdmi->plat_data = plat_data; 3353 hdmi->dev = dev; 3354 hdmi->sample_rate = 48000; 3355 hdmi->channels = 2; 3356 hdmi->disabled = true; 3357 hdmi->rxsense = true; 3358 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 3359 hdmi->mc_clkdis = 0x7f; 3360 hdmi->last_connector_result = connector_status_disconnected; 3361 3362 mutex_init(&hdmi->mutex); 3363 mutex_init(&hdmi->audio_mutex); 3364 mutex_init(&hdmi->cec_notifier_mutex); 3365 spin_lock_init(&hdmi->audio_lock); 3366 3367 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 3368 if (ddc_node) { 3369 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 3370 of_node_put(ddc_node); 3371 if (!hdmi->ddc) { 3372 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 3373 return ERR_PTR(-EPROBE_DEFER); 3374 } 3375 3376 } else { 3377 dev_dbg(hdmi->dev, "no ddc property found\n"); 3378 } 3379 3380 if (!plat_data->regm) { 3381 const struct regmap_config *reg_config; 3382 3383 of_property_read_u32(np, "reg-io-width", &val); 3384 switch (val) { 3385 case 4: 3386 reg_config = &hdmi_regmap_32bit_config; 3387 hdmi->reg_shift = 2; 3388 break; 3389 case 1: 3390 reg_config = &hdmi_regmap_8bit_config; 3391 break; 3392 default: 3393 dev_err(dev, "reg-io-width must be 1 or 4\n"); 3394 return ERR_PTR(-EINVAL); 3395 } 3396 3397 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3398 hdmi->regs = devm_ioremap_resource(dev, iores); 3399 if (IS_ERR(hdmi->regs)) { 3400 ret = PTR_ERR(hdmi->regs); 3401 goto err_res; 3402 } 3403 3404 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 3405 if (IS_ERR(hdmi->regm)) { 3406 dev_err(dev, "Failed to configure regmap\n"); 3407 ret = PTR_ERR(hdmi->regm); 3408 goto err_res; 3409 } 3410 } else { 3411 hdmi->regm = plat_data->regm; 3412 } 3413 3414 clk = devm_clk_get_enabled(hdmi->dev, "isfr"); 3415 if (IS_ERR(clk)) { 3416 ret = PTR_ERR(clk); 3417 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 3418 goto err_res; 3419 } 3420 3421 clk = devm_clk_get_enabled(hdmi->dev, "iahb"); 3422 if (IS_ERR(clk)) { 3423 ret = PTR_ERR(clk); 3424 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 3425 goto err_res; 3426 } 3427 3428 clk = devm_clk_get_optional_enabled(hdmi->dev, "cec"); 3429 if (IS_ERR(clk)) { 3430 ret = PTR_ERR(clk); 3431 if (ret != -EPROBE_DEFER) 3432 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 3433 ret); 3434 goto err_res; 3435 } 3436 3437 /* Product and revision IDs */ 3438 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 3439 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 3440 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 3441 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 3442 3443 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 3444 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 3445 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 3446 hdmi->version, prod_id0, prod_id1); 3447 ret = -ENODEV; 3448 goto err_res; 3449 } 3450 3451 ret = dw_hdmi_detect_phy(hdmi); 3452 if (ret < 0) 3453 goto err_res; 3454 3455 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 3456 hdmi->version >> 12, hdmi->version & 0xfff, 3457 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 3458 hdmi->phy.name); 3459 3460 dw_hdmi_init_hw(hdmi); 3461 3462 irq = platform_get_irq(pdev, 0); 3463 if (irq < 0) { 3464 ret = irq; 3465 goto err_res; 3466 } 3467 3468 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 3469 dw_hdmi_irq, IRQF_SHARED, 3470 dev_name(dev), hdmi); 3471 if (ret) 3472 goto err_res; 3473 3474 /* 3475 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 3476 * N and cts values before enabling phy 3477 */ 3478 hdmi_init_clk_regenerator(hdmi); 3479 3480 /* If DDC bus is not specified, try to register HDMI I2C bus */ 3481 if (!hdmi->ddc) { 3482 /* Look for (optional) stuff related to unwedging */ 3483 hdmi->pinctrl = devm_pinctrl_get(dev); 3484 if (!IS_ERR(hdmi->pinctrl)) { 3485 hdmi->unwedge_state = 3486 pinctrl_lookup_state(hdmi->pinctrl, "unwedge"); 3487 hdmi->default_state = 3488 pinctrl_lookup_state(hdmi->pinctrl, "default"); 3489 3490 if (IS_ERR(hdmi->default_state) || 3491 IS_ERR(hdmi->unwedge_state)) { 3492 if (!IS_ERR(hdmi->unwedge_state)) 3493 dev_warn(dev, 3494 "Unwedge requires default pinctrl\n"); 3495 hdmi->default_state = NULL; 3496 hdmi->unwedge_state = NULL; 3497 } 3498 } 3499 3500 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 3501 if (IS_ERR(hdmi->ddc)) 3502 hdmi->ddc = NULL; 3503 } 3504 3505 hdmi->bridge.driver_private = hdmi; 3506 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID 3507 | DRM_BRIDGE_OP_HPD; 3508 hdmi->bridge.interlace_allowed = true; 3509 hdmi->bridge.ddc = hdmi->ddc; 3510 hdmi->bridge.of_node = pdev->dev.of_node; 3511 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 3512 3513 if (hdmi->version >= 0x200a) 3514 hdmi->bridge.ycbcr_420_allowed = plat_data->ycbcr_420_allowed; 3515 3516 memset(&pdevinfo, 0, sizeof(pdevinfo)); 3517 pdevinfo.parent = dev; 3518 pdevinfo.id = PLATFORM_DEVID_AUTO; 3519 3520 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 3521 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 3522 3523 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 3524 struct dw_hdmi_audio_data audio; 3525 3526 audio.phys = iores->start; 3527 audio.base = hdmi->regs; 3528 audio.irq = irq; 3529 audio.hdmi = hdmi; 3530 audio.get_eld = hdmi_audio_get_eld; 3531 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 3532 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 3533 3534 pdevinfo.name = "dw-hdmi-ahb-audio"; 3535 pdevinfo.data = &audio; 3536 pdevinfo.size_data = sizeof(audio); 3537 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3538 hdmi->audio = platform_device_register_full(&pdevinfo); 3539 } else if (config0 & HDMI_CONFIG0_I2S) { 3540 struct dw_hdmi_i2s_audio_data audio; 3541 3542 audio.hdmi = hdmi; 3543 audio.get_eld = hdmi_audio_get_eld; 3544 audio.write = hdmi_writeb; 3545 audio.read = hdmi_readb; 3546 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 3547 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 3548 3549 pdevinfo.name = "dw-hdmi-i2s-audio"; 3550 pdevinfo.data = &audio; 3551 pdevinfo.size_data = sizeof(audio); 3552 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3553 hdmi->audio = platform_device_register_full(&pdevinfo); 3554 } else if (iores && config3 & HDMI_CONFIG3_GPAUD) { 3555 struct dw_hdmi_audio_data audio; 3556 3557 audio.phys = iores->start; 3558 audio.base = hdmi->regs; 3559 audio.irq = irq; 3560 audio.hdmi = hdmi; 3561 audio.get_eld = hdmi_audio_get_eld; 3562 3563 hdmi->enable_audio = dw_hdmi_gp_audio_enable; 3564 hdmi->disable_audio = dw_hdmi_gp_audio_disable; 3565 3566 pdevinfo.name = "dw-hdmi-gp-audio"; 3567 pdevinfo.id = PLATFORM_DEVID_NONE; 3568 pdevinfo.data = &audio; 3569 pdevinfo.size_data = sizeof(audio); 3570 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3571 hdmi->audio = platform_device_register_full(&pdevinfo); 3572 } 3573 3574 if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) { 3575 cec.hdmi = hdmi; 3576 cec.ops = &dw_hdmi_cec_ops; 3577 cec.irq = irq; 3578 3579 pdevinfo.name = "dw-hdmi-cec"; 3580 pdevinfo.data = &cec; 3581 pdevinfo.size_data = sizeof(cec); 3582 pdevinfo.dma_mask = 0; 3583 3584 hdmi->cec = platform_device_register_full(&pdevinfo); 3585 } 3586 3587 drm_bridge_add(&hdmi->bridge); 3588 3589 return hdmi; 3590 3591 err_res: 3592 i2c_put_adapter(hdmi->ddc); 3593 3594 return ERR_PTR(ret); 3595 } 3596 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 3597 3598 void dw_hdmi_remove(struct dw_hdmi *hdmi) 3599 { 3600 drm_bridge_remove(&hdmi->bridge); 3601 3602 if (hdmi->audio && !IS_ERR(hdmi->audio)) 3603 platform_device_unregister(hdmi->audio); 3604 if (!IS_ERR(hdmi->cec)) 3605 platform_device_unregister(hdmi->cec); 3606 3607 /* Disable all interrupts */ 3608 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 3609 3610 if (hdmi->i2c) 3611 i2c_del_adapter(&hdmi->i2c->adap); 3612 else 3613 i2c_put_adapter(hdmi->ddc); 3614 } 3615 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 3616 3617 /* ----------------------------------------------------------------------------- 3618 * Bind/unbind API, used from platforms based on the component framework. 3619 */ 3620 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 3621 struct drm_encoder *encoder, 3622 const struct dw_hdmi_plat_data *plat_data) 3623 { 3624 struct dw_hdmi *hdmi; 3625 int ret; 3626 3627 hdmi = dw_hdmi_probe(pdev, plat_data); 3628 if (IS_ERR(hdmi)) 3629 return hdmi; 3630 3631 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0); 3632 if (ret) { 3633 dw_hdmi_remove(hdmi); 3634 return ERR_PTR(ret); 3635 } 3636 3637 return hdmi; 3638 } 3639 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 3640 3641 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 3642 { 3643 dw_hdmi_remove(hdmi); 3644 } 3645 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 3646 3647 void dw_hdmi_resume(struct dw_hdmi *hdmi) 3648 { 3649 dw_hdmi_init_hw(hdmi); 3650 } 3651 EXPORT_SYMBOL_GPL(dw_hdmi_resume); 3652 3653 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 3654 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 3655 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 3656 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 3657 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 3658 MODULE_LICENSE("GPL"); 3659 MODULE_ALIAS("platform:dw-hdmi"); 3660