1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver 4 * 5 * Copyright (C) 2013-2015 Mentor Graphics Inc. 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/export.h> 13 #include <linux/hdmi.h> 14 #include <linux/i2c.h> 15 #include <linux/irq.h> 16 #include <linux/module.h> 17 #include <linux/mutex.h> 18 #include <linux/of.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/regmap.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/spinlock.h> 23 24 #include <media/cec-notifier.h> 25 26 #include <linux/media-bus-format.h> 27 #include <linux/videodev2.h> 28 29 #include <drm/bridge/dw_hdmi.h> 30 #include <drm/display/drm_hdmi_helper.h> 31 #include <drm/display/drm_scdc_helper.h> 32 #include <drm/drm_atomic.h> 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_bridge.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_of.h> 37 #include <drm/drm_print.h> 38 #include <drm/drm_probe_helper.h> 39 40 #include "dw-hdmi-audio.h" 41 #include "dw-hdmi-cec.h" 42 #include "dw-hdmi.h" 43 44 #define DDC_CI_ADDR 0x37 45 #define DDC_SEGMENT_ADDR 0x30 46 47 #define HDMI_EDID_LEN 512 48 49 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 50 #define SCDC_MIN_SOURCE_VERSION 0x1 51 52 #define HDMI14_MAX_TMDSCLK 340000000 53 54 static const u16 csc_coeff_default[3][4] = { 55 { 0x2000, 0x0000, 0x0000, 0x0000 }, 56 { 0x0000, 0x2000, 0x0000, 0x0000 }, 57 { 0x0000, 0x0000, 0x2000, 0x0000 } 58 }; 59 60 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 61 { 0x2000, 0x6926, 0x74fd, 0x010e }, 62 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 63 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 64 }; 65 66 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 67 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 68 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 69 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 70 }; 71 72 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 73 { 0x2591, 0x1322, 0x074b, 0x0000 }, 74 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 75 { 0x6acd, 0x7534, 0x2000, 0x0200 } 76 }; 77 78 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 79 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 80 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 81 { 0x6756, 0x78ab, 0x2000, 0x0200 } 82 }; 83 84 static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = { 85 { 0x1b7c, 0x0000, 0x0000, 0x0020 }, 86 { 0x0000, 0x1b7c, 0x0000, 0x0020 }, 87 { 0x0000, 0x0000, 0x1b7c, 0x0020 } 88 }; 89 90 struct hdmi_vmode { 91 bool mdataenablepolarity; 92 93 unsigned int mpixelclock; 94 unsigned int mpixelrepetitioninput; 95 unsigned int mpixelrepetitionoutput; 96 unsigned int mtmdsclock; 97 }; 98 99 struct hdmi_data_info { 100 unsigned int enc_in_bus_format; 101 unsigned int enc_out_bus_format; 102 unsigned int enc_in_encoding; 103 unsigned int enc_out_encoding; 104 unsigned int pix_repet_factor; 105 unsigned int hdcp_enable; 106 struct hdmi_vmode video_mode; 107 bool rgb_limited_range; 108 }; 109 110 struct dw_hdmi_i2c { 111 struct i2c_adapter adap; 112 113 struct mutex lock; /* used to serialize data transfers */ 114 struct completion cmp; 115 u8 stat; 116 117 u8 slave_reg; 118 bool is_regaddr; 119 bool is_segment; 120 }; 121 122 struct dw_hdmi_phy_data { 123 enum dw_hdmi_phy_type type; 124 const char *name; 125 unsigned int gen; 126 bool has_svsret; 127 int (*configure)(struct dw_hdmi *hdmi, 128 const struct dw_hdmi_plat_data *pdata, 129 unsigned long mpixelclock); 130 }; 131 132 struct dw_hdmi { 133 struct drm_connector connector; 134 struct drm_bridge bridge; 135 struct drm_bridge *next_bridge; 136 137 unsigned int version; 138 139 struct platform_device *audio; 140 struct platform_device *cec; 141 struct device *dev; 142 struct dw_hdmi_i2c *i2c; 143 144 struct hdmi_data_info hdmi_data; 145 const struct dw_hdmi_plat_data *plat_data; 146 147 int vic; 148 149 u8 edid[HDMI_EDID_LEN]; 150 151 struct { 152 const struct dw_hdmi_phy_ops *ops; 153 const char *name; 154 void *data; 155 bool enabled; 156 } phy; 157 158 struct drm_display_mode previous_mode; 159 160 struct i2c_adapter *ddc; 161 void __iomem *regs; 162 bool sink_is_hdmi; 163 bool sink_has_audio; 164 165 struct pinctrl *pinctrl; 166 struct pinctrl_state *default_state; 167 struct pinctrl_state *unwedge_state; 168 169 struct mutex mutex; /* for state below and previous_mode */ 170 enum drm_connector_force force; /* mutex-protected force state */ 171 struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */ 172 bool disabled; /* DRM has disabled our bridge */ 173 bool bridge_is_on; /* indicates the bridge is on */ 174 bool rxsense; /* rxsense state */ 175 u8 phy_mask; /* desired phy int mask settings */ 176 u8 mc_clkdis; /* clock disable register */ 177 178 spinlock_t audio_lock; 179 struct mutex audio_mutex; 180 unsigned int sample_non_pcm; 181 unsigned int sample_width; 182 unsigned int sample_rate; 183 unsigned int channels; 184 unsigned int audio_cts; 185 unsigned int audio_n; 186 bool audio_enable; 187 188 unsigned int reg_shift; 189 struct regmap *regm; 190 void (*enable_audio)(struct dw_hdmi *hdmi); 191 void (*disable_audio)(struct dw_hdmi *hdmi); 192 193 struct mutex cec_notifier_mutex; 194 struct cec_notifier *cec_notifier; 195 196 hdmi_codec_plugged_cb plugged_cb; 197 struct device *codec_dev; 198 enum drm_connector_status last_connector_result; 199 }; 200 201 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 202 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 203 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 204 205 #define HDMI_PHY_RX_SENSE \ 206 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 207 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 208 209 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 210 { 211 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 212 } 213 214 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 215 { 216 unsigned int val = 0; 217 218 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 219 220 return val; 221 } 222 223 static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged) 224 { 225 if (hdmi->plugged_cb && hdmi->codec_dev) 226 hdmi->plugged_cb(hdmi->codec_dev, plugged); 227 } 228 229 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn, 230 struct device *codec_dev) 231 { 232 bool plugged; 233 234 mutex_lock(&hdmi->mutex); 235 hdmi->plugged_cb = fn; 236 hdmi->codec_dev = codec_dev; 237 plugged = hdmi->last_connector_result == connector_status_connected; 238 handle_plugged_change(hdmi, plugged); 239 mutex_unlock(&hdmi->mutex); 240 241 return 0; 242 } 243 EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb); 244 245 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 246 { 247 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 248 } 249 250 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 251 u8 shift, u8 mask) 252 { 253 hdmi_modb(hdmi, data << shift, mask, reg); 254 } 255 256 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 257 { 258 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 259 HDMI_PHY_I2CM_INT_ADDR); 260 261 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 262 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 263 HDMI_PHY_I2CM_CTLINT_ADDR); 264 265 /* Software reset */ 266 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 267 268 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 269 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 270 271 /* Set done, not acknowledged and arbitration interrupt polarities */ 272 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 273 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 274 HDMI_I2CM_CTLINT); 275 276 /* Clear DONE and ERROR interrupts */ 277 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 278 HDMI_IH_I2CM_STAT0); 279 280 /* Mute DONE and ERROR interrupts */ 281 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 282 HDMI_IH_MUTE_I2CM_STAT0); 283 } 284 285 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi) 286 { 287 /* If no unwedge state then give up */ 288 if (!hdmi->unwedge_state) 289 return false; 290 291 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n"); 292 293 /* 294 * This is a huge hack to workaround a problem where the dw_hdmi i2c 295 * bus could sometimes get wedged. Once wedged there doesn't appear 296 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ) 297 * other than pulsing the SDA line. 298 * 299 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi) 300 * by: 301 * 1. Remux the pin as a GPIO output, driven low. 302 * 2. Wait a little while. 1 ms seems to work, but we'll do 10. 303 * 3. Immediately jump to remux the pin as dw_hdmi i2c again. 304 * 305 * At the moment of remuxing, the line will still be low due to its 306 * recent stint as an output, but then it will be pulled high by the 307 * (presumed) external pullup. dw_hdmi seems to see this as a rising 308 * edge and that seems to get it out of its jam. 309 * 310 * This wedging was only ever seen on one TV, and only on one of 311 * its HDMI ports. It happened when the TV was powered on while the 312 * device was plugged in. A scope trace shows the TV bringing both SDA 313 * and SCL low, then bringing them both back up at roughly the same 314 * time. Presumably this confuses dw_hdmi because it saw activity but 315 * no real STOP (maybe it thinks there's another master on the bus?). 316 * Giving it a clean rising edge of SDA while SCL is already high 317 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out 318 * of its stupor. 319 * 320 * Note that after coming back alive, transfers seem to immediately 321 * resume, so if we unwedge due to a timeout we should wait a little 322 * longer for our transfer to finish, since it might have just started 323 * now. 324 */ 325 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state); 326 msleep(10); 327 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state); 328 329 return true; 330 } 331 332 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi) 333 { 334 struct dw_hdmi_i2c *i2c = hdmi->i2c; 335 int stat; 336 337 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 338 if (!stat) { 339 /* If we can't unwedge, return timeout */ 340 if (!dw_hdmi_i2c_unwedge(hdmi)) 341 return -EAGAIN; 342 343 /* We tried to unwedge; give it another chance */ 344 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 345 if (!stat) 346 return -EAGAIN; 347 } 348 349 /* Check for error condition on the bus */ 350 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 351 return -EIO; 352 353 return 0; 354 } 355 356 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 357 unsigned char *buf, unsigned int length) 358 { 359 struct dw_hdmi_i2c *i2c = hdmi->i2c; 360 int ret; 361 362 if (!i2c->is_regaddr) { 363 dev_dbg(hdmi->dev, "set read register address to 0\n"); 364 i2c->slave_reg = 0x00; 365 i2c->is_regaddr = true; 366 } 367 368 while (length--) { 369 reinit_completion(&i2c->cmp); 370 371 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 372 if (i2c->is_segment) 373 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 374 HDMI_I2CM_OPERATION); 375 else 376 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 377 HDMI_I2CM_OPERATION); 378 379 ret = dw_hdmi_i2c_wait(hdmi); 380 if (ret) 381 return ret; 382 383 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 384 } 385 i2c->is_segment = false; 386 387 return 0; 388 } 389 390 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 391 unsigned char *buf, unsigned int length) 392 { 393 struct dw_hdmi_i2c *i2c = hdmi->i2c; 394 int ret; 395 396 if (!i2c->is_regaddr) { 397 /* Use the first write byte as register address */ 398 i2c->slave_reg = buf[0]; 399 length--; 400 buf++; 401 i2c->is_regaddr = true; 402 } 403 404 while (length--) { 405 reinit_completion(&i2c->cmp); 406 407 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 408 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 409 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 410 HDMI_I2CM_OPERATION); 411 412 ret = dw_hdmi_i2c_wait(hdmi); 413 if (ret) 414 return ret; 415 } 416 417 return 0; 418 } 419 420 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 421 struct i2c_msg *msgs, int num) 422 { 423 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 424 struct dw_hdmi_i2c *i2c = hdmi->i2c; 425 u8 addr = msgs[0].addr; 426 int i, ret = 0; 427 428 if (addr == DDC_CI_ADDR) 429 /* 430 * The internal I2C controller does not support the multi-byte 431 * read and write operations needed for DDC/CI. 432 * TOFIX: Blacklist the DDC/CI address until we filter out 433 * unsupported I2C operations. 434 */ 435 return -EOPNOTSUPP; 436 437 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 438 439 for (i = 0; i < num; i++) { 440 if (msgs[i].len == 0) { 441 dev_dbg(hdmi->dev, 442 "unsupported transfer %d/%d, no data\n", 443 i + 1, num); 444 return -EOPNOTSUPP; 445 } 446 } 447 448 mutex_lock(&i2c->lock); 449 450 /* Unmute DONE and ERROR interrupts */ 451 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 452 453 /* Set slave device address taken from the first I2C message */ 454 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 455 456 /* Set slave device register address on transfer */ 457 i2c->is_regaddr = false; 458 459 /* Set segment pointer for I2C extended read mode operation */ 460 i2c->is_segment = false; 461 462 for (i = 0; i < num; i++) { 463 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 464 i + 1, num, msgs[i].len, msgs[i].flags); 465 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 466 i2c->is_segment = true; 467 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 468 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 469 } else { 470 if (msgs[i].flags & I2C_M_RD) 471 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 472 msgs[i].len); 473 else 474 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 475 msgs[i].len); 476 } 477 if (ret < 0) 478 break; 479 } 480 481 if (!ret) 482 ret = num; 483 484 /* Mute DONE and ERROR interrupts */ 485 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 486 HDMI_IH_MUTE_I2CM_STAT0); 487 488 mutex_unlock(&i2c->lock); 489 490 return ret; 491 } 492 493 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 494 { 495 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 496 } 497 498 static const struct i2c_algorithm dw_hdmi_algorithm = { 499 .master_xfer = dw_hdmi_i2c_xfer, 500 .functionality = dw_hdmi_i2c_func, 501 }; 502 503 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 504 { 505 struct i2c_adapter *adap; 506 struct dw_hdmi_i2c *i2c; 507 int ret; 508 509 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 510 if (!i2c) 511 return ERR_PTR(-ENOMEM); 512 513 mutex_init(&i2c->lock); 514 init_completion(&i2c->cmp); 515 516 adap = &i2c->adap; 517 adap->owner = THIS_MODULE; 518 adap->dev.parent = hdmi->dev; 519 adap->algo = &dw_hdmi_algorithm; 520 strscpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 521 i2c_set_adapdata(adap, hdmi); 522 523 ret = i2c_add_adapter(adap); 524 if (ret) { 525 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 526 devm_kfree(hdmi->dev, i2c); 527 return ERR_PTR(ret); 528 } 529 530 hdmi->i2c = i2c; 531 532 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 533 534 return adap; 535 } 536 537 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 538 unsigned int n) 539 { 540 /* Must be set/cleared first */ 541 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 542 543 /* nshift factor = 0 */ 544 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 545 546 /* Use automatic CTS generation mode when CTS is not set */ 547 if (cts) 548 hdmi_writeb(hdmi, ((cts >> 16) & 549 HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 550 HDMI_AUD_CTS3_CTS_MANUAL, 551 HDMI_AUD_CTS3); 552 else 553 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); 554 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 555 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 556 557 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 558 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 559 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 560 } 561 562 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 563 { 564 unsigned int n = (128 * freq) / 1000; 565 unsigned int mult = 1; 566 567 while (freq > 48000) { 568 mult *= 2; 569 freq /= 2; 570 } 571 572 switch (freq) { 573 case 32000: 574 if (pixel_clk == 25175000) 575 n = 4576; 576 else if (pixel_clk == 27027000) 577 n = 4096; 578 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 579 n = 11648; 580 else if (pixel_clk == 297000000) 581 n = 3072; 582 else 583 n = 4096; 584 n *= mult; 585 break; 586 587 case 44100: 588 if (pixel_clk == 25175000) 589 n = 7007; 590 else if (pixel_clk == 74176000) 591 n = 17836; 592 else if (pixel_clk == 148352000) 593 n = 8918; 594 else if (pixel_clk == 297000000) 595 n = 4704; 596 else 597 n = 6272; 598 n *= mult; 599 break; 600 601 case 48000: 602 if (pixel_clk == 25175000) 603 n = 6864; 604 else if (pixel_clk == 27027000) 605 n = 6144; 606 else if (pixel_clk == 74176000) 607 n = 11648; 608 else if (pixel_clk == 148352000) 609 n = 5824; 610 else if (pixel_clk == 297000000) 611 n = 5120; 612 else 613 n = 6144; 614 n *= mult; 615 break; 616 617 default: 618 break; 619 } 620 621 return n; 622 } 623 624 /* 625 * When transmitting IEC60958 linear PCM audio, these registers allow to 626 * configure the channel status information of all the channel status 627 * bits in the IEC60958 frame. For the moment this configuration is only 628 * used when the I2S audio interface, General Purpose Audio (GPA), 629 * or AHB audio DMA (AHBAUDDMA) interface is active 630 * (for S/PDIF interface this information comes from the stream). 631 */ 632 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, 633 u8 *channel_status) 634 { 635 /* 636 * Set channel status register for frequency and word length. 637 * Use default values for other registers. 638 */ 639 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7); 640 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8); 641 } 642 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status); 643 644 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 645 unsigned long pixel_clk, unsigned int sample_rate) 646 { 647 unsigned long ftdms = pixel_clk; 648 unsigned int n, cts; 649 u8 config3; 650 u64 tmp; 651 652 n = hdmi_compute_n(sample_rate, pixel_clk); 653 654 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 655 656 /* Compute CTS when using internal AHB audio or General Parallel audio*/ 657 if ((config3 & HDMI_CONFIG3_AHBAUDDMA) || (config3 & HDMI_CONFIG3_GPAUD)) { 658 /* 659 * Compute the CTS value from the N value. Note that CTS and N 660 * can be up to 20 bits in total, so we need 64-bit math. Also 661 * note that our TDMS clock is not fully accurate; it is 662 * accurate to kHz. This can introduce an unnecessary remainder 663 * in the calculation below, so we don't try to warn about that. 664 */ 665 tmp = (u64)ftdms * n; 666 do_div(tmp, 128 * sample_rate); 667 cts = tmp; 668 669 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 670 __func__, sample_rate, 671 ftdms / 1000000, (ftdms / 1000) % 1000, 672 n, cts); 673 } else { 674 cts = 0; 675 } 676 677 spin_lock_irq(&hdmi->audio_lock); 678 hdmi->audio_n = n; 679 hdmi->audio_cts = cts; 680 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 681 spin_unlock_irq(&hdmi->audio_lock); 682 } 683 684 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 685 { 686 mutex_lock(&hdmi->audio_mutex); 687 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 688 mutex_unlock(&hdmi->audio_mutex); 689 } 690 691 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 692 { 693 mutex_lock(&hdmi->audio_mutex); 694 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 695 hdmi->sample_rate); 696 mutex_unlock(&hdmi->audio_mutex); 697 } 698 699 void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width) 700 { 701 mutex_lock(&hdmi->audio_mutex); 702 hdmi->sample_width = width; 703 mutex_unlock(&hdmi->audio_mutex); 704 } 705 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_width); 706 707 void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm) 708 { 709 mutex_lock(&hdmi->audio_mutex); 710 hdmi->sample_non_pcm = non_pcm; 711 mutex_unlock(&hdmi->audio_mutex); 712 } 713 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_non_pcm); 714 715 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 716 { 717 mutex_lock(&hdmi->audio_mutex); 718 hdmi->sample_rate = rate; 719 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 720 hdmi->sample_rate); 721 mutex_unlock(&hdmi->audio_mutex); 722 } 723 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 724 725 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt) 726 { 727 u8 layout; 728 729 mutex_lock(&hdmi->audio_mutex); 730 hdmi->channels = cnt; 731 732 /* 733 * For >2 channel PCM audio, we need to select layout 1 734 * and set an appropriate channel map. 735 */ 736 if (cnt > 2) 737 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1; 738 else 739 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0; 740 741 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, 742 HDMI_FC_AUDSCONF); 743 744 /* Set the audio infoframes channel count */ 745 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, 746 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0); 747 748 mutex_unlock(&hdmi->audio_mutex); 749 } 750 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count); 751 752 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca) 753 { 754 mutex_lock(&hdmi->audio_mutex); 755 756 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2); 757 758 mutex_unlock(&hdmi->audio_mutex); 759 } 760 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation); 761 762 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 763 { 764 if (enable) 765 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 766 else 767 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 768 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 769 } 770 771 static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi) 772 { 773 if (!hdmi->curr_conn) 774 return NULL; 775 776 return hdmi->curr_conn->eld; 777 } 778 779 static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi) 780 { 781 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 782 int sample_freq = 0x2, org_sample_freq = 0xD; 783 int ch_mask = BIT(hdmi->channels) - 1; 784 785 switch (hdmi->sample_rate) { 786 case 32000: 787 sample_freq = 0x03; 788 org_sample_freq = 0x0C; 789 break; 790 case 44100: 791 sample_freq = 0x00; 792 org_sample_freq = 0x0F; 793 break; 794 case 48000: 795 sample_freq = 0x02; 796 org_sample_freq = 0x0D; 797 break; 798 case 88200: 799 sample_freq = 0x08; 800 org_sample_freq = 0x07; 801 break; 802 case 96000: 803 sample_freq = 0x0A; 804 org_sample_freq = 0x05; 805 break; 806 case 176400: 807 sample_freq = 0x0C; 808 org_sample_freq = 0x03; 809 break; 810 case 192000: 811 sample_freq = 0x0E; 812 org_sample_freq = 0x01; 813 break; 814 default: 815 break; 816 } 817 818 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 819 hdmi_enable_audio_clk(hdmi, true); 820 821 hdmi_writeb(hdmi, 0x1, HDMI_FC_AUDSCHNLS0); 822 hdmi_writeb(hdmi, hdmi->channels, HDMI_FC_AUDSCHNLS2); 823 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS3); 824 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS4); 825 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS5); 826 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS6); 827 hdmi_writeb(hdmi, (0x3 << 4) | sample_freq, HDMI_FC_AUDSCHNLS7); 828 hdmi_writeb(hdmi, (org_sample_freq << 4) | 0xb, HDMI_FC_AUDSCHNLS8); 829 830 hdmi_writeb(hdmi, ch_mask, HDMI_GP_CONF1); 831 hdmi_writeb(hdmi, 0x02, HDMI_GP_CONF2); 832 hdmi_writeb(hdmi, 0x01, HDMI_GP_CONF0); 833 834 hdmi_modb(hdmi, 0x3, 0x3, HDMI_FC_DATAUTO3); 835 836 /* hbr */ 837 if (hdmi->sample_rate == 192000 && hdmi->channels == 8 && 838 hdmi->sample_width == 32 && hdmi->sample_non_pcm) 839 hdmi_modb(hdmi, 0x01, 0x01, HDMI_GP_CONF2); 840 841 if (pdata->enable_audio) 842 pdata->enable_audio(hdmi, 843 hdmi->channels, 844 hdmi->sample_width, 845 hdmi->sample_rate, 846 hdmi->sample_non_pcm); 847 } 848 849 static void dw_hdmi_gp_audio_disable(struct dw_hdmi *hdmi) 850 { 851 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 852 853 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 854 855 hdmi_modb(hdmi, 0, 0x3, HDMI_FC_DATAUTO3); 856 if (pdata->disable_audio) 857 pdata->disable_audio(hdmi); 858 859 hdmi_enable_audio_clk(hdmi, false); 860 } 861 862 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 863 { 864 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 865 } 866 867 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 868 { 869 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 870 } 871 872 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 873 { 874 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 875 hdmi_enable_audio_clk(hdmi, true); 876 } 877 878 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 879 { 880 hdmi_enable_audio_clk(hdmi, false); 881 } 882 883 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 884 { 885 unsigned long flags; 886 887 spin_lock_irqsave(&hdmi->audio_lock, flags); 888 hdmi->audio_enable = true; 889 if (hdmi->enable_audio) 890 hdmi->enable_audio(hdmi); 891 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 892 } 893 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 894 895 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 896 { 897 unsigned long flags; 898 899 spin_lock_irqsave(&hdmi->audio_lock, flags); 900 hdmi->audio_enable = false; 901 if (hdmi->disable_audio) 902 hdmi->disable_audio(hdmi); 903 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 904 } 905 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 906 907 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 908 { 909 switch (bus_format) { 910 case MEDIA_BUS_FMT_RGB888_1X24: 911 case MEDIA_BUS_FMT_RGB101010_1X30: 912 case MEDIA_BUS_FMT_RGB121212_1X36: 913 case MEDIA_BUS_FMT_RGB161616_1X48: 914 return true; 915 916 default: 917 return false; 918 } 919 } 920 921 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 922 { 923 switch (bus_format) { 924 case MEDIA_BUS_FMT_YUV8_1X24: 925 case MEDIA_BUS_FMT_YUV10_1X30: 926 case MEDIA_BUS_FMT_YUV12_1X36: 927 case MEDIA_BUS_FMT_YUV16_1X48: 928 return true; 929 930 default: 931 return false; 932 } 933 } 934 935 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 936 { 937 switch (bus_format) { 938 case MEDIA_BUS_FMT_UYVY8_1X16: 939 case MEDIA_BUS_FMT_UYVY10_1X20: 940 case MEDIA_BUS_FMT_UYVY12_1X24: 941 return true; 942 943 default: 944 return false; 945 } 946 } 947 948 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 949 { 950 switch (bus_format) { 951 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 952 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 953 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 954 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 955 return true; 956 957 default: 958 return false; 959 } 960 } 961 962 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 963 { 964 switch (bus_format) { 965 case MEDIA_BUS_FMT_RGB888_1X24: 966 case MEDIA_BUS_FMT_YUV8_1X24: 967 case MEDIA_BUS_FMT_UYVY8_1X16: 968 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 969 return 8; 970 971 case MEDIA_BUS_FMT_RGB101010_1X30: 972 case MEDIA_BUS_FMT_YUV10_1X30: 973 case MEDIA_BUS_FMT_UYVY10_1X20: 974 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 975 return 10; 976 977 case MEDIA_BUS_FMT_RGB121212_1X36: 978 case MEDIA_BUS_FMT_YUV12_1X36: 979 case MEDIA_BUS_FMT_UYVY12_1X24: 980 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 981 return 12; 982 983 case MEDIA_BUS_FMT_RGB161616_1X48: 984 case MEDIA_BUS_FMT_YUV16_1X48: 985 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 986 return 16; 987 988 default: 989 return 0; 990 } 991 } 992 993 /* 994 * this submodule is responsible for the video data synchronization. 995 * for example, for RGB 4:4:4 input, the data map is defined as 996 * pin{47~40} <==> R[7:0] 997 * pin{31~24} <==> G[7:0] 998 * pin{15~8} <==> B[7:0] 999 */ 1000 static void hdmi_video_sample(struct dw_hdmi *hdmi) 1001 { 1002 int color_format = 0; 1003 u8 val; 1004 1005 switch (hdmi->hdmi_data.enc_in_bus_format) { 1006 case MEDIA_BUS_FMT_RGB888_1X24: 1007 color_format = 0x01; 1008 break; 1009 case MEDIA_BUS_FMT_RGB101010_1X30: 1010 color_format = 0x03; 1011 break; 1012 case MEDIA_BUS_FMT_RGB121212_1X36: 1013 color_format = 0x05; 1014 break; 1015 case MEDIA_BUS_FMT_RGB161616_1X48: 1016 color_format = 0x07; 1017 break; 1018 1019 case MEDIA_BUS_FMT_YUV8_1X24: 1020 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1021 color_format = 0x09; 1022 break; 1023 case MEDIA_BUS_FMT_YUV10_1X30: 1024 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1025 color_format = 0x0B; 1026 break; 1027 case MEDIA_BUS_FMT_YUV12_1X36: 1028 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 1029 color_format = 0x0D; 1030 break; 1031 case MEDIA_BUS_FMT_YUV16_1X48: 1032 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1033 color_format = 0x0F; 1034 break; 1035 1036 case MEDIA_BUS_FMT_UYVY8_1X16: 1037 color_format = 0x16; 1038 break; 1039 case MEDIA_BUS_FMT_UYVY10_1X20: 1040 color_format = 0x14; 1041 break; 1042 case MEDIA_BUS_FMT_UYVY12_1X24: 1043 color_format = 0x12; 1044 break; 1045 1046 default: 1047 return; 1048 } 1049 1050 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 1051 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 1052 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 1053 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 1054 1055 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 1056 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 1057 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 1058 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 1059 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 1060 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 1061 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 1062 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 1063 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 1064 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 1065 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 1066 } 1067 1068 static int is_color_space_conversion(struct dw_hdmi *hdmi) 1069 { 1070 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1071 bool is_input_rgb, is_output_rgb; 1072 1073 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format); 1074 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format); 1075 1076 return (is_input_rgb != is_output_rgb) || 1077 (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range); 1078 } 1079 1080 static int is_color_space_decimation(struct dw_hdmi *hdmi) 1081 { 1082 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1083 return 0; 1084 1085 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 1086 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 1087 return 1; 1088 1089 return 0; 1090 } 1091 1092 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 1093 { 1094 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 1095 return 0; 1096 1097 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1098 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1099 return 1; 1100 1101 return 0; 1102 } 1103 1104 static bool is_csc_needed(struct dw_hdmi *hdmi) 1105 { 1106 return is_color_space_conversion(hdmi) || 1107 is_color_space_decimation(hdmi) || 1108 is_color_space_interpolation(hdmi); 1109 } 1110 1111 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 1112 { 1113 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 1114 bool is_input_rgb, is_output_rgb; 1115 unsigned i; 1116 u32 csc_scale = 1; 1117 1118 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); 1119 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); 1120 1121 if (!is_input_rgb && is_output_rgb) { 1122 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) 1123 csc_coeff = &csc_coeff_rgb_out_eitu601; 1124 else 1125 csc_coeff = &csc_coeff_rgb_out_eitu709; 1126 } else if (is_input_rgb && !is_output_rgb) { 1127 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) 1128 csc_coeff = &csc_coeff_rgb_in_eitu601; 1129 else 1130 csc_coeff = &csc_coeff_rgb_in_eitu709; 1131 csc_scale = 0; 1132 } else if (is_input_rgb && is_output_rgb && 1133 hdmi->hdmi_data.rgb_limited_range) { 1134 csc_coeff = &csc_coeff_rgb_full_to_rgb_limited; 1135 } 1136 1137 /* The CSC registers are sequential, alternating MSB then LSB */ 1138 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 1139 u16 coeff_a = (*csc_coeff)[0][i]; 1140 u16 coeff_b = (*csc_coeff)[1][i]; 1141 u16 coeff_c = (*csc_coeff)[2][i]; 1142 1143 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 1144 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 1145 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 1146 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 1147 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 1148 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 1149 } 1150 1151 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 1152 HDMI_CSC_SCALE); 1153 } 1154 1155 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1156 { 1157 int color_depth = 0; 1158 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1159 int decimation = 0; 1160 1161 /* YCC422 interpolation to 444 mode */ 1162 if (is_color_space_interpolation(hdmi)) 1163 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1164 else if (is_color_space_decimation(hdmi)) 1165 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1166 1167 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1168 case 8: 1169 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1170 break; 1171 case 10: 1172 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1173 break; 1174 case 12: 1175 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1176 break; 1177 case 16: 1178 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1179 break; 1180 1181 default: 1182 return; 1183 } 1184 1185 /* Configure the CSC registers */ 1186 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1187 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1188 HDMI_CSC_SCALE); 1189 1190 dw_hdmi_update_csc_coeffs(hdmi); 1191 } 1192 1193 /* 1194 * HDMI video packetizer is used to packetize the data. 1195 * for example, if input is YCC422 mode or repeater is used, 1196 * data should be repacked this module can be bypassed. 1197 */ 1198 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1199 { 1200 unsigned int color_depth = 0; 1201 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1202 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1203 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1204 u8 val, vp_conf; 1205 u8 clear_gcp_auto = 0; 1206 1207 1208 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1209 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1210 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1211 switch (hdmi_bus_fmt_color_depth( 1212 hdmi->hdmi_data.enc_out_bus_format)) { 1213 case 8: 1214 color_depth = 4; 1215 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1216 clear_gcp_auto = 1; 1217 break; 1218 case 10: 1219 color_depth = 5; 1220 break; 1221 case 12: 1222 color_depth = 6; 1223 break; 1224 case 16: 1225 color_depth = 7; 1226 break; 1227 default: 1228 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1229 } 1230 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1231 switch (hdmi_bus_fmt_color_depth( 1232 hdmi->hdmi_data.enc_out_bus_format)) { 1233 case 0: 1234 case 8: 1235 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1236 clear_gcp_auto = 1; 1237 break; 1238 case 10: 1239 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1240 break; 1241 case 12: 1242 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1243 break; 1244 1245 default: 1246 return; 1247 } 1248 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1249 } else { 1250 return; 1251 } 1252 1253 /* set the packetizer registers */ 1254 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1255 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 1256 ((hdmi_data->pix_repet_factor << 1257 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 1258 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 1259 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1260 1261 /* HDMI1.4b specification section 6.5.3: 1262 * Source shall only send GCPs with non-zero CD to sinks 1263 * that indicate support for Deep Color. 1264 * GCP only transmit CD and do not handle AVMUTE, PP norDefault_Phase (yet). 1265 * Disable Auto GCP when 24-bit color for sinks that not support Deep Color. 1266 */ 1267 val = hdmi_readb(hdmi, HDMI_FC_DATAUTO3); 1268 if (clear_gcp_auto == 1) 1269 val &= ~HDMI_FC_DATAUTO3_GCP_AUTO; 1270 else 1271 val |= HDMI_FC_DATAUTO3_GCP_AUTO; 1272 hdmi_writeb(hdmi, val, HDMI_FC_DATAUTO3); 1273 1274 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1275 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1276 1277 /* Data from pixel repeater block */ 1278 if (hdmi_data->pix_repet_factor > 1) { 1279 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1280 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1281 } else { /* data from packetizer block */ 1282 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1283 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1284 } 1285 1286 hdmi_modb(hdmi, vp_conf, 1287 HDMI_VP_CONF_PR_EN_MASK | 1288 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1289 1290 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1291 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1292 1293 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1294 1295 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1296 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1297 HDMI_VP_CONF_PP_EN_ENABLE | 1298 HDMI_VP_CONF_YCC422_EN_DISABLE; 1299 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1300 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1301 HDMI_VP_CONF_PP_EN_DISABLE | 1302 HDMI_VP_CONF_YCC422_EN_ENABLE; 1303 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1304 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1305 HDMI_VP_CONF_PP_EN_DISABLE | 1306 HDMI_VP_CONF_YCC422_EN_DISABLE; 1307 } else { 1308 return; 1309 } 1310 1311 hdmi_modb(hdmi, vp_conf, 1312 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1313 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1314 1315 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1316 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1317 HDMI_VP_STUFF_PP_STUFFING_MASK | 1318 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1319 1320 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1321 HDMI_VP_CONF); 1322 } 1323 1324 /* ----------------------------------------------------------------------------- 1325 * Synopsys PHY Handling 1326 */ 1327 1328 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 1329 unsigned char bit) 1330 { 1331 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 1332 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 1333 } 1334 1335 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 1336 { 1337 u32 val; 1338 1339 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 1340 if (msec-- == 0) 1341 return false; 1342 udelay(1000); 1343 } 1344 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1345 1346 return true; 1347 } 1348 1349 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1350 unsigned char addr) 1351 { 1352 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1353 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1354 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1355 HDMI_PHY_I2CM_DATAO_1_ADDR); 1356 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1357 HDMI_PHY_I2CM_DATAO_0_ADDR); 1358 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1359 HDMI_PHY_I2CM_OPERATION_ADDR); 1360 hdmi_phy_wait_i2c_done(hdmi, 1000); 1361 } 1362 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1363 1364 /* Filter out invalid setups to avoid configuring SCDC and scrambling */ 1365 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi, 1366 const struct drm_display_info *display) 1367 { 1368 /* Completely disable SCDC support for older controllers */ 1369 if (hdmi->version < 0x200a) 1370 return false; 1371 1372 /* Disable if no DDC bus */ 1373 if (!hdmi->ddc) 1374 return false; 1375 1376 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ 1377 if (!display->hdmi.scdc.supported || 1378 !display->hdmi.scdc.scrambling.supported) 1379 return false; 1380 1381 /* 1382 * Disable if display only support low TMDS rates and scrambling 1383 * for low rates is not supported either 1384 */ 1385 if (!display->hdmi.scdc.scrambling.low_rates && 1386 display->max_tmds_clock <= 340000) 1387 return false; 1388 1389 return true; 1390 } 1391 1392 /* 1393 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: 1394 * - The Source shall suspend transmission of the TMDS clock and data 1395 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it 1396 * from a 0 to a 1 or from a 1 to a 0 1397 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from 1398 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming 1399 * transmission of TMDS clock and data 1400 * 1401 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() 1402 * helper should called right before enabling the TMDS Clock and Data in 1403 * the PHY configuration callback. 1404 */ 1405 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi, 1406 const struct drm_display_info *display) 1407 { 1408 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1409 1410 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 1411 if (dw_hdmi_support_scdc(hdmi, display)) { 1412 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1413 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 1); 1414 else 1415 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 0); 1416 } 1417 } 1418 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); 1419 1420 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1421 { 1422 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1423 HDMI_PHY_CONF0_PDZ_OFFSET, 1424 HDMI_PHY_CONF0_PDZ_MASK); 1425 } 1426 1427 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1428 { 1429 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1430 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1431 HDMI_PHY_CONF0_ENTMDS_MASK); 1432 } 1433 1434 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1435 { 1436 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1437 HDMI_PHY_CONF0_SVSRET_OFFSET, 1438 HDMI_PHY_CONF0_SVSRET_MASK); 1439 } 1440 1441 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1442 { 1443 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1444 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1445 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1446 } 1447 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1448 1449 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1450 { 1451 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1452 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1453 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1454 } 1455 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1456 1457 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1458 { 1459 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1460 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1461 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1462 } 1463 1464 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1465 { 1466 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1467 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1468 HDMI_PHY_CONF0_SELDIPIF_MASK); 1469 } 1470 1471 void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi) 1472 { 1473 /* PHY reset. The reset signal is active low on Gen1 PHYs. */ 1474 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1475 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1476 } 1477 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset); 1478 1479 void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi) 1480 { 1481 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1482 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1483 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1484 } 1485 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset); 1486 1487 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1488 { 1489 hdmi_phy_test_clear(hdmi, 1); 1490 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1491 hdmi_phy_test_clear(hdmi, 0); 1492 } 1493 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1494 1495 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1496 { 1497 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1498 unsigned int i; 1499 u16 val; 1500 1501 if (phy->gen == 1) { 1502 dw_hdmi_phy_enable_tmds(hdmi, 0); 1503 dw_hdmi_phy_enable_powerdown(hdmi, true); 1504 return; 1505 } 1506 1507 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1508 1509 /* 1510 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1511 * to low power mode. 1512 */ 1513 for (i = 0; i < 5; ++i) { 1514 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1515 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1516 break; 1517 1518 usleep_range(1000, 2000); 1519 } 1520 1521 if (val & HDMI_PHY_TX_PHY_LOCK) 1522 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1523 else 1524 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1525 1526 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1527 } 1528 1529 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1530 { 1531 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1532 unsigned int i; 1533 u8 val; 1534 1535 if (phy->gen == 1) { 1536 dw_hdmi_phy_enable_powerdown(hdmi, false); 1537 1538 /* Toggle TMDS enable. */ 1539 dw_hdmi_phy_enable_tmds(hdmi, 0); 1540 dw_hdmi_phy_enable_tmds(hdmi, 1); 1541 return 0; 1542 } 1543 1544 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1545 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1546 1547 /* Wait for PHY PLL lock */ 1548 for (i = 0; i < 5; ++i) { 1549 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1550 if (val) 1551 break; 1552 1553 usleep_range(1000, 2000); 1554 } 1555 1556 if (!val) { 1557 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1558 return -ETIMEDOUT; 1559 } 1560 1561 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1562 return 0; 1563 } 1564 1565 /* 1566 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1567 * information the DWC MHL PHY has the same register layout and is thus also 1568 * supported by this function. 1569 */ 1570 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1571 const struct dw_hdmi_plat_data *pdata, 1572 unsigned long mpixelclock) 1573 { 1574 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1575 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1576 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1577 1578 /* TOFIX Will need 420 specific PHY configuration tables */ 1579 1580 /* PLL/MPLL Cfg - always match on final entry */ 1581 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1582 if (mpixelclock <= mpll_config->mpixelclock) 1583 break; 1584 1585 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1586 if (mpixelclock <= curr_ctrl->mpixelclock) 1587 break; 1588 1589 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1590 if (mpixelclock <= phy_config->mpixelclock) 1591 break; 1592 1593 if (mpll_config->mpixelclock == ~0UL || 1594 curr_ctrl->mpixelclock == ~0UL || 1595 phy_config->mpixelclock == ~0UL) 1596 return -EINVAL; 1597 1598 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1599 HDMI_3D_TX_PHY_CPCE_CTRL); 1600 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1601 HDMI_3D_TX_PHY_GMPCTRL); 1602 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1603 HDMI_3D_TX_PHY_CURRCTRL); 1604 1605 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1606 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1607 HDMI_3D_TX_PHY_MSM_CTRL); 1608 1609 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1610 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1611 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1612 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1613 HDMI_3D_TX_PHY_VLEVCTRL); 1614 1615 /* Override and disable clock termination. */ 1616 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1617 HDMI_3D_TX_PHY_CKCALCTRL); 1618 1619 return 0; 1620 } 1621 1622 static int hdmi_phy_configure(struct dw_hdmi *hdmi, 1623 const struct drm_display_info *display) 1624 { 1625 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1626 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1627 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1628 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1629 int ret; 1630 1631 dw_hdmi_phy_power_off(hdmi); 1632 1633 dw_hdmi_set_high_tmds_clock_ratio(hdmi, display); 1634 1635 /* Leave low power consumption mode by asserting SVSRET. */ 1636 if (phy->has_svsret) 1637 dw_hdmi_phy_enable_svsret(hdmi, 1); 1638 1639 dw_hdmi_phy_gen2_reset(hdmi); 1640 1641 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1642 1643 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1644 1645 /* Write to the PHY as configured by the platform */ 1646 if (pdata->configure_phy) 1647 ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock); 1648 else 1649 ret = phy->configure(hdmi, pdata, mpixelclock); 1650 if (ret) { 1651 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1652 mpixelclock); 1653 return ret; 1654 } 1655 1656 /* Wait for resuming transmission of TMDS clock and data */ 1657 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1658 msleep(100); 1659 1660 return dw_hdmi_phy_power_on(hdmi); 1661 } 1662 1663 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1664 const struct drm_display_info *display, 1665 const struct drm_display_mode *mode) 1666 { 1667 int i, ret; 1668 1669 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1670 for (i = 0; i < 2; i++) { 1671 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1672 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1673 1674 ret = hdmi_phy_configure(hdmi, display); 1675 if (ret) 1676 return ret; 1677 } 1678 1679 return 0; 1680 } 1681 1682 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1683 { 1684 dw_hdmi_phy_power_off(hdmi); 1685 } 1686 1687 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1688 void *data) 1689 { 1690 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1691 connector_status_connected : connector_status_disconnected; 1692 } 1693 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1694 1695 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1696 bool force, bool disabled, bool rxsense) 1697 { 1698 u8 old_mask = hdmi->phy_mask; 1699 1700 if (force || disabled || !rxsense) 1701 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1702 else 1703 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1704 1705 if (old_mask != hdmi->phy_mask) 1706 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1707 } 1708 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1709 1710 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1711 { 1712 /* 1713 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1714 * any pending interrupt. 1715 */ 1716 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1717 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1718 HDMI_IH_PHY_STAT0); 1719 1720 /* Enable cable hot plug irq. */ 1721 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1722 1723 /* Clear and unmute interrupts. */ 1724 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1725 HDMI_IH_PHY_STAT0); 1726 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1727 HDMI_IH_MUTE_PHY_STAT0); 1728 } 1729 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1730 1731 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1732 .init = dw_hdmi_phy_init, 1733 .disable = dw_hdmi_phy_disable, 1734 .read_hpd = dw_hdmi_phy_read_hpd, 1735 .update_hpd = dw_hdmi_phy_update_hpd, 1736 .setup_hpd = dw_hdmi_phy_setup_hpd, 1737 }; 1738 1739 /* ----------------------------------------------------------------------------- 1740 * HDMI TX Setup 1741 */ 1742 1743 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1744 { 1745 u8 de; 1746 1747 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1748 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1749 else 1750 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1751 1752 /* disable rx detect */ 1753 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1754 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1755 1756 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1757 1758 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1759 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1760 } 1761 1762 static void hdmi_config_AVI(struct dw_hdmi *hdmi, 1763 const struct drm_connector *connector, 1764 const struct drm_display_mode *mode) 1765 { 1766 struct hdmi_avi_infoframe frame; 1767 u8 val; 1768 1769 /* Initialise info frame from DRM mode */ 1770 drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1771 1772 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 1773 drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode, 1774 hdmi->hdmi_data.rgb_limited_range ? 1775 HDMI_QUANTIZATION_RANGE_LIMITED : 1776 HDMI_QUANTIZATION_RANGE_FULL); 1777 } else { 1778 frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 1779 frame.ycc_quantization_range = 1780 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 1781 } 1782 1783 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1784 frame.colorspace = HDMI_COLORSPACE_YUV444; 1785 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1786 frame.colorspace = HDMI_COLORSPACE_YUV422; 1787 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1788 frame.colorspace = HDMI_COLORSPACE_YUV420; 1789 else 1790 frame.colorspace = HDMI_COLORSPACE_RGB; 1791 1792 /* Set up colorimetry */ 1793 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 1794 switch (hdmi->hdmi_data.enc_out_encoding) { 1795 case V4L2_YCBCR_ENC_601: 1796 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1797 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1798 else 1799 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1800 frame.extended_colorimetry = 1801 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1802 break; 1803 case V4L2_YCBCR_ENC_709: 1804 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1805 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1806 else 1807 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1808 frame.extended_colorimetry = 1809 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1810 break; 1811 default: /* Carries no data */ 1812 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1813 frame.extended_colorimetry = 1814 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1815 break; 1816 } 1817 } else { 1818 frame.colorimetry = HDMI_COLORIMETRY_NONE; 1819 frame.extended_colorimetry = 1820 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1821 } 1822 1823 /* 1824 * The Designware IP uses a different byte format from standard 1825 * AVI info frames, though generally the bits are in the correct 1826 * bytes. 1827 */ 1828 1829 /* 1830 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1831 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1832 * bit 6 rather than 4. 1833 */ 1834 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1835 if (frame.active_aspect & 15) 1836 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1837 if (frame.top_bar || frame.bottom_bar) 1838 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1839 if (frame.left_bar || frame.right_bar) 1840 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1841 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1842 1843 /* AVI data byte 2 differences: none */ 1844 val = ((frame.colorimetry & 0x3) << 6) | 1845 ((frame.picture_aspect & 0x3) << 4) | 1846 (frame.active_aspect & 0xf); 1847 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1848 1849 /* AVI data byte 3 differences: none */ 1850 val = ((frame.extended_colorimetry & 0x7) << 4) | 1851 ((frame.quantization_range & 0x3) << 2) | 1852 (frame.nups & 0x3); 1853 if (frame.itc) 1854 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1855 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1856 1857 /* AVI data byte 4 differences: none */ 1858 val = frame.video_code & 0x7f; 1859 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1860 1861 /* AVI Data Byte 5- set up input and output pixel repetition */ 1862 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1863 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1864 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1865 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1866 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1867 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1868 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1869 1870 /* 1871 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1872 * ycc range in bits 2,3 rather than 6,7 1873 */ 1874 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1875 (frame.content_type & 0x3); 1876 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1877 1878 /* AVI Data Bytes 6-13 */ 1879 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1880 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1881 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1882 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1883 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1884 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1885 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1886 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1887 } 1888 1889 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1890 const struct drm_connector *connector, 1891 const struct drm_display_mode *mode) 1892 { 1893 struct hdmi_vendor_infoframe frame; 1894 u8 buffer[10]; 1895 ssize_t err; 1896 1897 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, connector, 1898 mode); 1899 if (err < 0) 1900 /* 1901 * Going into that statement does not means vendor infoframe 1902 * fails. It just informed us that vendor infoframe is not 1903 * needed for the selected mode. Only 4k or stereoscopic 3D 1904 * mode requires vendor infoframe. So just simply return. 1905 */ 1906 return; 1907 1908 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1909 if (err < 0) { 1910 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1911 err); 1912 return; 1913 } 1914 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1915 HDMI_FC_DATAUTO0_VSD_MASK); 1916 1917 /* Set the length of HDMI vendor specific InfoFrame payload */ 1918 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1919 1920 /* Set 24bit IEEE Registration Identifier */ 1921 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1922 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1923 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1924 1925 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1926 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1927 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1928 1929 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1930 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1931 1932 /* Packet frame interpolation */ 1933 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1934 1935 /* Auto packets per frame and line spacing */ 1936 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1937 1938 /* Configures the Frame Composer On RDRB mode */ 1939 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1940 HDMI_FC_DATAUTO0_VSD_MASK); 1941 } 1942 1943 static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, 1944 const struct drm_connector *connector) 1945 { 1946 const struct drm_connector_state *conn_state = connector->state; 1947 struct hdmi_drm_infoframe frame; 1948 u8 buffer[30]; 1949 ssize_t err; 1950 int i; 1951 1952 if (!hdmi->plat_data->use_drm_infoframe) 1953 return; 1954 1955 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE, 1956 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1957 1958 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state); 1959 if (err < 0) 1960 return; 1961 1962 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer)); 1963 if (err < 0) { 1964 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err); 1965 return; 1966 } 1967 1968 hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0); 1969 hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1); 1970 1971 for (i = 0; i < frame.length; i++) 1972 hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i); 1973 1974 hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP); 1975 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE, 1976 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1977 } 1978 1979 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1980 const struct drm_display_info *display, 1981 const struct drm_display_mode *mode) 1982 { 1983 u8 inv_val, bytes; 1984 const struct drm_hdmi_info *hdmi_info = &display->hdmi; 1985 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1986 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1987 unsigned int vdisplay, hdisplay; 1988 1989 vmode->mpixelclock = mode->clock * 1000; 1990 1991 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1992 1993 vmode->mtmdsclock = vmode->mpixelclock; 1994 1995 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1996 switch (hdmi_bus_fmt_color_depth( 1997 hdmi->hdmi_data.enc_out_bus_format)) { 1998 case 16: 1999 vmode->mtmdsclock = vmode->mpixelclock * 2; 2000 break; 2001 case 12: 2002 vmode->mtmdsclock = vmode->mpixelclock * 3 / 2; 2003 break; 2004 case 10: 2005 vmode->mtmdsclock = vmode->mpixelclock * 5 / 4; 2006 break; 2007 } 2008 } 2009 2010 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 2011 vmode->mtmdsclock /= 2; 2012 2013 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock); 2014 2015 /* Set up HDMI_FC_INVIDCONF */ 2016 inv_val = (hdmi->hdmi_data.hdcp_enable || 2017 (dw_hdmi_support_scdc(hdmi, display) && 2018 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 2019 hdmi_info->scdc.scrambling.low_rates)) ? 2020 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 2021 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 2022 2023 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 2024 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 2025 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 2026 2027 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 2028 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 2029 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 2030 2031 inv_val |= (vmode->mdataenablepolarity ? 2032 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 2033 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 2034 2035 if (hdmi->vic == 39) 2036 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 2037 else 2038 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 2039 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 2040 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 2041 2042 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 2043 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 2044 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 2045 2046 inv_val |= hdmi->sink_is_hdmi ? 2047 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 2048 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 2049 2050 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 2051 2052 hdisplay = mode->hdisplay; 2053 hblank = mode->htotal - mode->hdisplay; 2054 h_de_hs = mode->hsync_start - mode->hdisplay; 2055 hsync_len = mode->hsync_end - mode->hsync_start; 2056 2057 /* 2058 * When we're setting a YCbCr420 mode, we need 2059 * to adjust the horizontal timing to suit. 2060 */ 2061 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 2062 hdisplay /= 2; 2063 hblank /= 2; 2064 h_de_hs /= 2; 2065 hsync_len /= 2; 2066 } 2067 2068 vdisplay = mode->vdisplay; 2069 vblank = mode->vtotal - mode->vdisplay; 2070 v_de_vs = mode->vsync_start - mode->vdisplay; 2071 vsync_len = mode->vsync_end - mode->vsync_start; 2072 2073 /* 2074 * When we're setting an interlaced mode, we need 2075 * to adjust the vertical timing to suit. 2076 */ 2077 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 2078 vdisplay /= 2; 2079 vblank /= 2; 2080 v_de_vs /= 2; 2081 vsync_len /= 2; 2082 } 2083 2084 /* Scrambling Control */ 2085 if (dw_hdmi_support_scdc(hdmi, display)) { 2086 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 2087 hdmi_info->scdc.scrambling.low_rates) { 2088 /* 2089 * HDMI2.0 Specifies the following procedure: 2090 * After the Source Device has determined that 2091 * SCDC_Present is set (=1), the Source Device should 2092 * write the accurate Version of the Source Device 2093 * to the Source Version field in the SCDCS. 2094 * Source Devices compliant shall set the 2095 * Source Version = 1. 2096 */ 2097 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, 2098 &bytes); 2099 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, 2100 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 2101 2102 /* Enabled Scrambling in the Sink */ 2103 drm_scdc_set_scrambling(hdmi->curr_conn, 1); 2104 2105 /* 2106 * To activate the scrambler feature, you must ensure 2107 * that the quasi-static configuration bit 2108 * fc_invidconf.HDCP_keepout is set at configuration 2109 * time, before the required mc_swrstzreq.tmdsswrst_req 2110 * reset request is issued. 2111 */ 2112 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 2113 HDMI_MC_SWRSTZ); 2114 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 2115 } else { 2116 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 2117 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 2118 HDMI_MC_SWRSTZ); 2119 drm_scdc_set_scrambling(hdmi->curr_conn, 0); 2120 } 2121 } 2122 2123 /* Set up horizontal active pixel width */ 2124 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 2125 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 2126 2127 /* Set up vertical active lines */ 2128 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 2129 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 2130 2131 /* Set up horizontal blanking pixel region width */ 2132 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 2133 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 2134 2135 /* Set up vertical blanking pixel region width */ 2136 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 2137 2138 /* Set up HSYNC active edge delay width (in pixel clks) */ 2139 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 2140 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 2141 2142 /* Set up VSYNC active edge delay (in lines) */ 2143 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 2144 2145 /* Set up HSYNC active pulse width (in pixel clks) */ 2146 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 2147 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 2148 2149 /* Set up VSYNC active edge delay (in lines) */ 2150 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 2151 } 2152 2153 /* HDMI Initialization Step B.4 */ 2154 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 2155 { 2156 /* control period minimum duration */ 2157 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 2158 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 2159 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 2160 2161 /* Set to fill TMDS data channels */ 2162 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 2163 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 2164 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 2165 2166 /* Enable pixel clock and tmds data path */ 2167 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 2168 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 2169 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 2170 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 2171 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 2172 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 2173 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2174 2175 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 2176 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2177 2178 /* Enable csc path */ 2179 if (is_csc_needed(hdmi)) { 2180 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 2181 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2182 2183 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 2184 HDMI_MC_FLOWCTRL); 2185 } else { 2186 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE; 2187 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2188 2189 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 2190 HDMI_MC_FLOWCTRL); 2191 } 2192 } 2193 2194 /* Workaround to clear the overflow condition */ 2195 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 2196 { 2197 unsigned int count; 2198 unsigned int i; 2199 u8 val; 2200 2201 /* 2202 * Under some circumstances the Frame Composer arithmetic unit can miss 2203 * an FC register write due to being busy processing the previous one. 2204 * The issue can be worked around by issuing a TMDS software reset and 2205 * then write one of the FC registers several times. 2206 * 2207 * The number of iterations matters and depends on the HDMI TX revision 2208 * (and possibly on the platform). 2209 * 4 iterations for i.MX6Q(v1.30a) and 1 iteration for others. 2210 * i.MX6DL (v1.31a), Allwinner SoCs (v1.32a), Rockchip RK3288 SoC (v2.00a), 2211 * Amlogic Meson GX SoCs (v2.01a), RK3328/RK3399 SoCs (v2.11a) 2212 * and i.MX8MPlus (v2.13a) have been identified as needing the workaround 2213 * with a single iteration. 2214 */ 2215 2216 switch (hdmi->version) { 2217 case 0x130a: 2218 count = 4; 2219 break; 2220 default: 2221 count = 1; 2222 break; 2223 } 2224 2225 /* TMDS software reset */ 2226 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 2227 2228 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 2229 for (i = 0; i < count; i++) 2230 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 2231 } 2232 2233 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 2234 { 2235 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 2236 HDMI_IH_MUTE_FC_STAT2); 2237 } 2238 2239 static int dw_hdmi_setup(struct dw_hdmi *hdmi, 2240 const struct drm_connector *connector, 2241 const struct drm_display_mode *mode) 2242 { 2243 int ret; 2244 2245 hdmi_disable_overflow_interrupts(hdmi); 2246 2247 hdmi->vic = drm_match_cea_mode(mode); 2248 2249 if (!hdmi->vic) { 2250 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 2251 } else { 2252 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 2253 } 2254 2255 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 2256 (hdmi->vic == 21) || (hdmi->vic == 22) || 2257 (hdmi->vic == 2) || (hdmi->vic == 3) || 2258 (hdmi->vic == 17) || (hdmi->vic == 18)) 2259 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2260 else 2261 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2262 2263 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2264 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2265 2266 if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED) 2267 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2268 2269 /* TOFIX: Get input encoding from plat data or fallback to none */ 2270 if (hdmi->plat_data->input_bus_encoding) 2271 hdmi->hdmi_data.enc_in_encoding = 2272 hdmi->plat_data->input_bus_encoding; 2273 else 2274 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2275 2276 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED) 2277 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2278 2279 hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi && 2280 drm_default_rgb_quant_range(mode) == 2281 HDMI_QUANTIZATION_RANGE_LIMITED; 2282 2283 hdmi->hdmi_data.pix_repet_factor = 0; 2284 hdmi->hdmi_data.hdcp_enable = 0; 2285 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2286 2287 /* HDMI Initialization Step B.1 */ 2288 hdmi_av_composer(hdmi, &connector->display_info, mode); 2289 2290 /* HDMI Initializateion Step B.2 */ 2291 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, 2292 &connector->display_info, 2293 &hdmi->previous_mode); 2294 if (ret) 2295 return ret; 2296 hdmi->phy.enabled = true; 2297 2298 /* HDMI Initialization Step B.3 */ 2299 dw_hdmi_enable_video_path(hdmi); 2300 2301 if (hdmi->sink_has_audio) { 2302 dev_dbg(hdmi->dev, "sink has audio support\n"); 2303 2304 /* HDMI Initialization Step E - Configure audio */ 2305 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2306 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable); 2307 } 2308 2309 /* not for DVI mode */ 2310 if (hdmi->sink_is_hdmi) { 2311 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 2312 2313 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2314 hdmi_config_AVI(hdmi, connector, mode); 2315 hdmi_config_vendor_specific_infoframe(hdmi, connector, mode); 2316 hdmi_config_drm_infoframe(hdmi, connector); 2317 } else { 2318 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 2319 } 2320 2321 hdmi_video_packetize(hdmi); 2322 hdmi_video_csc(hdmi); 2323 hdmi_video_sample(hdmi); 2324 hdmi_tx_hdcp_config(hdmi); 2325 2326 dw_hdmi_clear_overflow(hdmi); 2327 2328 return 0; 2329 } 2330 2331 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 2332 { 2333 u8 ih_mute; 2334 2335 /* 2336 * Boot up defaults are: 2337 * HDMI_IH_MUTE = 0x03 (disabled) 2338 * HDMI_IH_MUTE_* = 0x00 (enabled) 2339 * 2340 * Disable top level interrupt bits in HDMI block 2341 */ 2342 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 2343 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2344 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 2345 2346 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2347 2348 /* by default mask all interrupts */ 2349 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 2350 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2351 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2352 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2353 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 2354 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 2355 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 2356 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 2357 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 2358 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 2359 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 2360 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 2361 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 2362 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 2363 2364 /* Disable interrupts in the IH_MUTE_* registers */ 2365 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2366 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2367 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2368 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2369 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 2370 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2371 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2372 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2373 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2374 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2375 2376 /* Enable top level interrupt bits in HDMI block */ 2377 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2378 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 2379 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2380 } 2381 2382 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 2383 { 2384 hdmi->bridge_is_on = true; 2385 2386 /* 2387 * The curr_conn field is guaranteed to be valid here, as this function 2388 * is only be called when !hdmi->disabled. 2389 */ 2390 dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); 2391 } 2392 2393 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 2394 { 2395 if (hdmi->phy.enabled) { 2396 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 2397 hdmi->phy.enabled = false; 2398 } 2399 2400 hdmi->bridge_is_on = false; 2401 } 2402 2403 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 2404 { 2405 int force = hdmi->force; 2406 2407 if (hdmi->disabled) { 2408 force = DRM_FORCE_OFF; 2409 } else if (force == DRM_FORCE_UNSPECIFIED) { 2410 if (hdmi->rxsense) 2411 force = DRM_FORCE_ON; 2412 else 2413 force = DRM_FORCE_OFF; 2414 } 2415 2416 if (force == DRM_FORCE_OFF) { 2417 if (hdmi->bridge_is_on) 2418 dw_hdmi_poweroff(hdmi); 2419 } else { 2420 if (!hdmi->bridge_is_on) 2421 dw_hdmi_poweron(hdmi); 2422 } 2423 } 2424 2425 /* 2426 * Adjust the detection of RXSENSE according to whether we have a forced 2427 * connection mode enabled, or whether we have been disabled. There is 2428 * no point processing RXSENSE interrupts if we have a forced connection 2429 * state, or DRM has us disabled. 2430 * 2431 * We also disable rxsense interrupts when we think we're disconnected 2432 * to avoid floating TDMS signals giving false rxsense interrupts. 2433 * 2434 * Note: we still need to listen for HPD interrupts even when DRM has us 2435 * disabled so that we can detect a connect event. 2436 */ 2437 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 2438 { 2439 if (hdmi->phy.ops->update_hpd) 2440 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 2441 hdmi->force, hdmi->disabled, 2442 hdmi->rxsense); 2443 } 2444 2445 static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi) 2446 { 2447 enum drm_connector_status result; 2448 2449 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 2450 hdmi->last_connector_result = result; 2451 2452 return result; 2453 } 2454 2455 static const struct drm_edid *dw_hdmi_edid_read(struct dw_hdmi *hdmi, 2456 struct drm_connector *connector) 2457 { 2458 const struct drm_edid *drm_edid; 2459 const struct edid *edid; 2460 2461 if (!hdmi->ddc) 2462 return NULL; 2463 2464 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc); 2465 if (!drm_edid) { 2466 dev_dbg(hdmi->dev, "failed to get edid\n"); 2467 return NULL; 2468 } 2469 2470 /* 2471 * FIXME: This should use connector->display_info.is_hdmi and 2472 * connector->display_info.has_audio from a path that has read the EDID 2473 * and called drm_edid_connector_update(). 2474 */ 2475 edid = drm_edid_raw(drm_edid); 2476 2477 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 2478 edid->width_cm, edid->height_cm); 2479 2480 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 2481 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2482 2483 return drm_edid; 2484 } 2485 2486 /* ----------------------------------------------------------------------------- 2487 * DRM Connector Operations 2488 */ 2489 2490 static enum drm_connector_status 2491 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 2492 { 2493 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2494 connector); 2495 return dw_hdmi_detect(hdmi); 2496 } 2497 2498 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 2499 { 2500 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2501 connector); 2502 const struct drm_edid *drm_edid; 2503 int ret; 2504 2505 drm_edid = dw_hdmi_edid_read(hdmi, connector); 2506 2507 drm_edid_connector_update(connector, drm_edid); 2508 cec_notifier_set_phys_addr(hdmi->cec_notifier, 2509 connector->display_info.source_physical_address); 2510 ret = drm_edid_connector_add_modes(connector); 2511 drm_edid_free(drm_edid); 2512 2513 return ret; 2514 } 2515 2516 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, 2517 struct drm_atomic_state *state) 2518 { 2519 struct drm_connector_state *old_state = 2520 drm_atomic_get_old_connector_state(state, connector); 2521 struct drm_connector_state *new_state = 2522 drm_atomic_get_new_connector_state(state, connector); 2523 struct drm_crtc *crtc = new_state->crtc; 2524 struct drm_crtc_state *crtc_state; 2525 2526 if (!crtc) 2527 return 0; 2528 2529 if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 2530 crtc_state = drm_atomic_get_crtc_state(state, crtc); 2531 if (IS_ERR(crtc_state)) 2532 return PTR_ERR(crtc_state); 2533 2534 crtc_state->mode_changed = true; 2535 } 2536 2537 return 0; 2538 } 2539 2540 static void dw_hdmi_connector_force(struct drm_connector *connector) 2541 { 2542 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2543 connector); 2544 2545 mutex_lock(&hdmi->mutex); 2546 hdmi->force = connector->force; 2547 dw_hdmi_update_power(hdmi); 2548 dw_hdmi_update_phy_mask(hdmi); 2549 mutex_unlock(&hdmi->mutex); 2550 } 2551 2552 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 2553 .fill_modes = drm_helper_probe_single_connector_modes, 2554 .detect = dw_hdmi_connector_detect, 2555 .destroy = drm_connector_cleanup, 2556 .force = dw_hdmi_connector_force, 2557 .reset = drm_atomic_helper_connector_reset, 2558 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2559 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2560 }; 2561 2562 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 2563 .get_modes = dw_hdmi_connector_get_modes, 2564 .atomic_check = dw_hdmi_connector_atomic_check, 2565 }; 2566 2567 static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) 2568 { 2569 struct drm_connector *connector = &hdmi->connector; 2570 struct cec_connector_info conn_info; 2571 struct cec_notifier *notifier; 2572 2573 if (hdmi->version >= 0x200a) 2574 connector->ycbcr_420_allowed = 2575 hdmi->plat_data->ycbcr_420_allowed; 2576 else 2577 connector->ycbcr_420_allowed = false; 2578 2579 connector->interlace_allowed = 1; 2580 connector->polled = DRM_CONNECTOR_POLL_HPD; 2581 2582 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 2583 2584 drm_connector_init_with_ddc(hdmi->bridge.dev, connector, 2585 &dw_hdmi_connector_funcs, 2586 DRM_MODE_CONNECTOR_HDMIA, 2587 hdmi->ddc); 2588 2589 /* 2590 * drm_connector_attach_max_bpc_property() requires the 2591 * connector to have a state. 2592 */ 2593 drm_atomic_helper_connector_reset(connector); 2594 2595 drm_connector_attach_max_bpc_property(connector, 8, 16); 2596 2597 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) 2598 drm_connector_attach_hdr_output_metadata_property(connector); 2599 2600 drm_connector_attach_encoder(connector, hdmi->bridge.encoder); 2601 2602 cec_fill_conn_info_from_drm(&conn_info, connector); 2603 2604 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info); 2605 if (!notifier) 2606 return -ENOMEM; 2607 2608 mutex_lock(&hdmi->cec_notifier_mutex); 2609 hdmi->cec_notifier = notifier; 2610 mutex_unlock(&hdmi->cec_notifier_mutex); 2611 2612 return 0; 2613 } 2614 2615 /* ----------------------------------------------------------------------------- 2616 * DRM Bridge Operations 2617 */ 2618 2619 /* 2620 * Possible output formats : 2621 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48, 2622 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36, 2623 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30, 2624 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24, 2625 * - MEDIA_BUS_FMT_RGB888_1X24, 2626 * - MEDIA_BUS_FMT_YUV16_1X48, 2627 * - MEDIA_BUS_FMT_RGB161616_1X48, 2628 * - MEDIA_BUS_FMT_UYVY12_1X24, 2629 * - MEDIA_BUS_FMT_YUV12_1X36, 2630 * - MEDIA_BUS_FMT_RGB121212_1X36, 2631 * - MEDIA_BUS_FMT_UYVY10_1X20, 2632 * - MEDIA_BUS_FMT_YUV10_1X30, 2633 * - MEDIA_BUS_FMT_RGB101010_1X30, 2634 * - MEDIA_BUS_FMT_UYVY8_1X16, 2635 * - MEDIA_BUS_FMT_YUV8_1X24, 2636 */ 2637 2638 /* Can return a maximum of 11 possible output formats for a mode/connector */ 2639 #define MAX_OUTPUT_SEL_FORMATS 11 2640 2641 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 2642 struct drm_bridge_state *bridge_state, 2643 struct drm_crtc_state *crtc_state, 2644 struct drm_connector_state *conn_state, 2645 unsigned int *num_output_fmts) 2646 { 2647 struct drm_connector *conn = conn_state->connector; 2648 struct drm_display_info *info = &conn->display_info; 2649 struct drm_display_mode *mode = &crtc_state->mode; 2650 u8 max_bpc = conn_state->max_requested_bpc; 2651 bool is_hdmi2_sink = info->hdmi.scdc.supported || 2652 (info->color_formats & DRM_COLOR_FORMAT_YCBCR420); 2653 u32 *output_fmts; 2654 unsigned int i = 0; 2655 2656 *num_output_fmts = 0; 2657 2658 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), 2659 GFP_KERNEL); 2660 if (!output_fmts) 2661 return NULL; 2662 2663 /* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */ 2664 if (list_is_singular(&bridge->encoder->bridge_chain) || 2665 list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) { 2666 *num_output_fmts = 1; 2667 output_fmts[0] = MEDIA_BUS_FMT_FIXED; 2668 2669 return output_fmts; 2670 } 2671 2672 /* 2673 * If the current mode enforces 4:2:0, force the output bus format 2674 * to 4:2:0 and do not add the YUV422/444/RGB formats 2675 */ 2676 if (conn->ycbcr_420_allowed && 2677 (drm_mode_is_420_only(info, mode) || 2678 (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) { 2679 2680 /* Order bus formats from 16bit to 8bit if supported */ 2681 if (max_bpc >= 16 && info->bpc == 16 && 2682 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)) 2683 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48; 2684 2685 if (max_bpc >= 12 && info->bpc >= 12 && 2686 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) 2687 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36; 2688 2689 if (max_bpc >= 10 && info->bpc >= 10 && 2690 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)) 2691 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30; 2692 2693 /* Default 8bit fallback */ 2694 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; 2695 2696 if (drm_mode_is_420_only(info, mode)) { 2697 *num_output_fmts = i; 2698 return output_fmts; 2699 } 2700 } 2701 2702 /* 2703 * Order bus formats from 16bit to 8bit and from YUV422 to RGB 2704 * if supported. In any case the default RGB888 format is added 2705 */ 2706 2707 /* Default 8bit RGB fallback */ 2708 output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2709 2710 if (max_bpc >= 16 && info->bpc == 16) { 2711 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2712 output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2713 2714 output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2715 } 2716 2717 if (max_bpc >= 12 && info->bpc >= 12) { 2718 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) 2719 output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2720 2721 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2722 output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2723 2724 output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2725 } 2726 2727 if (max_bpc >= 10 && info->bpc >= 10) { 2728 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) 2729 output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2730 2731 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2732 output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2733 2734 output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2735 } 2736 2737 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) 2738 output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2739 2740 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2741 output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2742 2743 *num_output_fmts = i; 2744 2745 return output_fmts; 2746 } 2747 2748 /* 2749 * Possible input formats : 2750 * - MEDIA_BUS_FMT_RGB888_1X24 2751 * - MEDIA_BUS_FMT_YUV8_1X24 2752 * - MEDIA_BUS_FMT_UYVY8_1X16 2753 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24 2754 * - MEDIA_BUS_FMT_RGB101010_1X30 2755 * - MEDIA_BUS_FMT_YUV10_1X30 2756 * - MEDIA_BUS_FMT_UYVY10_1X20 2757 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30 2758 * - MEDIA_BUS_FMT_RGB121212_1X36 2759 * - MEDIA_BUS_FMT_YUV12_1X36 2760 * - MEDIA_BUS_FMT_UYVY12_1X24 2761 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36 2762 * - MEDIA_BUS_FMT_RGB161616_1X48 2763 * - MEDIA_BUS_FMT_YUV16_1X48 2764 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48 2765 */ 2766 2767 /* Can return a maximum of 3 possible input formats for an output format */ 2768 #define MAX_INPUT_SEL_FORMATS 3 2769 2770 static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 2771 struct drm_bridge_state *bridge_state, 2772 struct drm_crtc_state *crtc_state, 2773 struct drm_connector_state *conn_state, 2774 u32 output_fmt, 2775 unsigned int *num_input_fmts) 2776 { 2777 u32 *input_fmts; 2778 unsigned int i = 0; 2779 2780 *num_input_fmts = 0; 2781 2782 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 2783 GFP_KERNEL); 2784 if (!input_fmts) 2785 return NULL; 2786 2787 switch (output_fmt) { 2788 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */ 2789 case MEDIA_BUS_FMT_FIXED: 2790 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2791 break; 2792 /* 8bit */ 2793 case MEDIA_BUS_FMT_RGB888_1X24: 2794 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2795 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2796 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2797 break; 2798 case MEDIA_BUS_FMT_YUV8_1X24: 2799 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2800 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2801 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2802 break; 2803 case MEDIA_BUS_FMT_UYVY8_1X16: 2804 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2805 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2806 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2807 break; 2808 2809 /* 10bit */ 2810 case MEDIA_BUS_FMT_RGB101010_1X30: 2811 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2812 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2813 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2814 break; 2815 case MEDIA_BUS_FMT_YUV10_1X30: 2816 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2817 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2818 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2819 break; 2820 case MEDIA_BUS_FMT_UYVY10_1X20: 2821 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2822 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2823 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2824 break; 2825 2826 /* 12bit */ 2827 case MEDIA_BUS_FMT_RGB121212_1X36: 2828 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2829 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2830 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2831 break; 2832 case MEDIA_BUS_FMT_YUV12_1X36: 2833 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2834 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2835 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2836 break; 2837 case MEDIA_BUS_FMT_UYVY12_1X24: 2838 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2839 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2840 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2841 break; 2842 2843 /* 16bit */ 2844 case MEDIA_BUS_FMT_RGB161616_1X48: 2845 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2846 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2847 break; 2848 case MEDIA_BUS_FMT_YUV16_1X48: 2849 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2850 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2851 break; 2852 2853 /*YUV 4:2:0 */ 2854 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2855 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2856 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 2857 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 2858 input_fmts[i++] = output_fmt; 2859 break; 2860 } 2861 2862 *num_input_fmts = i; 2863 2864 if (*num_input_fmts == 0) { 2865 kfree(input_fmts); 2866 input_fmts = NULL; 2867 } 2868 2869 return input_fmts; 2870 } 2871 2872 static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge, 2873 struct drm_bridge_state *bridge_state, 2874 struct drm_crtc_state *crtc_state, 2875 struct drm_connector_state *conn_state) 2876 { 2877 struct dw_hdmi *hdmi = bridge->driver_private; 2878 2879 hdmi->hdmi_data.enc_out_bus_format = 2880 bridge_state->output_bus_cfg.format; 2881 2882 hdmi->hdmi_data.enc_in_bus_format = 2883 bridge_state->input_bus_cfg.format; 2884 2885 dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n", 2886 bridge_state->input_bus_cfg.format, 2887 bridge_state->output_bus_cfg.format); 2888 2889 return 0; 2890 } 2891 2892 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge, 2893 struct drm_encoder *encoder, 2894 enum drm_bridge_attach_flags flags) 2895 { 2896 struct dw_hdmi *hdmi = bridge->driver_private; 2897 2898 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 2899 return drm_bridge_attach(encoder, hdmi->next_bridge, 2900 bridge, flags); 2901 2902 return dw_hdmi_connector_create(hdmi); 2903 } 2904 2905 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge) 2906 { 2907 struct dw_hdmi *hdmi = bridge->driver_private; 2908 2909 mutex_lock(&hdmi->cec_notifier_mutex); 2910 cec_notifier_conn_unregister(hdmi->cec_notifier); 2911 hdmi->cec_notifier = NULL; 2912 mutex_unlock(&hdmi->cec_notifier_mutex); 2913 } 2914 2915 static enum drm_mode_status 2916 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 2917 const struct drm_display_info *info, 2918 const struct drm_display_mode *mode) 2919 { 2920 struct dw_hdmi *hdmi = bridge->driver_private; 2921 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 2922 enum drm_mode_status mode_status = MODE_OK; 2923 2924 /* We don't support double-clocked modes */ 2925 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2926 return MODE_BAD; 2927 2928 if (pdata->mode_valid) 2929 mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info, 2930 mode); 2931 2932 return mode_status; 2933 } 2934 2935 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2936 const struct drm_display_mode *orig_mode, 2937 const struct drm_display_mode *mode) 2938 { 2939 struct dw_hdmi *hdmi = bridge->driver_private; 2940 2941 mutex_lock(&hdmi->mutex); 2942 2943 /* Store the display mode for plugin/DKMS poweron events */ 2944 drm_mode_copy(&hdmi->previous_mode, mode); 2945 2946 mutex_unlock(&hdmi->mutex); 2947 } 2948 2949 static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, 2950 struct drm_atomic_state *state) 2951 { 2952 struct dw_hdmi *hdmi = bridge->driver_private; 2953 2954 mutex_lock(&hdmi->mutex); 2955 hdmi->disabled = true; 2956 hdmi->curr_conn = NULL; 2957 dw_hdmi_update_power(hdmi); 2958 dw_hdmi_update_phy_mask(hdmi); 2959 handle_plugged_change(hdmi, false); 2960 mutex_unlock(&hdmi->mutex); 2961 } 2962 2963 static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, 2964 struct drm_atomic_state *state) 2965 { 2966 struct dw_hdmi *hdmi = bridge->driver_private; 2967 struct drm_connector *connector; 2968 2969 connector = drm_atomic_get_new_connector_for_encoder(state, 2970 bridge->encoder); 2971 2972 mutex_lock(&hdmi->mutex); 2973 hdmi->disabled = false; 2974 hdmi->curr_conn = connector; 2975 dw_hdmi_update_power(hdmi); 2976 dw_hdmi_update_phy_mask(hdmi); 2977 handle_plugged_change(hdmi, true); 2978 mutex_unlock(&hdmi->mutex); 2979 } 2980 2981 static enum drm_connector_status 2982 dw_hdmi_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 2983 { 2984 struct dw_hdmi *hdmi = bridge->driver_private; 2985 2986 return dw_hdmi_detect(hdmi); 2987 } 2988 2989 static const struct drm_edid *dw_hdmi_bridge_edid_read(struct drm_bridge *bridge, 2990 struct drm_connector *connector) 2991 { 2992 struct dw_hdmi *hdmi = bridge->driver_private; 2993 2994 return dw_hdmi_edid_read(hdmi, connector); 2995 } 2996 2997 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 2998 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2999 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 3000 .atomic_reset = drm_atomic_helper_bridge_reset, 3001 .attach = dw_hdmi_bridge_attach, 3002 .detach = dw_hdmi_bridge_detach, 3003 .atomic_check = dw_hdmi_bridge_atomic_check, 3004 .atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts, 3005 .atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts, 3006 .atomic_enable = dw_hdmi_bridge_atomic_enable, 3007 .atomic_disable = dw_hdmi_bridge_atomic_disable, 3008 .mode_set = dw_hdmi_bridge_mode_set, 3009 .mode_valid = dw_hdmi_bridge_mode_valid, 3010 .detect = dw_hdmi_bridge_detect, 3011 .edid_read = dw_hdmi_bridge_edid_read, 3012 }; 3013 3014 /* ----------------------------------------------------------------------------- 3015 * IRQ Handling 3016 */ 3017 3018 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 3019 { 3020 struct dw_hdmi_i2c *i2c = hdmi->i2c; 3021 unsigned int stat; 3022 3023 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 3024 if (!stat) 3025 return IRQ_NONE; 3026 3027 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 3028 3029 i2c->stat = stat; 3030 3031 complete(&i2c->cmp); 3032 3033 return IRQ_HANDLED; 3034 } 3035 3036 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 3037 { 3038 struct dw_hdmi *hdmi = dev_id; 3039 u8 intr_stat; 3040 irqreturn_t ret = IRQ_NONE; 3041 3042 if (hdmi->i2c) 3043 ret = dw_hdmi_i2c_irq(hdmi); 3044 3045 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 3046 if (intr_stat) { 3047 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 3048 return IRQ_WAKE_THREAD; 3049 } 3050 3051 return ret; 3052 } 3053 3054 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 3055 { 3056 mutex_lock(&hdmi->mutex); 3057 3058 if (!hdmi->force) { 3059 /* 3060 * If the RX sense status indicates we're disconnected, 3061 * clear the software rxsense status. 3062 */ 3063 if (!rx_sense) 3064 hdmi->rxsense = false; 3065 3066 /* 3067 * Only set the software rxsense status when both 3068 * rxsense and hpd indicates we're connected. 3069 * This avoids what seems to be bad behaviour in 3070 * at least iMX6S versions of the phy. 3071 */ 3072 if (hpd) 3073 hdmi->rxsense = true; 3074 3075 dw_hdmi_update_power(hdmi); 3076 dw_hdmi_update_phy_mask(hdmi); 3077 } 3078 mutex_unlock(&hdmi->mutex); 3079 } 3080 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 3081 3082 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 3083 { 3084 struct dw_hdmi *hdmi = dev_id; 3085 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 3086 enum drm_connector_status status = connector_status_unknown; 3087 3088 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 3089 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 3090 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 3091 3092 phy_pol_mask = 0; 3093 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 3094 phy_pol_mask |= HDMI_PHY_HPD; 3095 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 3096 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 3097 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 3098 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 3099 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 3100 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 3101 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 3102 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 3103 3104 if (phy_pol_mask) 3105 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 3106 3107 /* 3108 * RX sense tells us whether the TDMS transmitters are detecting 3109 * load - in other words, there's something listening on the 3110 * other end of the link. Use this to decide whether we should 3111 * power on the phy as HPD may be toggled by the sink to merely 3112 * ask the source to re-read the EDID. 3113 */ 3114 if (intr_stat & 3115 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 3116 dw_hdmi_setup_rx_sense(hdmi, 3117 phy_stat & HDMI_PHY_HPD, 3118 phy_stat & HDMI_PHY_RX_SENSE); 3119 3120 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { 3121 mutex_lock(&hdmi->cec_notifier_mutex); 3122 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); 3123 mutex_unlock(&hdmi->cec_notifier_mutex); 3124 } 3125 3126 if (phy_stat & HDMI_PHY_HPD) 3127 status = connector_status_connected; 3128 3129 if (!(phy_stat & (HDMI_PHY_HPD | HDMI_PHY_RX_SENSE))) 3130 status = connector_status_disconnected; 3131 } 3132 3133 if (status != connector_status_unknown) { 3134 dev_dbg(hdmi->dev, "EVENT=%s\n", 3135 status == connector_status_connected ? 3136 "plugin" : "plugout"); 3137 3138 if (hdmi->bridge.dev) { 3139 drm_helper_hpd_irq_event(hdmi->bridge.dev); 3140 drm_bridge_hpd_notify(&hdmi->bridge, status); 3141 } 3142 } 3143 3144 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 3145 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 3146 HDMI_IH_MUTE_PHY_STAT0); 3147 3148 return IRQ_HANDLED; 3149 } 3150 3151 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 3152 { 3153 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 3154 .name = "DWC HDMI TX PHY", 3155 .gen = 1, 3156 }, { 3157 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 3158 .name = "DWC MHL PHY + HEAC PHY", 3159 .gen = 2, 3160 .has_svsret = true, 3161 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3162 }, { 3163 .type = DW_HDMI_PHY_DWC_MHL_PHY, 3164 .name = "DWC MHL PHY", 3165 .gen = 2, 3166 .has_svsret = true, 3167 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3168 }, { 3169 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 3170 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 3171 .gen = 2, 3172 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3173 }, { 3174 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 3175 .name = "DWC HDMI 3D TX PHY", 3176 .gen = 2, 3177 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3178 }, { 3179 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 3180 .name = "DWC HDMI 2.0 TX PHY", 3181 .gen = 2, 3182 .has_svsret = true, 3183 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3184 }, { 3185 .type = DW_HDMI_PHY_VENDOR_PHY, 3186 .name = "Vendor PHY", 3187 } 3188 }; 3189 3190 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 3191 { 3192 unsigned int i; 3193 u8 phy_type; 3194 3195 phy_type = hdmi->plat_data->phy_force_vendor ? 3196 DW_HDMI_PHY_VENDOR_PHY : 3197 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 3198 3199 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 3200 /* Vendor PHYs require support from the glue layer. */ 3201 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 3202 dev_err(hdmi->dev, 3203 "Vendor HDMI PHY not supported by glue layer\n"); 3204 return -ENODEV; 3205 } 3206 3207 hdmi->phy.ops = hdmi->plat_data->phy_ops; 3208 hdmi->phy.data = hdmi->plat_data->phy_data; 3209 hdmi->phy.name = hdmi->plat_data->phy_name; 3210 return 0; 3211 } 3212 3213 /* Synopsys PHYs are handled internally. */ 3214 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 3215 if (dw_hdmi_phys[i].type == phy_type) { 3216 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 3217 hdmi->phy.name = dw_hdmi_phys[i].name; 3218 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 3219 3220 if (!dw_hdmi_phys[i].configure && 3221 !hdmi->plat_data->configure_phy) { 3222 dev_err(hdmi->dev, "%s requires platform support\n", 3223 hdmi->phy.name); 3224 return -ENODEV; 3225 } 3226 3227 return 0; 3228 } 3229 } 3230 3231 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 3232 return -ENODEV; 3233 } 3234 3235 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 3236 { 3237 mutex_lock(&hdmi->mutex); 3238 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 3239 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 3240 mutex_unlock(&hdmi->mutex); 3241 } 3242 3243 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 3244 { 3245 mutex_lock(&hdmi->mutex); 3246 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 3247 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 3248 mutex_unlock(&hdmi->mutex); 3249 } 3250 3251 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 3252 .write = hdmi_writeb, 3253 .read = hdmi_readb, 3254 .enable = dw_hdmi_cec_enable, 3255 .disable = dw_hdmi_cec_disable, 3256 }; 3257 3258 static const struct regmap_config hdmi_regmap_8bit_config = { 3259 .reg_bits = 32, 3260 .val_bits = 8, 3261 .reg_stride = 1, 3262 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 3263 }; 3264 3265 static const struct regmap_config hdmi_regmap_32bit_config = { 3266 .reg_bits = 32, 3267 .val_bits = 32, 3268 .reg_stride = 4, 3269 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 3270 }; 3271 3272 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi) 3273 { 3274 initialize_hdmi_ih_mutes(hdmi); 3275 3276 /* 3277 * Reset HDMI DDC I2C master controller and mute I2CM interrupts. 3278 * Even if we are using a separate i2c adapter doing this doesn't 3279 * hurt. 3280 */ 3281 dw_hdmi_i2c_init(hdmi); 3282 3283 if (hdmi->phy.ops->setup_hpd) 3284 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 3285 } 3286 3287 /* ----------------------------------------------------------------------------- 3288 * Probe/remove API, used from platforms based on the DRM bridge API. 3289 */ 3290 3291 static int dw_hdmi_parse_dt(struct dw_hdmi *hdmi) 3292 { 3293 struct device_node *remote; 3294 3295 if (!hdmi->plat_data->output_port) 3296 return 0; 3297 3298 3299 remote = of_graph_get_remote_node(hdmi->dev->of_node, 3300 hdmi->plat_data->output_port, 3301 -1); 3302 if (!remote) 3303 return -ENODEV; 3304 3305 hdmi->next_bridge = of_drm_find_bridge(remote); 3306 of_node_put(remote); 3307 if (!hdmi->next_bridge) 3308 return -EPROBE_DEFER; 3309 3310 return 0; 3311 } 3312 3313 bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi) 3314 { 3315 return hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format); 3316 } 3317 EXPORT_SYMBOL_GPL(dw_hdmi_bus_fmt_is_420); 3318 3319 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 3320 const struct dw_hdmi_plat_data *plat_data) 3321 { 3322 struct device *dev = &pdev->dev; 3323 struct device_node *np = dev->of_node; 3324 struct platform_device_info pdevinfo; 3325 struct device_node *ddc_node; 3326 struct dw_hdmi_cec_data cec; 3327 struct dw_hdmi *hdmi; 3328 struct clk *clk; 3329 struct resource *iores = NULL; 3330 int irq; 3331 int ret; 3332 u32 val = 1; 3333 u8 prod_id0; 3334 u8 prod_id1; 3335 u8 config0; 3336 u8 config3; 3337 3338 hdmi = devm_drm_bridge_alloc(dev, struct dw_hdmi, bridge, &dw_hdmi_bridge_funcs); 3339 if (IS_ERR(hdmi)) 3340 return hdmi; 3341 3342 hdmi->plat_data = plat_data; 3343 hdmi->dev = dev; 3344 hdmi->sample_rate = 48000; 3345 hdmi->channels = 2; 3346 hdmi->disabled = true; 3347 hdmi->rxsense = true; 3348 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 3349 hdmi->mc_clkdis = 0x7f; 3350 hdmi->last_connector_result = connector_status_disconnected; 3351 3352 mutex_init(&hdmi->mutex); 3353 mutex_init(&hdmi->audio_mutex); 3354 mutex_init(&hdmi->cec_notifier_mutex); 3355 spin_lock_init(&hdmi->audio_lock); 3356 3357 ret = dw_hdmi_parse_dt(hdmi); 3358 if (ret < 0) 3359 return ERR_PTR(ret); 3360 3361 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 3362 if (ddc_node) { 3363 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 3364 of_node_put(ddc_node); 3365 if (!hdmi->ddc) { 3366 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 3367 return ERR_PTR(-EPROBE_DEFER); 3368 } 3369 3370 } else { 3371 dev_dbg(hdmi->dev, "no ddc property found\n"); 3372 } 3373 3374 if (!plat_data->regm) { 3375 const struct regmap_config *reg_config; 3376 3377 of_property_read_u32(np, "reg-io-width", &val); 3378 switch (val) { 3379 case 4: 3380 reg_config = &hdmi_regmap_32bit_config; 3381 hdmi->reg_shift = 2; 3382 break; 3383 case 1: 3384 reg_config = &hdmi_regmap_8bit_config; 3385 break; 3386 default: 3387 dev_err(dev, "reg-io-width must be 1 or 4\n"); 3388 return ERR_PTR(-EINVAL); 3389 } 3390 3391 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3392 hdmi->regs = devm_ioremap_resource(dev, iores); 3393 if (IS_ERR(hdmi->regs)) { 3394 ret = PTR_ERR(hdmi->regs); 3395 goto err_res; 3396 } 3397 3398 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 3399 if (IS_ERR(hdmi->regm)) { 3400 dev_err(dev, "Failed to configure regmap\n"); 3401 ret = PTR_ERR(hdmi->regm); 3402 goto err_res; 3403 } 3404 } else { 3405 hdmi->regm = plat_data->regm; 3406 } 3407 3408 clk = devm_clk_get_enabled(hdmi->dev, "isfr"); 3409 if (IS_ERR(clk)) { 3410 ret = PTR_ERR(clk); 3411 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 3412 goto err_res; 3413 } 3414 3415 clk = devm_clk_get_enabled(hdmi->dev, "iahb"); 3416 if (IS_ERR(clk)) { 3417 ret = PTR_ERR(clk); 3418 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 3419 goto err_res; 3420 } 3421 3422 clk = devm_clk_get_optional_enabled(hdmi->dev, "cec"); 3423 if (IS_ERR(clk)) { 3424 ret = PTR_ERR(clk); 3425 if (ret != -EPROBE_DEFER) 3426 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 3427 ret); 3428 goto err_res; 3429 } 3430 3431 /* Product and revision IDs */ 3432 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 3433 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 3434 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 3435 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 3436 3437 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 3438 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 3439 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 3440 hdmi->version, prod_id0, prod_id1); 3441 ret = -ENODEV; 3442 goto err_res; 3443 } 3444 3445 ret = dw_hdmi_detect_phy(hdmi); 3446 if (ret < 0) 3447 goto err_res; 3448 3449 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 3450 hdmi->version >> 12, hdmi->version & 0xfff, 3451 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 3452 hdmi->phy.name); 3453 3454 dw_hdmi_init_hw(hdmi); 3455 3456 irq = platform_get_irq(pdev, 0); 3457 if (irq < 0) { 3458 ret = irq; 3459 goto err_res; 3460 } 3461 3462 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 3463 dw_hdmi_irq, IRQF_SHARED, 3464 dev_name(dev), hdmi); 3465 if (ret) 3466 goto err_res; 3467 3468 /* 3469 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 3470 * N and cts values before enabling phy 3471 */ 3472 hdmi_init_clk_regenerator(hdmi); 3473 3474 /* If DDC bus is not specified, try to register HDMI I2C bus */ 3475 if (!hdmi->ddc) { 3476 /* Look for (optional) stuff related to unwedging */ 3477 hdmi->pinctrl = devm_pinctrl_get(dev); 3478 if (!IS_ERR(hdmi->pinctrl)) { 3479 hdmi->unwedge_state = 3480 pinctrl_lookup_state(hdmi->pinctrl, "unwedge"); 3481 hdmi->default_state = 3482 pinctrl_lookup_state(hdmi->pinctrl, "default"); 3483 3484 if (IS_ERR(hdmi->default_state) || 3485 IS_ERR(hdmi->unwedge_state)) { 3486 if (!IS_ERR(hdmi->unwedge_state)) 3487 dev_warn(dev, 3488 "Unwedge requires default pinctrl\n"); 3489 hdmi->default_state = NULL; 3490 hdmi->unwedge_state = NULL; 3491 } 3492 } 3493 3494 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 3495 if (IS_ERR(hdmi->ddc)) 3496 hdmi->ddc = NULL; 3497 } 3498 3499 hdmi->bridge.driver_private = hdmi; 3500 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID 3501 | DRM_BRIDGE_OP_HPD; 3502 hdmi->bridge.interlace_allowed = true; 3503 hdmi->bridge.ddc = hdmi->ddc; 3504 hdmi->bridge.of_node = pdev->dev.of_node; 3505 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 3506 3507 if (hdmi->version >= 0x200a) 3508 hdmi->bridge.ycbcr_420_allowed = plat_data->ycbcr_420_allowed; 3509 3510 memset(&pdevinfo, 0, sizeof(pdevinfo)); 3511 pdevinfo.parent = dev; 3512 pdevinfo.id = PLATFORM_DEVID_AUTO; 3513 3514 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 3515 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 3516 3517 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 3518 struct dw_hdmi_audio_data audio; 3519 3520 audio.phys = iores->start; 3521 audio.base = hdmi->regs; 3522 audio.irq = irq; 3523 audio.hdmi = hdmi; 3524 audio.get_eld = hdmi_audio_get_eld; 3525 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 3526 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 3527 3528 pdevinfo.name = "dw-hdmi-ahb-audio"; 3529 pdevinfo.data = &audio; 3530 pdevinfo.size_data = sizeof(audio); 3531 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3532 hdmi->audio = platform_device_register_full(&pdevinfo); 3533 } else if (config0 & HDMI_CONFIG0_I2S) { 3534 struct dw_hdmi_i2s_audio_data audio; 3535 3536 audio.hdmi = hdmi; 3537 audio.get_eld = hdmi_audio_get_eld; 3538 audio.write = hdmi_writeb; 3539 audio.read = hdmi_readb; 3540 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 3541 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 3542 3543 pdevinfo.name = "dw-hdmi-i2s-audio"; 3544 pdevinfo.data = &audio; 3545 pdevinfo.size_data = sizeof(audio); 3546 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3547 hdmi->audio = platform_device_register_full(&pdevinfo); 3548 } else if (iores && config3 & HDMI_CONFIG3_GPAUD) { 3549 struct dw_hdmi_audio_data audio; 3550 3551 audio.phys = iores->start; 3552 audio.base = hdmi->regs; 3553 audio.irq = irq; 3554 audio.hdmi = hdmi; 3555 audio.get_eld = hdmi_audio_get_eld; 3556 3557 hdmi->enable_audio = dw_hdmi_gp_audio_enable; 3558 hdmi->disable_audio = dw_hdmi_gp_audio_disable; 3559 3560 pdevinfo.name = "dw-hdmi-gp-audio"; 3561 pdevinfo.id = PLATFORM_DEVID_NONE; 3562 pdevinfo.data = &audio; 3563 pdevinfo.size_data = sizeof(audio); 3564 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3565 hdmi->audio = platform_device_register_full(&pdevinfo); 3566 } 3567 3568 if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) { 3569 cec.hdmi = hdmi; 3570 cec.ops = &dw_hdmi_cec_ops; 3571 cec.irq = irq; 3572 3573 pdevinfo.name = "dw-hdmi-cec"; 3574 pdevinfo.data = &cec; 3575 pdevinfo.size_data = sizeof(cec); 3576 pdevinfo.dma_mask = 0; 3577 3578 hdmi->cec = platform_device_register_full(&pdevinfo); 3579 } 3580 3581 drm_bridge_add(&hdmi->bridge); 3582 3583 return hdmi; 3584 3585 err_res: 3586 i2c_put_adapter(hdmi->ddc); 3587 3588 return ERR_PTR(ret); 3589 } 3590 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 3591 3592 void dw_hdmi_remove(struct dw_hdmi *hdmi) 3593 { 3594 drm_bridge_remove(&hdmi->bridge); 3595 3596 if (hdmi->audio && !IS_ERR(hdmi->audio)) 3597 platform_device_unregister(hdmi->audio); 3598 if (!IS_ERR(hdmi->cec)) 3599 platform_device_unregister(hdmi->cec); 3600 3601 /* Disable all interrupts */ 3602 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 3603 3604 if (hdmi->i2c) 3605 i2c_del_adapter(&hdmi->i2c->adap); 3606 else 3607 i2c_put_adapter(hdmi->ddc); 3608 } 3609 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 3610 3611 /* ----------------------------------------------------------------------------- 3612 * Bind/unbind API, used from platforms based on the component framework. 3613 */ 3614 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 3615 struct drm_encoder *encoder, 3616 const struct dw_hdmi_plat_data *plat_data) 3617 { 3618 struct dw_hdmi *hdmi; 3619 int ret; 3620 3621 hdmi = dw_hdmi_probe(pdev, plat_data); 3622 if (IS_ERR(hdmi)) 3623 return hdmi; 3624 3625 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0); 3626 if (ret) { 3627 dw_hdmi_remove(hdmi); 3628 return ERR_PTR(ret); 3629 } 3630 3631 return hdmi; 3632 } 3633 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 3634 3635 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 3636 { 3637 dw_hdmi_remove(hdmi); 3638 } 3639 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 3640 3641 void dw_hdmi_resume(struct dw_hdmi *hdmi) 3642 { 3643 dw_hdmi_init_hw(hdmi); 3644 } 3645 EXPORT_SYMBOL_GPL(dw_hdmi_resume); 3646 3647 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 3648 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 3649 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 3650 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 3651 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 3652 MODULE_LICENSE("GPL"); 3653 MODULE_ALIAS("platform:dw-hdmi"); 3654