1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver 4 * 5 * Copyright (C) 2013-2015 Mentor Graphics Inc. 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/hdmi.h> 13 #include <linux/irq.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/regmap.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/spinlock.h> 21 22 #include <media/cec-notifier.h> 23 24 #include <uapi/linux/media-bus-format.h> 25 #include <uapi/linux/videodev2.h> 26 27 #include <drm/bridge/dw_hdmi.h> 28 #include <drm/drm_atomic_helper.h> 29 #include <drm/drm_edid.h> 30 #include <drm/drm_of.h> 31 #include <drm/drm_print.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_scdc_helper.h> 34 35 #include "dw-hdmi-audio.h" 36 #include "dw-hdmi-cec.h" 37 #include "dw-hdmi.h" 38 39 #define DDC_SEGMENT_ADDR 0x30 40 41 #define HDMI_EDID_LEN 512 42 43 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 44 #define SCDC_MIN_SOURCE_VERSION 0x1 45 46 #define HDMI14_MAX_TMDSCLK 340000000 47 48 enum hdmi_datamap { 49 RGB444_8B = 0x01, 50 RGB444_10B = 0x03, 51 RGB444_12B = 0x05, 52 RGB444_16B = 0x07, 53 YCbCr444_8B = 0x09, 54 YCbCr444_10B = 0x0B, 55 YCbCr444_12B = 0x0D, 56 YCbCr444_16B = 0x0F, 57 YCbCr422_8B = 0x16, 58 YCbCr422_10B = 0x14, 59 YCbCr422_12B = 0x12, 60 }; 61 62 static const u16 csc_coeff_default[3][4] = { 63 { 0x2000, 0x0000, 0x0000, 0x0000 }, 64 { 0x0000, 0x2000, 0x0000, 0x0000 }, 65 { 0x0000, 0x0000, 0x2000, 0x0000 } 66 }; 67 68 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 69 { 0x2000, 0x6926, 0x74fd, 0x010e }, 70 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 71 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 72 }; 73 74 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 75 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 76 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 77 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 78 }; 79 80 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 81 { 0x2591, 0x1322, 0x074b, 0x0000 }, 82 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 83 { 0x6acd, 0x7534, 0x2000, 0x0200 } 84 }; 85 86 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 87 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 88 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 89 { 0x6756, 0x78ab, 0x2000, 0x0200 } 90 }; 91 92 struct hdmi_vmode { 93 bool mdataenablepolarity; 94 95 unsigned int mpixelclock; 96 unsigned int mpixelrepetitioninput; 97 unsigned int mpixelrepetitionoutput; 98 unsigned int mtmdsclock; 99 }; 100 101 struct hdmi_data_info { 102 unsigned int enc_in_bus_format; 103 unsigned int enc_out_bus_format; 104 unsigned int enc_in_encoding; 105 unsigned int enc_out_encoding; 106 unsigned int pix_repet_factor; 107 unsigned int hdcp_enable; 108 struct hdmi_vmode video_mode; 109 }; 110 111 struct dw_hdmi_i2c { 112 struct i2c_adapter adap; 113 114 struct mutex lock; /* used to serialize data transfers */ 115 struct completion cmp; 116 u8 stat; 117 118 u8 slave_reg; 119 bool is_regaddr; 120 bool is_segment; 121 }; 122 123 struct dw_hdmi_phy_data { 124 enum dw_hdmi_phy_type type; 125 const char *name; 126 unsigned int gen; 127 bool has_svsret; 128 int (*configure)(struct dw_hdmi *hdmi, 129 const struct dw_hdmi_plat_data *pdata, 130 unsigned long mpixelclock); 131 }; 132 133 struct dw_hdmi { 134 struct drm_connector connector; 135 struct drm_bridge bridge; 136 137 unsigned int version; 138 139 struct platform_device *audio; 140 struct platform_device *cec; 141 struct device *dev; 142 struct clk *isfr_clk; 143 struct clk *iahb_clk; 144 struct clk *cec_clk; 145 struct dw_hdmi_i2c *i2c; 146 147 struct hdmi_data_info hdmi_data; 148 const struct dw_hdmi_plat_data *plat_data; 149 150 int vic; 151 152 u8 edid[HDMI_EDID_LEN]; 153 154 struct { 155 const struct dw_hdmi_phy_ops *ops; 156 const char *name; 157 void *data; 158 bool enabled; 159 } phy; 160 161 struct drm_display_mode previous_mode; 162 163 struct i2c_adapter *ddc; 164 void __iomem *regs; 165 bool sink_is_hdmi; 166 bool sink_has_audio; 167 168 struct pinctrl *pinctrl; 169 struct pinctrl_state *default_state; 170 struct pinctrl_state *unwedge_state; 171 172 struct mutex mutex; /* for state below and previous_mode */ 173 enum drm_connector_force force; /* mutex-protected force state */ 174 bool disabled; /* DRM has disabled our bridge */ 175 bool bridge_is_on; /* indicates the bridge is on */ 176 bool rxsense; /* rxsense state */ 177 u8 phy_mask; /* desired phy int mask settings */ 178 u8 mc_clkdis; /* clock disable register */ 179 180 spinlock_t audio_lock; 181 struct mutex audio_mutex; 182 unsigned int sample_rate; 183 unsigned int audio_cts; 184 unsigned int audio_n; 185 bool audio_enable; 186 187 unsigned int reg_shift; 188 struct regmap *regm; 189 void (*enable_audio)(struct dw_hdmi *hdmi); 190 void (*disable_audio)(struct dw_hdmi *hdmi); 191 192 struct cec_notifier *cec_notifier; 193 }; 194 195 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 196 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 197 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 198 199 #define HDMI_PHY_RX_SENSE \ 200 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 201 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 202 203 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 204 { 205 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 206 } 207 208 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 209 { 210 unsigned int val = 0; 211 212 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 213 214 return val; 215 } 216 217 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 218 { 219 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 220 } 221 222 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 223 u8 shift, u8 mask) 224 { 225 hdmi_modb(hdmi, data << shift, mask, reg); 226 } 227 228 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 229 { 230 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 231 HDMI_PHY_I2CM_INT_ADDR); 232 233 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 234 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 235 HDMI_PHY_I2CM_CTLINT_ADDR); 236 237 /* Software reset */ 238 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 239 240 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 241 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 242 243 /* Set done, not acknowledged and arbitration interrupt polarities */ 244 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 245 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 246 HDMI_I2CM_CTLINT); 247 248 /* Clear DONE and ERROR interrupts */ 249 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 250 HDMI_IH_I2CM_STAT0); 251 252 /* Mute DONE and ERROR interrupts */ 253 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 254 HDMI_IH_MUTE_I2CM_STAT0); 255 } 256 257 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi) 258 { 259 /* If no unwedge state then give up */ 260 if (!hdmi->unwedge_state) 261 return false; 262 263 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n"); 264 265 /* 266 * This is a huge hack to workaround a problem where the dw_hdmi i2c 267 * bus could sometimes get wedged. Once wedged there doesn't appear 268 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ) 269 * other than pulsing the SDA line. 270 * 271 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi) 272 * by: 273 * 1. Remux the pin as a GPIO output, driven low. 274 * 2. Wait a little while. 1 ms seems to work, but we'll do 10. 275 * 3. Immediately jump to remux the pin as dw_hdmi i2c again. 276 * 277 * At the moment of remuxing, the line will still be low due to its 278 * recent stint as an output, but then it will be pulled high by the 279 * (presumed) external pullup. dw_hdmi seems to see this as a rising 280 * edge and that seems to get it out of its jam. 281 * 282 * This wedging was only ever seen on one TV, and only on one of 283 * its HDMI ports. It happened when the TV was powered on while the 284 * device was plugged in. A scope trace shows the TV bringing both SDA 285 * and SCL low, then bringing them both back up at roughly the same 286 * time. Presumably this confuses dw_hdmi because it saw activity but 287 * no real STOP (maybe it thinks there's another master on the bus?). 288 * Giving it a clean rising edge of SDA while SCL is already high 289 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out 290 * of its stupor. 291 * 292 * Note that after coming back alive, transfers seem to immediately 293 * resume, so if we unwedge due to a timeout we should wait a little 294 * longer for our transfer to finish, since it might have just started 295 * now. 296 */ 297 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state); 298 msleep(10); 299 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state); 300 301 return true; 302 } 303 304 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi) 305 { 306 struct dw_hdmi_i2c *i2c = hdmi->i2c; 307 int stat; 308 309 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 310 if (!stat) { 311 /* If we can't unwedge, return timeout */ 312 if (!dw_hdmi_i2c_unwedge(hdmi)) 313 return -EAGAIN; 314 315 /* We tried to unwedge; give it another chance */ 316 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 317 if (!stat) 318 return -EAGAIN; 319 } 320 321 /* Check for error condition on the bus */ 322 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 323 return -EIO; 324 325 return 0; 326 } 327 328 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 329 unsigned char *buf, unsigned int length) 330 { 331 struct dw_hdmi_i2c *i2c = hdmi->i2c; 332 int ret; 333 334 if (!i2c->is_regaddr) { 335 dev_dbg(hdmi->dev, "set read register address to 0\n"); 336 i2c->slave_reg = 0x00; 337 i2c->is_regaddr = true; 338 } 339 340 while (length--) { 341 reinit_completion(&i2c->cmp); 342 343 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 344 if (i2c->is_segment) 345 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 346 HDMI_I2CM_OPERATION); 347 else 348 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 349 HDMI_I2CM_OPERATION); 350 351 ret = dw_hdmi_i2c_wait(hdmi); 352 if (ret) 353 return ret; 354 355 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 356 } 357 i2c->is_segment = false; 358 359 return 0; 360 } 361 362 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 363 unsigned char *buf, unsigned int length) 364 { 365 struct dw_hdmi_i2c *i2c = hdmi->i2c; 366 int ret; 367 368 if (!i2c->is_regaddr) { 369 /* Use the first write byte as register address */ 370 i2c->slave_reg = buf[0]; 371 length--; 372 buf++; 373 i2c->is_regaddr = true; 374 } 375 376 while (length--) { 377 reinit_completion(&i2c->cmp); 378 379 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 380 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 381 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 382 HDMI_I2CM_OPERATION); 383 384 ret = dw_hdmi_i2c_wait(hdmi); 385 if (ret) 386 return ret; 387 } 388 389 return 0; 390 } 391 392 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 393 struct i2c_msg *msgs, int num) 394 { 395 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 396 struct dw_hdmi_i2c *i2c = hdmi->i2c; 397 u8 addr = msgs[0].addr; 398 int i, ret = 0; 399 400 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 401 402 for (i = 0; i < num; i++) { 403 if (msgs[i].len == 0) { 404 dev_dbg(hdmi->dev, 405 "unsupported transfer %d/%d, no data\n", 406 i + 1, num); 407 return -EOPNOTSUPP; 408 } 409 } 410 411 mutex_lock(&i2c->lock); 412 413 /* Unmute DONE and ERROR interrupts */ 414 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 415 416 /* Set slave device address taken from the first I2C message */ 417 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 418 419 /* Set slave device register address on transfer */ 420 i2c->is_regaddr = false; 421 422 /* Set segment pointer for I2C extended read mode operation */ 423 i2c->is_segment = false; 424 425 for (i = 0; i < num; i++) { 426 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 427 i + 1, num, msgs[i].len, msgs[i].flags); 428 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 429 i2c->is_segment = true; 430 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 431 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 432 } else { 433 if (msgs[i].flags & I2C_M_RD) 434 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 435 msgs[i].len); 436 else 437 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 438 msgs[i].len); 439 } 440 if (ret < 0) 441 break; 442 } 443 444 if (!ret) 445 ret = num; 446 447 /* Mute DONE and ERROR interrupts */ 448 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 449 HDMI_IH_MUTE_I2CM_STAT0); 450 451 mutex_unlock(&i2c->lock); 452 453 return ret; 454 } 455 456 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 457 { 458 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 459 } 460 461 static const struct i2c_algorithm dw_hdmi_algorithm = { 462 .master_xfer = dw_hdmi_i2c_xfer, 463 .functionality = dw_hdmi_i2c_func, 464 }; 465 466 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 467 { 468 struct i2c_adapter *adap; 469 struct dw_hdmi_i2c *i2c; 470 int ret; 471 472 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 473 if (!i2c) 474 return ERR_PTR(-ENOMEM); 475 476 mutex_init(&i2c->lock); 477 init_completion(&i2c->cmp); 478 479 adap = &i2c->adap; 480 adap->class = I2C_CLASS_DDC; 481 adap->owner = THIS_MODULE; 482 adap->dev.parent = hdmi->dev; 483 adap->algo = &dw_hdmi_algorithm; 484 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 485 i2c_set_adapdata(adap, hdmi); 486 487 ret = i2c_add_adapter(adap); 488 if (ret) { 489 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 490 devm_kfree(hdmi->dev, i2c); 491 return ERR_PTR(ret); 492 } 493 494 hdmi->i2c = i2c; 495 496 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 497 498 return adap; 499 } 500 501 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 502 unsigned int n) 503 { 504 /* Must be set/cleared first */ 505 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 506 507 /* nshift factor = 0 */ 508 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 509 510 /* Use automatic CTS generation mode when CTS is not set */ 511 if (cts) 512 hdmi_writeb(hdmi, ((cts >> 16) & 513 HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 514 HDMI_AUD_CTS3_CTS_MANUAL, 515 HDMI_AUD_CTS3); 516 else 517 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); 518 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 519 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 520 521 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 522 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 523 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 524 } 525 526 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 527 { 528 unsigned int n = (128 * freq) / 1000; 529 unsigned int mult = 1; 530 531 while (freq > 48000) { 532 mult *= 2; 533 freq /= 2; 534 } 535 536 switch (freq) { 537 case 32000: 538 if (pixel_clk == 25175000) 539 n = 4576; 540 else if (pixel_clk == 27027000) 541 n = 4096; 542 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 543 n = 11648; 544 else 545 n = 4096; 546 n *= mult; 547 break; 548 549 case 44100: 550 if (pixel_clk == 25175000) 551 n = 7007; 552 else if (pixel_clk == 74176000) 553 n = 17836; 554 else if (pixel_clk == 148352000) 555 n = 8918; 556 else 557 n = 6272; 558 n *= mult; 559 break; 560 561 case 48000: 562 if (pixel_clk == 25175000) 563 n = 6864; 564 else if (pixel_clk == 27027000) 565 n = 6144; 566 else if (pixel_clk == 74176000) 567 n = 11648; 568 else if (pixel_clk == 148352000) 569 n = 5824; 570 else 571 n = 6144; 572 n *= mult; 573 break; 574 575 default: 576 break; 577 } 578 579 return n; 580 } 581 582 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 583 unsigned long pixel_clk, unsigned int sample_rate) 584 { 585 unsigned long ftdms = pixel_clk; 586 unsigned int n, cts; 587 u8 config3; 588 u64 tmp; 589 590 n = hdmi_compute_n(sample_rate, pixel_clk); 591 592 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 593 594 /* Only compute CTS when using internal AHB audio */ 595 if (config3 & HDMI_CONFIG3_AHBAUDDMA) { 596 /* 597 * Compute the CTS value from the N value. Note that CTS and N 598 * can be up to 20 bits in total, so we need 64-bit math. Also 599 * note that our TDMS clock is not fully accurate; it is 600 * accurate to kHz. This can introduce an unnecessary remainder 601 * in the calculation below, so we don't try to warn about that. 602 */ 603 tmp = (u64)ftdms * n; 604 do_div(tmp, 128 * sample_rate); 605 cts = tmp; 606 607 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 608 __func__, sample_rate, 609 ftdms / 1000000, (ftdms / 1000) % 1000, 610 n, cts); 611 } else { 612 cts = 0; 613 } 614 615 spin_lock_irq(&hdmi->audio_lock); 616 hdmi->audio_n = n; 617 hdmi->audio_cts = cts; 618 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 619 spin_unlock_irq(&hdmi->audio_lock); 620 } 621 622 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 623 { 624 mutex_lock(&hdmi->audio_mutex); 625 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 626 mutex_unlock(&hdmi->audio_mutex); 627 } 628 629 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 630 { 631 mutex_lock(&hdmi->audio_mutex); 632 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 633 hdmi->sample_rate); 634 mutex_unlock(&hdmi->audio_mutex); 635 } 636 637 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 638 { 639 mutex_lock(&hdmi->audio_mutex); 640 hdmi->sample_rate = rate; 641 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 642 hdmi->sample_rate); 643 mutex_unlock(&hdmi->audio_mutex); 644 } 645 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 646 647 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt) 648 { 649 u8 layout; 650 651 mutex_lock(&hdmi->audio_mutex); 652 653 /* 654 * For >2 channel PCM audio, we need to select layout 1 655 * and set an appropriate channel map. 656 */ 657 if (cnt > 2) 658 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1; 659 else 660 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0; 661 662 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, 663 HDMI_FC_AUDSCONF); 664 665 /* Set the audio infoframes channel count */ 666 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, 667 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0); 668 669 mutex_unlock(&hdmi->audio_mutex); 670 } 671 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count); 672 673 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca) 674 { 675 mutex_lock(&hdmi->audio_mutex); 676 677 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2); 678 679 mutex_unlock(&hdmi->audio_mutex); 680 } 681 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation); 682 683 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 684 { 685 if (enable) 686 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 687 else 688 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 689 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 690 } 691 692 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 693 { 694 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 695 } 696 697 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 698 { 699 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 700 } 701 702 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 703 { 704 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 705 hdmi_enable_audio_clk(hdmi, true); 706 } 707 708 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 709 { 710 hdmi_enable_audio_clk(hdmi, false); 711 } 712 713 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 714 { 715 unsigned long flags; 716 717 spin_lock_irqsave(&hdmi->audio_lock, flags); 718 hdmi->audio_enable = true; 719 if (hdmi->enable_audio) 720 hdmi->enable_audio(hdmi); 721 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 722 } 723 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 724 725 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 726 { 727 unsigned long flags; 728 729 spin_lock_irqsave(&hdmi->audio_lock, flags); 730 hdmi->audio_enable = false; 731 if (hdmi->disable_audio) 732 hdmi->disable_audio(hdmi); 733 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 734 } 735 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 736 737 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 738 { 739 switch (bus_format) { 740 case MEDIA_BUS_FMT_RGB888_1X24: 741 case MEDIA_BUS_FMT_RGB101010_1X30: 742 case MEDIA_BUS_FMT_RGB121212_1X36: 743 case MEDIA_BUS_FMT_RGB161616_1X48: 744 return true; 745 746 default: 747 return false; 748 } 749 } 750 751 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 752 { 753 switch (bus_format) { 754 case MEDIA_BUS_FMT_YUV8_1X24: 755 case MEDIA_BUS_FMT_YUV10_1X30: 756 case MEDIA_BUS_FMT_YUV12_1X36: 757 case MEDIA_BUS_FMT_YUV16_1X48: 758 return true; 759 760 default: 761 return false; 762 } 763 } 764 765 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 766 { 767 switch (bus_format) { 768 case MEDIA_BUS_FMT_UYVY8_1X16: 769 case MEDIA_BUS_FMT_UYVY10_1X20: 770 case MEDIA_BUS_FMT_UYVY12_1X24: 771 return true; 772 773 default: 774 return false; 775 } 776 } 777 778 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 779 { 780 switch (bus_format) { 781 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 782 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 783 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 784 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 785 return true; 786 787 default: 788 return false; 789 } 790 } 791 792 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 793 { 794 switch (bus_format) { 795 case MEDIA_BUS_FMT_RGB888_1X24: 796 case MEDIA_BUS_FMT_YUV8_1X24: 797 case MEDIA_BUS_FMT_UYVY8_1X16: 798 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 799 return 8; 800 801 case MEDIA_BUS_FMT_RGB101010_1X30: 802 case MEDIA_BUS_FMT_YUV10_1X30: 803 case MEDIA_BUS_FMT_UYVY10_1X20: 804 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 805 return 10; 806 807 case MEDIA_BUS_FMT_RGB121212_1X36: 808 case MEDIA_BUS_FMT_YUV12_1X36: 809 case MEDIA_BUS_FMT_UYVY12_1X24: 810 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 811 return 12; 812 813 case MEDIA_BUS_FMT_RGB161616_1X48: 814 case MEDIA_BUS_FMT_YUV16_1X48: 815 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 816 return 16; 817 818 default: 819 return 0; 820 } 821 } 822 823 /* 824 * this submodule is responsible for the video data synchronization. 825 * for example, for RGB 4:4:4 input, the data map is defined as 826 * pin{47~40} <==> R[7:0] 827 * pin{31~24} <==> G[7:0] 828 * pin{15~8} <==> B[7:0] 829 */ 830 static void hdmi_video_sample(struct dw_hdmi *hdmi) 831 { 832 int color_format = 0; 833 u8 val; 834 835 switch (hdmi->hdmi_data.enc_in_bus_format) { 836 case MEDIA_BUS_FMT_RGB888_1X24: 837 color_format = 0x01; 838 break; 839 case MEDIA_BUS_FMT_RGB101010_1X30: 840 color_format = 0x03; 841 break; 842 case MEDIA_BUS_FMT_RGB121212_1X36: 843 color_format = 0x05; 844 break; 845 case MEDIA_BUS_FMT_RGB161616_1X48: 846 color_format = 0x07; 847 break; 848 849 case MEDIA_BUS_FMT_YUV8_1X24: 850 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 851 color_format = 0x09; 852 break; 853 case MEDIA_BUS_FMT_YUV10_1X30: 854 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 855 color_format = 0x0B; 856 break; 857 case MEDIA_BUS_FMT_YUV12_1X36: 858 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 859 color_format = 0x0D; 860 break; 861 case MEDIA_BUS_FMT_YUV16_1X48: 862 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 863 color_format = 0x0F; 864 break; 865 866 case MEDIA_BUS_FMT_UYVY8_1X16: 867 color_format = 0x16; 868 break; 869 case MEDIA_BUS_FMT_UYVY10_1X20: 870 color_format = 0x14; 871 break; 872 case MEDIA_BUS_FMT_UYVY12_1X24: 873 color_format = 0x12; 874 break; 875 876 default: 877 return; 878 } 879 880 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 881 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 882 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 883 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 884 885 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 886 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 887 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 888 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 889 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 890 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 891 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 892 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 893 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 894 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 895 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 896 } 897 898 static int is_color_space_conversion(struct dw_hdmi *hdmi) 899 { 900 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format; 901 } 902 903 static int is_color_space_decimation(struct dw_hdmi *hdmi) 904 { 905 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 906 return 0; 907 908 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 909 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 910 return 1; 911 912 return 0; 913 } 914 915 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 916 { 917 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 918 return 0; 919 920 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 921 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 922 return 1; 923 924 return 0; 925 } 926 927 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 928 { 929 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 930 unsigned i; 931 u32 csc_scale = 1; 932 933 if (is_color_space_conversion(hdmi)) { 934 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 935 if (hdmi->hdmi_data.enc_out_encoding == 936 V4L2_YCBCR_ENC_601) 937 csc_coeff = &csc_coeff_rgb_out_eitu601; 938 else 939 csc_coeff = &csc_coeff_rgb_out_eitu709; 940 } else if (hdmi_bus_fmt_is_rgb( 941 hdmi->hdmi_data.enc_in_bus_format)) { 942 if (hdmi->hdmi_data.enc_out_encoding == 943 V4L2_YCBCR_ENC_601) 944 csc_coeff = &csc_coeff_rgb_in_eitu601; 945 else 946 csc_coeff = &csc_coeff_rgb_in_eitu709; 947 csc_scale = 0; 948 } 949 } 950 951 /* The CSC registers are sequential, alternating MSB then LSB */ 952 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 953 u16 coeff_a = (*csc_coeff)[0][i]; 954 u16 coeff_b = (*csc_coeff)[1][i]; 955 u16 coeff_c = (*csc_coeff)[2][i]; 956 957 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 958 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 959 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 960 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 961 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 962 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 963 } 964 965 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 966 HDMI_CSC_SCALE); 967 } 968 969 static void hdmi_video_csc(struct dw_hdmi *hdmi) 970 { 971 int color_depth = 0; 972 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 973 int decimation = 0; 974 975 /* YCC422 interpolation to 444 mode */ 976 if (is_color_space_interpolation(hdmi)) 977 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 978 else if (is_color_space_decimation(hdmi)) 979 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 980 981 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 982 case 8: 983 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 984 break; 985 case 10: 986 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 987 break; 988 case 12: 989 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 990 break; 991 case 16: 992 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 993 break; 994 995 default: 996 return; 997 } 998 999 /* Configure the CSC registers */ 1000 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1001 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1002 HDMI_CSC_SCALE); 1003 1004 dw_hdmi_update_csc_coeffs(hdmi); 1005 } 1006 1007 /* 1008 * HDMI video packetizer is used to packetize the data. 1009 * for example, if input is YCC422 mode or repeater is used, 1010 * data should be repacked this module can be bypassed. 1011 */ 1012 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1013 { 1014 unsigned int color_depth = 0; 1015 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1016 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1017 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1018 u8 val, vp_conf; 1019 1020 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1021 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1022 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1023 switch (hdmi_bus_fmt_color_depth( 1024 hdmi->hdmi_data.enc_out_bus_format)) { 1025 case 8: 1026 color_depth = 4; 1027 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1028 break; 1029 case 10: 1030 color_depth = 5; 1031 break; 1032 case 12: 1033 color_depth = 6; 1034 break; 1035 case 16: 1036 color_depth = 7; 1037 break; 1038 default: 1039 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1040 } 1041 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1042 switch (hdmi_bus_fmt_color_depth( 1043 hdmi->hdmi_data.enc_out_bus_format)) { 1044 case 0: 1045 case 8: 1046 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1047 break; 1048 case 10: 1049 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1050 break; 1051 case 12: 1052 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1053 break; 1054 1055 default: 1056 return; 1057 } 1058 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1059 } else { 1060 return; 1061 } 1062 1063 /* set the packetizer registers */ 1064 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1065 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 1066 ((hdmi_data->pix_repet_factor << 1067 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 1068 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 1069 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1070 1071 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1072 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1073 1074 /* Data from pixel repeater block */ 1075 if (hdmi_data->pix_repet_factor > 1) { 1076 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1077 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1078 } else { /* data from packetizer block */ 1079 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1080 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1081 } 1082 1083 hdmi_modb(hdmi, vp_conf, 1084 HDMI_VP_CONF_PR_EN_MASK | 1085 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1086 1087 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1088 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1089 1090 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1091 1092 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1093 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1094 HDMI_VP_CONF_PP_EN_ENABLE | 1095 HDMI_VP_CONF_YCC422_EN_DISABLE; 1096 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1097 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1098 HDMI_VP_CONF_PP_EN_DISABLE | 1099 HDMI_VP_CONF_YCC422_EN_ENABLE; 1100 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1101 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1102 HDMI_VP_CONF_PP_EN_DISABLE | 1103 HDMI_VP_CONF_YCC422_EN_DISABLE; 1104 } else { 1105 return; 1106 } 1107 1108 hdmi_modb(hdmi, vp_conf, 1109 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1110 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1111 1112 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1113 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1114 HDMI_VP_STUFF_PP_STUFFING_MASK | 1115 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1116 1117 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1118 HDMI_VP_CONF); 1119 } 1120 1121 /* ----------------------------------------------------------------------------- 1122 * Synopsys PHY Handling 1123 */ 1124 1125 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 1126 unsigned char bit) 1127 { 1128 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 1129 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 1130 } 1131 1132 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 1133 { 1134 u32 val; 1135 1136 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 1137 if (msec-- == 0) 1138 return false; 1139 udelay(1000); 1140 } 1141 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1142 1143 return true; 1144 } 1145 1146 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1147 unsigned char addr) 1148 { 1149 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1150 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1151 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1152 HDMI_PHY_I2CM_DATAO_1_ADDR); 1153 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1154 HDMI_PHY_I2CM_DATAO_0_ADDR); 1155 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1156 HDMI_PHY_I2CM_OPERATION_ADDR); 1157 hdmi_phy_wait_i2c_done(hdmi, 1000); 1158 } 1159 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1160 1161 /* Filter out invalid setups to avoid configuring SCDC and scrambling */ 1162 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi) 1163 { 1164 struct drm_display_info *display = &hdmi->connector.display_info; 1165 1166 /* Completely disable SCDC support for older controllers */ 1167 if (hdmi->version < 0x200a) 1168 return false; 1169 1170 /* Disable if no DDC bus */ 1171 if (!hdmi->ddc) 1172 return false; 1173 1174 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ 1175 if (!display->hdmi.scdc.supported || 1176 !display->hdmi.scdc.scrambling.supported) 1177 return false; 1178 1179 /* 1180 * Disable if display only support low TMDS rates and scrambling 1181 * for low rates is not supported either 1182 */ 1183 if (!display->hdmi.scdc.scrambling.low_rates && 1184 display->max_tmds_clock <= 340000) 1185 return false; 1186 1187 return true; 1188 } 1189 1190 /* 1191 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: 1192 * - The Source shall suspend transmission of the TMDS clock and data 1193 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it 1194 * from a 0 to a 1 or from a 1 to a 0 1195 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from 1196 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming 1197 * transmission of TMDS clock and data 1198 * 1199 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() 1200 * helper should called right before enabling the TMDS Clock and Data in 1201 * the PHY configuration callback. 1202 */ 1203 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi) 1204 { 1205 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1206 1207 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 1208 if (dw_hdmi_support_scdc(hdmi)) { 1209 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1210 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1); 1211 else 1212 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0); 1213 } 1214 } 1215 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); 1216 1217 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1218 { 1219 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1220 HDMI_PHY_CONF0_PDZ_OFFSET, 1221 HDMI_PHY_CONF0_PDZ_MASK); 1222 } 1223 1224 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1225 { 1226 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1227 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1228 HDMI_PHY_CONF0_ENTMDS_MASK); 1229 } 1230 1231 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1232 { 1233 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1234 HDMI_PHY_CONF0_SVSRET_OFFSET, 1235 HDMI_PHY_CONF0_SVSRET_MASK); 1236 } 1237 1238 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1239 { 1240 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1241 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1242 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1243 } 1244 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1245 1246 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1247 { 1248 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1249 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1250 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1251 } 1252 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1253 1254 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1255 { 1256 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1257 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1258 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1259 } 1260 1261 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1262 { 1263 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1264 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1265 HDMI_PHY_CONF0_SELDIPIF_MASK); 1266 } 1267 1268 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) 1269 { 1270 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1271 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1272 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1273 } 1274 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); 1275 1276 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1277 { 1278 hdmi_phy_test_clear(hdmi, 1); 1279 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1280 hdmi_phy_test_clear(hdmi, 0); 1281 } 1282 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1283 1284 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1285 { 1286 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1287 unsigned int i; 1288 u16 val; 1289 1290 if (phy->gen == 1) { 1291 dw_hdmi_phy_enable_tmds(hdmi, 0); 1292 dw_hdmi_phy_enable_powerdown(hdmi, true); 1293 return; 1294 } 1295 1296 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1297 1298 /* 1299 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1300 * to low power mode. 1301 */ 1302 for (i = 0; i < 5; ++i) { 1303 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1304 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1305 break; 1306 1307 usleep_range(1000, 2000); 1308 } 1309 1310 if (val & HDMI_PHY_TX_PHY_LOCK) 1311 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1312 else 1313 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1314 1315 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1316 } 1317 1318 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1319 { 1320 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1321 unsigned int i; 1322 u8 val; 1323 1324 if (phy->gen == 1) { 1325 dw_hdmi_phy_enable_powerdown(hdmi, false); 1326 1327 /* Toggle TMDS enable. */ 1328 dw_hdmi_phy_enable_tmds(hdmi, 0); 1329 dw_hdmi_phy_enable_tmds(hdmi, 1); 1330 return 0; 1331 } 1332 1333 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1334 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1335 1336 /* Wait for PHY PLL lock */ 1337 for (i = 0; i < 5; ++i) { 1338 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1339 if (val) 1340 break; 1341 1342 usleep_range(1000, 2000); 1343 } 1344 1345 if (!val) { 1346 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1347 return -ETIMEDOUT; 1348 } 1349 1350 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1351 return 0; 1352 } 1353 1354 /* 1355 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1356 * information the DWC MHL PHY has the same register layout and is thus also 1357 * supported by this function. 1358 */ 1359 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1360 const struct dw_hdmi_plat_data *pdata, 1361 unsigned long mpixelclock) 1362 { 1363 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1364 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1365 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1366 1367 /* TOFIX Will need 420 specific PHY configuration tables */ 1368 1369 /* PLL/MPLL Cfg - always match on final entry */ 1370 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1371 if (mpixelclock <= mpll_config->mpixelclock) 1372 break; 1373 1374 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1375 if (mpixelclock <= curr_ctrl->mpixelclock) 1376 break; 1377 1378 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1379 if (mpixelclock <= phy_config->mpixelclock) 1380 break; 1381 1382 if (mpll_config->mpixelclock == ~0UL || 1383 curr_ctrl->mpixelclock == ~0UL || 1384 phy_config->mpixelclock == ~0UL) 1385 return -EINVAL; 1386 1387 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1388 HDMI_3D_TX_PHY_CPCE_CTRL); 1389 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1390 HDMI_3D_TX_PHY_GMPCTRL); 1391 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1392 HDMI_3D_TX_PHY_CURRCTRL); 1393 1394 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1395 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1396 HDMI_3D_TX_PHY_MSM_CTRL); 1397 1398 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1399 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1400 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1401 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1402 HDMI_3D_TX_PHY_VLEVCTRL); 1403 1404 /* Override and disable clock termination. */ 1405 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1406 HDMI_3D_TX_PHY_CKCALCTRL); 1407 1408 return 0; 1409 } 1410 1411 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 1412 { 1413 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1414 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1415 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1416 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1417 int ret; 1418 1419 dw_hdmi_phy_power_off(hdmi); 1420 1421 dw_hdmi_set_high_tmds_clock_ratio(hdmi); 1422 1423 /* Leave low power consumption mode by asserting SVSRET. */ 1424 if (phy->has_svsret) 1425 dw_hdmi_phy_enable_svsret(hdmi, 1); 1426 1427 dw_hdmi_phy_reset(hdmi); 1428 1429 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1430 1431 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1432 1433 /* Write to the PHY as configured by the platform */ 1434 if (pdata->configure_phy) 1435 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 1436 else 1437 ret = phy->configure(hdmi, pdata, mpixelclock); 1438 if (ret) { 1439 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1440 mpixelclock); 1441 return ret; 1442 } 1443 1444 /* Wait for resuming transmission of TMDS clock and data */ 1445 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1446 msleep(100); 1447 1448 return dw_hdmi_phy_power_on(hdmi); 1449 } 1450 1451 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1452 struct drm_display_mode *mode) 1453 { 1454 int i, ret; 1455 1456 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1457 for (i = 0; i < 2; i++) { 1458 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1459 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1460 1461 ret = hdmi_phy_configure(hdmi); 1462 if (ret) 1463 return ret; 1464 } 1465 1466 return 0; 1467 } 1468 1469 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1470 { 1471 dw_hdmi_phy_power_off(hdmi); 1472 } 1473 1474 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1475 void *data) 1476 { 1477 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1478 connector_status_connected : connector_status_disconnected; 1479 } 1480 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1481 1482 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1483 bool force, bool disabled, bool rxsense) 1484 { 1485 u8 old_mask = hdmi->phy_mask; 1486 1487 if (force || disabled || !rxsense) 1488 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1489 else 1490 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1491 1492 if (old_mask != hdmi->phy_mask) 1493 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1494 } 1495 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1496 1497 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1498 { 1499 /* 1500 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1501 * any pending interrupt. 1502 */ 1503 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1504 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1505 HDMI_IH_PHY_STAT0); 1506 1507 /* Enable cable hot plug irq. */ 1508 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1509 1510 /* Clear and unmute interrupts. */ 1511 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1512 HDMI_IH_PHY_STAT0); 1513 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1514 HDMI_IH_MUTE_PHY_STAT0); 1515 } 1516 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1517 1518 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1519 .init = dw_hdmi_phy_init, 1520 .disable = dw_hdmi_phy_disable, 1521 .read_hpd = dw_hdmi_phy_read_hpd, 1522 .update_hpd = dw_hdmi_phy_update_hpd, 1523 .setup_hpd = dw_hdmi_phy_setup_hpd, 1524 }; 1525 1526 /* ----------------------------------------------------------------------------- 1527 * HDMI TX Setup 1528 */ 1529 1530 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1531 { 1532 u8 de; 1533 1534 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1535 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1536 else 1537 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1538 1539 /* disable rx detect */ 1540 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1541 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1542 1543 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1544 1545 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1546 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1547 } 1548 1549 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1550 { 1551 struct hdmi_avi_infoframe frame; 1552 u8 val; 1553 1554 /* Initialise info frame from DRM mode */ 1555 drm_hdmi_avi_infoframe_from_display_mode(&frame, 1556 &hdmi->connector, mode); 1557 1558 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1559 frame.colorspace = HDMI_COLORSPACE_YUV444; 1560 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1561 frame.colorspace = HDMI_COLORSPACE_YUV422; 1562 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1563 frame.colorspace = HDMI_COLORSPACE_YUV420; 1564 else 1565 frame.colorspace = HDMI_COLORSPACE_RGB; 1566 1567 /* Set up colorimetry */ 1568 switch (hdmi->hdmi_data.enc_out_encoding) { 1569 case V4L2_YCBCR_ENC_601: 1570 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1571 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1572 else 1573 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1574 frame.extended_colorimetry = 1575 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1576 break; 1577 case V4L2_YCBCR_ENC_709: 1578 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1579 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1580 else 1581 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1582 frame.extended_colorimetry = 1583 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1584 break; 1585 default: /* Carries no data */ 1586 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1587 frame.extended_colorimetry = 1588 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1589 break; 1590 } 1591 1592 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1593 1594 /* 1595 * The Designware IP uses a different byte format from standard 1596 * AVI info frames, though generally the bits are in the correct 1597 * bytes. 1598 */ 1599 1600 /* 1601 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1602 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1603 * bit 6 rather than 4. 1604 */ 1605 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1606 if (frame.active_aspect & 15) 1607 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1608 if (frame.top_bar || frame.bottom_bar) 1609 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1610 if (frame.left_bar || frame.right_bar) 1611 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1612 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1613 1614 /* AVI data byte 2 differences: none */ 1615 val = ((frame.colorimetry & 0x3) << 6) | 1616 ((frame.picture_aspect & 0x3) << 4) | 1617 (frame.active_aspect & 0xf); 1618 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1619 1620 /* AVI data byte 3 differences: none */ 1621 val = ((frame.extended_colorimetry & 0x7) << 4) | 1622 ((frame.quantization_range & 0x3) << 2) | 1623 (frame.nups & 0x3); 1624 if (frame.itc) 1625 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1626 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1627 1628 /* AVI data byte 4 differences: none */ 1629 val = frame.video_code & 0x7f; 1630 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1631 1632 /* AVI Data Byte 5- set up input and output pixel repetition */ 1633 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1634 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1635 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1636 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1637 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1638 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1639 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1640 1641 /* 1642 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1643 * ycc range in bits 2,3 rather than 6,7 1644 */ 1645 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1646 (frame.content_type & 0x3); 1647 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1648 1649 /* AVI Data Bytes 6-13 */ 1650 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1651 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1652 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1653 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1654 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1655 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1656 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1657 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1658 } 1659 1660 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1661 struct drm_display_mode *mode) 1662 { 1663 struct hdmi_vendor_infoframe frame; 1664 u8 buffer[10]; 1665 ssize_t err; 1666 1667 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1668 &hdmi->connector, 1669 mode); 1670 if (err < 0) 1671 /* 1672 * Going into that statement does not means vendor infoframe 1673 * fails. It just informed us that vendor infoframe is not 1674 * needed for the selected mode. Only 4k or stereoscopic 3D 1675 * mode requires vendor infoframe. So just simply return. 1676 */ 1677 return; 1678 1679 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1680 if (err < 0) { 1681 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1682 err); 1683 return; 1684 } 1685 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1686 HDMI_FC_DATAUTO0_VSD_MASK); 1687 1688 /* Set the length of HDMI vendor specific InfoFrame payload */ 1689 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1690 1691 /* Set 24bit IEEE Registration Identifier */ 1692 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1693 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1694 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1695 1696 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1697 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1698 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1699 1700 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1701 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1702 1703 /* Packet frame interpolation */ 1704 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1705 1706 /* Auto packets per frame and line spacing */ 1707 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1708 1709 /* Configures the Frame Composer On RDRB mode */ 1710 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1711 HDMI_FC_DATAUTO0_VSD_MASK); 1712 } 1713 1714 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1715 const struct drm_display_mode *mode) 1716 { 1717 u8 inv_val, bytes; 1718 struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi; 1719 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1720 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1721 unsigned int vdisplay, hdisplay; 1722 1723 vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000; 1724 1725 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1726 1727 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1728 vmode->mtmdsclock /= 2; 1729 1730 /* Set up HDMI_FC_INVIDCONF */ 1731 inv_val = (hdmi->hdmi_data.hdcp_enable || 1732 (dw_hdmi_support_scdc(hdmi) && 1733 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1734 hdmi_info->scdc.scrambling.low_rates)) ? 1735 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1736 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1737 1738 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1739 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1740 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1741 1742 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1743 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1744 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1745 1746 inv_val |= (vmode->mdataenablepolarity ? 1747 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1748 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1749 1750 if (hdmi->vic == 39) 1751 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1752 else 1753 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1754 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1755 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1756 1757 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1758 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1759 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1760 1761 inv_val |= hdmi->sink_is_hdmi ? 1762 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1763 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1764 1765 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1766 1767 hdisplay = mode->hdisplay; 1768 hblank = mode->htotal - mode->hdisplay; 1769 h_de_hs = mode->hsync_start - mode->hdisplay; 1770 hsync_len = mode->hsync_end - mode->hsync_start; 1771 1772 /* 1773 * When we're setting a YCbCr420 mode, we need 1774 * to adjust the horizontal timing to suit. 1775 */ 1776 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1777 hdisplay /= 2; 1778 hblank /= 2; 1779 h_de_hs /= 2; 1780 hsync_len /= 2; 1781 } 1782 1783 vdisplay = mode->vdisplay; 1784 vblank = mode->vtotal - mode->vdisplay; 1785 v_de_vs = mode->vsync_start - mode->vdisplay; 1786 vsync_len = mode->vsync_end - mode->vsync_start; 1787 1788 /* 1789 * When we're setting an interlaced mode, we need 1790 * to adjust the vertical timing to suit. 1791 */ 1792 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1793 vdisplay /= 2; 1794 vblank /= 2; 1795 v_de_vs /= 2; 1796 vsync_len /= 2; 1797 } 1798 1799 /* Scrambling Control */ 1800 if (dw_hdmi_support_scdc(hdmi)) { 1801 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1802 hdmi_info->scdc.scrambling.low_rates) { 1803 /* 1804 * HDMI2.0 Specifies the following procedure: 1805 * After the Source Device has determined that 1806 * SCDC_Present is set (=1), the Source Device should 1807 * write the accurate Version of the Source Device 1808 * to the Source Version field in the SCDCS. 1809 * Source Devices compliant shall set the 1810 * Source Version = 1. 1811 */ 1812 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, 1813 &bytes); 1814 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, 1815 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 1816 1817 /* Enabled Scrambling in the Sink */ 1818 drm_scdc_set_scrambling(hdmi->ddc, 1); 1819 1820 /* 1821 * To activate the scrambler feature, you must ensure 1822 * that the quasi-static configuration bit 1823 * fc_invidconf.HDCP_keepout is set at configuration 1824 * time, before the required mc_swrstzreq.tmdsswrst_req 1825 * reset request is issued. 1826 */ 1827 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1828 HDMI_MC_SWRSTZ); 1829 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 1830 } else { 1831 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 1832 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1833 HDMI_MC_SWRSTZ); 1834 drm_scdc_set_scrambling(hdmi->ddc, 0); 1835 } 1836 } 1837 1838 /* Set up horizontal active pixel width */ 1839 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1840 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1841 1842 /* Set up vertical active lines */ 1843 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1844 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1845 1846 /* Set up horizontal blanking pixel region width */ 1847 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1848 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1849 1850 /* Set up vertical blanking pixel region width */ 1851 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1852 1853 /* Set up HSYNC active edge delay width (in pixel clks) */ 1854 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1855 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1856 1857 /* Set up VSYNC active edge delay (in lines) */ 1858 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1859 1860 /* Set up HSYNC active pulse width (in pixel clks) */ 1861 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1862 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1863 1864 /* Set up VSYNC active edge delay (in lines) */ 1865 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1866 } 1867 1868 /* HDMI Initialization Step B.4 */ 1869 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1870 { 1871 /* control period minimum duration */ 1872 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1873 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1874 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1875 1876 /* Set to fill TMDS data channels */ 1877 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1878 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1879 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1880 1881 /* Enable pixel clock and tmds data path */ 1882 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 1883 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 1884 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 1885 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 1886 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1887 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1888 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1889 1890 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1891 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1892 1893 /* Enable csc path */ 1894 if (is_color_space_conversion(hdmi)) { 1895 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1896 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1897 } 1898 1899 /* Enable color space conversion if needed */ 1900 if (is_color_space_conversion(hdmi)) 1901 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1902 HDMI_MC_FLOWCTRL); 1903 else 1904 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1905 HDMI_MC_FLOWCTRL); 1906 } 1907 1908 /* Workaround to clear the overflow condition */ 1909 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1910 { 1911 unsigned int count; 1912 unsigned int i; 1913 u8 val; 1914 1915 /* 1916 * Under some circumstances the Frame Composer arithmetic unit can miss 1917 * an FC register write due to being busy processing the previous one. 1918 * The issue can be worked around by issuing a TMDS software reset and 1919 * then write one of the FC registers several times. 1920 * 1921 * The number of iterations matters and depends on the HDMI TX revision 1922 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL 1923 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified 1924 * as needing the workaround, with 4 iterations for v1.30a and 1 1925 * iteration for others. 1926 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing 1927 * the workaround with a single iteration. 1928 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have 1929 * been identified as needing the workaround with a single iteration. 1930 */ 1931 1932 switch (hdmi->version) { 1933 case 0x130a: 1934 count = 4; 1935 break; 1936 case 0x131a: 1937 case 0x132a: 1938 case 0x200a: 1939 case 0x201a: 1940 case 0x211a: 1941 case 0x212a: 1942 count = 1; 1943 break; 1944 default: 1945 return; 1946 } 1947 1948 /* TMDS software reset */ 1949 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 1950 1951 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 1952 for (i = 0; i < count; i++) 1953 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 1954 } 1955 1956 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 1957 { 1958 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 1959 HDMI_IH_MUTE_FC_STAT2); 1960 } 1961 1962 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1963 { 1964 int ret; 1965 1966 hdmi_disable_overflow_interrupts(hdmi); 1967 1968 hdmi->vic = drm_match_cea_mode(mode); 1969 1970 if (!hdmi->vic) { 1971 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 1972 } else { 1973 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 1974 } 1975 1976 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 1977 (hdmi->vic == 21) || (hdmi->vic == 22) || 1978 (hdmi->vic == 2) || (hdmi->vic == 3) || 1979 (hdmi->vic == 17) || (hdmi->vic == 18)) 1980 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 1981 else 1982 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 1983 1984 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 1985 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 1986 1987 /* TOFIX: Get input format from plat data or fallback to RGB888 */ 1988 if (hdmi->plat_data->input_bus_format) 1989 hdmi->hdmi_data.enc_in_bus_format = 1990 hdmi->plat_data->input_bus_format; 1991 else 1992 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 1993 1994 /* TOFIX: Get input encoding from plat data or fallback to none */ 1995 if (hdmi->plat_data->input_bus_encoding) 1996 hdmi->hdmi_data.enc_in_encoding = 1997 hdmi->plat_data->input_bus_encoding; 1998 else 1999 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2000 2001 /* TOFIX: Default to RGB888 output format */ 2002 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2003 2004 hdmi->hdmi_data.pix_repet_factor = 0; 2005 hdmi->hdmi_data.hdcp_enable = 0; 2006 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2007 2008 /* HDMI Initialization Step B.1 */ 2009 hdmi_av_composer(hdmi, mode); 2010 2011 /* HDMI Initializateion Step B.2 */ 2012 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); 2013 if (ret) 2014 return ret; 2015 hdmi->phy.enabled = true; 2016 2017 /* HDMI Initialization Step B.3 */ 2018 dw_hdmi_enable_video_path(hdmi); 2019 2020 if (hdmi->sink_has_audio) { 2021 dev_dbg(hdmi->dev, "sink has audio support\n"); 2022 2023 /* HDMI Initialization Step E - Configure audio */ 2024 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2025 hdmi_enable_audio_clk(hdmi, true); 2026 } 2027 2028 /* not for DVI mode */ 2029 if (hdmi->sink_is_hdmi) { 2030 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 2031 2032 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2033 hdmi_config_AVI(hdmi, mode); 2034 hdmi_config_vendor_specific_infoframe(hdmi, mode); 2035 } else { 2036 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 2037 } 2038 2039 hdmi_video_packetize(hdmi); 2040 hdmi_video_csc(hdmi); 2041 hdmi_video_sample(hdmi); 2042 hdmi_tx_hdcp_config(hdmi); 2043 2044 dw_hdmi_clear_overflow(hdmi); 2045 2046 return 0; 2047 } 2048 2049 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 2050 { 2051 u8 ih_mute; 2052 2053 /* 2054 * Boot up defaults are: 2055 * HDMI_IH_MUTE = 0x03 (disabled) 2056 * HDMI_IH_MUTE_* = 0x00 (enabled) 2057 * 2058 * Disable top level interrupt bits in HDMI block 2059 */ 2060 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 2061 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2062 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 2063 2064 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2065 2066 /* by default mask all interrupts */ 2067 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 2068 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2069 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2070 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2071 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 2072 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 2073 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 2074 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 2075 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 2076 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 2077 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 2078 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 2079 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 2080 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 2081 2082 /* Disable interrupts in the IH_MUTE_* registers */ 2083 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2084 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2085 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2086 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2087 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 2088 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2089 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2090 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2091 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2092 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2093 2094 /* Enable top level interrupt bits in HDMI block */ 2095 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2096 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 2097 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2098 } 2099 2100 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 2101 { 2102 hdmi->bridge_is_on = true; 2103 dw_hdmi_setup(hdmi, &hdmi->previous_mode); 2104 } 2105 2106 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 2107 { 2108 if (hdmi->phy.enabled) { 2109 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 2110 hdmi->phy.enabled = false; 2111 } 2112 2113 hdmi->bridge_is_on = false; 2114 } 2115 2116 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 2117 { 2118 int force = hdmi->force; 2119 2120 if (hdmi->disabled) { 2121 force = DRM_FORCE_OFF; 2122 } else if (force == DRM_FORCE_UNSPECIFIED) { 2123 if (hdmi->rxsense) 2124 force = DRM_FORCE_ON; 2125 else 2126 force = DRM_FORCE_OFF; 2127 } 2128 2129 if (force == DRM_FORCE_OFF) { 2130 if (hdmi->bridge_is_on) 2131 dw_hdmi_poweroff(hdmi); 2132 } else { 2133 if (!hdmi->bridge_is_on) 2134 dw_hdmi_poweron(hdmi); 2135 } 2136 } 2137 2138 /* 2139 * Adjust the detection of RXSENSE according to whether we have a forced 2140 * connection mode enabled, or whether we have been disabled. There is 2141 * no point processing RXSENSE interrupts if we have a forced connection 2142 * state, or DRM has us disabled. 2143 * 2144 * We also disable rxsense interrupts when we think we're disconnected 2145 * to avoid floating TDMS signals giving false rxsense interrupts. 2146 * 2147 * Note: we still need to listen for HPD interrupts even when DRM has us 2148 * disabled so that we can detect a connect event. 2149 */ 2150 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 2151 { 2152 if (hdmi->phy.ops->update_hpd) 2153 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 2154 hdmi->force, hdmi->disabled, 2155 hdmi->rxsense); 2156 } 2157 2158 static enum drm_connector_status 2159 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 2160 { 2161 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2162 connector); 2163 2164 mutex_lock(&hdmi->mutex); 2165 hdmi->force = DRM_FORCE_UNSPECIFIED; 2166 dw_hdmi_update_power(hdmi); 2167 dw_hdmi_update_phy_mask(hdmi); 2168 mutex_unlock(&hdmi->mutex); 2169 2170 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 2171 } 2172 2173 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 2174 { 2175 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2176 connector); 2177 struct edid *edid; 2178 int ret = 0; 2179 2180 if (!hdmi->ddc) 2181 return 0; 2182 2183 edid = drm_get_edid(connector, hdmi->ddc); 2184 if (edid) { 2185 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 2186 edid->width_cm, edid->height_cm); 2187 2188 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 2189 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2190 drm_connector_update_edid_property(connector, edid); 2191 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); 2192 ret = drm_add_edid_modes(connector, edid); 2193 kfree(edid); 2194 } else { 2195 dev_dbg(hdmi->dev, "failed to get edid\n"); 2196 } 2197 2198 return ret; 2199 } 2200 2201 static void dw_hdmi_connector_force(struct drm_connector *connector) 2202 { 2203 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2204 connector); 2205 2206 mutex_lock(&hdmi->mutex); 2207 hdmi->force = connector->force; 2208 dw_hdmi_update_power(hdmi); 2209 dw_hdmi_update_phy_mask(hdmi); 2210 mutex_unlock(&hdmi->mutex); 2211 } 2212 2213 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 2214 .fill_modes = drm_helper_probe_single_connector_modes, 2215 .detect = dw_hdmi_connector_detect, 2216 .destroy = drm_connector_cleanup, 2217 .force = dw_hdmi_connector_force, 2218 .reset = drm_atomic_helper_connector_reset, 2219 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2220 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2221 }; 2222 2223 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 2224 .get_modes = dw_hdmi_connector_get_modes, 2225 }; 2226 2227 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) 2228 { 2229 struct dw_hdmi *hdmi = bridge->driver_private; 2230 struct drm_encoder *encoder = bridge->encoder; 2231 struct drm_connector *connector = &hdmi->connector; 2232 2233 connector->interlace_allowed = 1; 2234 connector->polled = DRM_CONNECTOR_POLL_HPD; 2235 2236 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 2237 2238 drm_connector_init_with_ddc(bridge->dev, connector, 2239 &dw_hdmi_connector_funcs, 2240 DRM_MODE_CONNECTOR_HDMIA, 2241 hdmi->ddc); 2242 2243 drm_connector_attach_encoder(connector, encoder); 2244 2245 return 0; 2246 } 2247 2248 static enum drm_mode_status 2249 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 2250 const struct drm_display_mode *mode) 2251 { 2252 struct dw_hdmi *hdmi = bridge->driver_private; 2253 struct drm_connector *connector = &hdmi->connector; 2254 enum drm_mode_status mode_status = MODE_OK; 2255 2256 /* We don't support double-clocked modes */ 2257 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2258 return MODE_BAD; 2259 2260 if (hdmi->plat_data->mode_valid) 2261 mode_status = hdmi->plat_data->mode_valid(connector, mode); 2262 2263 return mode_status; 2264 } 2265 2266 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2267 const struct drm_display_mode *orig_mode, 2268 const struct drm_display_mode *mode) 2269 { 2270 struct dw_hdmi *hdmi = bridge->driver_private; 2271 2272 mutex_lock(&hdmi->mutex); 2273 2274 /* Store the display mode for plugin/DKMS poweron events */ 2275 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2276 2277 mutex_unlock(&hdmi->mutex); 2278 } 2279 2280 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) 2281 { 2282 struct dw_hdmi *hdmi = bridge->driver_private; 2283 2284 mutex_lock(&hdmi->mutex); 2285 hdmi->disabled = true; 2286 dw_hdmi_update_power(hdmi); 2287 dw_hdmi_update_phy_mask(hdmi); 2288 mutex_unlock(&hdmi->mutex); 2289 } 2290 2291 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) 2292 { 2293 struct dw_hdmi *hdmi = bridge->driver_private; 2294 2295 mutex_lock(&hdmi->mutex); 2296 hdmi->disabled = false; 2297 dw_hdmi_update_power(hdmi); 2298 dw_hdmi_update_phy_mask(hdmi); 2299 mutex_unlock(&hdmi->mutex); 2300 } 2301 2302 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 2303 .attach = dw_hdmi_bridge_attach, 2304 .enable = dw_hdmi_bridge_enable, 2305 .disable = dw_hdmi_bridge_disable, 2306 .mode_set = dw_hdmi_bridge_mode_set, 2307 .mode_valid = dw_hdmi_bridge_mode_valid, 2308 }; 2309 2310 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 2311 { 2312 struct dw_hdmi_i2c *i2c = hdmi->i2c; 2313 unsigned int stat; 2314 2315 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 2316 if (!stat) 2317 return IRQ_NONE; 2318 2319 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 2320 2321 i2c->stat = stat; 2322 2323 complete(&i2c->cmp); 2324 2325 return IRQ_HANDLED; 2326 } 2327 2328 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 2329 { 2330 struct dw_hdmi *hdmi = dev_id; 2331 u8 intr_stat; 2332 irqreturn_t ret = IRQ_NONE; 2333 2334 if (hdmi->i2c) 2335 ret = dw_hdmi_i2c_irq(hdmi); 2336 2337 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2338 if (intr_stat) { 2339 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2340 return IRQ_WAKE_THREAD; 2341 } 2342 2343 return ret; 2344 } 2345 2346 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 2347 { 2348 mutex_lock(&hdmi->mutex); 2349 2350 if (!hdmi->force) { 2351 /* 2352 * If the RX sense status indicates we're disconnected, 2353 * clear the software rxsense status. 2354 */ 2355 if (!rx_sense) 2356 hdmi->rxsense = false; 2357 2358 /* 2359 * Only set the software rxsense status when both 2360 * rxsense and hpd indicates we're connected. 2361 * This avoids what seems to be bad behaviour in 2362 * at least iMX6S versions of the phy. 2363 */ 2364 if (hpd) 2365 hdmi->rxsense = true; 2366 2367 dw_hdmi_update_power(hdmi); 2368 dw_hdmi_update_phy_mask(hdmi); 2369 } 2370 mutex_unlock(&hdmi->mutex); 2371 } 2372 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 2373 2374 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 2375 { 2376 struct dw_hdmi *hdmi = dev_id; 2377 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 2378 2379 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2380 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 2381 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 2382 2383 phy_pol_mask = 0; 2384 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 2385 phy_pol_mask |= HDMI_PHY_HPD; 2386 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 2387 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 2388 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 2389 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 2390 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 2391 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 2392 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 2393 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 2394 2395 if (phy_pol_mask) 2396 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 2397 2398 /* 2399 * RX sense tells us whether the TDMS transmitters are detecting 2400 * load - in other words, there's something listening on the 2401 * other end of the link. Use this to decide whether we should 2402 * power on the phy as HPD may be toggled by the sink to merely 2403 * ask the source to re-read the EDID. 2404 */ 2405 if (intr_stat & 2406 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 2407 dw_hdmi_setup_rx_sense(hdmi, 2408 phy_stat & HDMI_PHY_HPD, 2409 phy_stat & HDMI_PHY_RX_SENSE); 2410 2411 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) 2412 cec_notifier_set_phys_addr(hdmi->cec_notifier, 2413 CEC_PHYS_ADDR_INVALID); 2414 } 2415 2416 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { 2417 dev_dbg(hdmi->dev, "EVENT=%s\n", 2418 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); 2419 if (hdmi->bridge.dev) 2420 drm_helper_hpd_irq_event(hdmi->bridge.dev); 2421 } 2422 2423 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 2424 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 2425 HDMI_IH_MUTE_PHY_STAT0); 2426 2427 return IRQ_HANDLED; 2428 } 2429 2430 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 2431 { 2432 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 2433 .name = "DWC HDMI TX PHY", 2434 .gen = 1, 2435 }, { 2436 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 2437 .name = "DWC MHL PHY + HEAC PHY", 2438 .gen = 2, 2439 .has_svsret = true, 2440 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2441 }, { 2442 .type = DW_HDMI_PHY_DWC_MHL_PHY, 2443 .name = "DWC MHL PHY", 2444 .gen = 2, 2445 .has_svsret = true, 2446 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2447 }, { 2448 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 2449 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 2450 .gen = 2, 2451 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2452 }, { 2453 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 2454 .name = "DWC HDMI 3D TX PHY", 2455 .gen = 2, 2456 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2457 }, { 2458 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 2459 .name = "DWC HDMI 2.0 TX PHY", 2460 .gen = 2, 2461 .has_svsret = true, 2462 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2463 }, { 2464 .type = DW_HDMI_PHY_VENDOR_PHY, 2465 .name = "Vendor PHY", 2466 } 2467 }; 2468 2469 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 2470 { 2471 unsigned int i; 2472 u8 phy_type; 2473 2474 phy_type = hdmi->plat_data->phy_force_vendor ? 2475 DW_HDMI_PHY_VENDOR_PHY : 2476 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 2477 2478 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 2479 /* Vendor PHYs require support from the glue layer. */ 2480 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 2481 dev_err(hdmi->dev, 2482 "Vendor HDMI PHY not supported by glue layer\n"); 2483 return -ENODEV; 2484 } 2485 2486 hdmi->phy.ops = hdmi->plat_data->phy_ops; 2487 hdmi->phy.data = hdmi->plat_data->phy_data; 2488 hdmi->phy.name = hdmi->plat_data->phy_name; 2489 return 0; 2490 } 2491 2492 /* Synopsys PHYs are handled internally. */ 2493 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 2494 if (dw_hdmi_phys[i].type == phy_type) { 2495 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 2496 hdmi->phy.name = dw_hdmi_phys[i].name; 2497 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 2498 2499 if (!dw_hdmi_phys[i].configure && 2500 !hdmi->plat_data->configure_phy) { 2501 dev_err(hdmi->dev, "%s requires platform support\n", 2502 hdmi->phy.name); 2503 return -ENODEV; 2504 } 2505 2506 return 0; 2507 } 2508 } 2509 2510 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 2511 return -ENODEV; 2512 } 2513 2514 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 2515 { 2516 mutex_lock(&hdmi->mutex); 2517 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 2518 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2519 mutex_unlock(&hdmi->mutex); 2520 } 2521 2522 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 2523 { 2524 mutex_lock(&hdmi->mutex); 2525 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 2526 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2527 mutex_unlock(&hdmi->mutex); 2528 } 2529 2530 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 2531 .write = hdmi_writeb, 2532 .read = hdmi_readb, 2533 .enable = dw_hdmi_cec_enable, 2534 .disable = dw_hdmi_cec_disable, 2535 }; 2536 2537 static const struct regmap_config hdmi_regmap_8bit_config = { 2538 .reg_bits = 32, 2539 .val_bits = 8, 2540 .reg_stride = 1, 2541 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 2542 }; 2543 2544 static const struct regmap_config hdmi_regmap_32bit_config = { 2545 .reg_bits = 32, 2546 .val_bits = 32, 2547 .reg_stride = 4, 2548 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 2549 }; 2550 2551 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi) 2552 { 2553 initialize_hdmi_ih_mutes(hdmi); 2554 2555 /* 2556 * Reset HDMI DDC I2C master controller and mute I2CM interrupts. 2557 * Even if we are using a separate i2c adapter doing this doesn't 2558 * hurt. 2559 */ 2560 dw_hdmi_i2c_init(hdmi); 2561 2562 if (hdmi->phy.ops->setup_hpd) 2563 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 2564 } 2565 2566 static struct dw_hdmi * 2567 __dw_hdmi_probe(struct platform_device *pdev, 2568 const struct dw_hdmi_plat_data *plat_data) 2569 { 2570 struct device *dev = &pdev->dev; 2571 struct device_node *np = dev->of_node; 2572 struct platform_device_info pdevinfo; 2573 struct device_node *ddc_node; 2574 struct dw_hdmi_cec_data cec; 2575 struct dw_hdmi *hdmi; 2576 struct resource *iores = NULL; 2577 int irq; 2578 int ret; 2579 u32 val = 1; 2580 u8 prod_id0; 2581 u8 prod_id1; 2582 u8 config0; 2583 u8 config3; 2584 2585 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 2586 if (!hdmi) 2587 return ERR_PTR(-ENOMEM); 2588 2589 hdmi->plat_data = plat_data; 2590 hdmi->dev = dev; 2591 hdmi->sample_rate = 48000; 2592 hdmi->disabled = true; 2593 hdmi->rxsense = true; 2594 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 2595 hdmi->mc_clkdis = 0x7f; 2596 2597 mutex_init(&hdmi->mutex); 2598 mutex_init(&hdmi->audio_mutex); 2599 spin_lock_init(&hdmi->audio_lock); 2600 2601 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 2602 if (ddc_node) { 2603 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 2604 of_node_put(ddc_node); 2605 if (!hdmi->ddc) { 2606 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 2607 return ERR_PTR(-EPROBE_DEFER); 2608 } 2609 2610 } else { 2611 dev_dbg(hdmi->dev, "no ddc property found\n"); 2612 } 2613 2614 if (!plat_data->regm) { 2615 const struct regmap_config *reg_config; 2616 2617 of_property_read_u32(np, "reg-io-width", &val); 2618 switch (val) { 2619 case 4: 2620 reg_config = &hdmi_regmap_32bit_config; 2621 hdmi->reg_shift = 2; 2622 break; 2623 case 1: 2624 reg_config = &hdmi_regmap_8bit_config; 2625 break; 2626 default: 2627 dev_err(dev, "reg-io-width must be 1 or 4\n"); 2628 return ERR_PTR(-EINVAL); 2629 } 2630 2631 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2632 hdmi->regs = devm_ioremap_resource(dev, iores); 2633 if (IS_ERR(hdmi->regs)) { 2634 ret = PTR_ERR(hdmi->regs); 2635 goto err_res; 2636 } 2637 2638 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 2639 if (IS_ERR(hdmi->regm)) { 2640 dev_err(dev, "Failed to configure regmap\n"); 2641 ret = PTR_ERR(hdmi->regm); 2642 goto err_res; 2643 } 2644 } else { 2645 hdmi->regm = plat_data->regm; 2646 } 2647 2648 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 2649 if (IS_ERR(hdmi->isfr_clk)) { 2650 ret = PTR_ERR(hdmi->isfr_clk); 2651 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 2652 goto err_res; 2653 } 2654 2655 ret = clk_prepare_enable(hdmi->isfr_clk); 2656 if (ret) { 2657 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 2658 goto err_res; 2659 } 2660 2661 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 2662 if (IS_ERR(hdmi->iahb_clk)) { 2663 ret = PTR_ERR(hdmi->iahb_clk); 2664 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 2665 goto err_isfr; 2666 } 2667 2668 ret = clk_prepare_enable(hdmi->iahb_clk); 2669 if (ret) { 2670 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 2671 goto err_isfr; 2672 } 2673 2674 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec"); 2675 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) { 2676 hdmi->cec_clk = NULL; 2677 } else if (IS_ERR(hdmi->cec_clk)) { 2678 ret = PTR_ERR(hdmi->cec_clk); 2679 if (ret != -EPROBE_DEFER) 2680 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 2681 ret); 2682 2683 hdmi->cec_clk = NULL; 2684 goto err_iahb; 2685 } else { 2686 ret = clk_prepare_enable(hdmi->cec_clk); 2687 if (ret) { 2688 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", 2689 ret); 2690 goto err_iahb; 2691 } 2692 } 2693 2694 /* Product and revision IDs */ 2695 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2696 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2697 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 2698 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 2699 2700 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 2701 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 2702 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 2703 hdmi->version, prod_id0, prod_id1); 2704 ret = -ENODEV; 2705 goto err_iahb; 2706 } 2707 2708 ret = dw_hdmi_detect_phy(hdmi); 2709 if (ret < 0) 2710 goto err_iahb; 2711 2712 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 2713 hdmi->version >> 12, hdmi->version & 0xfff, 2714 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 2715 hdmi->phy.name); 2716 2717 dw_hdmi_init_hw(hdmi); 2718 2719 irq = platform_get_irq(pdev, 0); 2720 if (irq < 0) { 2721 ret = irq; 2722 goto err_iahb; 2723 } 2724 2725 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 2726 dw_hdmi_irq, IRQF_SHARED, 2727 dev_name(dev), hdmi); 2728 if (ret) 2729 goto err_iahb; 2730 2731 hdmi->cec_notifier = cec_notifier_get(dev); 2732 if (!hdmi->cec_notifier) { 2733 ret = -ENOMEM; 2734 goto err_iahb; 2735 } 2736 2737 /* 2738 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 2739 * N and cts values before enabling phy 2740 */ 2741 hdmi_init_clk_regenerator(hdmi); 2742 2743 /* If DDC bus is not specified, try to register HDMI I2C bus */ 2744 if (!hdmi->ddc) { 2745 /* Look for (optional) stuff related to unwedging */ 2746 hdmi->pinctrl = devm_pinctrl_get(dev); 2747 if (!IS_ERR(hdmi->pinctrl)) { 2748 hdmi->unwedge_state = 2749 pinctrl_lookup_state(hdmi->pinctrl, "unwedge"); 2750 hdmi->default_state = 2751 pinctrl_lookup_state(hdmi->pinctrl, "default"); 2752 2753 if (IS_ERR(hdmi->default_state) || 2754 IS_ERR(hdmi->unwedge_state)) { 2755 if (!IS_ERR(hdmi->unwedge_state)) 2756 dev_warn(dev, 2757 "Unwedge requires default pinctrl\n"); 2758 hdmi->default_state = NULL; 2759 hdmi->unwedge_state = NULL; 2760 } 2761 } 2762 2763 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 2764 if (IS_ERR(hdmi->ddc)) 2765 hdmi->ddc = NULL; 2766 } 2767 2768 hdmi->bridge.driver_private = hdmi; 2769 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 2770 #ifdef CONFIG_OF 2771 hdmi->bridge.of_node = pdev->dev.of_node; 2772 #endif 2773 2774 memset(&pdevinfo, 0, sizeof(pdevinfo)); 2775 pdevinfo.parent = dev; 2776 pdevinfo.id = PLATFORM_DEVID_AUTO; 2777 2778 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 2779 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 2780 2781 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 2782 struct dw_hdmi_audio_data audio; 2783 2784 audio.phys = iores->start; 2785 audio.base = hdmi->regs; 2786 audio.irq = irq; 2787 audio.hdmi = hdmi; 2788 audio.eld = hdmi->connector.eld; 2789 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 2790 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 2791 2792 pdevinfo.name = "dw-hdmi-ahb-audio"; 2793 pdevinfo.data = &audio; 2794 pdevinfo.size_data = sizeof(audio); 2795 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2796 hdmi->audio = platform_device_register_full(&pdevinfo); 2797 } else if (config0 & HDMI_CONFIG0_I2S) { 2798 struct dw_hdmi_i2s_audio_data audio; 2799 2800 audio.hdmi = hdmi; 2801 audio.eld = hdmi->connector.eld; 2802 audio.write = hdmi_writeb; 2803 audio.read = hdmi_readb; 2804 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 2805 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 2806 2807 pdevinfo.name = "dw-hdmi-i2s-audio"; 2808 pdevinfo.data = &audio; 2809 pdevinfo.size_data = sizeof(audio); 2810 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2811 hdmi->audio = platform_device_register_full(&pdevinfo); 2812 } 2813 2814 if (config0 & HDMI_CONFIG0_CEC) { 2815 cec.hdmi = hdmi; 2816 cec.ops = &dw_hdmi_cec_ops; 2817 cec.irq = irq; 2818 2819 pdevinfo.name = "dw-hdmi-cec"; 2820 pdevinfo.data = &cec; 2821 pdevinfo.size_data = sizeof(cec); 2822 pdevinfo.dma_mask = 0; 2823 2824 hdmi->cec = platform_device_register_full(&pdevinfo); 2825 } 2826 2827 return hdmi; 2828 2829 err_iahb: 2830 if (hdmi->i2c) { 2831 i2c_del_adapter(&hdmi->i2c->adap); 2832 hdmi->ddc = NULL; 2833 } 2834 2835 if (hdmi->cec_notifier) 2836 cec_notifier_put(hdmi->cec_notifier); 2837 2838 clk_disable_unprepare(hdmi->iahb_clk); 2839 if (hdmi->cec_clk) 2840 clk_disable_unprepare(hdmi->cec_clk); 2841 err_isfr: 2842 clk_disable_unprepare(hdmi->isfr_clk); 2843 err_res: 2844 i2c_put_adapter(hdmi->ddc); 2845 2846 return ERR_PTR(ret); 2847 } 2848 2849 static void __dw_hdmi_remove(struct dw_hdmi *hdmi) 2850 { 2851 if (hdmi->audio && !IS_ERR(hdmi->audio)) 2852 platform_device_unregister(hdmi->audio); 2853 if (!IS_ERR(hdmi->cec)) 2854 platform_device_unregister(hdmi->cec); 2855 2856 /* Disable all interrupts */ 2857 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2858 2859 if (hdmi->cec_notifier) 2860 cec_notifier_put(hdmi->cec_notifier); 2861 2862 clk_disable_unprepare(hdmi->iahb_clk); 2863 clk_disable_unprepare(hdmi->isfr_clk); 2864 if (hdmi->cec_clk) 2865 clk_disable_unprepare(hdmi->cec_clk); 2866 2867 if (hdmi->i2c) 2868 i2c_del_adapter(&hdmi->i2c->adap); 2869 else 2870 i2c_put_adapter(hdmi->ddc); 2871 } 2872 2873 /* ----------------------------------------------------------------------------- 2874 * Probe/remove API, used from platforms based on the DRM bridge API. 2875 */ 2876 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 2877 const struct dw_hdmi_plat_data *plat_data) 2878 { 2879 struct dw_hdmi *hdmi; 2880 2881 hdmi = __dw_hdmi_probe(pdev, plat_data); 2882 if (IS_ERR(hdmi)) 2883 return hdmi; 2884 2885 drm_bridge_add(&hdmi->bridge); 2886 2887 return hdmi; 2888 } 2889 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 2890 2891 void dw_hdmi_remove(struct dw_hdmi *hdmi) 2892 { 2893 drm_bridge_remove(&hdmi->bridge); 2894 2895 __dw_hdmi_remove(hdmi); 2896 } 2897 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 2898 2899 /* ----------------------------------------------------------------------------- 2900 * Bind/unbind API, used from platforms based on the component framework. 2901 */ 2902 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 2903 struct drm_encoder *encoder, 2904 const struct dw_hdmi_plat_data *plat_data) 2905 { 2906 struct dw_hdmi *hdmi; 2907 int ret; 2908 2909 hdmi = __dw_hdmi_probe(pdev, plat_data); 2910 if (IS_ERR(hdmi)) 2911 return hdmi; 2912 2913 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL); 2914 if (ret) { 2915 dw_hdmi_remove(hdmi); 2916 DRM_ERROR("Failed to initialize bridge with drm\n"); 2917 return ERR_PTR(ret); 2918 } 2919 2920 return hdmi; 2921 } 2922 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 2923 2924 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 2925 { 2926 __dw_hdmi_remove(hdmi); 2927 } 2928 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 2929 2930 void dw_hdmi_resume(struct dw_hdmi *hdmi) 2931 { 2932 dw_hdmi_init_hw(hdmi); 2933 } 2934 EXPORT_SYMBOL_GPL(dw_hdmi_resume); 2935 2936 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 2937 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 2938 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 2939 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 2940 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 2941 MODULE_LICENSE("GPL"); 2942 MODULE_ALIAS("platform:dw-hdmi"); 2943