1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver 4 * 5 * Copyright (C) 2013-2015 Mentor Graphics Inc. 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/export.h> 13 #include <linux/hdmi.h> 14 #include <linux/i2c.h> 15 #include <linux/irq.h> 16 #include <linux/module.h> 17 #include <linux/mutex.h> 18 #include <linux/of.h> 19 #include <linux/pinctrl/consumer.h> 20 #include <linux/regmap.h> 21 #include <linux/dma-mapping.h> 22 #include <linux/spinlock.h> 23 24 #include <media/cec-notifier.h> 25 26 #include <linux/media-bus-format.h> 27 #include <linux/videodev2.h> 28 29 #include <drm/bridge/dw_hdmi.h> 30 #include <drm/display/drm_hdmi_helper.h> 31 #include <drm/display/drm_scdc_helper.h> 32 #include <drm/drm_atomic.h> 33 #include <drm/drm_atomic_helper.h> 34 #include <drm/drm_bridge.h> 35 #include <drm/drm_edid.h> 36 #include <drm/drm_of.h> 37 #include <drm/drm_print.h> 38 #include <drm/drm_probe_helper.h> 39 40 #include "dw-hdmi-audio.h" 41 #include "dw-hdmi-cec.h" 42 #include "dw-hdmi.h" 43 44 #define DDC_CI_ADDR 0x37 45 #define DDC_SEGMENT_ADDR 0x30 46 47 #define HDMI_EDID_LEN 512 48 49 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 50 #define SCDC_MIN_SOURCE_VERSION 0x1 51 52 #define HDMI14_MAX_TMDSCLK 340000000 53 54 static const u16 csc_coeff_default[3][4] = { 55 { 0x2000, 0x0000, 0x0000, 0x0000 }, 56 { 0x0000, 0x2000, 0x0000, 0x0000 }, 57 { 0x0000, 0x0000, 0x2000, 0x0000 } 58 }; 59 60 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 61 { 0x2000, 0x6926, 0x74fd, 0x010e }, 62 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 63 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 64 }; 65 66 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 67 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 68 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 69 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 70 }; 71 72 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 73 { 0x2591, 0x1322, 0x074b, 0x0000 }, 74 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 75 { 0x6acd, 0x7534, 0x2000, 0x0200 } 76 }; 77 78 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 79 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 80 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 81 { 0x6756, 0x78ab, 0x2000, 0x0200 } 82 }; 83 84 static const u16 csc_coeff_rgb_full_to_rgb_limited[3][4] = { 85 { 0x1b7c, 0x0000, 0x0000, 0x0020 }, 86 { 0x0000, 0x1b7c, 0x0000, 0x0020 }, 87 { 0x0000, 0x0000, 0x1b7c, 0x0020 } 88 }; 89 90 struct hdmi_vmode { 91 bool mdataenablepolarity; 92 93 unsigned int mpixelclock; 94 unsigned int mpixelrepetitioninput; 95 unsigned int mpixelrepetitionoutput; 96 unsigned int mtmdsclock; 97 }; 98 99 struct hdmi_data_info { 100 unsigned int enc_in_bus_format; 101 unsigned int enc_out_bus_format; 102 unsigned int enc_in_encoding; 103 unsigned int enc_out_encoding; 104 unsigned int pix_repet_factor; 105 unsigned int hdcp_enable; 106 struct hdmi_vmode video_mode; 107 bool rgb_limited_range; 108 }; 109 110 struct dw_hdmi_i2c { 111 struct i2c_adapter adap; 112 113 struct mutex lock; /* used to serialize data transfers */ 114 struct completion cmp; 115 u8 stat; 116 117 u8 slave_reg; 118 bool is_regaddr; 119 bool is_segment; 120 }; 121 122 struct dw_hdmi_phy_data { 123 enum dw_hdmi_phy_type type; 124 const char *name; 125 unsigned int gen; 126 bool has_svsret; 127 int (*configure)(struct dw_hdmi *hdmi, 128 const struct dw_hdmi_plat_data *pdata, 129 unsigned long mpixelclock); 130 }; 131 132 struct dw_hdmi { 133 struct drm_connector connector; 134 struct drm_bridge bridge; 135 struct drm_bridge *next_bridge; 136 137 unsigned int version; 138 139 struct platform_device *audio; 140 struct platform_device *cec; 141 struct device *dev; 142 struct dw_hdmi_i2c *i2c; 143 144 struct hdmi_data_info hdmi_data; 145 const struct dw_hdmi_plat_data *plat_data; 146 147 int vic; 148 149 u8 edid[HDMI_EDID_LEN]; 150 151 struct { 152 const struct dw_hdmi_phy_ops *ops; 153 const char *name; 154 void *data; 155 bool enabled; 156 } phy; 157 158 struct drm_display_mode previous_mode; 159 160 struct i2c_adapter *ddc; 161 void __iomem *regs; 162 bool sink_is_hdmi; 163 bool sink_has_audio; 164 165 struct pinctrl *pinctrl; 166 struct pinctrl_state *default_state; 167 struct pinctrl_state *unwedge_state; 168 169 struct mutex mutex; /* for state below and previous_mode */ 170 enum drm_connector_force force; /* mutex-protected force state */ 171 struct drm_connector *curr_conn;/* current connector (only valid when !disabled) */ 172 bool disabled; /* DRM has disabled our bridge */ 173 bool bridge_is_on; /* indicates the bridge is on */ 174 bool rxsense; /* rxsense state */ 175 u8 phy_mask; /* desired phy int mask settings */ 176 u8 mc_clkdis; /* clock disable register */ 177 178 spinlock_t audio_lock; 179 struct mutex audio_mutex; 180 unsigned int sample_non_pcm; 181 unsigned int sample_width; 182 unsigned int sample_rate; 183 unsigned int channels; 184 unsigned int audio_cts; 185 unsigned int audio_n; 186 bool audio_enable; 187 188 unsigned int reg_shift; 189 struct regmap *regm; 190 void (*enable_audio)(struct dw_hdmi *hdmi); 191 void (*disable_audio)(struct dw_hdmi *hdmi); 192 193 struct mutex cec_notifier_mutex; 194 struct cec_notifier *cec_notifier; 195 196 hdmi_codec_plugged_cb plugged_cb; 197 struct device *codec_dev; 198 enum drm_connector_status last_connector_result; 199 }; 200 201 const struct dw_hdmi_plat_data *dw_hdmi_to_plat_data(struct dw_hdmi *hdmi) 202 { 203 return hdmi->plat_data; 204 } 205 EXPORT_SYMBOL_GPL(dw_hdmi_to_plat_data); 206 207 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 208 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 209 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 210 211 #define HDMI_PHY_RX_SENSE \ 212 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 213 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 214 215 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 216 { 217 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 218 } 219 220 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 221 { 222 unsigned int val = 0; 223 224 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 225 226 return val; 227 } 228 229 static void handle_plugged_change(struct dw_hdmi *hdmi, bool plugged) 230 { 231 if (hdmi->plugged_cb && hdmi->codec_dev) 232 hdmi->plugged_cb(hdmi->codec_dev, plugged); 233 } 234 235 int dw_hdmi_set_plugged_cb(struct dw_hdmi *hdmi, hdmi_codec_plugged_cb fn, 236 struct device *codec_dev) 237 { 238 bool plugged; 239 240 mutex_lock(&hdmi->mutex); 241 hdmi->plugged_cb = fn; 242 hdmi->codec_dev = codec_dev; 243 plugged = hdmi->last_connector_result == connector_status_connected; 244 handle_plugged_change(hdmi, plugged); 245 mutex_unlock(&hdmi->mutex); 246 247 return 0; 248 } 249 EXPORT_SYMBOL_GPL(dw_hdmi_set_plugged_cb); 250 251 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 252 { 253 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 254 } 255 256 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 257 u8 shift, u8 mask) 258 { 259 hdmi_modb(hdmi, data << shift, mask, reg); 260 } 261 262 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 263 { 264 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 265 HDMI_PHY_I2CM_INT_ADDR); 266 267 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 268 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 269 HDMI_PHY_I2CM_CTLINT_ADDR); 270 271 /* Software reset */ 272 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 273 274 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 275 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 276 277 /* Set done, not acknowledged and arbitration interrupt polarities */ 278 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 279 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 280 HDMI_I2CM_CTLINT); 281 282 /* Clear DONE and ERROR interrupts */ 283 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 284 HDMI_IH_I2CM_STAT0); 285 286 /* Mute DONE and ERROR interrupts */ 287 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 288 HDMI_IH_MUTE_I2CM_STAT0); 289 } 290 291 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi) 292 { 293 /* If no unwedge state then give up */ 294 if (!hdmi->unwedge_state) 295 return false; 296 297 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n"); 298 299 /* 300 * This is a huge hack to workaround a problem where the dw_hdmi i2c 301 * bus could sometimes get wedged. Once wedged there doesn't appear 302 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ) 303 * other than pulsing the SDA line. 304 * 305 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi) 306 * by: 307 * 1. Remux the pin as a GPIO output, driven low. 308 * 2. Wait a little while. 1 ms seems to work, but we'll do 10. 309 * 3. Immediately jump to remux the pin as dw_hdmi i2c again. 310 * 311 * At the moment of remuxing, the line will still be low due to its 312 * recent stint as an output, but then it will be pulled high by the 313 * (presumed) external pullup. dw_hdmi seems to see this as a rising 314 * edge and that seems to get it out of its jam. 315 * 316 * This wedging was only ever seen on one TV, and only on one of 317 * its HDMI ports. It happened when the TV was powered on while the 318 * device was plugged in. A scope trace shows the TV bringing both SDA 319 * and SCL low, then bringing them both back up at roughly the same 320 * time. Presumably this confuses dw_hdmi because it saw activity but 321 * no real STOP (maybe it thinks there's another master on the bus?). 322 * Giving it a clean rising edge of SDA while SCL is already high 323 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out 324 * of its stupor. 325 * 326 * Note that after coming back alive, transfers seem to immediately 327 * resume, so if we unwedge due to a timeout we should wait a little 328 * longer for our transfer to finish, since it might have just started 329 * now. 330 */ 331 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state); 332 msleep(10); 333 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state); 334 335 return true; 336 } 337 338 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi) 339 { 340 struct dw_hdmi_i2c *i2c = hdmi->i2c; 341 int stat; 342 343 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 344 if (!stat) { 345 /* If we can't unwedge, return timeout */ 346 if (!dw_hdmi_i2c_unwedge(hdmi)) 347 return -EAGAIN; 348 349 /* We tried to unwedge; give it another chance */ 350 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 351 if (!stat) 352 return -EAGAIN; 353 } 354 355 /* Check for error condition on the bus */ 356 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 357 return -EIO; 358 359 return 0; 360 } 361 362 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 363 unsigned char *buf, unsigned int length) 364 { 365 struct dw_hdmi_i2c *i2c = hdmi->i2c; 366 int ret; 367 368 if (!i2c->is_regaddr) { 369 dev_dbg(hdmi->dev, "set read register address to 0\n"); 370 i2c->slave_reg = 0x00; 371 i2c->is_regaddr = true; 372 } 373 374 while (length--) { 375 reinit_completion(&i2c->cmp); 376 377 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 378 if (i2c->is_segment) 379 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 380 HDMI_I2CM_OPERATION); 381 else 382 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 383 HDMI_I2CM_OPERATION); 384 385 ret = dw_hdmi_i2c_wait(hdmi); 386 if (ret) 387 return ret; 388 389 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 390 } 391 i2c->is_segment = false; 392 393 return 0; 394 } 395 396 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 397 unsigned char *buf, unsigned int length) 398 { 399 struct dw_hdmi_i2c *i2c = hdmi->i2c; 400 int ret; 401 402 if (!i2c->is_regaddr) { 403 /* Use the first write byte as register address */ 404 i2c->slave_reg = buf[0]; 405 length--; 406 buf++; 407 i2c->is_regaddr = true; 408 } 409 410 while (length--) { 411 reinit_completion(&i2c->cmp); 412 413 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 414 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 415 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 416 HDMI_I2CM_OPERATION); 417 418 ret = dw_hdmi_i2c_wait(hdmi); 419 if (ret) 420 return ret; 421 } 422 423 return 0; 424 } 425 426 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 427 struct i2c_msg *msgs, int num) 428 { 429 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 430 struct dw_hdmi_i2c *i2c = hdmi->i2c; 431 u8 addr = msgs[0].addr; 432 int i, ret = 0; 433 434 if (addr == DDC_CI_ADDR) 435 /* 436 * The internal I2C controller does not support the multi-byte 437 * read and write operations needed for DDC/CI. 438 * TOFIX: Blacklist the DDC/CI address until we filter out 439 * unsupported I2C operations. 440 */ 441 return -EOPNOTSUPP; 442 443 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 444 445 for (i = 0; i < num; i++) { 446 if (msgs[i].len == 0) { 447 dev_dbg(hdmi->dev, 448 "unsupported transfer %d/%d, no data\n", 449 i + 1, num); 450 return -EOPNOTSUPP; 451 } 452 } 453 454 mutex_lock(&i2c->lock); 455 456 /* Unmute DONE and ERROR interrupts */ 457 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 458 459 /* Set slave device address taken from the first I2C message */ 460 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 461 462 /* Set slave device register address on transfer */ 463 i2c->is_regaddr = false; 464 465 /* Set segment pointer for I2C extended read mode operation */ 466 i2c->is_segment = false; 467 468 for (i = 0; i < num; i++) { 469 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 470 i + 1, num, msgs[i].len, msgs[i].flags); 471 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 472 i2c->is_segment = true; 473 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 474 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 475 } else { 476 if (msgs[i].flags & I2C_M_RD) 477 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 478 msgs[i].len); 479 else 480 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 481 msgs[i].len); 482 } 483 if (ret < 0) 484 break; 485 } 486 487 if (!ret) 488 ret = num; 489 490 /* Mute DONE and ERROR interrupts */ 491 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 492 HDMI_IH_MUTE_I2CM_STAT0); 493 494 mutex_unlock(&i2c->lock); 495 496 return ret; 497 } 498 499 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 500 { 501 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 502 } 503 504 static const struct i2c_algorithm dw_hdmi_algorithm = { 505 .master_xfer = dw_hdmi_i2c_xfer, 506 .functionality = dw_hdmi_i2c_func, 507 }; 508 509 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 510 { 511 struct i2c_adapter *adap; 512 struct dw_hdmi_i2c *i2c; 513 int ret; 514 515 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 516 if (!i2c) 517 return ERR_PTR(-ENOMEM); 518 519 mutex_init(&i2c->lock); 520 init_completion(&i2c->cmp); 521 522 adap = &i2c->adap; 523 adap->owner = THIS_MODULE; 524 adap->dev.parent = hdmi->dev; 525 adap->algo = &dw_hdmi_algorithm; 526 strscpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 527 i2c_set_adapdata(adap, hdmi); 528 529 ret = i2c_add_adapter(adap); 530 if (ret) { 531 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 532 devm_kfree(hdmi->dev, i2c); 533 return ERR_PTR(ret); 534 } 535 536 hdmi->i2c = i2c; 537 538 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 539 540 return adap; 541 } 542 543 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 544 unsigned int n) 545 { 546 /* Must be set/cleared first */ 547 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 548 549 /* nshift factor = 0 */ 550 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 551 552 /* Use automatic CTS generation mode when CTS is not set */ 553 if (cts) 554 hdmi_writeb(hdmi, ((cts >> 16) & 555 HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 556 HDMI_AUD_CTS3_CTS_MANUAL, 557 HDMI_AUD_CTS3); 558 else 559 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); 560 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 561 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 562 563 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 564 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 565 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 566 } 567 568 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 569 { 570 unsigned int n = (128 * freq) / 1000; 571 unsigned int mult = 1; 572 573 while (freq > 48000) { 574 mult *= 2; 575 freq /= 2; 576 } 577 578 switch (freq) { 579 case 32000: 580 if (pixel_clk == 25175000) 581 n = 4576; 582 else if (pixel_clk == 27027000) 583 n = 4096; 584 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 585 n = 11648; 586 else if (pixel_clk == 297000000) 587 n = 3072; 588 else 589 n = 4096; 590 n *= mult; 591 break; 592 593 case 44100: 594 if (pixel_clk == 25175000) 595 n = 7007; 596 else if (pixel_clk == 74176000) 597 n = 17836; 598 else if (pixel_clk == 148352000) 599 n = 8918; 600 else if (pixel_clk == 297000000) 601 n = 4704; 602 else 603 n = 6272; 604 n *= mult; 605 break; 606 607 case 48000: 608 if (pixel_clk == 25175000) 609 n = 6864; 610 else if (pixel_clk == 27027000) 611 n = 6144; 612 else if (pixel_clk == 74176000) 613 n = 11648; 614 else if (pixel_clk == 148352000) 615 n = 5824; 616 else if (pixel_clk == 297000000) 617 n = 5120; 618 else 619 n = 6144; 620 n *= mult; 621 break; 622 623 default: 624 break; 625 } 626 627 return n; 628 } 629 630 /* 631 * When transmitting IEC60958 linear PCM audio, these registers allow to 632 * configure the channel status information of all the channel status 633 * bits in the IEC60958 frame. For the moment this configuration is only 634 * used when the I2S audio interface, General Purpose Audio (GPA), 635 * or AHB audio DMA (AHBAUDDMA) interface is active 636 * (for S/PDIF interface this information comes from the stream). 637 */ 638 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, 639 u8 *channel_status) 640 { 641 /* 642 * Set channel status register for frequency and word length. 643 * Use default values for other registers. 644 */ 645 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7); 646 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8); 647 } 648 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status); 649 650 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 651 unsigned long pixel_clk, unsigned int sample_rate) 652 { 653 unsigned long ftdms = pixel_clk; 654 unsigned int n, cts; 655 u8 config3; 656 u64 tmp; 657 658 n = hdmi_compute_n(sample_rate, pixel_clk); 659 660 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 661 662 /* Compute CTS when using internal AHB audio or General Parallel audio*/ 663 if ((config3 & HDMI_CONFIG3_AHBAUDDMA) || (config3 & HDMI_CONFIG3_GPAUD)) { 664 /* 665 * Compute the CTS value from the N value. Note that CTS and N 666 * can be up to 20 bits in total, so we need 64-bit math. Also 667 * note that our TDMS clock is not fully accurate; it is 668 * accurate to kHz. This can introduce an unnecessary remainder 669 * in the calculation below, so we don't try to warn about that. 670 */ 671 tmp = (u64)ftdms * n; 672 do_div(tmp, 128 * sample_rate); 673 cts = tmp; 674 675 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 676 __func__, sample_rate, 677 ftdms / 1000000, (ftdms / 1000) % 1000, 678 n, cts); 679 } else { 680 cts = 0; 681 } 682 683 spin_lock_irq(&hdmi->audio_lock); 684 hdmi->audio_n = n; 685 hdmi->audio_cts = cts; 686 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 687 spin_unlock_irq(&hdmi->audio_lock); 688 } 689 690 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 691 { 692 mutex_lock(&hdmi->audio_mutex); 693 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 694 mutex_unlock(&hdmi->audio_mutex); 695 } 696 697 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 698 { 699 mutex_lock(&hdmi->audio_mutex); 700 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 701 hdmi->sample_rate); 702 mutex_unlock(&hdmi->audio_mutex); 703 } 704 705 void dw_hdmi_set_sample_width(struct dw_hdmi *hdmi, unsigned int width) 706 { 707 mutex_lock(&hdmi->audio_mutex); 708 hdmi->sample_width = width; 709 mutex_unlock(&hdmi->audio_mutex); 710 } 711 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_width); 712 713 void dw_hdmi_set_sample_non_pcm(struct dw_hdmi *hdmi, unsigned int non_pcm) 714 { 715 mutex_lock(&hdmi->audio_mutex); 716 hdmi->sample_non_pcm = non_pcm; 717 mutex_unlock(&hdmi->audio_mutex); 718 } 719 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_non_pcm); 720 721 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 722 { 723 mutex_lock(&hdmi->audio_mutex); 724 hdmi->sample_rate = rate; 725 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 726 hdmi->sample_rate); 727 mutex_unlock(&hdmi->audio_mutex); 728 } 729 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 730 731 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt) 732 { 733 u8 layout; 734 735 mutex_lock(&hdmi->audio_mutex); 736 hdmi->channels = cnt; 737 738 /* 739 * For >2 channel PCM audio, we need to select layout 1 740 * and set an appropriate channel map. 741 */ 742 if (cnt > 2) 743 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1; 744 else 745 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0; 746 747 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, 748 HDMI_FC_AUDSCONF); 749 750 /* Set the audio infoframes channel count */ 751 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, 752 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0); 753 754 mutex_unlock(&hdmi->audio_mutex); 755 } 756 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count); 757 758 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca) 759 { 760 mutex_lock(&hdmi->audio_mutex); 761 762 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2); 763 764 mutex_unlock(&hdmi->audio_mutex); 765 } 766 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation); 767 768 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 769 { 770 if (enable) 771 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 772 else 773 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 774 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 775 } 776 777 static u8 *hdmi_audio_get_eld(struct dw_hdmi *hdmi) 778 { 779 if (!hdmi->curr_conn) 780 return NULL; 781 782 return hdmi->curr_conn->eld; 783 } 784 785 static void dw_hdmi_gp_audio_enable(struct dw_hdmi *hdmi) 786 { 787 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 788 int sample_freq = 0x2, org_sample_freq = 0xD; 789 int ch_mask = BIT(hdmi->channels) - 1; 790 791 switch (hdmi->sample_rate) { 792 case 32000: 793 sample_freq = 0x03; 794 org_sample_freq = 0x0C; 795 break; 796 case 44100: 797 sample_freq = 0x00; 798 org_sample_freq = 0x0F; 799 break; 800 case 48000: 801 sample_freq = 0x02; 802 org_sample_freq = 0x0D; 803 break; 804 case 88200: 805 sample_freq = 0x08; 806 org_sample_freq = 0x07; 807 break; 808 case 96000: 809 sample_freq = 0x0A; 810 org_sample_freq = 0x05; 811 break; 812 case 176400: 813 sample_freq = 0x0C; 814 org_sample_freq = 0x03; 815 break; 816 case 192000: 817 sample_freq = 0x0E; 818 org_sample_freq = 0x01; 819 break; 820 default: 821 break; 822 } 823 824 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 825 hdmi_enable_audio_clk(hdmi, true); 826 827 hdmi_writeb(hdmi, 0x1, HDMI_FC_AUDSCHNLS0); 828 hdmi_writeb(hdmi, hdmi->channels, HDMI_FC_AUDSCHNLS2); 829 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS3); 830 hdmi_writeb(hdmi, 0x22, HDMI_FC_AUDSCHNLS4); 831 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS5); 832 hdmi_writeb(hdmi, 0x11, HDMI_FC_AUDSCHNLS6); 833 hdmi_writeb(hdmi, (0x3 << 4) | sample_freq, HDMI_FC_AUDSCHNLS7); 834 hdmi_writeb(hdmi, (org_sample_freq << 4) | 0xb, HDMI_FC_AUDSCHNLS8); 835 836 hdmi_writeb(hdmi, ch_mask, HDMI_GP_CONF1); 837 hdmi_writeb(hdmi, 0x02, HDMI_GP_CONF2); 838 hdmi_writeb(hdmi, 0x01, HDMI_GP_CONF0); 839 840 hdmi_modb(hdmi, 0x3, 0x3, HDMI_FC_DATAUTO3); 841 842 /* hbr */ 843 if (hdmi->sample_rate == 192000 && hdmi->channels == 8 && 844 hdmi->sample_width == 32 && hdmi->sample_non_pcm) 845 hdmi_modb(hdmi, 0x01, 0x01, HDMI_GP_CONF2); 846 847 if (pdata->enable_audio) 848 pdata->enable_audio(hdmi, 849 hdmi->channels, 850 hdmi->sample_width, 851 hdmi->sample_rate, 852 hdmi->sample_non_pcm); 853 } 854 855 static void dw_hdmi_gp_audio_disable(struct dw_hdmi *hdmi) 856 { 857 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 858 859 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 860 861 hdmi_modb(hdmi, 0, 0x3, HDMI_FC_DATAUTO3); 862 if (pdata->disable_audio) 863 pdata->disable_audio(hdmi); 864 865 hdmi_enable_audio_clk(hdmi, false); 866 } 867 868 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 869 { 870 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 871 } 872 873 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 874 { 875 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 876 } 877 878 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 879 { 880 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 881 hdmi_enable_audio_clk(hdmi, true); 882 } 883 884 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 885 { 886 hdmi_enable_audio_clk(hdmi, false); 887 } 888 889 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 890 { 891 unsigned long flags; 892 893 spin_lock_irqsave(&hdmi->audio_lock, flags); 894 hdmi->audio_enable = true; 895 if (hdmi->enable_audio) 896 hdmi->enable_audio(hdmi); 897 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 898 } 899 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 900 901 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 902 { 903 unsigned long flags; 904 905 spin_lock_irqsave(&hdmi->audio_lock, flags); 906 hdmi->audio_enable = false; 907 if (hdmi->disable_audio) 908 hdmi->disable_audio(hdmi); 909 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 910 } 911 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 912 913 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 914 { 915 switch (bus_format) { 916 case MEDIA_BUS_FMT_RGB888_1X24: 917 case MEDIA_BUS_FMT_RGB101010_1X30: 918 case MEDIA_BUS_FMT_RGB121212_1X36: 919 case MEDIA_BUS_FMT_RGB161616_1X48: 920 return true; 921 922 default: 923 return false; 924 } 925 } 926 927 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 928 { 929 switch (bus_format) { 930 case MEDIA_BUS_FMT_YUV8_1X24: 931 case MEDIA_BUS_FMT_YUV10_1X30: 932 case MEDIA_BUS_FMT_YUV12_1X36: 933 case MEDIA_BUS_FMT_YUV16_1X48: 934 return true; 935 936 default: 937 return false; 938 } 939 } 940 941 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 942 { 943 switch (bus_format) { 944 case MEDIA_BUS_FMT_UYVY8_1X16: 945 case MEDIA_BUS_FMT_UYVY10_1X20: 946 case MEDIA_BUS_FMT_UYVY12_1X24: 947 return true; 948 949 default: 950 return false; 951 } 952 } 953 954 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 955 { 956 switch (bus_format) { 957 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 958 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 959 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 960 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 961 return true; 962 963 default: 964 return false; 965 } 966 } 967 968 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 969 { 970 switch (bus_format) { 971 case MEDIA_BUS_FMT_RGB888_1X24: 972 case MEDIA_BUS_FMT_YUV8_1X24: 973 case MEDIA_BUS_FMT_UYVY8_1X16: 974 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 975 return 8; 976 977 case MEDIA_BUS_FMT_RGB101010_1X30: 978 case MEDIA_BUS_FMT_YUV10_1X30: 979 case MEDIA_BUS_FMT_UYVY10_1X20: 980 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 981 return 10; 982 983 case MEDIA_BUS_FMT_RGB121212_1X36: 984 case MEDIA_BUS_FMT_YUV12_1X36: 985 case MEDIA_BUS_FMT_UYVY12_1X24: 986 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 987 return 12; 988 989 case MEDIA_BUS_FMT_RGB161616_1X48: 990 case MEDIA_BUS_FMT_YUV16_1X48: 991 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 992 return 16; 993 994 default: 995 return 0; 996 } 997 } 998 999 /* 1000 * this submodule is responsible for the video data synchronization. 1001 * for example, for RGB 4:4:4 input, the data map is defined as 1002 * pin{47~40} <==> R[7:0] 1003 * pin{31~24} <==> G[7:0] 1004 * pin{15~8} <==> B[7:0] 1005 */ 1006 static void hdmi_video_sample(struct dw_hdmi *hdmi) 1007 { 1008 int color_format = 0; 1009 u8 val; 1010 1011 switch (hdmi->hdmi_data.enc_in_bus_format) { 1012 case MEDIA_BUS_FMT_RGB888_1X24: 1013 color_format = 0x01; 1014 break; 1015 case MEDIA_BUS_FMT_RGB101010_1X30: 1016 color_format = 0x03; 1017 break; 1018 case MEDIA_BUS_FMT_RGB121212_1X36: 1019 color_format = 0x05; 1020 break; 1021 case MEDIA_BUS_FMT_RGB161616_1X48: 1022 color_format = 0x07; 1023 break; 1024 1025 case MEDIA_BUS_FMT_YUV8_1X24: 1026 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 1027 color_format = 0x09; 1028 break; 1029 case MEDIA_BUS_FMT_YUV10_1X30: 1030 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 1031 color_format = 0x0B; 1032 break; 1033 case MEDIA_BUS_FMT_YUV12_1X36: 1034 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 1035 color_format = 0x0D; 1036 break; 1037 case MEDIA_BUS_FMT_YUV16_1X48: 1038 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 1039 color_format = 0x0F; 1040 break; 1041 1042 case MEDIA_BUS_FMT_UYVY8_1X16: 1043 color_format = 0x16; 1044 break; 1045 case MEDIA_BUS_FMT_UYVY10_1X20: 1046 color_format = 0x14; 1047 break; 1048 case MEDIA_BUS_FMT_UYVY12_1X24: 1049 color_format = 0x12; 1050 break; 1051 1052 default: 1053 return; 1054 } 1055 1056 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 1057 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 1058 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 1059 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 1060 1061 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 1062 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 1063 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 1064 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 1065 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 1066 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 1067 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 1068 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 1069 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 1070 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 1071 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 1072 } 1073 1074 static int is_color_space_conversion(struct dw_hdmi *hdmi) 1075 { 1076 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1077 bool is_input_rgb, is_output_rgb; 1078 1079 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_in_bus_format); 1080 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi_data->enc_out_bus_format); 1081 1082 return (is_input_rgb != is_output_rgb) || 1083 (is_input_rgb && is_output_rgb && hdmi_data->rgb_limited_range); 1084 } 1085 1086 static int is_color_space_decimation(struct dw_hdmi *hdmi) 1087 { 1088 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1089 return 0; 1090 1091 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 1092 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 1093 return 1; 1094 1095 return 0; 1096 } 1097 1098 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 1099 { 1100 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 1101 return 0; 1102 1103 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1104 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1105 return 1; 1106 1107 return 0; 1108 } 1109 1110 static bool is_csc_needed(struct dw_hdmi *hdmi) 1111 { 1112 return is_color_space_conversion(hdmi) || 1113 is_color_space_decimation(hdmi) || 1114 is_color_space_interpolation(hdmi); 1115 } 1116 1117 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 1118 { 1119 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 1120 bool is_input_rgb, is_output_rgb; 1121 unsigned i; 1122 u32 csc_scale = 1; 1123 1124 is_input_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format); 1125 is_output_rgb = hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format); 1126 1127 if (!is_input_rgb && is_output_rgb) { 1128 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) 1129 csc_coeff = &csc_coeff_rgb_out_eitu601; 1130 else 1131 csc_coeff = &csc_coeff_rgb_out_eitu709; 1132 } else if (is_input_rgb && !is_output_rgb) { 1133 if (hdmi->hdmi_data.enc_out_encoding == V4L2_YCBCR_ENC_601) 1134 csc_coeff = &csc_coeff_rgb_in_eitu601; 1135 else 1136 csc_coeff = &csc_coeff_rgb_in_eitu709; 1137 csc_scale = 0; 1138 } else if (is_input_rgb && is_output_rgb && 1139 hdmi->hdmi_data.rgb_limited_range) { 1140 csc_coeff = &csc_coeff_rgb_full_to_rgb_limited; 1141 } 1142 1143 /* The CSC registers are sequential, alternating MSB then LSB */ 1144 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 1145 u16 coeff_a = (*csc_coeff)[0][i]; 1146 u16 coeff_b = (*csc_coeff)[1][i]; 1147 u16 coeff_c = (*csc_coeff)[2][i]; 1148 1149 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 1150 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 1151 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 1152 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 1153 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 1154 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 1155 } 1156 1157 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 1158 HDMI_CSC_SCALE); 1159 } 1160 1161 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1162 { 1163 int color_depth = 0; 1164 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1165 int decimation = 0; 1166 1167 /* YCC422 interpolation to 444 mode */ 1168 if (is_color_space_interpolation(hdmi)) 1169 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1170 else if (is_color_space_decimation(hdmi)) 1171 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1172 1173 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1174 case 8: 1175 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1176 break; 1177 case 10: 1178 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1179 break; 1180 case 12: 1181 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1182 break; 1183 case 16: 1184 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1185 break; 1186 1187 default: 1188 return; 1189 } 1190 1191 /* Configure the CSC registers */ 1192 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1193 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1194 HDMI_CSC_SCALE); 1195 1196 dw_hdmi_update_csc_coeffs(hdmi); 1197 } 1198 1199 /* 1200 * HDMI video packetizer is used to packetize the data. 1201 * for example, if input is YCC422 mode or repeater is used, 1202 * data should be repacked this module can be bypassed. 1203 */ 1204 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1205 { 1206 unsigned int color_depth = 0; 1207 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1208 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1209 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1210 u8 val, vp_conf; 1211 u8 clear_gcp_auto = 0; 1212 1213 1214 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1215 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1216 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1217 switch (hdmi_bus_fmt_color_depth( 1218 hdmi->hdmi_data.enc_out_bus_format)) { 1219 case 8: 1220 color_depth = 4; 1221 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1222 clear_gcp_auto = 1; 1223 break; 1224 case 10: 1225 color_depth = 5; 1226 break; 1227 case 12: 1228 color_depth = 6; 1229 break; 1230 case 16: 1231 color_depth = 7; 1232 break; 1233 default: 1234 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1235 } 1236 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1237 switch (hdmi_bus_fmt_color_depth( 1238 hdmi->hdmi_data.enc_out_bus_format)) { 1239 case 0: 1240 case 8: 1241 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1242 clear_gcp_auto = 1; 1243 break; 1244 case 10: 1245 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1246 break; 1247 case 12: 1248 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1249 break; 1250 1251 default: 1252 return; 1253 } 1254 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1255 } else { 1256 return; 1257 } 1258 1259 /* set the packetizer registers */ 1260 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1261 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 1262 ((hdmi_data->pix_repet_factor << 1263 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 1264 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 1265 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1266 1267 /* HDMI1.4b specification section 6.5.3: 1268 * Source shall only send GCPs with non-zero CD to sinks 1269 * that indicate support for Deep Color. 1270 * GCP only transmit CD and do not handle AVMUTE, PP norDefault_Phase (yet). 1271 * Disable Auto GCP when 24-bit color for sinks that not support Deep Color. 1272 */ 1273 val = hdmi_readb(hdmi, HDMI_FC_DATAUTO3); 1274 if (clear_gcp_auto == 1) 1275 val &= ~HDMI_FC_DATAUTO3_GCP_AUTO; 1276 else 1277 val |= HDMI_FC_DATAUTO3_GCP_AUTO; 1278 hdmi_writeb(hdmi, val, HDMI_FC_DATAUTO3); 1279 1280 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1281 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1282 1283 /* Data from pixel repeater block */ 1284 if (hdmi_data->pix_repet_factor > 1) { 1285 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1286 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1287 } else { /* data from packetizer block */ 1288 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1289 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1290 } 1291 1292 hdmi_modb(hdmi, vp_conf, 1293 HDMI_VP_CONF_PR_EN_MASK | 1294 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1295 1296 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1297 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1298 1299 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1300 1301 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1302 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1303 HDMI_VP_CONF_PP_EN_ENABLE | 1304 HDMI_VP_CONF_YCC422_EN_DISABLE; 1305 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1306 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1307 HDMI_VP_CONF_PP_EN_DISABLE | 1308 HDMI_VP_CONF_YCC422_EN_ENABLE; 1309 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1310 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1311 HDMI_VP_CONF_PP_EN_DISABLE | 1312 HDMI_VP_CONF_YCC422_EN_DISABLE; 1313 } else { 1314 return; 1315 } 1316 1317 hdmi_modb(hdmi, vp_conf, 1318 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1319 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1320 1321 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1322 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1323 HDMI_VP_STUFF_PP_STUFFING_MASK | 1324 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1325 1326 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1327 HDMI_VP_CONF); 1328 } 1329 1330 /* ----------------------------------------------------------------------------- 1331 * Synopsys PHY Handling 1332 */ 1333 1334 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 1335 unsigned char bit) 1336 { 1337 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 1338 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 1339 } 1340 1341 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 1342 { 1343 u32 val; 1344 1345 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 1346 if (msec-- == 0) 1347 return false; 1348 udelay(1000); 1349 } 1350 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1351 1352 return true; 1353 } 1354 1355 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1356 unsigned char addr) 1357 { 1358 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1359 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1360 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1361 HDMI_PHY_I2CM_DATAO_1_ADDR); 1362 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1363 HDMI_PHY_I2CM_DATAO_0_ADDR); 1364 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1365 HDMI_PHY_I2CM_OPERATION_ADDR); 1366 hdmi_phy_wait_i2c_done(hdmi, 1000); 1367 } 1368 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1369 1370 /* Filter out invalid setups to avoid configuring SCDC and scrambling */ 1371 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi, 1372 const struct drm_display_info *display) 1373 { 1374 /* Completely disable SCDC support for older controllers */ 1375 if (hdmi->version < 0x200a) 1376 return false; 1377 1378 /* Disable if no DDC bus */ 1379 if (!hdmi->ddc) 1380 return false; 1381 1382 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ 1383 if (!display->hdmi.scdc.supported || 1384 !display->hdmi.scdc.scrambling.supported) 1385 return false; 1386 1387 /* 1388 * Disable if display only support low TMDS rates and scrambling 1389 * for low rates is not supported either 1390 */ 1391 if (!display->hdmi.scdc.scrambling.low_rates && 1392 display->max_tmds_clock <= 340000) 1393 return false; 1394 1395 return true; 1396 } 1397 1398 /* 1399 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: 1400 * - The Source shall suspend transmission of the TMDS clock and data 1401 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it 1402 * from a 0 to a 1 or from a 1 to a 0 1403 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from 1404 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming 1405 * transmission of TMDS clock and data 1406 * 1407 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() 1408 * helper should called right before enabling the TMDS Clock and Data in 1409 * the PHY configuration callback. 1410 */ 1411 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi, 1412 const struct drm_display_info *display) 1413 { 1414 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1415 1416 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 1417 if (dw_hdmi_support_scdc(hdmi, display)) { 1418 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1419 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 1); 1420 else 1421 drm_scdc_set_high_tmds_clock_ratio(hdmi->curr_conn, 0); 1422 } 1423 } 1424 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); 1425 1426 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1427 { 1428 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1429 HDMI_PHY_CONF0_PDZ_OFFSET, 1430 HDMI_PHY_CONF0_PDZ_MASK); 1431 } 1432 1433 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1434 { 1435 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1436 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1437 HDMI_PHY_CONF0_ENTMDS_MASK); 1438 } 1439 1440 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1441 { 1442 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1443 HDMI_PHY_CONF0_SVSRET_OFFSET, 1444 HDMI_PHY_CONF0_SVSRET_MASK); 1445 } 1446 1447 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1448 { 1449 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1450 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1451 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1452 } 1453 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1454 1455 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1456 { 1457 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1458 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1459 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1460 } 1461 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1462 1463 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1464 { 1465 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1466 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1467 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1468 } 1469 1470 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1471 { 1472 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1473 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1474 HDMI_PHY_CONF0_SELDIPIF_MASK); 1475 } 1476 1477 void dw_hdmi_phy_gen1_reset(struct dw_hdmi *hdmi) 1478 { 1479 /* PHY reset. The reset signal is active low on Gen1 PHYs. */ 1480 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1481 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1482 } 1483 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen1_reset); 1484 1485 void dw_hdmi_phy_gen2_reset(struct dw_hdmi *hdmi) 1486 { 1487 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1488 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1489 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1490 } 1491 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_reset); 1492 1493 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1494 { 1495 hdmi_phy_test_clear(hdmi, 1); 1496 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1497 hdmi_phy_test_clear(hdmi, 0); 1498 } 1499 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1500 1501 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1502 { 1503 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1504 unsigned int i; 1505 u16 val; 1506 1507 if (phy->gen == 1) { 1508 dw_hdmi_phy_enable_tmds(hdmi, 0); 1509 dw_hdmi_phy_enable_powerdown(hdmi, true); 1510 return; 1511 } 1512 1513 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1514 1515 /* 1516 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1517 * to low power mode. 1518 */ 1519 for (i = 0; i < 5; ++i) { 1520 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1521 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1522 break; 1523 1524 usleep_range(1000, 2000); 1525 } 1526 1527 if (val & HDMI_PHY_TX_PHY_LOCK) 1528 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1529 else 1530 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1531 1532 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1533 } 1534 1535 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1536 { 1537 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1538 unsigned int i; 1539 u8 val; 1540 1541 if (phy->gen == 1) { 1542 dw_hdmi_phy_enable_powerdown(hdmi, false); 1543 1544 /* Toggle TMDS enable. */ 1545 dw_hdmi_phy_enable_tmds(hdmi, 0); 1546 dw_hdmi_phy_enable_tmds(hdmi, 1); 1547 return 0; 1548 } 1549 1550 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1551 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1552 1553 /* Wait for PHY PLL lock */ 1554 for (i = 0; i < 5; ++i) { 1555 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1556 if (val) 1557 break; 1558 1559 usleep_range(1000, 2000); 1560 } 1561 1562 if (!val) { 1563 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1564 return -ETIMEDOUT; 1565 } 1566 1567 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1568 return 0; 1569 } 1570 1571 /* 1572 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1573 * information the DWC MHL PHY has the same register layout and is thus also 1574 * supported by this function. 1575 */ 1576 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1577 const struct dw_hdmi_plat_data *pdata, 1578 unsigned long mpixelclock) 1579 { 1580 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1581 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1582 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1583 1584 /* TOFIX Will need 420 specific PHY configuration tables */ 1585 1586 /* PLL/MPLL Cfg - always match on final entry */ 1587 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1588 if (mpixelclock <= mpll_config->mpixelclock) 1589 break; 1590 1591 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1592 if (mpixelclock <= curr_ctrl->mpixelclock) 1593 break; 1594 1595 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1596 if (mpixelclock <= phy_config->mpixelclock) 1597 break; 1598 1599 if (mpll_config->mpixelclock == ~0UL || 1600 curr_ctrl->mpixelclock == ~0UL || 1601 phy_config->mpixelclock == ~0UL) 1602 return -EINVAL; 1603 1604 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1605 HDMI_3D_TX_PHY_CPCE_CTRL); 1606 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1607 HDMI_3D_TX_PHY_GMPCTRL); 1608 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1609 HDMI_3D_TX_PHY_CURRCTRL); 1610 1611 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1612 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1613 HDMI_3D_TX_PHY_MSM_CTRL); 1614 1615 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1616 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1617 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1618 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1619 HDMI_3D_TX_PHY_VLEVCTRL); 1620 1621 /* Override and disable clock termination. */ 1622 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1623 HDMI_3D_TX_PHY_CKCALCTRL); 1624 1625 return 0; 1626 } 1627 1628 static int hdmi_phy_configure(struct dw_hdmi *hdmi, 1629 const struct drm_display_info *display) 1630 { 1631 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1632 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1633 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1634 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1635 int ret; 1636 1637 dw_hdmi_phy_power_off(hdmi); 1638 1639 dw_hdmi_set_high_tmds_clock_ratio(hdmi, display); 1640 1641 /* Leave low power consumption mode by asserting SVSRET. */ 1642 if (phy->has_svsret) 1643 dw_hdmi_phy_enable_svsret(hdmi, 1); 1644 1645 dw_hdmi_phy_gen2_reset(hdmi); 1646 1647 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1648 1649 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1650 1651 /* Write to the PHY as configured by the platform */ 1652 if (pdata->configure_phy) 1653 ret = pdata->configure_phy(hdmi, pdata->priv_data, mpixelclock); 1654 else 1655 ret = phy->configure(hdmi, pdata, mpixelclock); 1656 if (ret) { 1657 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1658 mpixelclock); 1659 return ret; 1660 } 1661 1662 /* Wait for resuming transmission of TMDS clock and data */ 1663 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1664 msleep(100); 1665 1666 return dw_hdmi_phy_power_on(hdmi); 1667 } 1668 1669 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1670 const struct drm_display_info *display, 1671 const struct drm_display_mode *mode) 1672 { 1673 int i, ret; 1674 1675 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1676 for (i = 0; i < 2; i++) { 1677 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1678 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1679 1680 ret = hdmi_phy_configure(hdmi, display); 1681 if (ret) 1682 return ret; 1683 } 1684 1685 return 0; 1686 } 1687 1688 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1689 { 1690 dw_hdmi_phy_power_off(hdmi); 1691 } 1692 1693 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1694 void *data) 1695 { 1696 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1697 connector_status_connected : connector_status_disconnected; 1698 } 1699 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1700 1701 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1702 bool force, bool disabled, bool rxsense) 1703 { 1704 u8 old_mask = hdmi->phy_mask; 1705 1706 if (force || disabled || !rxsense) 1707 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1708 else 1709 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1710 1711 if (old_mask != hdmi->phy_mask) 1712 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1713 } 1714 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1715 1716 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1717 { 1718 /* 1719 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1720 * any pending interrupt. 1721 */ 1722 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1723 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1724 HDMI_IH_PHY_STAT0); 1725 1726 /* Enable cable hot plug irq. */ 1727 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1728 1729 /* Clear and unmute interrupts. */ 1730 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1731 HDMI_IH_PHY_STAT0); 1732 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1733 HDMI_IH_MUTE_PHY_STAT0); 1734 } 1735 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1736 1737 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1738 .init = dw_hdmi_phy_init, 1739 .disable = dw_hdmi_phy_disable, 1740 .read_hpd = dw_hdmi_phy_read_hpd, 1741 .update_hpd = dw_hdmi_phy_update_hpd, 1742 .setup_hpd = dw_hdmi_phy_setup_hpd, 1743 }; 1744 1745 /* ----------------------------------------------------------------------------- 1746 * HDMI TX Setup 1747 */ 1748 1749 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1750 { 1751 u8 de; 1752 1753 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1754 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1755 else 1756 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1757 1758 /* disable rx detect */ 1759 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1760 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1761 1762 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1763 1764 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1765 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1766 } 1767 1768 static void hdmi_config_AVI(struct dw_hdmi *hdmi, 1769 const struct drm_connector *connector, 1770 const struct drm_display_mode *mode) 1771 { 1772 struct hdmi_avi_infoframe frame; 1773 u8 val; 1774 1775 /* Initialise info frame from DRM mode */ 1776 drm_hdmi_avi_infoframe_from_display_mode(&frame, connector, mode); 1777 1778 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 1779 drm_hdmi_avi_infoframe_quant_range(&frame, connector, mode, 1780 hdmi->hdmi_data.rgb_limited_range ? 1781 HDMI_QUANTIZATION_RANGE_LIMITED : 1782 HDMI_QUANTIZATION_RANGE_FULL); 1783 } else { 1784 frame.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT; 1785 frame.ycc_quantization_range = 1786 HDMI_YCC_QUANTIZATION_RANGE_LIMITED; 1787 } 1788 1789 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1790 frame.colorspace = HDMI_COLORSPACE_YUV444; 1791 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1792 frame.colorspace = HDMI_COLORSPACE_YUV422; 1793 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1794 frame.colorspace = HDMI_COLORSPACE_YUV420; 1795 else 1796 frame.colorspace = HDMI_COLORSPACE_RGB; 1797 1798 /* Set up colorimetry */ 1799 if (!hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 1800 switch (hdmi->hdmi_data.enc_out_encoding) { 1801 case V4L2_YCBCR_ENC_601: 1802 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1803 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1804 else 1805 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1806 frame.extended_colorimetry = 1807 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1808 break; 1809 case V4L2_YCBCR_ENC_709: 1810 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1811 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1812 else 1813 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1814 frame.extended_colorimetry = 1815 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1816 break; 1817 default: /* Carries no data */ 1818 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1819 frame.extended_colorimetry = 1820 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1821 break; 1822 } 1823 } else { 1824 frame.colorimetry = HDMI_COLORIMETRY_NONE; 1825 frame.extended_colorimetry = 1826 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1827 } 1828 1829 /* 1830 * The Designware IP uses a different byte format from standard 1831 * AVI info frames, though generally the bits are in the correct 1832 * bytes. 1833 */ 1834 1835 /* 1836 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1837 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1838 * bit 6 rather than 4. 1839 */ 1840 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1841 if (frame.active_aspect & 15) 1842 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1843 if (frame.top_bar || frame.bottom_bar) 1844 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1845 if (frame.left_bar || frame.right_bar) 1846 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1847 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1848 1849 /* AVI data byte 2 differences: none */ 1850 val = ((frame.colorimetry & 0x3) << 6) | 1851 ((frame.picture_aspect & 0x3) << 4) | 1852 (frame.active_aspect & 0xf); 1853 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1854 1855 /* AVI data byte 3 differences: none */ 1856 val = ((frame.extended_colorimetry & 0x7) << 4) | 1857 ((frame.quantization_range & 0x3) << 2) | 1858 (frame.nups & 0x3); 1859 if (frame.itc) 1860 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1861 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1862 1863 /* AVI data byte 4 differences: none */ 1864 val = frame.video_code & 0x7f; 1865 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1866 1867 /* AVI Data Byte 5- set up input and output pixel repetition */ 1868 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1869 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1870 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1871 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1872 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1873 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1874 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1875 1876 /* 1877 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1878 * ycc range in bits 2,3 rather than 6,7 1879 */ 1880 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1881 (frame.content_type & 0x3); 1882 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1883 1884 /* AVI Data Bytes 6-13 */ 1885 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1886 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1887 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1888 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1889 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1890 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1891 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1892 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1893 } 1894 1895 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1896 const struct drm_connector *connector, 1897 const struct drm_display_mode *mode) 1898 { 1899 struct hdmi_vendor_infoframe frame; 1900 u8 buffer[10]; 1901 ssize_t err; 1902 1903 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, connector, 1904 mode); 1905 if (err < 0) 1906 /* 1907 * Going into that statement does not means vendor infoframe 1908 * fails. It just informed us that vendor infoframe is not 1909 * needed for the selected mode. Only 4k or stereoscopic 3D 1910 * mode requires vendor infoframe. So just simply return. 1911 */ 1912 return; 1913 1914 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1915 if (err < 0) { 1916 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1917 err); 1918 return; 1919 } 1920 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1921 HDMI_FC_DATAUTO0_VSD_MASK); 1922 1923 /* Set the length of HDMI vendor specific InfoFrame payload */ 1924 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1925 1926 /* Set 24bit IEEE Registration Identifier */ 1927 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1928 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1929 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1930 1931 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1932 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1933 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1934 1935 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1936 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1937 1938 /* Packet frame interpolation */ 1939 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1940 1941 /* Auto packets per frame and line spacing */ 1942 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1943 1944 /* Configures the Frame Composer On RDRB mode */ 1945 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1946 HDMI_FC_DATAUTO0_VSD_MASK); 1947 } 1948 1949 static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi, 1950 const struct drm_connector *connector) 1951 { 1952 const struct drm_connector_state *conn_state = connector->state; 1953 struct hdmi_drm_infoframe frame; 1954 u8 buffer[30]; 1955 ssize_t err; 1956 int i; 1957 1958 if (!hdmi->plat_data->use_drm_infoframe) 1959 return; 1960 1961 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE, 1962 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1963 1964 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state); 1965 if (err < 0) 1966 return; 1967 1968 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer)); 1969 if (err < 0) { 1970 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err); 1971 return; 1972 } 1973 1974 hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0); 1975 hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1); 1976 1977 for (i = 0; i < frame.length; i++) 1978 hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i); 1979 1980 hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP); 1981 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE, 1982 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1983 } 1984 1985 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1986 const struct drm_display_info *display, 1987 const struct drm_display_mode *mode) 1988 { 1989 u8 inv_val, bytes; 1990 const struct drm_hdmi_info *hdmi_info = &display->hdmi; 1991 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1992 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1993 unsigned int vdisplay, hdisplay; 1994 1995 vmode->mpixelclock = mode->clock * 1000; 1996 1997 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1998 1999 vmode->mtmdsclock = vmode->mpixelclock; 2000 2001 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 2002 switch (hdmi_bus_fmt_color_depth( 2003 hdmi->hdmi_data.enc_out_bus_format)) { 2004 case 16: 2005 vmode->mtmdsclock = vmode->mpixelclock * 2; 2006 break; 2007 case 12: 2008 vmode->mtmdsclock = vmode->mpixelclock * 3 / 2; 2009 break; 2010 case 10: 2011 vmode->mtmdsclock = vmode->mpixelclock * 5 / 4; 2012 break; 2013 } 2014 } 2015 2016 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 2017 vmode->mtmdsclock /= 2; 2018 2019 dev_dbg(hdmi->dev, "final tmdsclock = %d\n", vmode->mtmdsclock); 2020 2021 /* Set up HDMI_FC_INVIDCONF */ 2022 inv_val = (hdmi->hdmi_data.hdcp_enable || 2023 (dw_hdmi_support_scdc(hdmi, display) && 2024 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 2025 hdmi_info->scdc.scrambling.low_rates)) ? 2026 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 2027 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 2028 2029 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 2030 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 2031 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 2032 2033 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 2034 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 2035 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 2036 2037 inv_val |= (vmode->mdataenablepolarity ? 2038 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 2039 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 2040 2041 if (hdmi->vic == 39) 2042 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 2043 else 2044 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 2045 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 2046 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 2047 2048 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 2049 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 2050 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 2051 2052 inv_val |= hdmi->sink_is_hdmi ? 2053 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 2054 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 2055 2056 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 2057 2058 hdisplay = mode->hdisplay; 2059 hblank = mode->htotal - mode->hdisplay; 2060 h_de_hs = mode->hsync_start - mode->hdisplay; 2061 hsync_len = mode->hsync_end - mode->hsync_start; 2062 2063 /* 2064 * When we're setting a YCbCr420 mode, we need 2065 * to adjust the horizontal timing to suit. 2066 */ 2067 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 2068 hdisplay /= 2; 2069 hblank /= 2; 2070 h_de_hs /= 2; 2071 hsync_len /= 2; 2072 } 2073 2074 vdisplay = mode->vdisplay; 2075 vblank = mode->vtotal - mode->vdisplay; 2076 v_de_vs = mode->vsync_start - mode->vdisplay; 2077 vsync_len = mode->vsync_end - mode->vsync_start; 2078 2079 /* 2080 * When we're setting an interlaced mode, we need 2081 * to adjust the vertical timing to suit. 2082 */ 2083 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 2084 vdisplay /= 2; 2085 vblank /= 2; 2086 v_de_vs /= 2; 2087 vsync_len /= 2; 2088 } 2089 2090 /* Scrambling Control */ 2091 if (dw_hdmi_support_scdc(hdmi, display)) { 2092 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 2093 hdmi_info->scdc.scrambling.low_rates) { 2094 /* 2095 * HDMI2.0 Specifies the following procedure: 2096 * After the Source Device has determined that 2097 * SCDC_Present is set (=1), the Source Device should 2098 * write the accurate Version of the Source Device 2099 * to the Source Version field in the SCDCS. 2100 * Source Devices compliant shall set the 2101 * Source Version = 1. 2102 */ 2103 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, 2104 &bytes); 2105 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, 2106 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 2107 2108 /* Enabled Scrambling in the Sink */ 2109 drm_scdc_set_scrambling(hdmi->curr_conn, 1); 2110 2111 /* 2112 * To activate the scrambler feature, you must ensure 2113 * that the quasi-static configuration bit 2114 * fc_invidconf.HDCP_keepout is set at configuration 2115 * time, before the required mc_swrstzreq.tmdsswrst_req 2116 * reset request is issued. 2117 */ 2118 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 2119 HDMI_MC_SWRSTZ); 2120 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 2121 } else { 2122 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 2123 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 2124 HDMI_MC_SWRSTZ); 2125 drm_scdc_set_scrambling(hdmi->curr_conn, 0); 2126 } 2127 } 2128 2129 /* Set up horizontal active pixel width */ 2130 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 2131 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 2132 2133 /* Set up vertical active lines */ 2134 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 2135 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 2136 2137 /* Set up horizontal blanking pixel region width */ 2138 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 2139 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 2140 2141 /* Set up vertical blanking pixel region width */ 2142 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 2143 2144 /* Set up HSYNC active edge delay width (in pixel clks) */ 2145 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 2146 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 2147 2148 /* Set up VSYNC active edge delay (in lines) */ 2149 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 2150 2151 /* Set up HSYNC active pulse width (in pixel clks) */ 2152 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 2153 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 2154 2155 /* Set up VSYNC active edge delay (in lines) */ 2156 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 2157 } 2158 2159 /* HDMI Initialization Step B.4 */ 2160 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 2161 { 2162 /* control period minimum duration */ 2163 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 2164 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 2165 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 2166 2167 /* Set to fill TMDS data channels */ 2168 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 2169 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 2170 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 2171 2172 /* Enable pixel clock and tmds data path */ 2173 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 2174 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 2175 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 2176 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 2177 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 2178 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 2179 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2180 2181 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 2182 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2183 2184 /* Enable csc path */ 2185 if (is_csc_needed(hdmi)) { 2186 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 2187 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2188 2189 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 2190 HDMI_MC_FLOWCTRL); 2191 } else { 2192 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CSCCLK_DISABLE; 2193 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2194 2195 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 2196 HDMI_MC_FLOWCTRL); 2197 } 2198 } 2199 2200 /* Workaround to clear the overflow condition */ 2201 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 2202 { 2203 unsigned int count; 2204 unsigned int i; 2205 u8 val; 2206 2207 /* 2208 * Under some circumstances the Frame Composer arithmetic unit can miss 2209 * an FC register write due to being busy processing the previous one. 2210 * The issue can be worked around by issuing a TMDS software reset and 2211 * then write one of the FC registers several times. 2212 * 2213 * The number of iterations matters and depends on the HDMI TX revision 2214 * (and possibly on the platform). 2215 * 4 iterations for i.MX6Q(v1.30a) and 1 iteration for others. 2216 * i.MX6DL (v1.31a), Allwinner SoCs (v1.32a), Rockchip RK3288 SoC (v2.00a), 2217 * Amlogic Meson GX SoCs (v2.01a), RK3328/RK3399 SoCs (v2.11a) 2218 * and i.MX8MPlus (v2.13a) have been identified as needing the workaround 2219 * with a single iteration. 2220 */ 2221 2222 switch (hdmi->version) { 2223 case 0x130a: 2224 count = 4; 2225 break; 2226 default: 2227 count = 1; 2228 break; 2229 } 2230 2231 /* TMDS software reset */ 2232 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 2233 2234 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 2235 for (i = 0; i < count; i++) 2236 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 2237 } 2238 2239 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 2240 { 2241 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 2242 HDMI_IH_MUTE_FC_STAT2); 2243 } 2244 2245 static int dw_hdmi_setup(struct dw_hdmi *hdmi, 2246 const struct drm_connector *connector, 2247 const struct drm_display_mode *mode) 2248 { 2249 int ret; 2250 2251 hdmi_disable_overflow_interrupts(hdmi); 2252 2253 hdmi->vic = drm_match_cea_mode(mode); 2254 2255 if (!hdmi->vic) { 2256 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 2257 } else { 2258 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 2259 } 2260 2261 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 2262 (hdmi->vic == 21) || (hdmi->vic == 22) || 2263 (hdmi->vic == 2) || (hdmi->vic == 3) || 2264 (hdmi->vic == 17) || (hdmi->vic == 18)) 2265 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2266 else 2267 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2268 2269 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2270 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2271 2272 if (hdmi->hdmi_data.enc_in_bus_format == MEDIA_BUS_FMT_FIXED) 2273 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2274 2275 /* TOFIX: Get input encoding from plat data or fallback to none */ 2276 if (hdmi->plat_data->input_bus_encoding) 2277 hdmi->hdmi_data.enc_in_encoding = 2278 hdmi->plat_data->input_bus_encoding; 2279 else 2280 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2281 2282 if (hdmi->hdmi_data.enc_out_bus_format == MEDIA_BUS_FMT_FIXED) 2283 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2284 2285 hdmi->hdmi_data.rgb_limited_range = hdmi->sink_is_hdmi && 2286 drm_default_rgb_quant_range(mode) == 2287 HDMI_QUANTIZATION_RANGE_LIMITED; 2288 2289 hdmi->hdmi_data.pix_repet_factor = 0; 2290 hdmi->hdmi_data.hdcp_enable = 0; 2291 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2292 2293 /* HDMI Initialization Step B.1 */ 2294 hdmi_av_composer(hdmi, &connector->display_info, mode); 2295 2296 /* HDMI Initializateion Step B.2 */ 2297 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, 2298 &connector->display_info, 2299 &hdmi->previous_mode); 2300 if (ret) 2301 return ret; 2302 hdmi->phy.enabled = true; 2303 2304 /* HDMI Initialization Step B.3 */ 2305 dw_hdmi_enable_video_path(hdmi); 2306 2307 if (hdmi->sink_has_audio) { 2308 dev_dbg(hdmi->dev, "sink has audio support\n"); 2309 2310 /* HDMI Initialization Step E - Configure audio */ 2311 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2312 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable); 2313 } 2314 2315 /* not for DVI mode */ 2316 if (hdmi->sink_is_hdmi) { 2317 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 2318 2319 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2320 hdmi_config_AVI(hdmi, connector, mode); 2321 hdmi_config_vendor_specific_infoframe(hdmi, connector, mode); 2322 hdmi_config_drm_infoframe(hdmi, connector); 2323 } else { 2324 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 2325 } 2326 2327 hdmi_video_packetize(hdmi); 2328 hdmi_video_csc(hdmi); 2329 hdmi_video_sample(hdmi); 2330 hdmi_tx_hdcp_config(hdmi); 2331 2332 dw_hdmi_clear_overflow(hdmi); 2333 2334 return 0; 2335 } 2336 2337 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 2338 { 2339 u8 ih_mute; 2340 2341 /* 2342 * Boot up defaults are: 2343 * HDMI_IH_MUTE = 0x03 (disabled) 2344 * HDMI_IH_MUTE_* = 0x00 (enabled) 2345 * 2346 * Disable top level interrupt bits in HDMI block 2347 */ 2348 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 2349 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2350 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 2351 2352 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2353 2354 /* by default mask all interrupts */ 2355 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 2356 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2357 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2358 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2359 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 2360 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 2361 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 2362 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 2363 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 2364 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 2365 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 2366 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 2367 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 2368 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 2369 2370 /* Disable interrupts in the IH_MUTE_* registers */ 2371 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2372 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2373 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2374 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2375 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 2376 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2377 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2378 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2379 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2380 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2381 2382 /* Enable top level interrupt bits in HDMI block */ 2383 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2384 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 2385 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2386 } 2387 2388 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 2389 { 2390 hdmi->bridge_is_on = true; 2391 2392 /* 2393 * The curr_conn field is guaranteed to be valid here, as this function 2394 * is only be called when !hdmi->disabled. 2395 */ 2396 dw_hdmi_setup(hdmi, hdmi->curr_conn, &hdmi->previous_mode); 2397 } 2398 2399 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 2400 { 2401 if (hdmi->phy.enabled) { 2402 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 2403 hdmi->phy.enabled = false; 2404 } 2405 2406 hdmi->bridge_is_on = false; 2407 } 2408 2409 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 2410 { 2411 int force = hdmi->force; 2412 2413 if (hdmi->disabled) { 2414 force = DRM_FORCE_OFF; 2415 } else if (force == DRM_FORCE_UNSPECIFIED) { 2416 if (hdmi->rxsense) 2417 force = DRM_FORCE_ON; 2418 else 2419 force = DRM_FORCE_OFF; 2420 } 2421 2422 if (force == DRM_FORCE_OFF) { 2423 if (hdmi->bridge_is_on) 2424 dw_hdmi_poweroff(hdmi); 2425 } else { 2426 if (!hdmi->bridge_is_on) 2427 dw_hdmi_poweron(hdmi); 2428 } 2429 } 2430 2431 /* 2432 * Adjust the detection of RXSENSE according to whether we have a forced 2433 * connection mode enabled, or whether we have been disabled. There is 2434 * no point processing RXSENSE interrupts if we have a forced connection 2435 * state, or DRM has us disabled. 2436 * 2437 * We also disable rxsense interrupts when we think we're disconnected 2438 * to avoid floating TDMS signals giving false rxsense interrupts. 2439 * 2440 * Note: we still need to listen for HPD interrupts even when DRM has us 2441 * disabled so that we can detect a connect event. 2442 */ 2443 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 2444 { 2445 if (hdmi->phy.ops->update_hpd) 2446 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 2447 hdmi->force, hdmi->disabled, 2448 hdmi->rxsense); 2449 } 2450 2451 static enum drm_connector_status dw_hdmi_detect(struct dw_hdmi *hdmi) 2452 { 2453 enum drm_connector_status result; 2454 2455 result = hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 2456 hdmi->last_connector_result = result; 2457 2458 return result; 2459 } 2460 2461 static const struct drm_edid *dw_hdmi_edid_read(struct dw_hdmi *hdmi, 2462 struct drm_connector *connector) 2463 { 2464 const struct drm_edid *drm_edid; 2465 const struct edid *edid; 2466 2467 if (!hdmi->ddc) 2468 return NULL; 2469 2470 drm_edid = drm_edid_read_ddc(connector, hdmi->ddc); 2471 if (!drm_edid) { 2472 dev_dbg(hdmi->dev, "failed to get edid\n"); 2473 return NULL; 2474 } 2475 2476 /* 2477 * FIXME: This should use connector->display_info.is_hdmi and 2478 * connector->display_info.has_audio from a path that has read the EDID 2479 * and called drm_edid_connector_update(). 2480 */ 2481 edid = drm_edid_raw(drm_edid); 2482 2483 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 2484 edid->width_cm, edid->height_cm); 2485 2486 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 2487 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2488 2489 return drm_edid; 2490 } 2491 2492 /* ----------------------------------------------------------------------------- 2493 * DRM Connector Operations 2494 */ 2495 2496 static enum drm_connector_status 2497 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 2498 { 2499 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2500 connector); 2501 return dw_hdmi_detect(hdmi); 2502 } 2503 2504 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 2505 { 2506 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2507 connector); 2508 const struct drm_edid *drm_edid; 2509 int ret; 2510 2511 drm_edid = dw_hdmi_edid_read(hdmi, connector); 2512 2513 drm_edid_connector_update(connector, drm_edid); 2514 cec_notifier_set_phys_addr(hdmi->cec_notifier, 2515 connector->display_info.source_physical_address); 2516 ret = drm_edid_connector_add_modes(connector); 2517 drm_edid_free(drm_edid); 2518 2519 return ret; 2520 } 2521 2522 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, 2523 struct drm_atomic_state *state) 2524 { 2525 struct drm_connector_state *old_state = 2526 drm_atomic_get_old_connector_state(state, connector); 2527 struct drm_connector_state *new_state = 2528 drm_atomic_get_new_connector_state(state, connector); 2529 struct drm_crtc *crtc = new_state->crtc; 2530 struct drm_crtc_state *crtc_state; 2531 2532 if (!crtc) 2533 return 0; 2534 2535 if (!drm_connector_atomic_hdr_metadata_equal(old_state, new_state)) { 2536 crtc_state = drm_atomic_get_crtc_state(state, crtc); 2537 if (IS_ERR(crtc_state)) 2538 return PTR_ERR(crtc_state); 2539 2540 crtc_state->mode_changed = true; 2541 } 2542 2543 return 0; 2544 } 2545 2546 static void dw_hdmi_connector_force(struct drm_connector *connector) 2547 { 2548 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2549 connector); 2550 2551 mutex_lock(&hdmi->mutex); 2552 hdmi->force = connector->force; 2553 dw_hdmi_update_power(hdmi); 2554 dw_hdmi_update_phy_mask(hdmi); 2555 mutex_unlock(&hdmi->mutex); 2556 } 2557 2558 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 2559 .fill_modes = drm_helper_probe_single_connector_modes, 2560 .detect = dw_hdmi_connector_detect, 2561 .destroy = drm_connector_cleanup, 2562 .force = dw_hdmi_connector_force, 2563 .reset = drm_atomic_helper_connector_reset, 2564 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2565 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2566 }; 2567 2568 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 2569 .get_modes = dw_hdmi_connector_get_modes, 2570 .atomic_check = dw_hdmi_connector_atomic_check, 2571 }; 2572 2573 static int dw_hdmi_connector_create(struct dw_hdmi *hdmi) 2574 { 2575 struct drm_connector *connector = &hdmi->connector; 2576 struct cec_connector_info conn_info; 2577 struct cec_notifier *notifier; 2578 2579 if (hdmi->version >= 0x200a) 2580 connector->ycbcr_420_allowed = 2581 hdmi->plat_data->ycbcr_420_allowed; 2582 else 2583 connector->ycbcr_420_allowed = false; 2584 2585 connector->interlace_allowed = 1; 2586 connector->polled = DRM_CONNECTOR_POLL_HPD; 2587 2588 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 2589 2590 drm_connector_init_with_ddc(hdmi->bridge.dev, connector, 2591 &dw_hdmi_connector_funcs, 2592 DRM_MODE_CONNECTOR_HDMIA, 2593 hdmi->ddc); 2594 2595 /* 2596 * drm_connector_attach_max_bpc_property() requires the 2597 * connector to have a state. 2598 */ 2599 drm_atomic_helper_connector_reset(connector); 2600 2601 drm_connector_attach_max_bpc_property(connector, 8, 16); 2602 2603 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) 2604 drm_connector_attach_hdr_output_metadata_property(connector); 2605 2606 drm_connector_attach_encoder(connector, hdmi->bridge.encoder); 2607 2608 cec_fill_conn_info_from_drm(&conn_info, connector); 2609 2610 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info); 2611 if (!notifier) 2612 return -ENOMEM; 2613 2614 mutex_lock(&hdmi->cec_notifier_mutex); 2615 hdmi->cec_notifier = notifier; 2616 mutex_unlock(&hdmi->cec_notifier_mutex); 2617 2618 return 0; 2619 } 2620 2621 /* ----------------------------------------------------------------------------- 2622 * DRM Bridge Operations 2623 */ 2624 2625 /* 2626 * Possible output formats : 2627 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48, 2628 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36, 2629 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30, 2630 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24, 2631 * - MEDIA_BUS_FMT_RGB888_1X24, 2632 * - MEDIA_BUS_FMT_YUV16_1X48, 2633 * - MEDIA_BUS_FMT_RGB161616_1X48, 2634 * - MEDIA_BUS_FMT_UYVY12_1X24, 2635 * - MEDIA_BUS_FMT_YUV12_1X36, 2636 * - MEDIA_BUS_FMT_RGB121212_1X36, 2637 * - MEDIA_BUS_FMT_UYVY10_1X20, 2638 * - MEDIA_BUS_FMT_YUV10_1X30, 2639 * - MEDIA_BUS_FMT_RGB101010_1X30, 2640 * - MEDIA_BUS_FMT_UYVY8_1X16, 2641 * - MEDIA_BUS_FMT_YUV8_1X24, 2642 */ 2643 2644 /* Can return a maximum of 11 possible output formats for a mode/connector */ 2645 #define MAX_OUTPUT_SEL_FORMATS 11 2646 2647 static u32 *dw_hdmi_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 2648 struct drm_bridge_state *bridge_state, 2649 struct drm_crtc_state *crtc_state, 2650 struct drm_connector_state *conn_state, 2651 unsigned int *num_output_fmts) 2652 { 2653 struct drm_connector *conn = conn_state->connector; 2654 struct drm_display_info *info = &conn->display_info; 2655 struct drm_display_mode *mode = &crtc_state->mode; 2656 u8 max_bpc = conn_state->max_requested_bpc; 2657 bool is_hdmi2_sink = info->hdmi.scdc.supported || 2658 (info->color_formats & DRM_COLOR_FORMAT_YCBCR420); 2659 u32 *output_fmts; 2660 unsigned int i = 0; 2661 2662 *num_output_fmts = 0; 2663 2664 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), 2665 GFP_KERNEL); 2666 if (!output_fmts) 2667 return NULL; 2668 2669 /* If dw-hdmi is the first or only bridge, avoid negociating with ourselves */ 2670 if (list_is_singular(&bridge->encoder->bridge_chain) || 2671 list_is_first(&bridge->chain_node, &bridge->encoder->bridge_chain)) { 2672 *num_output_fmts = 1; 2673 output_fmts[0] = MEDIA_BUS_FMT_FIXED; 2674 2675 return output_fmts; 2676 } 2677 2678 /* 2679 * If the current mode enforces 4:2:0, force the output bus format 2680 * to 4:2:0 and do not add the YUV422/444/RGB formats 2681 */ 2682 if (conn->ycbcr_420_allowed && 2683 (drm_mode_is_420_only(info, mode) || 2684 (is_hdmi2_sink && drm_mode_is_420_also(info, mode)))) { 2685 2686 /* Order bus formats from 16bit to 8bit if supported */ 2687 if (max_bpc >= 16 && info->bpc == 16 && 2688 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_48)) 2689 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY16_0_5X48; 2690 2691 if (max_bpc >= 12 && info->bpc >= 12 && 2692 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_36)) 2693 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY12_0_5X36; 2694 2695 if (max_bpc >= 10 && info->bpc >= 10 && 2696 (info->hdmi.y420_dc_modes & DRM_EDID_YCBCR420_DC_30)) 2697 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY10_0_5X30; 2698 2699 /* Default 8bit fallback */ 2700 output_fmts[i++] = MEDIA_BUS_FMT_UYYVYY8_0_5X24; 2701 2702 if (drm_mode_is_420_only(info, mode)) { 2703 *num_output_fmts = i; 2704 return output_fmts; 2705 } 2706 } 2707 2708 /* 2709 * Order bus formats from 16bit to 8bit and from YUV422 to RGB 2710 * if supported. In any case the default RGB888 format is added 2711 */ 2712 2713 /* Default 8bit RGB fallback */ 2714 output_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2715 2716 if (max_bpc >= 16 && info->bpc == 16) { 2717 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2718 output_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2719 2720 output_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2721 } 2722 2723 if (max_bpc >= 12 && info->bpc >= 12) { 2724 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) 2725 output_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2726 2727 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2728 output_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2729 2730 output_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2731 } 2732 2733 if (max_bpc >= 10 && info->bpc >= 10) { 2734 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) 2735 output_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2736 2737 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2738 output_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2739 2740 output_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2741 } 2742 2743 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR422) 2744 output_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2745 2746 if (info->color_formats & DRM_COLOR_FORMAT_YCBCR444) 2747 output_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2748 2749 *num_output_fmts = i; 2750 2751 return output_fmts; 2752 } 2753 2754 /* 2755 * Possible input formats : 2756 * - MEDIA_BUS_FMT_RGB888_1X24 2757 * - MEDIA_BUS_FMT_YUV8_1X24 2758 * - MEDIA_BUS_FMT_UYVY8_1X16 2759 * - MEDIA_BUS_FMT_UYYVYY8_0_5X24 2760 * - MEDIA_BUS_FMT_RGB101010_1X30 2761 * - MEDIA_BUS_FMT_YUV10_1X30 2762 * - MEDIA_BUS_FMT_UYVY10_1X20 2763 * - MEDIA_BUS_FMT_UYYVYY10_0_5X30 2764 * - MEDIA_BUS_FMT_RGB121212_1X36 2765 * - MEDIA_BUS_FMT_YUV12_1X36 2766 * - MEDIA_BUS_FMT_UYVY12_1X24 2767 * - MEDIA_BUS_FMT_UYYVYY12_0_5X36 2768 * - MEDIA_BUS_FMT_RGB161616_1X48 2769 * - MEDIA_BUS_FMT_YUV16_1X48 2770 * - MEDIA_BUS_FMT_UYYVYY16_0_5X48 2771 */ 2772 2773 /* Can return a maximum of 3 possible input formats for an output format */ 2774 #define MAX_INPUT_SEL_FORMATS 3 2775 2776 static u32 *dw_hdmi_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 2777 struct drm_bridge_state *bridge_state, 2778 struct drm_crtc_state *crtc_state, 2779 struct drm_connector_state *conn_state, 2780 u32 output_fmt, 2781 unsigned int *num_input_fmts) 2782 { 2783 u32 *input_fmts; 2784 unsigned int i = 0; 2785 2786 *num_input_fmts = 0; 2787 2788 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 2789 GFP_KERNEL); 2790 if (!input_fmts) 2791 return NULL; 2792 2793 switch (output_fmt) { 2794 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */ 2795 case MEDIA_BUS_FMT_FIXED: 2796 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2797 break; 2798 /* 8bit */ 2799 case MEDIA_BUS_FMT_RGB888_1X24: 2800 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2801 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2802 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2803 break; 2804 case MEDIA_BUS_FMT_YUV8_1X24: 2805 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2806 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2807 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2808 break; 2809 case MEDIA_BUS_FMT_UYVY8_1X16: 2810 input_fmts[i++] = MEDIA_BUS_FMT_UYVY8_1X16; 2811 input_fmts[i++] = MEDIA_BUS_FMT_YUV8_1X24; 2812 input_fmts[i++] = MEDIA_BUS_FMT_RGB888_1X24; 2813 break; 2814 2815 /* 10bit */ 2816 case MEDIA_BUS_FMT_RGB101010_1X30: 2817 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2818 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2819 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2820 break; 2821 case MEDIA_BUS_FMT_YUV10_1X30: 2822 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2823 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2824 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2825 break; 2826 case MEDIA_BUS_FMT_UYVY10_1X20: 2827 input_fmts[i++] = MEDIA_BUS_FMT_UYVY10_1X20; 2828 input_fmts[i++] = MEDIA_BUS_FMT_YUV10_1X30; 2829 input_fmts[i++] = MEDIA_BUS_FMT_RGB101010_1X30; 2830 break; 2831 2832 /* 12bit */ 2833 case MEDIA_BUS_FMT_RGB121212_1X36: 2834 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2835 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2836 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2837 break; 2838 case MEDIA_BUS_FMT_YUV12_1X36: 2839 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2840 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2841 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2842 break; 2843 case MEDIA_BUS_FMT_UYVY12_1X24: 2844 input_fmts[i++] = MEDIA_BUS_FMT_UYVY12_1X24; 2845 input_fmts[i++] = MEDIA_BUS_FMT_YUV12_1X36; 2846 input_fmts[i++] = MEDIA_BUS_FMT_RGB121212_1X36; 2847 break; 2848 2849 /* 16bit */ 2850 case MEDIA_BUS_FMT_RGB161616_1X48: 2851 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2852 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2853 break; 2854 case MEDIA_BUS_FMT_YUV16_1X48: 2855 input_fmts[i++] = MEDIA_BUS_FMT_YUV16_1X48; 2856 input_fmts[i++] = MEDIA_BUS_FMT_RGB161616_1X48; 2857 break; 2858 2859 /*YUV 4:2:0 */ 2860 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 2861 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 2862 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 2863 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 2864 input_fmts[i++] = output_fmt; 2865 break; 2866 } 2867 2868 *num_input_fmts = i; 2869 2870 if (*num_input_fmts == 0) { 2871 kfree(input_fmts); 2872 input_fmts = NULL; 2873 } 2874 2875 return input_fmts; 2876 } 2877 2878 static int dw_hdmi_bridge_atomic_check(struct drm_bridge *bridge, 2879 struct drm_bridge_state *bridge_state, 2880 struct drm_crtc_state *crtc_state, 2881 struct drm_connector_state *conn_state) 2882 { 2883 struct dw_hdmi *hdmi = bridge->driver_private; 2884 2885 hdmi->hdmi_data.enc_out_bus_format = 2886 bridge_state->output_bus_cfg.format; 2887 2888 hdmi->hdmi_data.enc_in_bus_format = 2889 bridge_state->input_bus_cfg.format; 2890 2891 dev_dbg(hdmi->dev, "input format 0x%04x, output format 0x%04x\n", 2892 bridge_state->input_bus_cfg.format, 2893 bridge_state->output_bus_cfg.format); 2894 2895 return 0; 2896 } 2897 2898 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge, 2899 struct drm_encoder *encoder, 2900 enum drm_bridge_attach_flags flags) 2901 { 2902 struct dw_hdmi *hdmi = bridge->driver_private; 2903 2904 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 2905 return drm_bridge_attach(encoder, hdmi->next_bridge, 2906 bridge, flags); 2907 2908 return dw_hdmi_connector_create(hdmi); 2909 } 2910 2911 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge) 2912 { 2913 struct dw_hdmi *hdmi = bridge->driver_private; 2914 2915 mutex_lock(&hdmi->cec_notifier_mutex); 2916 cec_notifier_conn_unregister(hdmi->cec_notifier); 2917 hdmi->cec_notifier = NULL; 2918 mutex_unlock(&hdmi->cec_notifier_mutex); 2919 } 2920 2921 static enum drm_mode_status 2922 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 2923 const struct drm_display_info *info, 2924 const struct drm_display_mode *mode) 2925 { 2926 struct dw_hdmi *hdmi = bridge->driver_private; 2927 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 2928 enum drm_mode_status mode_status = MODE_OK; 2929 2930 /* We don't support double-clocked modes */ 2931 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2932 return MODE_BAD; 2933 2934 if (pdata->mode_valid) 2935 mode_status = pdata->mode_valid(hdmi, pdata->priv_data, info, 2936 mode); 2937 2938 return mode_status; 2939 } 2940 2941 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2942 const struct drm_display_mode *orig_mode, 2943 const struct drm_display_mode *mode) 2944 { 2945 struct dw_hdmi *hdmi = bridge->driver_private; 2946 2947 mutex_lock(&hdmi->mutex); 2948 2949 /* Store the display mode for plugin/DKMS poweron events */ 2950 drm_mode_copy(&hdmi->previous_mode, mode); 2951 2952 mutex_unlock(&hdmi->mutex); 2953 } 2954 2955 static void dw_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, 2956 struct drm_atomic_state *state) 2957 { 2958 struct dw_hdmi *hdmi = bridge->driver_private; 2959 2960 mutex_lock(&hdmi->mutex); 2961 hdmi->disabled = true; 2962 hdmi->curr_conn = NULL; 2963 dw_hdmi_update_power(hdmi); 2964 dw_hdmi_update_phy_mask(hdmi); 2965 handle_plugged_change(hdmi, false); 2966 mutex_unlock(&hdmi->mutex); 2967 } 2968 2969 static void dw_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, 2970 struct drm_atomic_state *state) 2971 { 2972 struct dw_hdmi *hdmi = bridge->driver_private; 2973 struct drm_connector *connector; 2974 2975 connector = drm_atomic_get_new_connector_for_encoder(state, 2976 bridge->encoder); 2977 2978 mutex_lock(&hdmi->mutex); 2979 hdmi->disabled = false; 2980 hdmi->curr_conn = connector; 2981 dw_hdmi_update_power(hdmi); 2982 dw_hdmi_update_phy_mask(hdmi); 2983 handle_plugged_change(hdmi, true); 2984 mutex_unlock(&hdmi->mutex); 2985 } 2986 2987 static enum drm_connector_status 2988 dw_hdmi_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 2989 { 2990 struct dw_hdmi *hdmi = bridge->driver_private; 2991 2992 return dw_hdmi_detect(hdmi); 2993 } 2994 2995 static const struct drm_edid *dw_hdmi_bridge_edid_read(struct drm_bridge *bridge, 2996 struct drm_connector *connector) 2997 { 2998 struct dw_hdmi *hdmi = bridge->driver_private; 2999 3000 return dw_hdmi_edid_read(hdmi, connector); 3001 } 3002 3003 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 3004 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 3005 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 3006 .atomic_reset = drm_atomic_helper_bridge_reset, 3007 .attach = dw_hdmi_bridge_attach, 3008 .detach = dw_hdmi_bridge_detach, 3009 .atomic_check = dw_hdmi_bridge_atomic_check, 3010 .atomic_get_output_bus_fmts = dw_hdmi_bridge_atomic_get_output_bus_fmts, 3011 .atomic_get_input_bus_fmts = dw_hdmi_bridge_atomic_get_input_bus_fmts, 3012 .atomic_enable = dw_hdmi_bridge_atomic_enable, 3013 .atomic_disable = dw_hdmi_bridge_atomic_disable, 3014 .mode_set = dw_hdmi_bridge_mode_set, 3015 .mode_valid = dw_hdmi_bridge_mode_valid, 3016 .detect = dw_hdmi_bridge_detect, 3017 .edid_read = dw_hdmi_bridge_edid_read, 3018 }; 3019 3020 /* ----------------------------------------------------------------------------- 3021 * IRQ Handling 3022 */ 3023 3024 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 3025 { 3026 struct dw_hdmi_i2c *i2c = hdmi->i2c; 3027 unsigned int stat; 3028 3029 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 3030 if (!stat) 3031 return IRQ_NONE; 3032 3033 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 3034 3035 i2c->stat = stat; 3036 3037 complete(&i2c->cmp); 3038 3039 return IRQ_HANDLED; 3040 } 3041 3042 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 3043 { 3044 struct dw_hdmi *hdmi = dev_id; 3045 u8 intr_stat; 3046 irqreturn_t ret = IRQ_NONE; 3047 3048 if (hdmi->i2c) 3049 ret = dw_hdmi_i2c_irq(hdmi); 3050 3051 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 3052 if (intr_stat) { 3053 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 3054 return IRQ_WAKE_THREAD; 3055 } 3056 3057 return ret; 3058 } 3059 3060 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 3061 { 3062 mutex_lock(&hdmi->mutex); 3063 3064 if (!hdmi->force) { 3065 /* 3066 * If the RX sense status indicates we're disconnected, 3067 * clear the software rxsense status. 3068 */ 3069 if (!rx_sense) 3070 hdmi->rxsense = false; 3071 3072 /* 3073 * Only set the software rxsense status when both 3074 * rxsense and hpd indicates we're connected. 3075 * This avoids what seems to be bad behaviour in 3076 * at least iMX6S versions of the phy. 3077 */ 3078 if (hpd) 3079 hdmi->rxsense = true; 3080 3081 dw_hdmi_update_power(hdmi); 3082 dw_hdmi_update_phy_mask(hdmi); 3083 } 3084 mutex_unlock(&hdmi->mutex); 3085 } 3086 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 3087 3088 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 3089 { 3090 struct dw_hdmi *hdmi = dev_id; 3091 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 3092 enum drm_connector_status status = connector_status_unknown; 3093 3094 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 3095 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 3096 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 3097 3098 phy_pol_mask = 0; 3099 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 3100 phy_pol_mask |= HDMI_PHY_HPD; 3101 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 3102 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 3103 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 3104 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 3105 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 3106 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 3107 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 3108 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 3109 3110 if (phy_pol_mask) 3111 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 3112 3113 /* 3114 * RX sense tells us whether the TDMS transmitters are detecting 3115 * load - in other words, there's something listening on the 3116 * other end of the link. Use this to decide whether we should 3117 * power on the phy as HPD may be toggled by the sink to merely 3118 * ask the source to re-read the EDID. 3119 */ 3120 if (intr_stat & 3121 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 3122 dw_hdmi_setup_rx_sense(hdmi, 3123 phy_stat & HDMI_PHY_HPD, 3124 phy_stat & HDMI_PHY_RX_SENSE); 3125 3126 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { 3127 mutex_lock(&hdmi->cec_notifier_mutex); 3128 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); 3129 mutex_unlock(&hdmi->cec_notifier_mutex); 3130 } 3131 3132 if (phy_stat & HDMI_PHY_HPD) 3133 status = connector_status_connected; 3134 3135 if (!(phy_stat & (HDMI_PHY_HPD | HDMI_PHY_RX_SENSE))) 3136 status = connector_status_disconnected; 3137 } 3138 3139 if (status != connector_status_unknown) { 3140 dev_dbg(hdmi->dev, "EVENT=%s\n", 3141 status == connector_status_connected ? 3142 "plugin" : "plugout"); 3143 3144 if (hdmi->bridge.dev) { 3145 drm_helper_hpd_irq_event(hdmi->bridge.dev); 3146 drm_bridge_hpd_notify(&hdmi->bridge, status); 3147 } 3148 } 3149 3150 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 3151 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 3152 HDMI_IH_MUTE_PHY_STAT0); 3153 3154 return IRQ_HANDLED; 3155 } 3156 3157 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 3158 { 3159 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 3160 .name = "DWC HDMI TX PHY", 3161 .gen = 1, 3162 }, { 3163 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 3164 .name = "DWC MHL PHY + HEAC PHY", 3165 .gen = 2, 3166 .has_svsret = true, 3167 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3168 }, { 3169 .type = DW_HDMI_PHY_DWC_MHL_PHY, 3170 .name = "DWC MHL PHY", 3171 .gen = 2, 3172 .has_svsret = true, 3173 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3174 }, { 3175 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 3176 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 3177 .gen = 2, 3178 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3179 }, { 3180 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 3181 .name = "DWC HDMI 3D TX PHY", 3182 .gen = 2, 3183 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3184 }, { 3185 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 3186 .name = "DWC HDMI 2.0 TX PHY", 3187 .gen = 2, 3188 .has_svsret = true, 3189 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 3190 }, { 3191 .type = DW_HDMI_PHY_VENDOR_PHY, 3192 .name = "Vendor PHY", 3193 } 3194 }; 3195 3196 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 3197 { 3198 unsigned int i; 3199 u8 phy_type; 3200 3201 phy_type = hdmi->plat_data->phy_force_vendor ? 3202 DW_HDMI_PHY_VENDOR_PHY : 3203 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 3204 3205 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 3206 /* Vendor PHYs require support from the glue layer. */ 3207 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 3208 dev_err(hdmi->dev, 3209 "Vendor HDMI PHY not supported by glue layer\n"); 3210 return -ENODEV; 3211 } 3212 3213 hdmi->phy.ops = hdmi->plat_data->phy_ops; 3214 hdmi->phy.data = hdmi->plat_data->phy_data; 3215 hdmi->phy.name = hdmi->plat_data->phy_name; 3216 return 0; 3217 } 3218 3219 /* Synopsys PHYs are handled internally. */ 3220 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 3221 if (dw_hdmi_phys[i].type == phy_type) { 3222 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 3223 hdmi->phy.name = dw_hdmi_phys[i].name; 3224 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 3225 3226 if (!dw_hdmi_phys[i].configure && 3227 !hdmi->plat_data->configure_phy) { 3228 dev_err(hdmi->dev, "%s requires platform support\n", 3229 hdmi->phy.name); 3230 return -ENODEV; 3231 } 3232 3233 return 0; 3234 } 3235 } 3236 3237 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 3238 return -ENODEV; 3239 } 3240 3241 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 3242 { 3243 mutex_lock(&hdmi->mutex); 3244 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 3245 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 3246 mutex_unlock(&hdmi->mutex); 3247 } 3248 3249 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 3250 { 3251 mutex_lock(&hdmi->mutex); 3252 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 3253 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 3254 mutex_unlock(&hdmi->mutex); 3255 } 3256 3257 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 3258 .write = hdmi_writeb, 3259 .read = hdmi_readb, 3260 .enable = dw_hdmi_cec_enable, 3261 .disable = dw_hdmi_cec_disable, 3262 }; 3263 3264 static const struct regmap_config hdmi_regmap_8bit_config = { 3265 .reg_bits = 32, 3266 .val_bits = 8, 3267 .reg_stride = 1, 3268 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 3269 }; 3270 3271 static const struct regmap_config hdmi_regmap_32bit_config = { 3272 .reg_bits = 32, 3273 .val_bits = 32, 3274 .reg_stride = 4, 3275 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 3276 }; 3277 3278 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi) 3279 { 3280 initialize_hdmi_ih_mutes(hdmi); 3281 3282 /* 3283 * Reset HDMI DDC I2C master controller and mute I2CM interrupts. 3284 * Even if we are using a separate i2c adapter doing this doesn't 3285 * hurt. 3286 */ 3287 dw_hdmi_i2c_init(hdmi); 3288 3289 if (hdmi->phy.ops->setup_hpd) 3290 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 3291 } 3292 3293 /* ----------------------------------------------------------------------------- 3294 * Probe/remove API, used from platforms based on the DRM bridge API. 3295 */ 3296 3297 static int dw_hdmi_parse_dt(struct dw_hdmi *hdmi) 3298 { 3299 struct device_node *remote; 3300 3301 if (!hdmi->plat_data->output_port) 3302 return 0; 3303 3304 3305 remote = of_graph_get_remote_node(hdmi->dev->of_node, 3306 hdmi->plat_data->output_port, 3307 -1); 3308 if (!remote) 3309 return -ENODEV; 3310 3311 hdmi->next_bridge = of_drm_find_bridge(remote); 3312 of_node_put(remote); 3313 if (!hdmi->next_bridge) 3314 return -EPROBE_DEFER; 3315 3316 return 0; 3317 } 3318 3319 bool dw_hdmi_bus_fmt_is_420(struct dw_hdmi *hdmi) 3320 { 3321 return hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format); 3322 } 3323 EXPORT_SYMBOL_GPL(dw_hdmi_bus_fmt_is_420); 3324 3325 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 3326 const struct dw_hdmi_plat_data *plat_data) 3327 { 3328 struct device *dev = &pdev->dev; 3329 struct device_node *np = dev->of_node; 3330 struct platform_device_info pdevinfo; 3331 struct device_node *ddc_node; 3332 struct dw_hdmi_cec_data cec; 3333 struct dw_hdmi *hdmi; 3334 struct clk *clk; 3335 struct resource *iores = NULL; 3336 int irq; 3337 int ret; 3338 u32 val = 1; 3339 u8 prod_id0; 3340 u8 prod_id1; 3341 u8 config0; 3342 u8 config3; 3343 3344 hdmi = devm_drm_bridge_alloc(dev, struct dw_hdmi, bridge, &dw_hdmi_bridge_funcs); 3345 if (IS_ERR(hdmi)) 3346 return hdmi; 3347 3348 hdmi->plat_data = plat_data; 3349 hdmi->dev = dev; 3350 hdmi->sample_rate = 48000; 3351 hdmi->channels = 2; 3352 hdmi->disabled = true; 3353 hdmi->rxsense = true; 3354 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 3355 hdmi->mc_clkdis = 0x7f; 3356 hdmi->last_connector_result = connector_status_disconnected; 3357 3358 mutex_init(&hdmi->mutex); 3359 mutex_init(&hdmi->audio_mutex); 3360 mutex_init(&hdmi->cec_notifier_mutex); 3361 spin_lock_init(&hdmi->audio_lock); 3362 3363 ret = dw_hdmi_parse_dt(hdmi); 3364 if (ret < 0) 3365 return ERR_PTR(ret); 3366 3367 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 3368 if (ddc_node) { 3369 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 3370 of_node_put(ddc_node); 3371 if (!hdmi->ddc) { 3372 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 3373 return ERR_PTR(-EPROBE_DEFER); 3374 } 3375 3376 } else { 3377 dev_dbg(hdmi->dev, "no ddc property found\n"); 3378 } 3379 3380 if (!plat_data->regm) { 3381 const struct regmap_config *reg_config; 3382 3383 of_property_read_u32(np, "reg-io-width", &val); 3384 switch (val) { 3385 case 4: 3386 reg_config = &hdmi_regmap_32bit_config; 3387 hdmi->reg_shift = 2; 3388 break; 3389 case 1: 3390 reg_config = &hdmi_regmap_8bit_config; 3391 break; 3392 default: 3393 dev_err(dev, "reg-io-width must be 1 or 4\n"); 3394 return ERR_PTR(-EINVAL); 3395 } 3396 3397 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 3398 hdmi->regs = devm_ioremap_resource(dev, iores); 3399 if (IS_ERR(hdmi->regs)) { 3400 ret = PTR_ERR(hdmi->regs); 3401 goto err_res; 3402 } 3403 3404 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 3405 if (IS_ERR(hdmi->regm)) { 3406 dev_err(dev, "Failed to configure regmap\n"); 3407 ret = PTR_ERR(hdmi->regm); 3408 goto err_res; 3409 } 3410 } else { 3411 hdmi->regm = plat_data->regm; 3412 } 3413 3414 clk = devm_clk_get_enabled(hdmi->dev, "isfr"); 3415 if (IS_ERR(clk)) { 3416 ret = PTR_ERR(clk); 3417 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 3418 goto err_res; 3419 } 3420 3421 clk = devm_clk_get_enabled(hdmi->dev, "iahb"); 3422 if (IS_ERR(clk)) { 3423 ret = PTR_ERR(clk); 3424 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 3425 goto err_res; 3426 } 3427 3428 clk = devm_clk_get_optional_enabled(hdmi->dev, "cec"); 3429 if (IS_ERR(clk)) { 3430 ret = PTR_ERR(clk); 3431 if (ret != -EPROBE_DEFER) 3432 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 3433 ret); 3434 goto err_res; 3435 } 3436 3437 /* Product and revision IDs */ 3438 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 3439 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 3440 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 3441 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 3442 3443 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 3444 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 3445 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 3446 hdmi->version, prod_id0, prod_id1); 3447 ret = -ENODEV; 3448 goto err_res; 3449 } 3450 3451 ret = dw_hdmi_detect_phy(hdmi); 3452 if (ret < 0) 3453 goto err_res; 3454 3455 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 3456 hdmi->version >> 12, hdmi->version & 0xfff, 3457 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 3458 hdmi->phy.name); 3459 3460 dw_hdmi_init_hw(hdmi); 3461 3462 irq = platform_get_irq(pdev, 0); 3463 if (irq < 0) { 3464 ret = irq; 3465 goto err_res; 3466 } 3467 3468 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 3469 dw_hdmi_irq, IRQF_SHARED, 3470 dev_name(dev), hdmi); 3471 if (ret) 3472 goto err_res; 3473 3474 /* 3475 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 3476 * N and cts values before enabling phy 3477 */ 3478 hdmi_init_clk_regenerator(hdmi); 3479 3480 /* If DDC bus is not specified, try to register HDMI I2C bus */ 3481 if (!hdmi->ddc) { 3482 /* Look for (optional) stuff related to unwedging */ 3483 hdmi->pinctrl = devm_pinctrl_get(dev); 3484 if (!IS_ERR(hdmi->pinctrl)) { 3485 hdmi->unwedge_state = 3486 pinctrl_lookup_state(hdmi->pinctrl, "unwedge"); 3487 hdmi->default_state = 3488 pinctrl_lookup_state(hdmi->pinctrl, "default"); 3489 3490 if (IS_ERR(hdmi->default_state) || 3491 IS_ERR(hdmi->unwedge_state)) { 3492 if (!IS_ERR(hdmi->unwedge_state)) 3493 dev_warn(dev, 3494 "Unwedge requires default pinctrl\n"); 3495 hdmi->default_state = NULL; 3496 hdmi->unwedge_state = NULL; 3497 } 3498 } 3499 3500 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 3501 if (IS_ERR(hdmi->ddc)) 3502 hdmi->ddc = NULL; 3503 } 3504 3505 hdmi->bridge.driver_private = hdmi; 3506 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID 3507 | DRM_BRIDGE_OP_HPD; 3508 hdmi->bridge.interlace_allowed = true; 3509 hdmi->bridge.ddc = hdmi->ddc; 3510 hdmi->bridge.of_node = pdev->dev.of_node; 3511 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 3512 3513 if (hdmi->version >= 0x200a) 3514 hdmi->bridge.ycbcr_420_allowed = plat_data->ycbcr_420_allowed; 3515 3516 memset(&pdevinfo, 0, sizeof(pdevinfo)); 3517 pdevinfo.parent = dev; 3518 pdevinfo.id = PLATFORM_DEVID_AUTO; 3519 3520 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 3521 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 3522 3523 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 3524 struct dw_hdmi_audio_data audio; 3525 3526 audio.phys = iores->start; 3527 audio.base = hdmi->regs; 3528 audio.irq = irq; 3529 audio.hdmi = hdmi; 3530 audio.get_eld = hdmi_audio_get_eld; 3531 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 3532 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 3533 3534 pdevinfo.name = "dw-hdmi-ahb-audio"; 3535 pdevinfo.data = &audio; 3536 pdevinfo.size_data = sizeof(audio); 3537 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3538 hdmi->audio = platform_device_register_full(&pdevinfo); 3539 } else if (config0 & HDMI_CONFIG0_I2S) { 3540 struct dw_hdmi_i2s_audio_data audio; 3541 3542 audio.hdmi = hdmi; 3543 audio.get_eld = hdmi_audio_get_eld; 3544 audio.write = hdmi_writeb; 3545 audio.read = hdmi_readb; 3546 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 3547 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 3548 3549 pdevinfo.name = "dw-hdmi-i2s-audio"; 3550 pdevinfo.data = &audio; 3551 pdevinfo.size_data = sizeof(audio); 3552 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3553 hdmi->audio = platform_device_register_full(&pdevinfo); 3554 } else if (iores && config3 & HDMI_CONFIG3_GPAUD) { 3555 struct dw_hdmi_audio_data audio; 3556 3557 audio.phys = iores->start; 3558 audio.base = hdmi->regs; 3559 audio.irq = irq; 3560 audio.hdmi = hdmi; 3561 audio.get_eld = hdmi_audio_get_eld; 3562 3563 hdmi->enable_audio = dw_hdmi_gp_audio_enable; 3564 hdmi->disable_audio = dw_hdmi_gp_audio_disable; 3565 3566 pdevinfo.name = "dw-hdmi-gp-audio"; 3567 pdevinfo.id = PLATFORM_DEVID_NONE; 3568 pdevinfo.data = &audio; 3569 pdevinfo.size_data = sizeof(audio); 3570 pdevinfo.dma_mask = DMA_BIT_MASK(32); 3571 hdmi->audio = platform_device_register_full(&pdevinfo); 3572 } 3573 3574 if (!plat_data->disable_cec && (config0 & HDMI_CONFIG0_CEC)) { 3575 cec.hdmi = hdmi; 3576 cec.ops = &dw_hdmi_cec_ops; 3577 cec.irq = irq; 3578 3579 pdevinfo.name = "dw-hdmi-cec"; 3580 pdevinfo.data = &cec; 3581 pdevinfo.size_data = sizeof(cec); 3582 pdevinfo.dma_mask = 0; 3583 3584 hdmi->cec = platform_device_register_full(&pdevinfo); 3585 } 3586 3587 drm_bridge_add(&hdmi->bridge); 3588 3589 return hdmi; 3590 3591 err_res: 3592 i2c_put_adapter(hdmi->ddc); 3593 3594 return ERR_PTR(ret); 3595 } 3596 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 3597 3598 void dw_hdmi_remove(struct dw_hdmi *hdmi) 3599 { 3600 drm_bridge_remove(&hdmi->bridge); 3601 3602 if (hdmi->audio && !IS_ERR(hdmi->audio)) 3603 platform_device_unregister(hdmi->audio); 3604 if (!IS_ERR(hdmi->cec)) 3605 platform_device_unregister(hdmi->cec); 3606 3607 /* Disable all interrupts */ 3608 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 3609 3610 if (hdmi->i2c) 3611 i2c_del_adapter(&hdmi->i2c->adap); 3612 else 3613 i2c_put_adapter(hdmi->ddc); 3614 } 3615 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 3616 3617 /* ----------------------------------------------------------------------------- 3618 * Bind/unbind API, used from platforms based on the component framework. 3619 */ 3620 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 3621 struct drm_encoder *encoder, 3622 const struct dw_hdmi_plat_data *plat_data) 3623 { 3624 struct dw_hdmi *hdmi; 3625 int ret; 3626 3627 hdmi = dw_hdmi_probe(pdev, plat_data); 3628 if (IS_ERR(hdmi)) 3629 return hdmi; 3630 3631 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 0); 3632 if (ret) { 3633 dw_hdmi_remove(hdmi); 3634 return ERR_PTR(ret); 3635 } 3636 3637 return hdmi; 3638 } 3639 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 3640 3641 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 3642 { 3643 dw_hdmi_remove(hdmi); 3644 } 3645 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 3646 3647 void dw_hdmi_resume(struct dw_hdmi *hdmi) 3648 { 3649 dw_hdmi_init_hw(hdmi); 3650 } 3651 EXPORT_SYMBOL_GPL(dw_hdmi_resume); 3652 3653 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 3654 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 3655 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 3656 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 3657 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 3658 MODULE_LICENSE("GPL"); 3659 MODULE_ALIAS("platform:dw-hdmi"); 3660