1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * DesignWare High-Definition Multimedia Interface (HDMI) driver 4 * 5 * Copyright (C) 2013-2015 Mentor Graphics Inc. 6 * Copyright (C) 2011-2013 Freescale Semiconductor, Inc. 7 * Copyright (C) 2010, Guennadi Liakhovetski <g.liakhovetski@gmx.de> 8 */ 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/err.h> 12 #include <linux/hdmi.h> 13 #include <linux/irq.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of_device.h> 17 #include <linux/pinctrl/consumer.h> 18 #include <linux/regmap.h> 19 #include <linux/dma-mapping.h> 20 #include <linux/spinlock.h> 21 22 #include <media/cec-notifier.h> 23 24 #include <uapi/linux/media-bus-format.h> 25 #include <uapi/linux/videodev2.h> 26 27 #include <drm/bridge/dw_hdmi.h> 28 #include <drm/drm_atomic.h> 29 #include <drm/drm_atomic_helper.h> 30 #include <drm/drm_bridge.h> 31 #include <drm/drm_edid.h> 32 #include <drm/drm_of.h> 33 #include <drm/drm_print.h> 34 #include <drm/drm_probe_helper.h> 35 #include <drm/drm_scdc_helper.h> 36 37 #include "dw-hdmi-audio.h" 38 #include "dw-hdmi-cec.h" 39 #include "dw-hdmi.h" 40 41 #define DDC_CI_ADDR 0x37 42 #define DDC_SEGMENT_ADDR 0x30 43 44 #define HDMI_EDID_LEN 512 45 46 /* DW-HDMI Controller >= 0x200a are at least compliant with SCDC version 1 */ 47 #define SCDC_MIN_SOURCE_VERSION 0x1 48 49 #define HDMI14_MAX_TMDSCLK 340000000 50 51 enum hdmi_datamap { 52 RGB444_8B = 0x01, 53 RGB444_10B = 0x03, 54 RGB444_12B = 0x05, 55 RGB444_16B = 0x07, 56 YCbCr444_8B = 0x09, 57 YCbCr444_10B = 0x0B, 58 YCbCr444_12B = 0x0D, 59 YCbCr444_16B = 0x0F, 60 YCbCr422_8B = 0x16, 61 YCbCr422_10B = 0x14, 62 YCbCr422_12B = 0x12, 63 }; 64 65 static const u16 csc_coeff_default[3][4] = { 66 { 0x2000, 0x0000, 0x0000, 0x0000 }, 67 { 0x0000, 0x2000, 0x0000, 0x0000 }, 68 { 0x0000, 0x0000, 0x2000, 0x0000 } 69 }; 70 71 static const u16 csc_coeff_rgb_out_eitu601[3][4] = { 72 { 0x2000, 0x6926, 0x74fd, 0x010e }, 73 { 0x2000, 0x2cdd, 0x0000, 0x7e9a }, 74 { 0x2000, 0x0000, 0x38b4, 0x7e3b } 75 }; 76 77 static const u16 csc_coeff_rgb_out_eitu709[3][4] = { 78 { 0x2000, 0x7106, 0x7a02, 0x00a7 }, 79 { 0x2000, 0x3264, 0x0000, 0x7e6d }, 80 { 0x2000, 0x0000, 0x3b61, 0x7e25 } 81 }; 82 83 static const u16 csc_coeff_rgb_in_eitu601[3][4] = { 84 { 0x2591, 0x1322, 0x074b, 0x0000 }, 85 { 0x6535, 0x2000, 0x7acc, 0x0200 }, 86 { 0x6acd, 0x7534, 0x2000, 0x0200 } 87 }; 88 89 static const u16 csc_coeff_rgb_in_eitu709[3][4] = { 90 { 0x2dc5, 0x0d9b, 0x049e, 0x0000 }, 91 { 0x62f0, 0x2000, 0x7d11, 0x0200 }, 92 { 0x6756, 0x78ab, 0x2000, 0x0200 } 93 }; 94 95 struct hdmi_vmode { 96 bool mdataenablepolarity; 97 98 unsigned int mpixelclock; 99 unsigned int mpixelrepetitioninput; 100 unsigned int mpixelrepetitionoutput; 101 unsigned int mtmdsclock; 102 }; 103 104 struct hdmi_data_info { 105 unsigned int enc_in_bus_format; 106 unsigned int enc_out_bus_format; 107 unsigned int enc_in_encoding; 108 unsigned int enc_out_encoding; 109 unsigned int pix_repet_factor; 110 unsigned int hdcp_enable; 111 struct hdmi_vmode video_mode; 112 }; 113 114 struct dw_hdmi_i2c { 115 struct i2c_adapter adap; 116 117 struct mutex lock; /* used to serialize data transfers */ 118 struct completion cmp; 119 u8 stat; 120 121 u8 slave_reg; 122 bool is_regaddr; 123 bool is_segment; 124 }; 125 126 struct dw_hdmi_phy_data { 127 enum dw_hdmi_phy_type type; 128 const char *name; 129 unsigned int gen; 130 bool has_svsret; 131 int (*configure)(struct dw_hdmi *hdmi, 132 const struct dw_hdmi_plat_data *pdata, 133 unsigned long mpixelclock); 134 }; 135 136 struct dw_hdmi { 137 struct drm_connector connector; 138 struct drm_bridge bridge; 139 140 unsigned int version; 141 142 struct platform_device *audio; 143 struct platform_device *cec; 144 struct device *dev; 145 struct clk *isfr_clk; 146 struct clk *iahb_clk; 147 struct clk *cec_clk; 148 struct dw_hdmi_i2c *i2c; 149 150 struct hdmi_data_info hdmi_data; 151 const struct dw_hdmi_plat_data *plat_data; 152 153 int vic; 154 155 u8 edid[HDMI_EDID_LEN]; 156 157 struct { 158 const struct dw_hdmi_phy_ops *ops; 159 const char *name; 160 void *data; 161 bool enabled; 162 } phy; 163 164 struct drm_display_mode previous_mode; 165 166 struct i2c_adapter *ddc; 167 void __iomem *regs; 168 bool sink_is_hdmi; 169 bool sink_has_audio; 170 171 struct pinctrl *pinctrl; 172 struct pinctrl_state *default_state; 173 struct pinctrl_state *unwedge_state; 174 175 struct mutex mutex; /* for state below and previous_mode */ 176 enum drm_connector_force force; /* mutex-protected force state */ 177 bool disabled; /* DRM has disabled our bridge */ 178 bool bridge_is_on; /* indicates the bridge is on */ 179 bool rxsense; /* rxsense state */ 180 u8 phy_mask; /* desired phy int mask settings */ 181 u8 mc_clkdis; /* clock disable register */ 182 183 spinlock_t audio_lock; 184 struct mutex audio_mutex; 185 unsigned int sample_rate; 186 unsigned int audio_cts; 187 unsigned int audio_n; 188 bool audio_enable; 189 190 unsigned int reg_shift; 191 struct regmap *regm; 192 void (*enable_audio)(struct dw_hdmi *hdmi); 193 void (*disable_audio)(struct dw_hdmi *hdmi); 194 195 struct mutex cec_notifier_mutex; 196 struct cec_notifier *cec_notifier; 197 }; 198 199 #define HDMI_IH_PHY_STAT0_RX_SENSE \ 200 (HDMI_IH_PHY_STAT0_RX_SENSE0 | HDMI_IH_PHY_STAT0_RX_SENSE1 | \ 201 HDMI_IH_PHY_STAT0_RX_SENSE2 | HDMI_IH_PHY_STAT0_RX_SENSE3) 202 203 #define HDMI_PHY_RX_SENSE \ 204 (HDMI_PHY_RX_SENSE0 | HDMI_PHY_RX_SENSE1 | \ 205 HDMI_PHY_RX_SENSE2 | HDMI_PHY_RX_SENSE3) 206 207 static inline void hdmi_writeb(struct dw_hdmi *hdmi, u8 val, int offset) 208 { 209 regmap_write(hdmi->regm, offset << hdmi->reg_shift, val); 210 } 211 212 static inline u8 hdmi_readb(struct dw_hdmi *hdmi, int offset) 213 { 214 unsigned int val = 0; 215 216 regmap_read(hdmi->regm, offset << hdmi->reg_shift, &val); 217 218 return val; 219 } 220 221 static void hdmi_modb(struct dw_hdmi *hdmi, u8 data, u8 mask, unsigned reg) 222 { 223 regmap_update_bits(hdmi->regm, reg << hdmi->reg_shift, mask, data); 224 } 225 226 static void hdmi_mask_writeb(struct dw_hdmi *hdmi, u8 data, unsigned int reg, 227 u8 shift, u8 mask) 228 { 229 hdmi_modb(hdmi, data << shift, mask, reg); 230 } 231 232 static void dw_hdmi_i2c_init(struct dw_hdmi *hdmi) 233 { 234 hdmi_writeb(hdmi, HDMI_PHY_I2CM_INT_ADDR_DONE_POL, 235 HDMI_PHY_I2CM_INT_ADDR); 236 237 hdmi_writeb(hdmi, HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL | 238 HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL, 239 HDMI_PHY_I2CM_CTLINT_ADDR); 240 241 /* Software reset */ 242 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_SOFTRSTZ); 243 244 /* Set Standard Mode speed (determined to be 100KHz on iMX6) */ 245 hdmi_writeb(hdmi, 0x00, HDMI_I2CM_DIV); 246 247 /* Set done, not acknowledged and arbitration interrupt polarities */ 248 hdmi_writeb(hdmi, HDMI_I2CM_INT_DONE_POL, HDMI_I2CM_INT); 249 hdmi_writeb(hdmi, HDMI_I2CM_CTLINT_NAC_POL | HDMI_I2CM_CTLINT_ARB_POL, 250 HDMI_I2CM_CTLINT); 251 252 /* Clear DONE and ERROR interrupts */ 253 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 254 HDMI_IH_I2CM_STAT0); 255 256 /* Mute DONE and ERROR interrupts */ 257 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 258 HDMI_IH_MUTE_I2CM_STAT0); 259 } 260 261 static bool dw_hdmi_i2c_unwedge(struct dw_hdmi *hdmi) 262 { 263 /* If no unwedge state then give up */ 264 if (!hdmi->unwedge_state) 265 return false; 266 267 dev_info(hdmi->dev, "Attempting to unwedge stuck i2c bus\n"); 268 269 /* 270 * This is a huge hack to workaround a problem where the dw_hdmi i2c 271 * bus could sometimes get wedged. Once wedged there doesn't appear 272 * to be any way to unwedge it (including the HDMI_I2CM_SOFTRSTZ) 273 * other than pulsing the SDA line. 274 * 275 * We appear to be able to pulse the SDA line (in the eyes of dw_hdmi) 276 * by: 277 * 1. Remux the pin as a GPIO output, driven low. 278 * 2. Wait a little while. 1 ms seems to work, but we'll do 10. 279 * 3. Immediately jump to remux the pin as dw_hdmi i2c again. 280 * 281 * At the moment of remuxing, the line will still be low due to its 282 * recent stint as an output, but then it will be pulled high by the 283 * (presumed) external pullup. dw_hdmi seems to see this as a rising 284 * edge and that seems to get it out of its jam. 285 * 286 * This wedging was only ever seen on one TV, and only on one of 287 * its HDMI ports. It happened when the TV was powered on while the 288 * device was plugged in. A scope trace shows the TV bringing both SDA 289 * and SCL low, then bringing them both back up at roughly the same 290 * time. Presumably this confuses dw_hdmi because it saw activity but 291 * no real STOP (maybe it thinks there's another master on the bus?). 292 * Giving it a clean rising edge of SDA while SCL is already high 293 * presumably makes dw_hdmi see a STOP which seems to bring dw_hdmi out 294 * of its stupor. 295 * 296 * Note that after coming back alive, transfers seem to immediately 297 * resume, so if we unwedge due to a timeout we should wait a little 298 * longer for our transfer to finish, since it might have just started 299 * now. 300 */ 301 pinctrl_select_state(hdmi->pinctrl, hdmi->unwedge_state); 302 msleep(10); 303 pinctrl_select_state(hdmi->pinctrl, hdmi->default_state); 304 305 return true; 306 } 307 308 static int dw_hdmi_i2c_wait(struct dw_hdmi *hdmi) 309 { 310 struct dw_hdmi_i2c *i2c = hdmi->i2c; 311 int stat; 312 313 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 314 if (!stat) { 315 /* If we can't unwedge, return timeout */ 316 if (!dw_hdmi_i2c_unwedge(hdmi)) 317 return -EAGAIN; 318 319 /* We tried to unwedge; give it another chance */ 320 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 321 if (!stat) 322 return -EAGAIN; 323 } 324 325 /* Check for error condition on the bus */ 326 if (i2c->stat & HDMI_IH_I2CM_STAT0_ERROR) 327 return -EIO; 328 329 return 0; 330 } 331 332 static int dw_hdmi_i2c_read(struct dw_hdmi *hdmi, 333 unsigned char *buf, unsigned int length) 334 { 335 struct dw_hdmi_i2c *i2c = hdmi->i2c; 336 int ret; 337 338 if (!i2c->is_regaddr) { 339 dev_dbg(hdmi->dev, "set read register address to 0\n"); 340 i2c->slave_reg = 0x00; 341 i2c->is_regaddr = true; 342 } 343 344 while (length--) { 345 reinit_completion(&i2c->cmp); 346 347 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 348 if (i2c->is_segment) 349 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ_EXT, 350 HDMI_I2CM_OPERATION); 351 else 352 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_READ, 353 HDMI_I2CM_OPERATION); 354 355 ret = dw_hdmi_i2c_wait(hdmi); 356 if (ret) 357 return ret; 358 359 *buf++ = hdmi_readb(hdmi, HDMI_I2CM_DATAI); 360 } 361 i2c->is_segment = false; 362 363 return 0; 364 } 365 366 static int dw_hdmi_i2c_write(struct dw_hdmi *hdmi, 367 unsigned char *buf, unsigned int length) 368 { 369 struct dw_hdmi_i2c *i2c = hdmi->i2c; 370 int ret; 371 372 if (!i2c->is_regaddr) { 373 /* Use the first write byte as register address */ 374 i2c->slave_reg = buf[0]; 375 length--; 376 buf++; 377 i2c->is_regaddr = true; 378 } 379 380 while (length--) { 381 reinit_completion(&i2c->cmp); 382 383 hdmi_writeb(hdmi, *buf++, HDMI_I2CM_DATAO); 384 hdmi_writeb(hdmi, i2c->slave_reg++, HDMI_I2CM_ADDRESS); 385 hdmi_writeb(hdmi, HDMI_I2CM_OPERATION_WRITE, 386 HDMI_I2CM_OPERATION); 387 388 ret = dw_hdmi_i2c_wait(hdmi); 389 if (ret) 390 return ret; 391 } 392 393 return 0; 394 } 395 396 static int dw_hdmi_i2c_xfer(struct i2c_adapter *adap, 397 struct i2c_msg *msgs, int num) 398 { 399 struct dw_hdmi *hdmi = i2c_get_adapdata(adap); 400 struct dw_hdmi_i2c *i2c = hdmi->i2c; 401 u8 addr = msgs[0].addr; 402 int i, ret = 0; 403 404 if (addr == DDC_CI_ADDR) 405 /* 406 * The internal I2C controller does not support the multi-byte 407 * read and write operations needed for DDC/CI. 408 * TOFIX: Blacklist the DDC/CI address until we filter out 409 * unsupported I2C operations. 410 */ 411 return -EOPNOTSUPP; 412 413 dev_dbg(hdmi->dev, "xfer: num: %d, addr: %#x\n", num, addr); 414 415 for (i = 0; i < num; i++) { 416 if (msgs[i].len == 0) { 417 dev_dbg(hdmi->dev, 418 "unsupported transfer %d/%d, no data\n", 419 i + 1, num); 420 return -EOPNOTSUPP; 421 } 422 } 423 424 mutex_lock(&i2c->lock); 425 426 /* Unmute DONE and ERROR interrupts */ 427 hdmi_writeb(hdmi, 0x00, HDMI_IH_MUTE_I2CM_STAT0); 428 429 /* Set slave device address taken from the first I2C message */ 430 hdmi_writeb(hdmi, addr, HDMI_I2CM_SLAVE); 431 432 /* Set slave device register address on transfer */ 433 i2c->is_regaddr = false; 434 435 /* Set segment pointer for I2C extended read mode operation */ 436 i2c->is_segment = false; 437 438 for (i = 0; i < num; i++) { 439 dev_dbg(hdmi->dev, "xfer: num: %d/%d, len: %d, flags: %#x\n", 440 i + 1, num, msgs[i].len, msgs[i].flags); 441 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 442 i2c->is_segment = true; 443 hdmi_writeb(hdmi, DDC_SEGMENT_ADDR, HDMI_I2CM_SEGADDR); 444 hdmi_writeb(hdmi, *msgs[i].buf, HDMI_I2CM_SEGPTR); 445 } else { 446 if (msgs[i].flags & I2C_M_RD) 447 ret = dw_hdmi_i2c_read(hdmi, msgs[i].buf, 448 msgs[i].len); 449 else 450 ret = dw_hdmi_i2c_write(hdmi, msgs[i].buf, 451 msgs[i].len); 452 } 453 if (ret < 0) 454 break; 455 } 456 457 if (!ret) 458 ret = num; 459 460 /* Mute DONE and ERROR interrupts */ 461 hdmi_writeb(hdmi, HDMI_IH_I2CM_STAT0_ERROR | HDMI_IH_I2CM_STAT0_DONE, 462 HDMI_IH_MUTE_I2CM_STAT0); 463 464 mutex_unlock(&i2c->lock); 465 466 return ret; 467 } 468 469 static u32 dw_hdmi_i2c_func(struct i2c_adapter *adapter) 470 { 471 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 472 } 473 474 static const struct i2c_algorithm dw_hdmi_algorithm = { 475 .master_xfer = dw_hdmi_i2c_xfer, 476 .functionality = dw_hdmi_i2c_func, 477 }; 478 479 static struct i2c_adapter *dw_hdmi_i2c_adapter(struct dw_hdmi *hdmi) 480 { 481 struct i2c_adapter *adap; 482 struct dw_hdmi_i2c *i2c; 483 int ret; 484 485 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 486 if (!i2c) 487 return ERR_PTR(-ENOMEM); 488 489 mutex_init(&i2c->lock); 490 init_completion(&i2c->cmp); 491 492 adap = &i2c->adap; 493 adap->class = I2C_CLASS_DDC; 494 adap->owner = THIS_MODULE; 495 adap->dev.parent = hdmi->dev; 496 adap->algo = &dw_hdmi_algorithm; 497 strlcpy(adap->name, "DesignWare HDMI", sizeof(adap->name)); 498 i2c_set_adapdata(adap, hdmi); 499 500 ret = i2c_add_adapter(adap); 501 if (ret) { 502 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 503 devm_kfree(hdmi->dev, i2c); 504 return ERR_PTR(ret); 505 } 506 507 hdmi->i2c = i2c; 508 509 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 510 511 return adap; 512 } 513 514 static void hdmi_set_cts_n(struct dw_hdmi *hdmi, unsigned int cts, 515 unsigned int n) 516 { 517 /* Must be set/cleared first */ 518 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_CTS_MANUAL, HDMI_AUD_CTS3); 519 520 /* nshift factor = 0 */ 521 hdmi_modb(hdmi, 0, HDMI_AUD_CTS3_N_SHIFT_MASK, HDMI_AUD_CTS3); 522 523 /* Use automatic CTS generation mode when CTS is not set */ 524 if (cts) 525 hdmi_writeb(hdmi, ((cts >> 16) & 526 HDMI_AUD_CTS3_AUDCTS19_16_MASK) | 527 HDMI_AUD_CTS3_CTS_MANUAL, 528 HDMI_AUD_CTS3); 529 else 530 hdmi_writeb(hdmi, 0, HDMI_AUD_CTS3); 531 hdmi_writeb(hdmi, (cts >> 8) & 0xff, HDMI_AUD_CTS2); 532 hdmi_writeb(hdmi, cts & 0xff, HDMI_AUD_CTS1); 533 534 hdmi_writeb(hdmi, (n >> 16) & 0x0f, HDMI_AUD_N3); 535 hdmi_writeb(hdmi, (n >> 8) & 0xff, HDMI_AUD_N2); 536 hdmi_writeb(hdmi, n & 0xff, HDMI_AUD_N1); 537 } 538 539 static unsigned int hdmi_compute_n(unsigned int freq, unsigned long pixel_clk) 540 { 541 unsigned int n = (128 * freq) / 1000; 542 unsigned int mult = 1; 543 544 while (freq > 48000) { 545 mult *= 2; 546 freq /= 2; 547 } 548 549 switch (freq) { 550 case 32000: 551 if (pixel_clk == 25175000) 552 n = 4576; 553 else if (pixel_clk == 27027000) 554 n = 4096; 555 else if (pixel_clk == 74176000 || pixel_clk == 148352000) 556 n = 11648; 557 else 558 n = 4096; 559 n *= mult; 560 break; 561 562 case 44100: 563 if (pixel_clk == 25175000) 564 n = 7007; 565 else if (pixel_clk == 74176000) 566 n = 17836; 567 else if (pixel_clk == 148352000) 568 n = 8918; 569 else 570 n = 6272; 571 n *= mult; 572 break; 573 574 case 48000: 575 if (pixel_clk == 25175000) 576 n = 6864; 577 else if (pixel_clk == 27027000) 578 n = 6144; 579 else if (pixel_clk == 74176000) 580 n = 11648; 581 else if (pixel_clk == 148352000) 582 n = 5824; 583 else 584 n = 6144; 585 n *= mult; 586 break; 587 588 default: 589 break; 590 } 591 592 return n; 593 } 594 595 /* 596 * When transmitting IEC60958 linear PCM audio, these registers allow to 597 * configure the channel status information of all the channel status 598 * bits in the IEC60958 frame. For the moment this configuration is only 599 * used when the I2S audio interface, General Purpose Audio (GPA), 600 * or AHB audio DMA (AHBAUDDMA) interface is active 601 * (for S/PDIF interface this information comes from the stream). 602 */ 603 void dw_hdmi_set_channel_status(struct dw_hdmi *hdmi, 604 u8 *channel_status) 605 { 606 /* 607 * Set channel status register for frequency and word length. 608 * Use default values for other registers. 609 */ 610 hdmi_writeb(hdmi, channel_status[3], HDMI_FC_AUDSCHNLS7); 611 hdmi_writeb(hdmi, channel_status[4], HDMI_FC_AUDSCHNLS8); 612 } 613 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_status); 614 615 static void hdmi_set_clk_regenerator(struct dw_hdmi *hdmi, 616 unsigned long pixel_clk, unsigned int sample_rate) 617 { 618 unsigned long ftdms = pixel_clk; 619 unsigned int n, cts; 620 u8 config3; 621 u64 tmp; 622 623 n = hdmi_compute_n(sample_rate, pixel_clk); 624 625 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 626 627 /* Only compute CTS when using internal AHB audio */ 628 if (config3 & HDMI_CONFIG3_AHBAUDDMA) { 629 /* 630 * Compute the CTS value from the N value. Note that CTS and N 631 * can be up to 20 bits in total, so we need 64-bit math. Also 632 * note that our TDMS clock is not fully accurate; it is 633 * accurate to kHz. This can introduce an unnecessary remainder 634 * in the calculation below, so we don't try to warn about that. 635 */ 636 tmp = (u64)ftdms * n; 637 do_div(tmp, 128 * sample_rate); 638 cts = tmp; 639 640 dev_dbg(hdmi->dev, "%s: fs=%uHz ftdms=%lu.%03luMHz N=%d cts=%d\n", 641 __func__, sample_rate, 642 ftdms / 1000000, (ftdms / 1000) % 1000, 643 n, cts); 644 } else { 645 cts = 0; 646 } 647 648 spin_lock_irq(&hdmi->audio_lock); 649 hdmi->audio_n = n; 650 hdmi->audio_cts = cts; 651 hdmi_set_cts_n(hdmi, cts, hdmi->audio_enable ? n : 0); 652 spin_unlock_irq(&hdmi->audio_lock); 653 } 654 655 static void hdmi_init_clk_regenerator(struct dw_hdmi *hdmi) 656 { 657 mutex_lock(&hdmi->audio_mutex); 658 hdmi_set_clk_regenerator(hdmi, 74250000, hdmi->sample_rate); 659 mutex_unlock(&hdmi->audio_mutex); 660 } 661 662 static void hdmi_clk_regenerator_update_pixel_clock(struct dw_hdmi *hdmi) 663 { 664 mutex_lock(&hdmi->audio_mutex); 665 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 666 hdmi->sample_rate); 667 mutex_unlock(&hdmi->audio_mutex); 668 } 669 670 void dw_hdmi_set_sample_rate(struct dw_hdmi *hdmi, unsigned int rate) 671 { 672 mutex_lock(&hdmi->audio_mutex); 673 hdmi->sample_rate = rate; 674 hdmi_set_clk_regenerator(hdmi, hdmi->hdmi_data.video_mode.mtmdsclock, 675 hdmi->sample_rate); 676 mutex_unlock(&hdmi->audio_mutex); 677 } 678 EXPORT_SYMBOL_GPL(dw_hdmi_set_sample_rate); 679 680 void dw_hdmi_set_channel_count(struct dw_hdmi *hdmi, unsigned int cnt) 681 { 682 u8 layout; 683 684 mutex_lock(&hdmi->audio_mutex); 685 686 /* 687 * For >2 channel PCM audio, we need to select layout 1 688 * and set an appropriate channel map. 689 */ 690 if (cnt > 2) 691 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT1; 692 else 693 layout = HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_LAYOUT0; 694 695 hdmi_modb(hdmi, layout, HDMI_FC_AUDSCONF_AUD_PACKET_LAYOUT_MASK, 696 HDMI_FC_AUDSCONF); 697 698 /* Set the audio infoframes channel count */ 699 hdmi_modb(hdmi, (cnt - 1) << HDMI_FC_AUDICONF0_CC_OFFSET, 700 HDMI_FC_AUDICONF0_CC_MASK, HDMI_FC_AUDICONF0); 701 702 mutex_unlock(&hdmi->audio_mutex); 703 } 704 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_count); 705 706 void dw_hdmi_set_channel_allocation(struct dw_hdmi *hdmi, unsigned int ca) 707 { 708 mutex_lock(&hdmi->audio_mutex); 709 710 hdmi_writeb(hdmi, ca, HDMI_FC_AUDICONF2); 711 712 mutex_unlock(&hdmi->audio_mutex); 713 } 714 EXPORT_SYMBOL_GPL(dw_hdmi_set_channel_allocation); 715 716 static void hdmi_enable_audio_clk(struct dw_hdmi *hdmi, bool enable) 717 { 718 if (enable) 719 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_AUDCLK_DISABLE; 720 else 721 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_AUDCLK_DISABLE; 722 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 723 } 724 725 static void dw_hdmi_ahb_audio_enable(struct dw_hdmi *hdmi) 726 { 727 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 728 } 729 730 static void dw_hdmi_ahb_audio_disable(struct dw_hdmi *hdmi) 731 { 732 hdmi_set_cts_n(hdmi, hdmi->audio_cts, 0); 733 } 734 735 static void dw_hdmi_i2s_audio_enable(struct dw_hdmi *hdmi) 736 { 737 hdmi_set_cts_n(hdmi, hdmi->audio_cts, hdmi->audio_n); 738 hdmi_enable_audio_clk(hdmi, true); 739 } 740 741 static void dw_hdmi_i2s_audio_disable(struct dw_hdmi *hdmi) 742 { 743 hdmi_enable_audio_clk(hdmi, false); 744 } 745 746 void dw_hdmi_audio_enable(struct dw_hdmi *hdmi) 747 { 748 unsigned long flags; 749 750 spin_lock_irqsave(&hdmi->audio_lock, flags); 751 hdmi->audio_enable = true; 752 if (hdmi->enable_audio) 753 hdmi->enable_audio(hdmi); 754 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 755 } 756 EXPORT_SYMBOL_GPL(dw_hdmi_audio_enable); 757 758 void dw_hdmi_audio_disable(struct dw_hdmi *hdmi) 759 { 760 unsigned long flags; 761 762 spin_lock_irqsave(&hdmi->audio_lock, flags); 763 hdmi->audio_enable = false; 764 if (hdmi->disable_audio) 765 hdmi->disable_audio(hdmi); 766 spin_unlock_irqrestore(&hdmi->audio_lock, flags); 767 } 768 EXPORT_SYMBOL_GPL(dw_hdmi_audio_disable); 769 770 static bool hdmi_bus_fmt_is_rgb(unsigned int bus_format) 771 { 772 switch (bus_format) { 773 case MEDIA_BUS_FMT_RGB888_1X24: 774 case MEDIA_BUS_FMT_RGB101010_1X30: 775 case MEDIA_BUS_FMT_RGB121212_1X36: 776 case MEDIA_BUS_FMT_RGB161616_1X48: 777 return true; 778 779 default: 780 return false; 781 } 782 } 783 784 static bool hdmi_bus_fmt_is_yuv444(unsigned int bus_format) 785 { 786 switch (bus_format) { 787 case MEDIA_BUS_FMT_YUV8_1X24: 788 case MEDIA_BUS_FMT_YUV10_1X30: 789 case MEDIA_BUS_FMT_YUV12_1X36: 790 case MEDIA_BUS_FMT_YUV16_1X48: 791 return true; 792 793 default: 794 return false; 795 } 796 } 797 798 static bool hdmi_bus_fmt_is_yuv422(unsigned int bus_format) 799 { 800 switch (bus_format) { 801 case MEDIA_BUS_FMT_UYVY8_1X16: 802 case MEDIA_BUS_FMT_UYVY10_1X20: 803 case MEDIA_BUS_FMT_UYVY12_1X24: 804 return true; 805 806 default: 807 return false; 808 } 809 } 810 811 static bool hdmi_bus_fmt_is_yuv420(unsigned int bus_format) 812 { 813 switch (bus_format) { 814 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 815 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 816 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 817 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 818 return true; 819 820 default: 821 return false; 822 } 823 } 824 825 static int hdmi_bus_fmt_color_depth(unsigned int bus_format) 826 { 827 switch (bus_format) { 828 case MEDIA_BUS_FMT_RGB888_1X24: 829 case MEDIA_BUS_FMT_YUV8_1X24: 830 case MEDIA_BUS_FMT_UYVY8_1X16: 831 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 832 return 8; 833 834 case MEDIA_BUS_FMT_RGB101010_1X30: 835 case MEDIA_BUS_FMT_YUV10_1X30: 836 case MEDIA_BUS_FMT_UYVY10_1X20: 837 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 838 return 10; 839 840 case MEDIA_BUS_FMT_RGB121212_1X36: 841 case MEDIA_BUS_FMT_YUV12_1X36: 842 case MEDIA_BUS_FMT_UYVY12_1X24: 843 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 844 return 12; 845 846 case MEDIA_BUS_FMT_RGB161616_1X48: 847 case MEDIA_BUS_FMT_YUV16_1X48: 848 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 849 return 16; 850 851 default: 852 return 0; 853 } 854 } 855 856 /* 857 * this submodule is responsible for the video data synchronization. 858 * for example, for RGB 4:4:4 input, the data map is defined as 859 * pin{47~40} <==> R[7:0] 860 * pin{31~24} <==> G[7:0] 861 * pin{15~8} <==> B[7:0] 862 */ 863 static void hdmi_video_sample(struct dw_hdmi *hdmi) 864 { 865 int color_format = 0; 866 u8 val; 867 868 switch (hdmi->hdmi_data.enc_in_bus_format) { 869 case MEDIA_BUS_FMT_RGB888_1X24: 870 color_format = 0x01; 871 break; 872 case MEDIA_BUS_FMT_RGB101010_1X30: 873 color_format = 0x03; 874 break; 875 case MEDIA_BUS_FMT_RGB121212_1X36: 876 color_format = 0x05; 877 break; 878 case MEDIA_BUS_FMT_RGB161616_1X48: 879 color_format = 0x07; 880 break; 881 882 case MEDIA_BUS_FMT_YUV8_1X24: 883 case MEDIA_BUS_FMT_UYYVYY8_0_5X24: 884 color_format = 0x09; 885 break; 886 case MEDIA_BUS_FMT_YUV10_1X30: 887 case MEDIA_BUS_FMT_UYYVYY10_0_5X30: 888 color_format = 0x0B; 889 break; 890 case MEDIA_BUS_FMT_YUV12_1X36: 891 case MEDIA_BUS_FMT_UYYVYY12_0_5X36: 892 color_format = 0x0D; 893 break; 894 case MEDIA_BUS_FMT_YUV16_1X48: 895 case MEDIA_BUS_FMT_UYYVYY16_0_5X48: 896 color_format = 0x0F; 897 break; 898 899 case MEDIA_BUS_FMT_UYVY8_1X16: 900 color_format = 0x16; 901 break; 902 case MEDIA_BUS_FMT_UYVY10_1X20: 903 color_format = 0x14; 904 break; 905 case MEDIA_BUS_FMT_UYVY12_1X24: 906 color_format = 0x12; 907 break; 908 909 default: 910 return; 911 } 912 913 val = HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE | 914 ((color_format << HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET) & 915 HDMI_TX_INVID0_VIDEO_MAPPING_MASK); 916 hdmi_writeb(hdmi, val, HDMI_TX_INVID0); 917 918 /* Enable TX stuffing: When DE is inactive, fix the output data to 0 */ 919 val = HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE | 920 HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE | 921 HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE; 922 hdmi_writeb(hdmi, val, HDMI_TX_INSTUFFING); 923 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA0); 924 hdmi_writeb(hdmi, 0x0, HDMI_TX_GYDATA1); 925 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA0); 926 hdmi_writeb(hdmi, 0x0, HDMI_TX_RCRDATA1); 927 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA0); 928 hdmi_writeb(hdmi, 0x0, HDMI_TX_BCBDATA1); 929 } 930 931 static int is_color_space_conversion(struct dw_hdmi *hdmi) 932 { 933 return hdmi->hdmi_data.enc_in_bus_format != hdmi->hdmi_data.enc_out_bus_format; 934 } 935 936 static int is_color_space_decimation(struct dw_hdmi *hdmi) 937 { 938 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 939 return 0; 940 941 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_in_bus_format) || 942 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_in_bus_format)) 943 return 1; 944 945 return 0; 946 } 947 948 static int is_color_space_interpolation(struct dw_hdmi *hdmi) 949 { 950 if (!hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_in_bus_format)) 951 return 0; 952 953 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 954 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 955 return 1; 956 957 return 0; 958 } 959 960 static void dw_hdmi_update_csc_coeffs(struct dw_hdmi *hdmi) 961 { 962 const u16 (*csc_coeff)[3][4] = &csc_coeff_default; 963 unsigned i; 964 u32 csc_scale = 1; 965 966 if (is_color_space_conversion(hdmi)) { 967 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format)) { 968 if (hdmi->hdmi_data.enc_out_encoding == 969 V4L2_YCBCR_ENC_601) 970 csc_coeff = &csc_coeff_rgb_out_eitu601; 971 else 972 csc_coeff = &csc_coeff_rgb_out_eitu709; 973 } else if (hdmi_bus_fmt_is_rgb( 974 hdmi->hdmi_data.enc_in_bus_format)) { 975 if (hdmi->hdmi_data.enc_out_encoding == 976 V4L2_YCBCR_ENC_601) 977 csc_coeff = &csc_coeff_rgb_in_eitu601; 978 else 979 csc_coeff = &csc_coeff_rgb_in_eitu709; 980 csc_scale = 0; 981 } 982 } 983 984 /* The CSC registers are sequential, alternating MSB then LSB */ 985 for (i = 0; i < ARRAY_SIZE(csc_coeff_default[0]); i++) { 986 u16 coeff_a = (*csc_coeff)[0][i]; 987 u16 coeff_b = (*csc_coeff)[1][i]; 988 u16 coeff_c = (*csc_coeff)[2][i]; 989 990 hdmi_writeb(hdmi, coeff_a & 0xff, HDMI_CSC_COEF_A1_LSB + i * 2); 991 hdmi_writeb(hdmi, coeff_a >> 8, HDMI_CSC_COEF_A1_MSB + i * 2); 992 hdmi_writeb(hdmi, coeff_b & 0xff, HDMI_CSC_COEF_B1_LSB + i * 2); 993 hdmi_writeb(hdmi, coeff_b >> 8, HDMI_CSC_COEF_B1_MSB + i * 2); 994 hdmi_writeb(hdmi, coeff_c & 0xff, HDMI_CSC_COEF_C1_LSB + i * 2); 995 hdmi_writeb(hdmi, coeff_c >> 8, HDMI_CSC_COEF_C1_MSB + i * 2); 996 } 997 998 hdmi_modb(hdmi, csc_scale, HDMI_CSC_SCALE_CSCSCALE_MASK, 999 HDMI_CSC_SCALE); 1000 } 1001 1002 static void hdmi_video_csc(struct dw_hdmi *hdmi) 1003 { 1004 int color_depth = 0; 1005 int interpolation = HDMI_CSC_CFG_INTMODE_DISABLE; 1006 int decimation = 0; 1007 1008 /* YCC422 interpolation to 444 mode */ 1009 if (is_color_space_interpolation(hdmi)) 1010 interpolation = HDMI_CSC_CFG_INTMODE_CHROMA_INT_FORMULA1; 1011 else if (is_color_space_decimation(hdmi)) 1012 decimation = HDMI_CSC_CFG_DECMODE_CHROMA_INT_FORMULA3; 1013 1014 switch (hdmi_bus_fmt_color_depth(hdmi->hdmi_data.enc_out_bus_format)) { 1015 case 8: 1016 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_24BPP; 1017 break; 1018 case 10: 1019 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_30BPP; 1020 break; 1021 case 12: 1022 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_36BPP; 1023 break; 1024 case 16: 1025 color_depth = HDMI_CSC_SCALE_CSC_COLORDE_PTH_48BPP; 1026 break; 1027 1028 default: 1029 return; 1030 } 1031 1032 /* Configure the CSC registers */ 1033 hdmi_writeb(hdmi, interpolation | decimation, HDMI_CSC_CFG); 1034 hdmi_modb(hdmi, color_depth, HDMI_CSC_SCALE_CSC_COLORDE_PTH_MASK, 1035 HDMI_CSC_SCALE); 1036 1037 dw_hdmi_update_csc_coeffs(hdmi); 1038 } 1039 1040 /* 1041 * HDMI video packetizer is used to packetize the data. 1042 * for example, if input is YCC422 mode or repeater is used, 1043 * data should be repacked this module can be bypassed. 1044 */ 1045 static void hdmi_video_packetize(struct dw_hdmi *hdmi) 1046 { 1047 unsigned int color_depth = 0; 1048 unsigned int remap_size = HDMI_VP_REMAP_YCC422_16bit; 1049 unsigned int output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_PP; 1050 struct hdmi_data_info *hdmi_data = &hdmi->hdmi_data; 1051 u8 val, vp_conf; 1052 1053 if (hdmi_bus_fmt_is_rgb(hdmi->hdmi_data.enc_out_bus_format) || 1054 hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format) || 1055 hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1056 switch (hdmi_bus_fmt_color_depth( 1057 hdmi->hdmi_data.enc_out_bus_format)) { 1058 case 8: 1059 color_depth = 4; 1060 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1061 break; 1062 case 10: 1063 color_depth = 5; 1064 break; 1065 case 12: 1066 color_depth = 6; 1067 break; 1068 case 16: 1069 color_depth = 7; 1070 break; 1071 default: 1072 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS; 1073 } 1074 } else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) { 1075 switch (hdmi_bus_fmt_color_depth( 1076 hdmi->hdmi_data.enc_out_bus_format)) { 1077 case 0: 1078 case 8: 1079 remap_size = HDMI_VP_REMAP_YCC422_16bit; 1080 break; 1081 case 10: 1082 remap_size = HDMI_VP_REMAP_YCC422_20bit; 1083 break; 1084 case 12: 1085 remap_size = HDMI_VP_REMAP_YCC422_24bit; 1086 break; 1087 1088 default: 1089 return; 1090 } 1091 output_select = HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422; 1092 } else { 1093 return; 1094 } 1095 1096 /* set the packetizer registers */ 1097 val = ((color_depth << HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET) & 1098 HDMI_VP_PR_CD_COLOR_DEPTH_MASK) | 1099 ((hdmi_data->pix_repet_factor << 1100 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET) & 1101 HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK); 1102 hdmi_writeb(hdmi, val, HDMI_VP_PR_CD); 1103 1104 hdmi_modb(hdmi, HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE, 1105 HDMI_VP_STUFF_PR_STUFFING_MASK, HDMI_VP_STUFF); 1106 1107 /* Data from pixel repeater block */ 1108 if (hdmi_data->pix_repet_factor > 1) { 1109 vp_conf = HDMI_VP_CONF_PR_EN_ENABLE | 1110 HDMI_VP_CONF_BYPASS_SELECT_PIX_REPEATER; 1111 } else { /* data from packetizer block */ 1112 vp_conf = HDMI_VP_CONF_PR_EN_DISABLE | 1113 HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER; 1114 } 1115 1116 hdmi_modb(hdmi, vp_conf, 1117 HDMI_VP_CONF_PR_EN_MASK | 1118 HDMI_VP_CONF_BYPASS_SELECT_MASK, HDMI_VP_CONF); 1119 1120 hdmi_modb(hdmi, 1 << HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET, 1121 HDMI_VP_STUFF_IDEFAULT_PHASE_MASK, HDMI_VP_STUFF); 1122 1123 hdmi_writeb(hdmi, remap_size, HDMI_VP_REMAP); 1124 1125 if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_PP) { 1126 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1127 HDMI_VP_CONF_PP_EN_ENABLE | 1128 HDMI_VP_CONF_YCC422_EN_DISABLE; 1129 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_YCC422) { 1130 vp_conf = HDMI_VP_CONF_BYPASS_EN_DISABLE | 1131 HDMI_VP_CONF_PP_EN_DISABLE | 1132 HDMI_VP_CONF_YCC422_EN_ENABLE; 1133 } else if (output_select == HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS) { 1134 vp_conf = HDMI_VP_CONF_BYPASS_EN_ENABLE | 1135 HDMI_VP_CONF_PP_EN_DISABLE | 1136 HDMI_VP_CONF_YCC422_EN_DISABLE; 1137 } else { 1138 return; 1139 } 1140 1141 hdmi_modb(hdmi, vp_conf, 1142 HDMI_VP_CONF_BYPASS_EN_MASK | HDMI_VP_CONF_PP_EN_ENMASK | 1143 HDMI_VP_CONF_YCC422_EN_MASK, HDMI_VP_CONF); 1144 1145 hdmi_modb(hdmi, HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE | 1146 HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE, 1147 HDMI_VP_STUFF_PP_STUFFING_MASK | 1148 HDMI_VP_STUFF_YCC422_STUFFING_MASK, HDMI_VP_STUFF); 1149 1150 hdmi_modb(hdmi, output_select, HDMI_VP_CONF_OUTPUT_SELECTOR_MASK, 1151 HDMI_VP_CONF); 1152 } 1153 1154 /* ----------------------------------------------------------------------------- 1155 * Synopsys PHY Handling 1156 */ 1157 1158 static inline void hdmi_phy_test_clear(struct dw_hdmi *hdmi, 1159 unsigned char bit) 1160 { 1161 hdmi_modb(hdmi, bit << HDMI_PHY_TST0_TSTCLR_OFFSET, 1162 HDMI_PHY_TST0_TSTCLR_MASK, HDMI_PHY_TST0); 1163 } 1164 1165 static bool hdmi_phy_wait_i2c_done(struct dw_hdmi *hdmi, int msec) 1166 { 1167 u32 val; 1168 1169 while ((val = hdmi_readb(hdmi, HDMI_IH_I2CMPHY_STAT0) & 0x3) == 0) { 1170 if (msec-- == 0) 1171 return false; 1172 udelay(1000); 1173 } 1174 hdmi_writeb(hdmi, val, HDMI_IH_I2CMPHY_STAT0); 1175 1176 return true; 1177 } 1178 1179 void dw_hdmi_phy_i2c_write(struct dw_hdmi *hdmi, unsigned short data, 1180 unsigned char addr) 1181 { 1182 hdmi_writeb(hdmi, 0xFF, HDMI_IH_I2CMPHY_STAT0); 1183 hdmi_writeb(hdmi, addr, HDMI_PHY_I2CM_ADDRESS_ADDR); 1184 hdmi_writeb(hdmi, (unsigned char)(data >> 8), 1185 HDMI_PHY_I2CM_DATAO_1_ADDR); 1186 hdmi_writeb(hdmi, (unsigned char)(data >> 0), 1187 HDMI_PHY_I2CM_DATAO_0_ADDR); 1188 hdmi_writeb(hdmi, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE, 1189 HDMI_PHY_I2CM_OPERATION_ADDR); 1190 hdmi_phy_wait_i2c_done(hdmi, 1000); 1191 } 1192 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_write); 1193 1194 /* Filter out invalid setups to avoid configuring SCDC and scrambling */ 1195 static bool dw_hdmi_support_scdc(struct dw_hdmi *hdmi) 1196 { 1197 struct drm_display_info *display = &hdmi->connector.display_info; 1198 1199 /* Completely disable SCDC support for older controllers */ 1200 if (hdmi->version < 0x200a) 1201 return false; 1202 1203 /* Disable if no DDC bus */ 1204 if (!hdmi->ddc) 1205 return false; 1206 1207 /* Disable if SCDC is not supported, or if an HF-VSDB block is absent */ 1208 if (!display->hdmi.scdc.supported || 1209 !display->hdmi.scdc.scrambling.supported) 1210 return false; 1211 1212 /* 1213 * Disable if display only support low TMDS rates and scrambling 1214 * for low rates is not supported either 1215 */ 1216 if (!display->hdmi.scdc.scrambling.low_rates && 1217 display->max_tmds_clock <= 340000) 1218 return false; 1219 1220 return true; 1221 } 1222 1223 /* 1224 * HDMI2.0 Specifies the following procedure for High TMDS Bit Rates: 1225 * - The Source shall suspend transmission of the TMDS clock and data 1226 * - The Source shall write to the TMDS_Bit_Clock_Ratio bit to change it 1227 * from a 0 to a 1 or from a 1 to a 0 1228 * - The Source shall allow a minimum of 1 ms and a maximum of 100 ms from 1229 * the time the TMDS_Bit_Clock_Ratio bit is written until resuming 1230 * transmission of TMDS clock and data 1231 * 1232 * To respect the 100ms maximum delay, the dw_hdmi_set_high_tmds_clock_ratio() 1233 * helper should called right before enabling the TMDS Clock and Data in 1234 * the PHY configuration callback. 1235 */ 1236 void dw_hdmi_set_high_tmds_clock_ratio(struct dw_hdmi *hdmi) 1237 { 1238 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1239 1240 /* Control for TMDS Bit Period/TMDS Clock-Period Ratio */ 1241 if (dw_hdmi_support_scdc(hdmi)) { 1242 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1243 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 1); 1244 else 1245 drm_scdc_set_high_tmds_clock_ratio(hdmi->ddc, 0); 1246 } 1247 } 1248 EXPORT_SYMBOL_GPL(dw_hdmi_set_high_tmds_clock_ratio); 1249 1250 static void dw_hdmi_phy_enable_powerdown(struct dw_hdmi *hdmi, bool enable) 1251 { 1252 hdmi_mask_writeb(hdmi, !enable, HDMI_PHY_CONF0, 1253 HDMI_PHY_CONF0_PDZ_OFFSET, 1254 HDMI_PHY_CONF0_PDZ_MASK); 1255 } 1256 1257 static void dw_hdmi_phy_enable_tmds(struct dw_hdmi *hdmi, u8 enable) 1258 { 1259 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1260 HDMI_PHY_CONF0_ENTMDS_OFFSET, 1261 HDMI_PHY_CONF0_ENTMDS_MASK); 1262 } 1263 1264 static void dw_hdmi_phy_enable_svsret(struct dw_hdmi *hdmi, u8 enable) 1265 { 1266 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1267 HDMI_PHY_CONF0_SVSRET_OFFSET, 1268 HDMI_PHY_CONF0_SVSRET_MASK); 1269 } 1270 1271 void dw_hdmi_phy_gen2_pddq(struct dw_hdmi *hdmi, u8 enable) 1272 { 1273 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1274 HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET, 1275 HDMI_PHY_CONF0_GEN2_PDDQ_MASK); 1276 } 1277 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_pddq); 1278 1279 void dw_hdmi_phy_gen2_txpwron(struct dw_hdmi *hdmi, u8 enable) 1280 { 1281 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1282 HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET, 1283 HDMI_PHY_CONF0_GEN2_TXPWRON_MASK); 1284 } 1285 EXPORT_SYMBOL_GPL(dw_hdmi_phy_gen2_txpwron); 1286 1287 static void dw_hdmi_phy_sel_data_en_pol(struct dw_hdmi *hdmi, u8 enable) 1288 { 1289 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1290 HDMI_PHY_CONF0_SELDATAENPOL_OFFSET, 1291 HDMI_PHY_CONF0_SELDATAENPOL_MASK); 1292 } 1293 1294 static void dw_hdmi_phy_sel_interface_control(struct dw_hdmi *hdmi, u8 enable) 1295 { 1296 hdmi_mask_writeb(hdmi, enable, HDMI_PHY_CONF0, 1297 HDMI_PHY_CONF0_SELDIPIF_OFFSET, 1298 HDMI_PHY_CONF0_SELDIPIF_MASK); 1299 } 1300 1301 void dw_hdmi_phy_reset(struct dw_hdmi *hdmi) 1302 { 1303 /* PHY reset. The reset signal is active high on Gen2 PHYs. */ 1304 hdmi_writeb(hdmi, HDMI_MC_PHYRSTZ_PHYRSTZ, HDMI_MC_PHYRSTZ); 1305 hdmi_writeb(hdmi, 0, HDMI_MC_PHYRSTZ); 1306 } 1307 EXPORT_SYMBOL_GPL(dw_hdmi_phy_reset); 1308 1309 void dw_hdmi_phy_i2c_set_addr(struct dw_hdmi *hdmi, u8 address) 1310 { 1311 hdmi_phy_test_clear(hdmi, 1); 1312 hdmi_writeb(hdmi, address, HDMI_PHY_I2CM_SLAVE_ADDR); 1313 hdmi_phy_test_clear(hdmi, 0); 1314 } 1315 EXPORT_SYMBOL_GPL(dw_hdmi_phy_i2c_set_addr); 1316 1317 static void dw_hdmi_phy_power_off(struct dw_hdmi *hdmi) 1318 { 1319 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1320 unsigned int i; 1321 u16 val; 1322 1323 if (phy->gen == 1) { 1324 dw_hdmi_phy_enable_tmds(hdmi, 0); 1325 dw_hdmi_phy_enable_powerdown(hdmi, true); 1326 return; 1327 } 1328 1329 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 1330 1331 /* 1332 * Wait for TX_PHY_LOCK to be deasserted to indicate that the PHY went 1333 * to low power mode. 1334 */ 1335 for (i = 0; i < 5; ++i) { 1336 val = hdmi_readb(hdmi, HDMI_PHY_STAT0); 1337 if (!(val & HDMI_PHY_TX_PHY_LOCK)) 1338 break; 1339 1340 usleep_range(1000, 2000); 1341 } 1342 1343 if (val & HDMI_PHY_TX_PHY_LOCK) 1344 dev_warn(hdmi->dev, "PHY failed to power down\n"); 1345 else 1346 dev_dbg(hdmi->dev, "PHY powered down in %u iterations\n", i); 1347 1348 dw_hdmi_phy_gen2_pddq(hdmi, 1); 1349 } 1350 1351 static int dw_hdmi_phy_power_on(struct dw_hdmi *hdmi) 1352 { 1353 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1354 unsigned int i; 1355 u8 val; 1356 1357 if (phy->gen == 1) { 1358 dw_hdmi_phy_enable_powerdown(hdmi, false); 1359 1360 /* Toggle TMDS enable. */ 1361 dw_hdmi_phy_enable_tmds(hdmi, 0); 1362 dw_hdmi_phy_enable_tmds(hdmi, 1); 1363 return 0; 1364 } 1365 1366 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 1367 dw_hdmi_phy_gen2_pddq(hdmi, 0); 1368 1369 /* Wait for PHY PLL lock */ 1370 for (i = 0; i < 5; ++i) { 1371 val = hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_TX_PHY_LOCK; 1372 if (val) 1373 break; 1374 1375 usleep_range(1000, 2000); 1376 } 1377 1378 if (!val) { 1379 dev_err(hdmi->dev, "PHY PLL failed to lock\n"); 1380 return -ETIMEDOUT; 1381 } 1382 1383 dev_dbg(hdmi->dev, "PHY PLL locked %u iterations\n", i); 1384 return 0; 1385 } 1386 1387 /* 1388 * PHY configuration function for the DWC HDMI 3D TX PHY. Based on the available 1389 * information the DWC MHL PHY has the same register layout and is thus also 1390 * supported by this function. 1391 */ 1392 static int hdmi_phy_configure_dwc_hdmi_3d_tx(struct dw_hdmi *hdmi, 1393 const struct dw_hdmi_plat_data *pdata, 1394 unsigned long mpixelclock) 1395 { 1396 const struct dw_hdmi_mpll_config *mpll_config = pdata->mpll_cfg; 1397 const struct dw_hdmi_curr_ctrl *curr_ctrl = pdata->cur_ctr; 1398 const struct dw_hdmi_phy_config *phy_config = pdata->phy_config; 1399 1400 /* TOFIX Will need 420 specific PHY configuration tables */ 1401 1402 /* PLL/MPLL Cfg - always match on final entry */ 1403 for (; mpll_config->mpixelclock != ~0UL; mpll_config++) 1404 if (mpixelclock <= mpll_config->mpixelclock) 1405 break; 1406 1407 for (; curr_ctrl->mpixelclock != ~0UL; curr_ctrl++) 1408 if (mpixelclock <= curr_ctrl->mpixelclock) 1409 break; 1410 1411 for (; phy_config->mpixelclock != ~0UL; phy_config++) 1412 if (mpixelclock <= phy_config->mpixelclock) 1413 break; 1414 1415 if (mpll_config->mpixelclock == ~0UL || 1416 curr_ctrl->mpixelclock == ~0UL || 1417 phy_config->mpixelclock == ~0UL) 1418 return -EINVAL; 1419 1420 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].cpce, 1421 HDMI_3D_TX_PHY_CPCE_CTRL); 1422 dw_hdmi_phy_i2c_write(hdmi, mpll_config->res[0].gmp, 1423 HDMI_3D_TX_PHY_GMPCTRL); 1424 dw_hdmi_phy_i2c_write(hdmi, curr_ctrl->curr[0], 1425 HDMI_3D_TX_PHY_CURRCTRL); 1426 1427 dw_hdmi_phy_i2c_write(hdmi, 0, HDMI_3D_TX_PHY_PLLPHBYCTRL); 1428 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_MSM_CTRL_CKO_SEL_FB_CLK, 1429 HDMI_3D_TX_PHY_MSM_CTRL); 1430 1431 dw_hdmi_phy_i2c_write(hdmi, phy_config->term, HDMI_3D_TX_PHY_TXTERM); 1432 dw_hdmi_phy_i2c_write(hdmi, phy_config->sym_ctr, 1433 HDMI_3D_TX_PHY_CKSYMTXCTRL); 1434 dw_hdmi_phy_i2c_write(hdmi, phy_config->vlev_ctr, 1435 HDMI_3D_TX_PHY_VLEVCTRL); 1436 1437 /* Override and disable clock termination. */ 1438 dw_hdmi_phy_i2c_write(hdmi, HDMI_3D_TX_PHY_CKCALCTRL_OVERRIDE, 1439 HDMI_3D_TX_PHY_CKCALCTRL); 1440 1441 return 0; 1442 } 1443 1444 static int hdmi_phy_configure(struct dw_hdmi *hdmi) 1445 { 1446 const struct dw_hdmi_phy_data *phy = hdmi->phy.data; 1447 const struct dw_hdmi_plat_data *pdata = hdmi->plat_data; 1448 unsigned long mpixelclock = hdmi->hdmi_data.video_mode.mpixelclock; 1449 unsigned long mtmdsclock = hdmi->hdmi_data.video_mode.mtmdsclock; 1450 int ret; 1451 1452 dw_hdmi_phy_power_off(hdmi); 1453 1454 dw_hdmi_set_high_tmds_clock_ratio(hdmi); 1455 1456 /* Leave low power consumption mode by asserting SVSRET. */ 1457 if (phy->has_svsret) 1458 dw_hdmi_phy_enable_svsret(hdmi, 1); 1459 1460 dw_hdmi_phy_reset(hdmi); 1461 1462 hdmi_writeb(hdmi, HDMI_MC_HEACPHY_RST_ASSERT, HDMI_MC_HEACPHY_RST); 1463 1464 dw_hdmi_phy_i2c_set_addr(hdmi, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2); 1465 1466 /* Write to the PHY as configured by the platform */ 1467 if (pdata->configure_phy) 1468 ret = pdata->configure_phy(hdmi, pdata, mpixelclock); 1469 else 1470 ret = phy->configure(hdmi, pdata, mpixelclock); 1471 if (ret) { 1472 dev_err(hdmi->dev, "PHY configuration failed (clock %lu)\n", 1473 mpixelclock); 1474 return ret; 1475 } 1476 1477 /* Wait for resuming transmission of TMDS clock and data */ 1478 if (mtmdsclock > HDMI14_MAX_TMDSCLK) 1479 msleep(100); 1480 1481 return dw_hdmi_phy_power_on(hdmi); 1482 } 1483 1484 static int dw_hdmi_phy_init(struct dw_hdmi *hdmi, void *data, 1485 struct drm_display_mode *mode) 1486 { 1487 int i, ret; 1488 1489 /* HDMI Phy spec says to do the phy initialization sequence twice */ 1490 for (i = 0; i < 2; i++) { 1491 dw_hdmi_phy_sel_data_en_pol(hdmi, 1); 1492 dw_hdmi_phy_sel_interface_control(hdmi, 0); 1493 1494 ret = hdmi_phy_configure(hdmi); 1495 if (ret) 1496 return ret; 1497 } 1498 1499 return 0; 1500 } 1501 1502 static void dw_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 1503 { 1504 dw_hdmi_phy_power_off(hdmi); 1505 } 1506 1507 enum drm_connector_status dw_hdmi_phy_read_hpd(struct dw_hdmi *hdmi, 1508 void *data) 1509 { 1510 return hdmi_readb(hdmi, HDMI_PHY_STAT0) & HDMI_PHY_HPD ? 1511 connector_status_connected : connector_status_disconnected; 1512 } 1513 EXPORT_SYMBOL_GPL(dw_hdmi_phy_read_hpd); 1514 1515 void dw_hdmi_phy_update_hpd(struct dw_hdmi *hdmi, void *data, 1516 bool force, bool disabled, bool rxsense) 1517 { 1518 u8 old_mask = hdmi->phy_mask; 1519 1520 if (force || disabled || !rxsense) 1521 hdmi->phy_mask |= HDMI_PHY_RX_SENSE; 1522 else 1523 hdmi->phy_mask &= ~HDMI_PHY_RX_SENSE; 1524 1525 if (old_mask != hdmi->phy_mask) 1526 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1527 } 1528 EXPORT_SYMBOL_GPL(dw_hdmi_phy_update_hpd); 1529 1530 void dw_hdmi_phy_setup_hpd(struct dw_hdmi *hdmi, void *data) 1531 { 1532 /* 1533 * Configure the PHY RX SENSE and HPD interrupts polarities and clear 1534 * any pending interrupt. 1535 */ 1536 hdmi_writeb(hdmi, HDMI_PHY_HPD | HDMI_PHY_RX_SENSE, HDMI_PHY_POL0); 1537 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1538 HDMI_IH_PHY_STAT0); 1539 1540 /* Enable cable hot plug irq. */ 1541 hdmi_writeb(hdmi, hdmi->phy_mask, HDMI_PHY_MASK0); 1542 1543 /* Clear and unmute interrupts. */ 1544 hdmi_writeb(hdmi, HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE, 1545 HDMI_IH_PHY_STAT0); 1546 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 1547 HDMI_IH_MUTE_PHY_STAT0); 1548 } 1549 EXPORT_SYMBOL_GPL(dw_hdmi_phy_setup_hpd); 1550 1551 static const struct dw_hdmi_phy_ops dw_hdmi_synopsys_phy_ops = { 1552 .init = dw_hdmi_phy_init, 1553 .disable = dw_hdmi_phy_disable, 1554 .read_hpd = dw_hdmi_phy_read_hpd, 1555 .update_hpd = dw_hdmi_phy_update_hpd, 1556 .setup_hpd = dw_hdmi_phy_setup_hpd, 1557 }; 1558 1559 /* ----------------------------------------------------------------------------- 1560 * HDMI TX Setup 1561 */ 1562 1563 static void hdmi_tx_hdcp_config(struct dw_hdmi *hdmi) 1564 { 1565 u8 de; 1566 1567 if (hdmi->hdmi_data.video_mode.mdataenablepolarity) 1568 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_HIGH; 1569 else 1570 de = HDMI_A_VIDPOLCFG_DATAENPOL_ACTIVE_LOW; 1571 1572 /* disable rx detect */ 1573 hdmi_modb(hdmi, HDMI_A_HDCPCFG0_RXDETECT_DISABLE, 1574 HDMI_A_HDCPCFG0_RXDETECT_MASK, HDMI_A_HDCPCFG0); 1575 1576 hdmi_modb(hdmi, de, HDMI_A_VIDPOLCFG_DATAENPOL_MASK, HDMI_A_VIDPOLCFG); 1577 1578 hdmi_modb(hdmi, HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_DISABLE, 1579 HDMI_A_HDCPCFG1_ENCRYPTIONDISABLE_MASK, HDMI_A_HDCPCFG1); 1580 } 1581 1582 static void hdmi_config_AVI(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 1583 { 1584 struct hdmi_avi_infoframe frame; 1585 u8 val; 1586 1587 /* Initialise info frame from DRM mode */ 1588 drm_hdmi_avi_infoframe_from_display_mode(&frame, 1589 &hdmi->connector, mode); 1590 1591 if (hdmi_bus_fmt_is_yuv444(hdmi->hdmi_data.enc_out_bus_format)) 1592 frame.colorspace = HDMI_COLORSPACE_YUV444; 1593 else if (hdmi_bus_fmt_is_yuv422(hdmi->hdmi_data.enc_out_bus_format)) 1594 frame.colorspace = HDMI_COLORSPACE_YUV422; 1595 else if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1596 frame.colorspace = HDMI_COLORSPACE_YUV420; 1597 else 1598 frame.colorspace = HDMI_COLORSPACE_RGB; 1599 1600 /* Set up colorimetry */ 1601 switch (hdmi->hdmi_data.enc_out_encoding) { 1602 case V4L2_YCBCR_ENC_601: 1603 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV601) 1604 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1605 else 1606 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1607 frame.extended_colorimetry = 1608 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1609 break; 1610 case V4L2_YCBCR_ENC_709: 1611 if (hdmi->hdmi_data.enc_in_encoding == V4L2_YCBCR_ENC_XV709) 1612 frame.colorimetry = HDMI_COLORIMETRY_EXTENDED; 1613 else 1614 frame.colorimetry = HDMI_COLORIMETRY_ITU_709; 1615 frame.extended_colorimetry = 1616 HDMI_EXTENDED_COLORIMETRY_XV_YCC_709; 1617 break; 1618 default: /* Carries no data */ 1619 frame.colorimetry = HDMI_COLORIMETRY_ITU_601; 1620 frame.extended_colorimetry = 1621 HDMI_EXTENDED_COLORIMETRY_XV_YCC_601; 1622 break; 1623 } 1624 1625 frame.scan_mode = HDMI_SCAN_MODE_NONE; 1626 1627 /* 1628 * The Designware IP uses a different byte format from standard 1629 * AVI info frames, though generally the bits are in the correct 1630 * bytes. 1631 */ 1632 1633 /* 1634 * AVI data byte 1 differences: Colorspace in bits 0,1 rather than 5,6, 1635 * scan info in bits 4,5 rather than 0,1 and active aspect present in 1636 * bit 6 rather than 4. 1637 */ 1638 val = (frame.scan_mode & 3) << 4 | (frame.colorspace & 3); 1639 if (frame.active_aspect & 15) 1640 val |= HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT; 1641 if (frame.top_bar || frame.bottom_bar) 1642 val |= HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR; 1643 if (frame.left_bar || frame.right_bar) 1644 val |= HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR; 1645 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF0); 1646 1647 /* AVI data byte 2 differences: none */ 1648 val = ((frame.colorimetry & 0x3) << 6) | 1649 ((frame.picture_aspect & 0x3) << 4) | 1650 (frame.active_aspect & 0xf); 1651 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF1); 1652 1653 /* AVI data byte 3 differences: none */ 1654 val = ((frame.extended_colorimetry & 0x7) << 4) | 1655 ((frame.quantization_range & 0x3) << 2) | 1656 (frame.nups & 0x3); 1657 if (frame.itc) 1658 val |= HDMI_FC_AVICONF2_IT_CONTENT_VALID; 1659 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF2); 1660 1661 /* AVI data byte 4 differences: none */ 1662 val = frame.video_code & 0x7f; 1663 hdmi_writeb(hdmi, val, HDMI_FC_AVIVID); 1664 1665 /* AVI Data Byte 5- set up input and output pixel repetition */ 1666 val = (((hdmi->hdmi_data.video_mode.mpixelrepetitioninput + 1) << 1667 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_OFFSET) & 1668 HDMI_FC_PRCONF_INCOMING_PR_FACTOR_MASK) | 1669 ((hdmi->hdmi_data.video_mode.mpixelrepetitionoutput << 1670 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_OFFSET) & 1671 HDMI_FC_PRCONF_OUTPUT_PR_FACTOR_MASK); 1672 hdmi_writeb(hdmi, val, HDMI_FC_PRCONF); 1673 1674 /* 1675 * AVI data byte 5 differences: content type in 0,1 rather than 4,5, 1676 * ycc range in bits 2,3 rather than 6,7 1677 */ 1678 val = ((frame.ycc_quantization_range & 0x3) << 2) | 1679 (frame.content_type & 0x3); 1680 hdmi_writeb(hdmi, val, HDMI_FC_AVICONF3); 1681 1682 /* AVI Data Bytes 6-13 */ 1683 hdmi_writeb(hdmi, frame.top_bar & 0xff, HDMI_FC_AVIETB0); 1684 hdmi_writeb(hdmi, (frame.top_bar >> 8) & 0xff, HDMI_FC_AVIETB1); 1685 hdmi_writeb(hdmi, frame.bottom_bar & 0xff, HDMI_FC_AVISBB0); 1686 hdmi_writeb(hdmi, (frame.bottom_bar >> 8) & 0xff, HDMI_FC_AVISBB1); 1687 hdmi_writeb(hdmi, frame.left_bar & 0xff, HDMI_FC_AVIELB0); 1688 hdmi_writeb(hdmi, (frame.left_bar >> 8) & 0xff, HDMI_FC_AVIELB1); 1689 hdmi_writeb(hdmi, frame.right_bar & 0xff, HDMI_FC_AVISRB0); 1690 hdmi_writeb(hdmi, (frame.right_bar >> 8) & 0xff, HDMI_FC_AVISRB1); 1691 } 1692 1693 static void hdmi_config_vendor_specific_infoframe(struct dw_hdmi *hdmi, 1694 struct drm_display_mode *mode) 1695 { 1696 struct hdmi_vendor_infoframe frame; 1697 u8 buffer[10]; 1698 ssize_t err; 1699 1700 err = drm_hdmi_vendor_infoframe_from_display_mode(&frame, 1701 &hdmi->connector, 1702 mode); 1703 if (err < 0) 1704 /* 1705 * Going into that statement does not means vendor infoframe 1706 * fails. It just informed us that vendor infoframe is not 1707 * needed for the selected mode. Only 4k or stereoscopic 3D 1708 * mode requires vendor infoframe. So just simply return. 1709 */ 1710 return; 1711 1712 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer)); 1713 if (err < 0) { 1714 dev_err(hdmi->dev, "Failed to pack vendor infoframe: %zd\n", 1715 err); 1716 return; 1717 } 1718 hdmi_mask_writeb(hdmi, 0, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1719 HDMI_FC_DATAUTO0_VSD_MASK); 1720 1721 /* Set the length of HDMI vendor specific InfoFrame payload */ 1722 hdmi_writeb(hdmi, buffer[2], HDMI_FC_VSDSIZE); 1723 1724 /* Set 24bit IEEE Registration Identifier */ 1725 hdmi_writeb(hdmi, buffer[4], HDMI_FC_VSDIEEEID0); 1726 hdmi_writeb(hdmi, buffer[5], HDMI_FC_VSDIEEEID1); 1727 hdmi_writeb(hdmi, buffer[6], HDMI_FC_VSDIEEEID2); 1728 1729 /* Set HDMI_Video_Format and HDMI_VIC/3D_Structure */ 1730 hdmi_writeb(hdmi, buffer[7], HDMI_FC_VSDPAYLOAD0); 1731 hdmi_writeb(hdmi, buffer[8], HDMI_FC_VSDPAYLOAD1); 1732 1733 if (frame.s3d_struct >= HDMI_3D_STRUCTURE_SIDE_BY_SIDE_HALF) 1734 hdmi_writeb(hdmi, buffer[9], HDMI_FC_VSDPAYLOAD2); 1735 1736 /* Packet frame interpolation */ 1737 hdmi_writeb(hdmi, 1, HDMI_FC_DATAUTO1); 1738 1739 /* Auto packets per frame and line spacing */ 1740 hdmi_writeb(hdmi, 0x11, HDMI_FC_DATAUTO2); 1741 1742 /* Configures the Frame Composer On RDRB mode */ 1743 hdmi_mask_writeb(hdmi, 1, HDMI_FC_DATAUTO0, HDMI_FC_DATAUTO0_VSD_OFFSET, 1744 HDMI_FC_DATAUTO0_VSD_MASK); 1745 } 1746 1747 static void hdmi_config_drm_infoframe(struct dw_hdmi *hdmi) 1748 { 1749 const struct drm_connector_state *conn_state = hdmi->connector.state; 1750 struct hdmi_drm_infoframe frame; 1751 u8 buffer[30]; 1752 ssize_t err; 1753 int i; 1754 1755 if (!hdmi->plat_data->use_drm_infoframe) 1756 return; 1757 1758 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_DISABLE, 1759 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1760 1761 err = drm_hdmi_infoframe_set_hdr_metadata(&frame, conn_state); 1762 if (err < 0) 1763 return; 1764 1765 err = hdmi_drm_infoframe_pack(&frame, buffer, sizeof(buffer)); 1766 if (err < 0) { 1767 dev_err(hdmi->dev, "Failed to pack drm infoframe: %zd\n", err); 1768 return; 1769 } 1770 1771 hdmi_writeb(hdmi, frame.version, HDMI_FC_DRM_HB0); 1772 hdmi_writeb(hdmi, frame.length, HDMI_FC_DRM_HB1); 1773 1774 for (i = 0; i < frame.length; i++) 1775 hdmi_writeb(hdmi, buffer[4 + i], HDMI_FC_DRM_PB0 + i); 1776 1777 hdmi_writeb(hdmi, 1, HDMI_FC_DRM_UP); 1778 hdmi_modb(hdmi, HDMI_FC_PACKET_TX_EN_DRM_ENABLE, 1779 HDMI_FC_PACKET_TX_EN_DRM_MASK, HDMI_FC_PACKET_TX_EN); 1780 } 1781 1782 static void hdmi_av_composer(struct dw_hdmi *hdmi, 1783 const struct drm_display_mode *mode) 1784 { 1785 u8 inv_val, bytes; 1786 struct drm_hdmi_info *hdmi_info = &hdmi->connector.display_info.hdmi; 1787 struct hdmi_vmode *vmode = &hdmi->hdmi_data.video_mode; 1788 int hblank, vblank, h_de_hs, v_de_vs, hsync_len, vsync_len; 1789 unsigned int vdisplay, hdisplay; 1790 1791 vmode->mtmdsclock = vmode->mpixelclock = mode->clock * 1000; 1792 1793 dev_dbg(hdmi->dev, "final pixclk = %d\n", vmode->mpixelclock); 1794 1795 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) 1796 vmode->mtmdsclock /= 2; 1797 1798 /* Set up HDMI_FC_INVIDCONF */ 1799 inv_val = (hdmi->hdmi_data.hdcp_enable || 1800 (dw_hdmi_support_scdc(hdmi) && 1801 (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1802 hdmi_info->scdc.scrambling.low_rates)) ? 1803 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE : 1804 HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE); 1805 1806 inv_val |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 1807 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH : 1808 HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW; 1809 1810 inv_val |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 1811 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH : 1812 HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW; 1813 1814 inv_val |= (vmode->mdataenablepolarity ? 1815 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH : 1816 HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW); 1817 1818 if (hdmi->vic == 39) 1819 inv_val |= HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH; 1820 else 1821 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1822 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH : 1823 HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW; 1824 1825 inv_val |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 1826 HDMI_FC_INVIDCONF_IN_I_P_INTERLACED : 1827 HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE; 1828 1829 inv_val |= hdmi->sink_is_hdmi ? 1830 HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE : 1831 HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE; 1832 1833 hdmi_writeb(hdmi, inv_val, HDMI_FC_INVIDCONF); 1834 1835 hdisplay = mode->hdisplay; 1836 hblank = mode->htotal - mode->hdisplay; 1837 h_de_hs = mode->hsync_start - mode->hdisplay; 1838 hsync_len = mode->hsync_end - mode->hsync_start; 1839 1840 /* 1841 * When we're setting a YCbCr420 mode, we need 1842 * to adjust the horizontal timing to suit. 1843 */ 1844 if (hdmi_bus_fmt_is_yuv420(hdmi->hdmi_data.enc_out_bus_format)) { 1845 hdisplay /= 2; 1846 hblank /= 2; 1847 h_de_hs /= 2; 1848 hsync_len /= 2; 1849 } 1850 1851 vdisplay = mode->vdisplay; 1852 vblank = mode->vtotal - mode->vdisplay; 1853 v_de_vs = mode->vsync_start - mode->vdisplay; 1854 vsync_len = mode->vsync_end - mode->vsync_start; 1855 1856 /* 1857 * When we're setting an interlaced mode, we need 1858 * to adjust the vertical timing to suit. 1859 */ 1860 if (mode->flags & DRM_MODE_FLAG_INTERLACE) { 1861 vdisplay /= 2; 1862 vblank /= 2; 1863 v_de_vs /= 2; 1864 vsync_len /= 2; 1865 } 1866 1867 /* Scrambling Control */ 1868 if (dw_hdmi_support_scdc(hdmi)) { 1869 if (vmode->mtmdsclock > HDMI14_MAX_TMDSCLK || 1870 hdmi_info->scdc.scrambling.low_rates) { 1871 /* 1872 * HDMI2.0 Specifies the following procedure: 1873 * After the Source Device has determined that 1874 * SCDC_Present is set (=1), the Source Device should 1875 * write the accurate Version of the Source Device 1876 * to the Source Version field in the SCDCS. 1877 * Source Devices compliant shall set the 1878 * Source Version = 1. 1879 */ 1880 drm_scdc_readb(hdmi->ddc, SCDC_SINK_VERSION, 1881 &bytes); 1882 drm_scdc_writeb(hdmi->ddc, SCDC_SOURCE_VERSION, 1883 min_t(u8, bytes, SCDC_MIN_SOURCE_VERSION)); 1884 1885 /* Enabled Scrambling in the Sink */ 1886 drm_scdc_set_scrambling(hdmi->ddc, 1); 1887 1888 /* 1889 * To activate the scrambler feature, you must ensure 1890 * that the quasi-static configuration bit 1891 * fc_invidconf.HDCP_keepout is set at configuration 1892 * time, before the required mc_swrstzreq.tmdsswrst_req 1893 * reset request is issued. 1894 */ 1895 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1896 HDMI_MC_SWRSTZ); 1897 hdmi_writeb(hdmi, 1, HDMI_FC_SCRAMBLER_CTRL); 1898 } else { 1899 hdmi_writeb(hdmi, 0, HDMI_FC_SCRAMBLER_CTRL); 1900 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, 1901 HDMI_MC_SWRSTZ); 1902 drm_scdc_set_scrambling(hdmi->ddc, 0); 1903 } 1904 } 1905 1906 /* Set up horizontal active pixel width */ 1907 hdmi_writeb(hdmi, hdisplay >> 8, HDMI_FC_INHACTV1); 1908 hdmi_writeb(hdmi, hdisplay, HDMI_FC_INHACTV0); 1909 1910 /* Set up vertical active lines */ 1911 hdmi_writeb(hdmi, vdisplay >> 8, HDMI_FC_INVACTV1); 1912 hdmi_writeb(hdmi, vdisplay, HDMI_FC_INVACTV0); 1913 1914 /* Set up horizontal blanking pixel region width */ 1915 hdmi_writeb(hdmi, hblank >> 8, HDMI_FC_INHBLANK1); 1916 hdmi_writeb(hdmi, hblank, HDMI_FC_INHBLANK0); 1917 1918 /* Set up vertical blanking pixel region width */ 1919 hdmi_writeb(hdmi, vblank, HDMI_FC_INVBLANK); 1920 1921 /* Set up HSYNC active edge delay width (in pixel clks) */ 1922 hdmi_writeb(hdmi, h_de_hs >> 8, HDMI_FC_HSYNCINDELAY1); 1923 hdmi_writeb(hdmi, h_de_hs, HDMI_FC_HSYNCINDELAY0); 1924 1925 /* Set up VSYNC active edge delay (in lines) */ 1926 hdmi_writeb(hdmi, v_de_vs, HDMI_FC_VSYNCINDELAY); 1927 1928 /* Set up HSYNC active pulse width (in pixel clks) */ 1929 hdmi_writeb(hdmi, hsync_len >> 8, HDMI_FC_HSYNCINWIDTH1); 1930 hdmi_writeb(hdmi, hsync_len, HDMI_FC_HSYNCINWIDTH0); 1931 1932 /* Set up VSYNC active edge delay (in lines) */ 1933 hdmi_writeb(hdmi, vsync_len, HDMI_FC_VSYNCINWIDTH); 1934 } 1935 1936 /* HDMI Initialization Step B.4 */ 1937 static void dw_hdmi_enable_video_path(struct dw_hdmi *hdmi) 1938 { 1939 /* control period minimum duration */ 1940 hdmi_writeb(hdmi, 12, HDMI_FC_CTRLDUR); 1941 hdmi_writeb(hdmi, 32, HDMI_FC_EXCTRLDUR); 1942 hdmi_writeb(hdmi, 1, HDMI_FC_EXCTRLSPAC); 1943 1944 /* Set to fill TMDS data channels */ 1945 hdmi_writeb(hdmi, 0x0B, HDMI_FC_CH0PREAM); 1946 hdmi_writeb(hdmi, 0x16, HDMI_FC_CH1PREAM); 1947 hdmi_writeb(hdmi, 0x21, HDMI_FC_CH2PREAM); 1948 1949 /* Enable pixel clock and tmds data path */ 1950 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_HDCPCLK_DISABLE | 1951 HDMI_MC_CLKDIS_CSCCLK_DISABLE | 1952 HDMI_MC_CLKDIS_AUDCLK_DISABLE | 1953 HDMI_MC_CLKDIS_PREPCLK_DISABLE | 1954 HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1955 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_PIXELCLK_DISABLE; 1956 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1957 1958 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_TMDSCLK_DISABLE; 1959 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1960 1961 /* Enable csc path */ 1962 if (is_color_space_conversion(hdmi)) { 1963 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CSCCLK_DISABLE; 1964 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 1965 } 1966 1967 /* Enable color space conversion if needed */ 1968 if (is_color_space_conversion(hdmi)) 1969 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH, 1970 HDMI_MC_FLOWCTRL); 1971 else 1972 hdmi_writeb(hdmi, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS, 1973 HDMI_MC_FLOWCTRL); 1974 } 1975 1976 /* Workaround to clear the overflow condition */ 1977 static void dw_hdmi_clear_overflow(struct dw_hdmi *hdmi) 1978 { 1979 unsigned int count; 1980 unsigned int i; 1981 u8 val; 1982 1983 /* 1984 * Under some circumstances the Frame Composer arithmetic unit can miss 1985 * an FC register write due to being busy processing the previous one. 1986 * The issue can be worked around by issuing a TMDS software reset and 1987 * then write one of the FC registers several times. 1988 * 1989 * The number of iterations matters and depends on the HDMI TX revision 1990 * (and possibly on the platform). So far i.MX6Q (v1.30a), i.MX6DL 1991 * (v1.31a) and multiple Allwinner SoCs (v1.32a) have been identified 1992 * as needing the workaround, with 4 iterations for v1.30a and 1 1993 * iteration for others. 1994 * The Amlogic Meson GX SoCs (v2.01a) have been identified as needing 1995 * the workaround with a single iteration. 1996 * The Rockchip RK3288 SoC (v2.00a) and RK3328/RK3399 SoCs (v2.11a) have 1997 * been identified as needing the workaround with a single iteration. 1998 */ 1999 2000 switch (hdmi->version) { 2001 case 0x130a: 2002 count = 4; 2003 break; 2004 case 0x131a: 2005 case 0x132a: 2006 case 0x200a: 2007 case 0x201a: 2008 case 0x211a: 2009 case 0x212a: 2010 count = 1; 2011 break; 2012 default: 2013 return; 2014 } 2015 2016 /* TMDS software reset */ 2017 hdmi_writeb(hdmi, (u8)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ, HDMI_MC_SWRSTZ); 2018 2019 val = hdmi_readb(hdmi, HDMI_FC_INVIDCONF); 2020 for (i = 0; i < count; i++) 2021 hdmi_writeb(hdmi, val, HDMI_FC_INVIDCONF); 2022 } 2023 2024 static void hdmi_disable_overflow_interrupts(struct dw_hdmi *hdmi) 2025 { 2026 hdmi_writeb(hdmi, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK, 2027 HDMI_IH_MUTE_FC_STAT2); 2028 } 2029 2030 static int dw_hdmi_setup(struct dw_hdmi *hdmi, struct drm_display_mode *mode) 2031 { 2032 int ret; 2033 2034 hdmi_disable_overflow_interrupts(hdmi); 2035 2036 hdmi->vic = drm_match_cea_mode(mode); 2037 2038 if (!hdmi->vic) { 2039 dev_dbg(hdmi->dev, "Non-CEA mode used in HDMI\n"); 2040 } else { 2041 dev_dbg(hdmi->dev, "CEA mode used vic=%d\n", hdmi->vic); 2042 } 2043 2044 if ((hdmi->vic == 6) || (hdmi->vic == 7) || 2045 (hdmi->vic == 21) || (hdmi->vic == 22) || 2046 (hdmi->vic == 2) || (hdmi->vic == 3) || 2047 (hdmi->vic == 17) || (hdmi->vic == 18)) 2048 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_601; 2049 else 2050 hdmi->hdmi_data.enc_out_encoding = V4L2_YCBCR_ENC_709; 2051 2052 hdmi->hdmi_data.video_mode.mpixelrepetitionoutput = 0; 2053 hdmi->hdmi_data.video_mode.mpixelrepetitioninput = 0; 2054 2055 /* TOFIX: Get input format from plat data or fallback to RGB888 */ 2056 if (hdmi->plat_data->input_bus_format) 2057 hdmi->hdmi_data.enc_in_bus_format = 2058 hdmi->plat_data->input_bus_format; 2059 else 2060 hdmi->hdmi_data.enc_in_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2061 2062 /* TOFIX: Get input encoding from plat data or fallback to none */ 2063 if (hdmi->plat_data->input_bus_encoding) 2064 hdmi->hdmi_data.enc_in_encoding = 2065 hdmi->plat_data->input_bus_encoding; 2066 else 2067 hdmi->hdmi_data.enc_in_encoding = V4L2_YCBCR_ENC_DEFAULT; 2068 2069 /* TOFIX: Default to RGB888 output format */ 2070 hdmi->hdmi_data.enc_out_bus_format = MEDIA_BUS_FMT_RGB888_1X24; 2071 2072 hdmi->hdmi_data.pix_repet_factor = 0; 2073 hdmi->hdmi_data.hdcp_enable = 0; 2074 hdmi->hdmi_data.video_mode.mdataenablepolarity = true; 2075 2076 /* HDMI Initialization Step B.1 */ 2077 hdmi_av_composer(hdmi, mode); 2078 2079 /* HDMI Initializateion Step B.2 */ 2080 ret = hdmi->phy.ops->init(hdmi, hdmi->phy.data, &hdmi->previous_mode); 2081 if (ret) 2082 return ret; 2083 hdmi->phy.enabled = true; 2084 2085 /* HDMI Initialization Step B.3 */ 2086 dw_hdmi_enable_video_path(hdmi); 2087 2088 if (hdmi->sink_has_audio) { 2089 dev_dbg(hdmi->dev, "sink has audio support\n"); 2090 2091 /* HDMI Initialization Step E - Configure audio */ 2092 hdmi_clk_regenerator_update_pixel_clock(hdmi); 2093 hdmi_enable_audio_clk(hdmi, hdmi->audio_enable); 2094 } 2095 2096 /* not for DVI mode */ 2097 if (hdmi->sink_is_hdmi) { 2098 dev_dbg(hdmi->dev, "%s HDMI mode\n", __func__); 2099 2100 /* HDMI Initialization Step F - Configure AVI InfoFrame */ 2101 hdmi_config_AVI(hdmi, mode); 2102 hdmi_config_vendor_specific_infoframe(hdmi, mode); 2103 hdmi_config_drm_infoframe(hdmi); 2104 } else { 2105 dev_dbg(hdmi->dev, "%s DVI mode\n", __func__); 2106 } 2107 2108 hdmi_video_packetize(hdmi); 2109 hdmi_video_csc(hdmi); 2110 hdmi_video_sample(hdmi); 2111 hdmi_tx_hdcp_config(hdmi); 2112 2113 dw_hdmi_clear_overflow(hdmi); 2114 2115 return 0; 2116 } 2117 2118 static void initialize_hdmi_ih_mutes(struct dw_hdmi *hdmi) 2119 { 2120 u8 ih_mute; 2121 2122 /* 2123 * Boot up defaults are: 2124 * HDMI_IH_MUTE = 0x03 (disabled) 2125 * HDMI_IH_MUTE_* = 0x00 (enabled) 2126 * 2127 * Disable top level interrupt bits in HDMI block 2128 */ 2129 ih_mute = hdmi_readb(hdmi, HDMI_IH_MUTE) | 2130 HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2131 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT; 2132 2133 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2134 2135 /* by default mask all interrupts */ 2136 hdmi_writeb(hdmi, 0xff, HDMI_VP_MASK); 2137 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK0); 2138 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK1); 2139 hdmi_writeb(hdmi, 0xff, HDMI_FC_MASK2); 2140 hdmi_writeb(hdmi, 0xff, HDMI_PHY_MASK0); 2141 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_INT_ADDR); 2142 hdmi_writeb(hdmi, 0xff, HDMI_PHY_I2CM_CTLINT_ADDR); 2143 hdmi_writeb(hdmi, 0xff, HDMI_AUD_INT); 2144 hdmi_writeb(hdmi, 0xff, HDMI_AUD_SPDIFINT); 2145 hdmi_writeb(hdmi, 0xff, HDMI_AUD_HBR_MASK); 2146 hdmi_writeb(hdmi, 0xff, HDMI_GP_MASK); 2147 hdmi_writeb(hdmi, 0xff, HDMI_A_APIINTMSK); 2148 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_INT); 2149 hdmi_writeb(hdmi, 0xff, HDMI_I2CM_CTLINT); 2150 2151 /* Disable interrupts in the IH_MUTE_* registers */ 2152 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT0); 2153 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT1); 2154 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_FC_STAT2); 2155 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AS_STAT0); 2156 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_PHY_STAT0); 2157 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CM_STAT0); 2158 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_CEC_STAT0); 2159 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_VP_STAT0); 2160 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_I2CMPHY_STAT0); 2161 hdmi_writeb(hdmi, 0xff, HDMI_IH_MUTE_AHBDMAAUD_STAT0); 2162 2163 /* Enable top level interrupt bits in HDMI block */ 2164 ih_mute &= ~(HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT | 2165 HDMI_IH_MUTE_MUTE_ALL_INTERRUPT); 2166 hdmi_writeb(hdmi, ih_mute, HDMI_IH_MUTE); 2167 } 2168 2169 static void dw_hdmi_poweron(struct dw_hdmi *hdmi) 2170 { 2171 hdmi->bridge_is_on = true; 2172 dw_hdmi_setup(hdmi, &hdmi->previous_mode); 2173 } 2174 2175 static void dw_hdmi_poweroff(struct dw_hdmi *hdmi) 2176 { 2177 if (hdmi->phy.enabled) { 2178 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 2179 hdmi->phy.enabled = false; 2180 } 2181 2182 hdmi->bridge_is_on = false; 2183 } 2184 2185 static void dw_hdmi_update_power(struct dw_hdmi *hdmi) 2186 { 2187 int force = hdmi->force; 2188 2189 if (hdmi->disabled) { 2190 force = DRM_FORCE_OFF; 2191 } else if (force == DRM_FORCE_UNSPECIFIED) { 2192 if (hdmi->rxsense) 2193 force = DRM_FORCE_ON; 2194 else 2195 force = DRM_FORCE_OFF; 2196 } 2197 2198 if (force == DRM_FORCE_OFF) { 2199 if (hdmi->bridge_is_on) 2200 dw_hdmi_poweroff(hdmi); 2201 } else { 2202 if (!hdmi->bridge_is_on) 2203 dw_hdmi_poweron(hdmi); 2204 } 2205 } 2206 2207 /* 2208 * Adjust the detection of RXSENSE according to whether we have a forced 2209 * connection mode enabled, or whether we have been disabled. There is 2210 * no point processing RXSENSE interrupts if we have a forced connection 2211 * state, or DRM has us disabled. 2212 * 2213 * We also disable rxsense interrupts when we think we're disconnected 2214 * to avoid floating TDMS signals giving false rxsense interrupts. 2215 * 2216 * Note: we still need to listen for HPD interrupts even when DRM has us 2217 * disabled so that we can detect a connect event. 2218 */ 2219 static void dw_hdmi_update_phy_mask(struct dw_hdmi *hdmi) 2220 { 2221 if (hdmi->phy.ops->update_hpd) 2222 hdmi->phy.ops->update_hpd(hdmi, hdmi->phy.data, 2223 hdmi->force, hdmi->disabled, 2224 hdmi->rxsense); 2225 } 2226 2227 static enum drm_connector_status 2228 dw_hdmi_connector_detect(struct drm_connector *connector, bool force) 2229 { 2230 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2231 connector); 2232 2233 mutex_lock(&hdmi->mutex); 2234 hdmi->force = DRM_FORCE_UNSPECIFIED; 2235 dw_hdmi_update_power(hdmi); 2236 dw_hdmi_update_phy_mask(hdmi); 2237 mutex_unlock(&hdmi->mutex); 2238 2239 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 2240 } 2241 2242 static int dw_hdmi_connector_get_modes(struct drm_connector *connector) 2243 { 2244 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2245 connector); 2246 struct edid *edid; 2247 int ret = 0; 2248 2249 if (!hdmi->ddc) 2250 return 0; 2251 2252 edid = drm_get_edid(connector, hdmi->ddc); 2253 if (edid) { 2254 dev_dbg(hdmi->dev, "got edid: width[%d] x height[%d]\n", 2255 edid->width_cm, edid->height_cm); 2256 2257 hdmi->sink_is_hdmi = drm_detect_hdmi_monitor(edid); 2258 hdmi->sink_has_audio = drm_detect_monitor_audio(edid); 2259 drm_connector_update_edid_property(connector, edid); 2260 cec_notifier_set_phys_addr_from_edid(hdmi->cec_notifier, edid); 2261 ret = drm_add_edid_modes(connector, edid); 2262 kfree(edid); 2263 } else { 2264 dev_dbg(hdmi->dev, "failed to get edid\n"); 2265 } 2266 2267 return ret; 2268 } 2269 2270 static bool hdr_metadata_equal(const struct drm_connector_state *old_state, 2271 const struct drm_connector_state *new_state) 2272 { 2273 struct drm_property_blob *old_blob = old_state->hdr_output_metadata; 2274 struct drm_property_blob *new_blob = new_state->hdr_output_metadata; 2275 2276 if (!old_blob || !new_blob) 2277 return old_blob == new_blob; 2278 2279 if (old_blob->length != new_blob->length) 2280 return false; 2281 2282 return !memcmp(old_blob->data, new_blob->data, old_blob->length); 2283 } 2284 2285 static int dw_hdmi_connector_atomic_check(struct drm_connector *connector, 2286 struct drm_atomic_state *state) 2287 { 2288 struct drm_connector_state *old_state = 2289 drm_atomic_get_old_connector_state(state, connector); 2290 struct drm_connector_state *new_state = 2291 drm_atomic_get_new_connector_state(state, connector); 2292 struct drm_crtc *crtc = new_state->crtc; 2293 struct drm_crtc_state *crtc_state; 2294 2295 if (!crtc) 2296 return 0; 2297 2298 if (!hdr_metadata_equal(old_state, new_state)) { 2299 crtc_state = drm_atomic_get_crtc_state(state, crtc); 2300 if (IS_ERR(crtc_state)) 2301 return PTR_ERR(crtc_state); 2302 2303 crtc_state->mode_changed = true; 2304 } 2305 2306 return 0; 2307 } 2308 2309 static void dw_hdmi_connector_force(struct drm_connector *connector) 2310 { 2311 struct dw_hdmi *hdmi = container_of(connector, struct dw_hdmi, 2312 connector); 2313 2314 mutex_lock(&hdmi->mutex); 2315 hdmi->force = connector->force; 2316 dw_hdmi_update_power(hdmi); 2317 dw_hdmi_update_phy_mask(hdmi); 2318 mutex_unlock(&hdmi->mutex); 2319 } 2320 2321 static const struct drm_connector_funcs dw_hdmi_connector_funcs = { 2322 .fill_modes = drm_helper_probe_single_connector_modes, 2323 .detect = dw_hdmi_connector_detect, 2324 .destroy = drm_connector_cleanup, 2325 .force = dw_hdmi_connector_force, 2326 .reset = drm_atomic_helper_connector_reset, 2327 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 2328 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 2329 }; 2330 2331 static const struct drm_connector_helper_funcs dw_hdmi_connector_helper_funcs = { 2332 .get_modes = dw_hdmi_connector_get_modes, 2333 .atomic_check = dw_hdmi_connector_atomic_check, 2334 }; 2335 2336 static int dw_hdmi_bridge_attach(struct drm_bridge *bridge) 2337 { 2338 struct dw_hdmi *hdmi = bridge->driver_private; 2339 struct drm_encoder *encoder = bridge->encoder; 2340 struct drm_connector *connector = &hdmi->connector; 2341 struct cec_connector_info conn_info; 2342 struct cec_notifier *notifier; 2343 2344 connector->interlace_allowed = 1; 2345 connector->polled = DRM_CONNECTOR_POLL_HPD; 2346 2347 drm_connector_helper_add(connector, &dw_hdmi_connector_helper_funcs); 2348 2349 drm_connector_init_with_ddc(bridge->dev, connector, 2350 &dw_hdmi_connector_funcs, 2351 DRM_MODE_CONNECTOR_HDMIA, 2352 hdmi->ddc); 2353 2354 if (hdmi->version >= 0x200a && hdmi->plat_data->use_drm_infoframe) 2355 drm_object_attach_property(&connector->base, 2356 connector->dev->mode_config.hdr_output_metadata_property, 0); 2357 2358 drm_connector_attach_encoder(connector, encoder); 2359 2360 cec_fill_conn_info_from_drm(&conn_info, connector); 2361 2362 notifier = cec_notifier_conn_register(hdmi->dev, NULL, &conn_info); 2363 if (!notifier) 2364 return -ENOMEM; 2365 2366 mutex_lock(&hdmi->cec_notifier_mutex); 2367 hdmi->cec_notifier = notifier; 2368 mutex_unlock(&hdmi->cec_notifier_mutex); 2369 2370 return 0; 2371 } 2372 2373 static void dw_hdmi_bridge_detach(struct drm_bridge *bridge) 2374 { 2375 struct dw_hdmi *hdmi = bridge->driver_private; 2376 2377 mutex_lock(&hdmi->cec_notifier_mutex); 2378 cec_notifier_conn_unregister(hdmi->cec_notifier); 2379 hdmi->cec_notifier = NULL; 2380 mutex_unlock(&hdmi->cec_notifier_mutex); 2381 } 2382 2383 static enum drm_mode_status 2384 dw_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 2385 const struct drm_display_mode *mode) 2386 { 2387 struct dw_hdmi *hdmi = bridge->driver_private; 2388 struct drm_connector *connector = &hdmi->connector; 2389 enum drm_mode_status mode_status = MODE_OK; 2390 2391 /* We don't support double-clocked modes */ 2392 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 2393 return MODE_BAD; 2394 2395 if (hdmi->plat_data->mode_valid) 2396 mode_status = hdmi->plat_data->mode_valid(connector, mode); 2397 2398 return mode_status; 2399 } 2400 2401 static void dw_hdmi_bridge_mode_set(struct drm_bridge *bridge, 2402 const struct drm_display_mode *orig_mode, 2403 const struct drm_display_mode *mode) 2404 { 2405 struct dw_hdmi *hdmi = bridge->driver_private; 2406 2407 mutex_lock(&hdmi->mutex); 2408 2409 /* Store the display mode for plugin/DKMS poweron events */ 2410 memcpy(&hdmi->previous_mode, mode, sizeof(hdmi->previous_mode)); 2411 2412 mutex_unlock(&hdmi->mutex); 2413 } 2414 2415 static void dw_hdmi_bridge_disable(struct drm_bridge *bridge) 2416 { 2417 struct dw_hdmi *hdmi = bridge->driver_private; 2418 2419 mutex_lock(&hdmi->mutex); 2420 hdmi->disabled = true; 2421 dw_hdmi_update_power(hdmi); 2422 dw_hdmi_update_phy_mask(hdmi); 2423 mutex_unlock(&hdmi->mutex); 2424 } 2425 2426 static void dw_hdmi_bridge_enable(struct drm_bridge *bridge) 2427 { 2428 struct dw_hdmi *hdmi = bridge->driver_private; 2429 2430 mutex_lock(&hdmi->mutex); 2431 hdmi->disabled = false; 2432 dw_hdmi_update_power(hdmi); 2433 dw_hdmi_update_phy_mask(hdmi); 2434 mutex_unlock(&hdmi->mutex); 2435 } 2436 2437 static const struct drm_bridge_funcs dw_hdmi_bridge_funcs = { 2438 .attach = dw_hdmi_bridge_attach, 2439 .detach = dw_hdmi_bridge_detach, 2440 .enable = dw_hdmi_bridge_enable, 2441 .disable = dw_hdmi_bridge_disable, 2442 .mode_set = dw_hdmi_bridge_mode_set, 2443 .mode_valid = dw_hdmi_bridge_mode_valid, 2444 }; 2445 2446 static irqreturn_t dw_hdmi_i2c_irq(struct dw_hdmi *hdmi) 2447 { 2448 struct dw_hdmi_i2c *i2c = hdmi->i2c; 2449 unsigned int stat; 2450 2451 stat = hdmi_readb(hdmi, HDMI_IH_I2CM_STAT0); 2452 if (!stat) 2453 return IRQ_NONE; 2454 2455 hdmi_writeb(hdmi, stat, HDMI_IH_I2CM_STAT0); 2456 2457 i2c->stat = stat; 2458 2459 complete(&i2c->cmp); 2460 2461 return IRQ_HANDLED; 2462 } 2463 2464 static irqreturn_t dw_hdmi_hardirq(int irq, void *dev_id) 2465 { 2466 struct dw_hdmi *hdmi = dev_id; 2467 u8 intr_stat; 2468 irqreturn_t ret = IRQ_NONE; 2469 2470 if (hdmi->i2c) 2471 ret = dw_hdmi_i2c_irq(hdmi); 2472 2473 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2474 if (intr_stat) { 2475 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2476 return IRQ_WAKE_THREAD; 2477 } 2478 2479 return ret; 2480 } 2481 2482 void dw_hdmi_setup_rx_sense(struct dw_hdmi *hdmi, bool hpd, bool rx_sense) 2483 { 2484 mutex_lock(&hdmi->mutex); 2485 2486 if (!hdmi->force) { 2487 /* 2488 * If the RX sense status indicates we're disconnected, 2489 * clear the software rxsense status. 2490 */ 2491 if (!rx_sense) 2492 hdmi->rxsense = false; 2493 2494 /* 2495 * Only set the software rxsense status when both 2496 * rxsense and hpd indicates we're connected. 2497 * This avoids what seems to be bad behaviour in 2498 * at least iMX6S versions of the phy. 2499 */ 2500 if (hpd) 2501 hdmi->rxsense = true; 2502 2503 dw_hdmi_update_power(hdmi); 2504 dw_hdmi_update_phy_mask(hdmi); 2505 } 2506 mutex_unlock(&hdmi->mutex); 2507 } 2508 EXPORT_SYMBOL_GPL(dw_hdmi_setup_rx_sense); 2509 2510 static irqreturn_t dw_hdmi_irq(int irq, void *dev_id) 2511 { 2512 struct dw_hdmi *hdmi = dev_id; 2513 u8 intr_stat, phy_int_pol, phy_pol_mask, phy_stat; 2514 2515 intr_stat = hdmi_readb(hdmi, HDMI_IH_PHY_STAT0); 2516 phy_int_pol = hdmi_readb(hdmi, HDMI_PHY_POL0); 2517 phy_stat = hdmi_readb(hdmi, HDMI_PHY_STAT0); 2518 2519 phy_pol_mask = 0; 2520 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) 2521 phy_pol_mask |= HDMI_PHY_HPD; 2522 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE0) 2523 phy_pol_mask |= HDMI_PHY_RX_SENSE0; 2524 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE1) 2525 phy_pol_mask |= HDMI_PHY_RX_SENSE1; 2526 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE2) 2527 phy_pol_mask |= HDMI_PHY_RX_SENSE2; 2528 if (intr_stat & HDMI_IH_PHY_STAT0_RX_SENSE3) 2529 phy_pol_mask |= HDMI_PHY_RX_SENSE3; 2530 2531 if (phy_pol_mask) 2532 hdmi_modb(hdmi, ~phy_int_pol, phy_pol_mask, HDMI_PHY_POL0); 2533 2534 /* 2535 * RX sense tells us whether the TDMS transmitters are detecting 2536 * load - in other words, there's something listening on the 2537 * other end of the link. Use this to decide whether we should 2538 * power on the phy as HPD may be toggled by the sink to merely 2539 * ask the source to re-read the EDID. 2540 */ 2541 if (intr_stat & 2542 (HDMI_IH_PHY_STAT0_RX_SENSE | HDMI_IH_PHY_STAT0_HPD)) { 2543 dw_hdmi_setup_rx_sense(hdmi, 2544 phy_stat & HDMI_PHY_HPD, 2545 phy_stat & HDMI_PHY_RX_SENSE); 2546 2547 if ((phy_stat & (HDMI_PHY_RX_SENSE | HDMI_PHY_HPD)) == 0) { 2548 mutex_lock(&hdmi->cec_notifier_mutex); 2549 cec_notifier_phys_addr_invalidate(hdmi->cec_notifier); 2550 mutex_unlock(&hdmi->cec_notifier_mutex); 2551 } 2552 } 2553 2554 if (intr_stat & HDMI_IH_PHY_STAT0_HPD) { 2555 dev_dbg(hdmi->dev, "EVENT=%s\n", 2556 phy_int_pol & HDMI_PHY_HPD ? "plugin" : "plugout"); 2557 if (hdmi->bridge.dev) 2558 drm_helper_hpd_irq_event(hdmi->bridge.dev); 2559 } 2560 2561 hdmi_writeb(hdmi, intr_stat, HDMI_IH_PHY_STAT0); 2562 hdmi_writeb(hdmi, ~(HDMI_IH_PHY_STAT0_HPD | HDMI_IH_PHY_STAT0_RX_SENSE), 2563 HDMI_IH_MUTE_PHY_STAT0); 2564 2565 return IRQ_HANDLED; 2566 } 2567 2568 static const struct dw_hdmi_phy_data dw_hdmi_phys[] = { 2569 { 2570 .type = DW_HDMI_PHY_DWC_HDMI_TX_PHY, 2571 .name = "DWC HDMI TX PHY", 2572 .gen = 1, 2573 }, { 2574 .type = DW_HDMI_PHY_DWC_MHL_PHY_HEAC, 2575 .name = "DWC MHL PHY + HEAC PHY", 2576 .gen = 2, 2577 .has_svsret = true, 2578 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2579 }, { 2580 .type = DW_HDMI_PHY_DWC_MHL_PHY, 2581 .name = "DWC MHL PHY", 2582 .gen = 2, 2583 .has_svsret = true, 2584 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2585 }, { 2586 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY_HEAC, 2587 .name = "DWC HDMI 3D TX PHY + HEAC PHY", 2588 .gen = 2, 2589 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2590 }, { 2591 .type = DW_HDMI_PHY_DWC_HDMI_3D_TX_PHY, 2592 .name = "DWC HDMI 3D TX PHY", 2593 .gen = 2, 2594 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2595 }, { 2596 .type = DW_HDMI_PHY_DWC_HDMI20_TX_PHY, 2597 .name = "DWC HDMI 2.0 TX PHY", 2598 .gen = 2, 2599 .has_svsret = true, 2600 .configure = hdmi_phy_configure_dwc_hdmi_3d_tx, 2601 }, { 2602 .type = DW_HDMI_PHY_VENDOR_PHY, 2603 .name = "Vendor PHY", 2604 } 2605 }; 2606 2607 static int dw_hdmi_detect_phy(struct dw_hdmi *hdmi) 2608 { 2609 unsigned int i; 2610 u8 phy_type; 2611 2612 phy_type = hdmi->plat_data->phy_force_vendor ? 2613 DW_HDMI_PHY_VENDOR_PHY : 2614 hdmi_readb(hdmi, HDMI_CONFIG2_ID); 2615 2616 if (phy_type == DW_HDMI_PHY_VENDOR_PHY) { 2617 /* Vendor PHYs require support from the glue layer. */ 2618 if (!hdmi->plat_data->phy_ops || !hdmi->plat_data->phy_name) { 2619 dev_err(hdmi->dev, 2620 "Vendor HDMI PHY not supported by glue layer\n"); 2621 return -ENODEV; 2622 } 2623 2624 hdmi->phy.ops = hdmi->plat_data->phy_ops; 2625 hdmi->phy.data = hdmi->plat_data->phy_data; 2626 hdmi->phy.name = hdmi->plat_data->phy_name; 2627 return 0; 2628 } 2629 2630 /* Synopsys PHYs are handled internally. */ 2631 for (i = 0; i < ARRAY_SIZE(dw_hdmi_phys); ++i) { 2632 if (dw_hdmi_phys[i].type == phy_type) { 2633 hdmi->phy.ops = &dw_hdmi_synopsys_phy_ops; 2634 hdmi->phy.name = dw_hdmi_phys[i].name; 2635 hdmi->phy.data = (void *)&dw_hdmi_phys[i]; 2636 2637 if (!dw_hdmi_phys[i].configure && 2638 !hdmi->plat_data->configure_phy) { 2639 dev_err(hdmi->dev, "%s requires platform support\n", 2640 hdmi->phy.name); 2641 return -ENODEV; 2642 } 2643 2644 return 0; 2645 } 2646 } 2647 2648 dev_err(hdmi->dev, "Unsupported HDMI PHY type (%02x)\n", phy_type); 2649 return -ENODEV; 2650 } 2651 2652 static void dw_hdmi_cec_enable(struct dw_hdmi *hdmi) 2653 { 2654 mutex_lock(&hdmi->mutex); 2655 hdmi->mc_clkdis &= ~HDMI_MC_CLKDIS_CECCLK_DISABLE; 2656 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2657 mutex_unlock(&hdmi->mutex); 2658 } 2659 2660 static void dw_hdmi_cec_disable(struct dw_hdmi *hdmi) 2661 { 2662 mutex_lock(&hdmi->mutex); 2663 hdmi->mc_clkdis |= HDMI_MC_CLKDIS_CECCLK_DISABLE; 2664 hdmi_writeb(hdmi, hdmi->mc_clkdis, HDMI_MC_CLKDIS); 2665 mutex_unlock(&hdmi->mutex); 2666 } 2667 2668 static const struct dw_hdmi_cec_ops dw_hdmi_cec_ops = { 2669 .write = hdmi_writeb, 2670 .read = hdmi_readb, 2671 .enable = dw_hdmi_cec_enable, 2672 .disable = dw_hdmi_cec_disable, 2673 }; 2674 2675 static const struct regmap_config hdmi_regmap_8bit_config = { 2676 .reg_bits = 32, 2677 .val_bits = 8, 2678 .reg_stride = 1, 2679 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR, 2680 }; 2681 2682 static const struct regmap_config hdmi_regmap_32bit_config = { 2683 .reg_bits = 32, 2684 .val_bits = 32, 2685 .reg_stride = 4, 2686 .max_register = HDMI_I2CM_FS_SCL_LCNT_0_ADDR << 2, 2687 }; 2688 2689 static void dw_hdmi_init_hw(struct dw_hdmi *hdmi) 2690 { 2691 initialize_hdmi_ih_mutes(hdmi); 2692 2693 /* 2694 * Reset HDMI DDC I2C master controller and mute I2CM interrupts. 2695 * Even if we are using a separate i2c adapter doing this doesn't 2696 * hurt. 2697 */ 2698 dw_hdmi_i2c_init(hdmi); 2699 2700 if (hdmi->phy.ops->setup_hpd) 2701 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 2702 } 2703 2704 static struct dw_hdmi * 2705 __dw_hdmi_probe(struct platform_device *pdev, 2706 const struct dw_hdmi_plat_data *plat_data) 2707 { 2708 struct device *dev = &pdev->dev; 2709 struct device_node *np = dev->of_node; 2710 struct platform_device_info pdevinfo; 2711 struct device_node *ddc_node; 2712 struct dw_hdmi_cec_data cec; 2713 struct dw_hdmi *hdmi; 2714 struct resource *iores = NULL; 2715 int irq; 2716 int ret; 2717 u32 val = 1; 2718 u8 prod_id0; 2719 u8 prod_id1; 2720 u8 config0; 2721 u8 config3; 2722 2723 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 2724 if (!hdmi) 2725 return ERR_PTR(-ENOMEM); 2726 2727 hdmi->plat_data = plat_data; 2728 hdmi->dev = dev; 2729 hdmi->sample_rate = 48000; 2730 hdmi->disabled = true; 2731 hdmi->rxsense = true; 2732 hdmi->phy_mask = (u8)~(HDMI_PHY_HPD | HDMI_PHY_RX_SENSE); 2733 hdmi->mc_clkdis = 0x7f; 2734 2735 mutex_init(&hdmi->mutex); 2736 mutex_init(&hdmi->audio_mutex); 2737 mutex_init(&hdmi->cec_notifier_mutex); 2738 spin_lock_init(&hdmi->audio_lock); 2739 2740 ddc_node = of_parse_phandle(np, "ddc-i2c-bus", 0); 2741 if (ddc_node) { 2742 hdmi->ddc = of_get_i2c_adapter_by_node(ddc_node); 2743 of_node_put(ddc_node); 2744 if (!hdmi->ddc) { 2745 dev_dbg(hdmi->dev, "failed to read ddc node\n"); 2746 return ERR_PTR(-EPROBE_DEFER); 2747 } 2748 2749 } else { 2750 dev_dbg(hdmi->dev, "no ddc property found\n"); 2751 } 2752 2753 if (!plat_data->regm) { 2754 const struct regmap_config *reg_config; 2755 2756 of_property_read_u32(np, "reg-io-width", &val); 2757 switch (val) { 2758 case 4: 2759 reg_config = &hdmi_regmap_32bit_config; 2760 hdmi->reg_shift = 2; 2761 break; 2762 case 1: 2763 reg_config = &hdmi_regmap_8bit_config; 2764 break; 2765 default: 2766 dev_err(dev, "reg-io-width must be 1 or 4\n"); 2767 return ERR_PTR(-EINVAL); 2768 } 2769 2770 iores = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2771 hdmi->regs = devm_ioremap_resource(dev, iores); 2772 if (IS_ERR(hdmi->regs)) { 2773 ret = PTR_ERR(hdmi->regs); 2774 goto err_res; 2775 } 2776 2777 hdmi->regm = devm_regmap_init_mmio(dev, hdmi->regs, reg_config); 2778 if (IS_ERR(hdmi->regm)) { 2779 dev_err(dev, "Failed to configure regmap\n"); 2780 ret = PTR_ERR(hdmi->regm); 2781 goto err_res; 2782 } 2783 } else { 2784 hdmi->regm = plat_data->regm; 2785 } 2786 2787 hdmi->isfr_clk = devm_clk_get(hdmi->dev, "isfr"); 2788 if (IS_ERR(hdmi->isfr_clk)) { 2789 ret = PTR_ERR(hdmi->isfr_clk); 2790 dev_err(hdmi->dev, "Unable to get HDMI isfr clk: %d\n", ret); 2791 goto err_res; 2792 } 2793 2794 ret = clk_prepare_enable(hdmi->isfr_clk); 2795 if (ret) { 2796 dev_err(hdmi->dev, "Cannot enable HDMI isfr clock: %d\n", ret); 2797 goto err_res; 2798 } 2799 2800 hdmi->iahb_clk = devm_clk_get(hdmi->dev, "iahb"); 2801 if (IS_ERR(hdmi->iahb_clk)) { 2802 ret = PTR_ERR(hdmi->iahb_clk); 2803 dev_err(hdmi->dev, "Unable to get HDMI iahb clk: %d\n", ret); 2804 goto err_isfr; 2805 } 2806 2807 ret = clk_prepare_enable(hdmi->iahb_clk); 2808 if (ret) { 2809 dev_err(hdmi->dev, "Cannot enable HDMI iahb clock: %d\n", ret); 2810 goto err_isfr; 2811 } 2812 2813 hdmi->cec_clk = devm_clk_get(hdmi->dev, "cec"); 2814 if (PTR_ERR(hdmi->cec_clk) == -ENOENT) { 2815 hdmi->cec_clk = NULL; 2816 } else if (IS_ERR(hdmi->cec_clk)) { 2817 ret = PTR_ERR(hdmi->cec_clk); 2818 if (ret != -EPROBE_DEFER) 2819 dev_err(hdmi->dev, "Cannot get HDMI cec clock: %d\n", 2820 ret); 2821 2822 hdmi->cec_clk = NULL; 2823 goto err_iahb; 2824 } else { 2825 ret = clk_prepare_enable(hdmi->cec_clk); 2826 if (ret) { 2827 dev_err(hdmi->dev, "Cannot enable HDMI cec clock: %d\n", 2828 ret); 2829 goto err_iahb; 2830 } 2831 } 2832 2833 /* Product and revision IDs */ 2834 hdmi->version = (hdmi_readb(hdmi, HDMI_DESIGN_ID) << 8) 2835 | (hdmi_readb(hdmi, HDMI_REVISION_ID) << 0); 2836 prod_id0 = hdmi_readb(hdmi, HDMI_PRODUCT_ID0); 2837 prod_id1 = hdmi_readb(hdmi, HDMI_PRODUCT_ID1); 2838 2839 if (prod_id0 != HDMI_PRODUCT_ID0_HDMI_TX || 2840 (prod_id1 & ~HDMI_PRODUCT_ID1_HDCP) != HDMI_PRODUCT_ID1_HDMI_TX) { 2841 dev_err(dev, "Unsupported HDMI controller (%04x:%02x:%02x)\n", 2842 hdmi->version, prod_id0, prod_id1); 2843 ret = -ENODEV; 2844 goto err_iahb; 2845 } 2846 2847 ret = dw_hdmi_detect_phy(hdmi); 2848 if (ret < 0) 2849 goto err_iahb; 2850 2851 dev_info(dev, "Detected HDMI TX controller v%x.%03x %s HDCP (%s)\n", 2852 hdmi->version >> 12, hdmi->version & 0xfff, 2853 prod_id1 & HDMI_PRODUCT_ID1_HDCP ? "with" : "without", 2854 hdmi->phy.name); 2855 2856 dw_hdmi_init_hw(hdmi); 2857 2858 irq = platform_get_irq(pdev, 0); 2859 if (irq < 0) { 2860 ret = irq; 2861 goto err_iahb; 2862 } 2863 2864 ret = devm_request_threaded_irq(dev, irq, dw_hdmi_hardirq, 2865 dw_hdmi_irq, IRQF_SHARED, 2866 dev_name(dev), hdmi); 2867 if (ret) 2868 goto err_iahb; 2869 2870 /* 2871 * To prevent overflows in HDMI_IH_FC_STAT2, set the clk regenerator 2872 * N and cts values before enabling phy 2873 */ 2874 hdmi_init_clk_regenerator(hdmi); 2875 2876 /* If DDC bus is not specified, try to register HDMI I2C bus */ 2877 if (!hdmi->ddc) { 2878 /* Look for (optional) stuff related to unwedging */ 2879 hdmi->pinctrl = devm_pinctrl_get(dev); 2880 if (!IS_ERR(hdmi->pinctrl)) { 2881 hdmi->unwedge_state = 2882 pinctrl_lookup_state(hdmi->pinctrl, "unwedge"); 2883 hdmi->default_state = 2884 pinctrl_lookup_state(hdmi->pinctrl, "default"); 2885 2886 if (IS_ERR(hdmi->default_state) || 2887 IS_ERR(hdmi->unwedge_state)) { 2888 if (!IS_ERR(hdmi->unwedge_state)) 2889 dev_warn(dev, 2890 "Unwedge requires default pinctrl\n"); 2891 hdmi->default_state = NULL; 2892 hdmi->unwedge_state = NULL; 2893 } 2894 } 2895 2896 hdmi->ddc = dw_hdmi_i2c_adapter(hdmi); 2897 if (IS_ERR(hdmi->ddc)) 2898 hdmi->ddc = NULL; 2899 } 2900 2901 hdmi->bridge.driver_private = hdmi; 2902 hdmi->bridge.funcs = &dw_hdmi_bridge_funcs; 2903 #ifdef CONFIG_OF 2904 hdmi->bridge.of_node = pdev->dev.of_node; 2905 #endif 2906 2907 memset(&pdevinfo, 0, sizeof(pdevinfo)); 2908 pdevinfo.parent = dev; 2909 pdevinfo.id = PLATFORM_DEVID_AUTO; 2910 2911 config0 = hdmi_readb(hdmi, HDMI_CONFIG0_ID); 2912 config3 = hdmi_readb(hdmi, HDMI_CONFIG3_ID); 2913 2914 if (iores && config3 & HDMI_CONFIG3_AHBAUDDMA) { 2915 struct dw_hdmi_audio_data audio; 2916 2917 audio.phys = iores->start; 2918 audio.base = hdmi->regs; 2919 audio.irq = irq; 2920 audio.hdmi = hdmi; 2921 audio.eld = hdmi->connector.eld; 2922 hdmi->enable_audio = dw_hdmi_ahb_audio_enable; 2923 hdmi->disable_audio = dw_hdmi_ahb_audio_disable; 2924 2925 pdevinfo.name = "dw-hdmi-ahb-audio"; 2926 pdevinfo.data = &audio; 2927 pdevinfo.size_data = sizeof(audio); 2928 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2929 hdmi->audio = platform_device_register_full(&pdevinfo); 2930 } else if (config0 & HDMI_CONFIG0_I2S) { 2931 struct dw_hdmi_i2s_audio_data audio; 2932 2933 audio.hdmi = hdmi; 2934 audio.eld = hdmi->connector.eld; 2935 audio.write = hdmi_writeb; 2936 audio.read = hdmi_readb; 2937 hdmi->enable_audio = dw_hdmi_i2s_audio_enable; 2938 hdmi->disable_audio = dw_hdmi_i2s_audio_disable; 2939 2940 pdevinfo.name = "dw-hdmi-i2s-audio"; 2941 pdevinfo.data = &audio; 2942 pdevinfo.size_data = sizeof(audio); 2943 pdevinfo.dma_mask = DMA_BIT_MASK(32); 2944 hdmi->audio = platform_device_register_full(&pdevinfo); 2945 } 2946 2947 if (config0 & HDMI_CONFIG0_CEC) { 2948 cec.hdmi = hdmi; 2949 cec.ops = &dw_hdmi_cec_ops; 2950 cec.irq = irq; 2951 2952 pdevinfo.name = "dw-hdmi-cec"; 2953 pdevinfo.data = &cec; 2954 pdevinfo.size_data = sizeof(cec); 2955 pdevinfo.dma_mask = 0; 2956 2957 hdmi->cec = platform_device_register_full(&pdevinfo); 2958 } 2959 2960 return hdmi; 2961 2962 err_iahb: 2963 if (hdmi->i2c) { 2964 i2c_del_adapter(&hdmi->i2c->adap); 2965 hdmi->ddc = NULL; 2966 } 2967 2968 clk_disable_unprepare(hdmi->iahb_clk); 2969 if (hdmi->cec_clk) 2970 clk_disable_unprepare(hdmi->cec_clk); 2971 err_isfr: 2972 clk_disable_unprepare(hdmi->isfr_clk); 2973 err_res: 2974 i2c_put_adapter(hdmi->ddc); 2975 2976 return ERR_PTR(ret); 2977 } 2978 2979 static void __dw_hdmi_remove(struct dw_hdmi *hdmi) 2980 { 2981 if (hdmi->audio && !IS_ERR(hdmi->audio)) 2982 platform_device_unregister(hdmi->audio); 2983 if (!IS_ERR(hdmi->cec)) 2984 platform_device_unregister(hdmi->cec); 2985 2986 /* Disable all interrupts */ 2987 hdmi_writeb(hdmi, ~0, HDMI_IH_MUTE_PHY_STAT0); 2988 2989 clk_disable_unprepare(hdmi->iahb_clk); 2990 clk_disable_unprepare(hdmi->isfr_clk); 2991 if (hdmi->cec_clk) 2992 clk_disable_unprepare(hdmi->cec_clk); 2993 2994 if (hdmi->i2c) 2995 i2c_del_adapter(&hdmi->i2c->adap); 2996 else 2997 i2c_put_adapter(hdmi->ddc); 2998 } 2999 3000 /* ----------------------------------------------------------------------------- 3001 * Probe/remove API, used from platforms based on the DRM bridge API. 3002 */ 3003 struct dw_hdmi *dw_hdmi_probe(struct platform_device *pdev, 3004 const struct dw_hdmi_plat_data *plat_data) 3005 { 3006 struct dw_hdmi *hdmi; 3007 3008 hdmi = __dw_hdmi_probe(pdev, plat_data); 3009 if (IS_ERR(hdmi)) 3010 return hdmi; 3011 3012 drm_bridge_add(&hdmi->bridge); 3013 3014 return hdmi; 3015 } 3016 EXPORT_SYMBOL_GPL(dw_hdmi_probe); 3017 3018 void dw_hdmi_remove(struct dw_hdmi *hdmi) 3019 { 3020 drm_bridge_remove(&hdmi->bridge); 3021 3022 __dw_hdmi_remove(hdmi); 3023 } 3024 EXPORT_SYMBOL_GPL(dw_hdmi_remove); 3025 3026 /* ----------------------------------------------------------------------------- 3027 * Bind/unbind API, used from platforms based on the component framework. 3028 */ 3029 struct dw_hdmi *dw_hdmi_bind(struct platform_device *pdev, 3030 struct drm_encoder *encoder, 3031 const struct dw_hdmi_plat_data *plat_data) 3032 { 3033 struct dw_hdmi *hdmi; 3034 int ret; 3035 3036 hdmi = __dw_hdmi_probe(pdev, plat_data); 3037 if (IS_ERR(hdmi)) 3038 return hdmi; 3039 3040 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL); 3041 if (ret) { 3042 dw_hdmi_remove(hdmi); 3043 DRM_ERROR("Failed to initialize bridge with drm\n"); 3044 return ERR_PTR(ret); 3045 } 3046 3047 return hdmi; 3048 } 3049 EXPORT_SYMBOL_GPL(dw_hdmi_bind); 3050 3051 void dw_hdmi_unbind(struct dw_hdmi *hdmi) 3052 { 3053 __dw_hdmi_remove(hdmi); 3054 } 3055 EXPORT_SYMBOL_GPL(dw_hdmi_unbind); 3056 3057 void dw_hdmi_resume(struct dw_hdmi *hdmi) 3058 { 3059 dw_hdmi_init_hw(hdmi); 3060 } 3061 EXPORT_SYMBOL_GPL(dw_hdmi_resume); 3062 3063 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>"); 3064 MODULE_AUTHOR("Andy Yan <andy.yan@rock-chips.com>"); 3065 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>"); 3066 MODULE_AUTHOR("Vladimir Zapolskiy <vladimir_zapolskiy@mentor.com>"); 3067 MODULE_DESCRIPTION("DW HDMI transmitter driver"); 3068 MODULE_LICENSE("GPL"); 3069 MODULE_ALIAS("platform:dw-hdmi"); 3070