1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2024 Collabora Ltd. 5 * 6 * Author: Algea Cao <algea.cao@rock-chips.com> 7 * Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> 8 */ 9 #include <linux/completion.h> 10 #include <linux/hdmi.h> 11 #include <linux/export.h> 12 #include <linux/i2c.h> 13 #include <linux/irq.h> 14 #include <linux/minmax.h> 15 #include <linux/module.h> 16 #include <linux/mutex.h> 17 #include <linux/of.h> 18 #include <linux/workqueue.h> 19 20 #include <drm/bridge/dw_hdmi_qp.h> 21 #include <drm/display/drm_hdmi_helper.h> 22 #include <drm/display/drm_hdmi_cec_helper.h> 23 #include <drm/display/drm_hdmi_state_helper.h> 24 #include <drm/drm_atomic.h> 25 #include <drm/drm_atomic_helper.h> 26 #include <drm/drm_bridge.h> 27 #include <drm/drm_connector.h> 28 #include <drm/drm_edid.h> 29 #include <drm/drm_modes.h> 30 #include <drm/drm_print.h> 31 32 #include <media/cec.h> 33 34 #include <sound/hdmi-codec.h> 35 36 #include "dw-hdmi-qp.h" 37 38 #define DDC_CI_ADDR 0x37 39 #define DDC_SEGMENT_ADDR 0x30 40 41 #define HDMI14_MAX_TMDSCLK 340000000 42 43 #define SCRAMB_POLL_DELAY_MS 3000 44 45 /* 46 * Unless otherwise noted, entries in this table are 100% optimization. 47 * Values can be obtained from dw_hdmi_qp_compute_n() but that function is 48 * slow so we pre-compute values we expect to see. 49 * 50 * The values for TMDS 25175, 25200, 27000, 54000, 74250 and 148500 kHz are 51 * the recommended N values specified in the Audio chapter of the HDMI 52 * specification. 53 */ 54 static const struct dw_hdmi_audio_tmds_n { 55 unsigned long tmds; 56 unsigned int n_32k; 57 unsigned int n_44k1; 58 unsigned int n_48k; 59 } common_tmds_n_table[] = { 60 { .tmds = 25175000, .n_32k = 4576, .n_44k1 = 7007, .n_48k = 6864, }, 61 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 62 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 63 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, }, 64 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, }, 65 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 66 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 67 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 68 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 69 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 70 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 71 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 72 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 73 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 74 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, }, 75 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 76 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, }, 77 { .tmds = 73250000, .n_32k = 11648, .n_44k1 = 14112, .n_48k = 6144, }, 78 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 79 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, }, 80 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 81 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 82 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 83 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 84 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 85 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 86 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 87 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 88 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 89 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 90 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, }, 91 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 92 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 93 { .tmds = 146250000, .n_32k = 11648, .n_44k1 = 6272, .n_48k = 6144, }, 94 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 95 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 96 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 97 98 /* For 297 MHz+ HDMI spec have some other rule for setting N */ 99 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, }, 100 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240,}, 101 102 /* End of table */ 103 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, }, 104 }; 105 106 /* 107 * These are the CTS values as recommended in the Audio chapter of the HDMI 108 * specification. 109 */ 110 static const struct dw_hdmi_audio_tmds_cts { 111 unsigned long tmds; 112 unsigned int cts_32k; 113 unsigned int cts_44k1; 114 unsigned int cts_48k; 115 } common_tmds_cts_table[] = { 116 { .tmds = 25175000, .cts_32k = 28125, .cts_44k1 = 31250, .cts_48k = 28125, }, 117 { .tmds = 25200000, .cts_32k = 25200, .cts_44k1 = 28000, .cts_48k = 25200, }, 118 { .tmds = 27000000, .cts_32k = 27000, .cts_44k1 = 30000, .cts_48k = 27000, }, 119 { .tmds = 54000000, .cts_32k = 54000, .cts_44k1 = 60000, .cts_48k = 54000, }, 120 { .tmds = 74250000, .cts_32k = 74250, .cts_44k1 = 82500, .cts_48k = 74250, }, 121 { .tmds = 148500000, .cts_32k = 148500, .cts_44k1 = 165000, .cts_48k = 148500, }, 122 123 /* End of table */ 124 { .tmds = 0, .cts_32k = 0, .cts_44k1 = 0, .cts_48k = 0, }, 125 }; 126 127 struct dw_hdmi_qp_i2c { 128 struct i2c_adapter adap; 129 130 struct mutex lock; /* used to serialize data transfers */ 131 struct completion cmp; 132 u8 stat; 133 134 u8 slave_reg; 135 bool is_regaddr; 136 bool is_segment; 137 }; 138 139 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC 140 struct dw_hdmi_qp_cec { 141 struct drm_connector *connector; 142 int irq; 143 u32 addresses; 144 struct cec_msg rx_msg; 145 u8 tx_status; 146 bool tx_done; 147 bool rx_done; 148 }; 149 #endif 150 151 struct dw_hdmi_qp { 152 struct drm_bridge bridge; 153 154 struct device *dev; 155 struct dw_hdmi_qp_i2c *i2c; 156 157 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC 158 struct dw_hdmi_qp_cec *cec; 159 #endif 160 161 struct { 162 const struct dw_hdmi_qp_phy_ops *ops; 163 void *data; 164 } phy; 165 166 unsigned long ref_clk_rate; 167 struct regmap *regm; 168 int main_irq; 169 170 unsigned long tmds_char_rate; 171 bool no_hpd; 172 }; 173 174 static void dw_hdmi_qp_write(struct dw_hdmi_qp *hdmi, unsigned int val, 175 int offset) 176 { 177 regmap_write(hdmi->regm, offset, val); 178 } 179 180 static unsigned int dw_hdmi_qp_read(struct dw_hdmi_qp *hdmi, int offset) 181 { 182 unsigned int val = 0; 183 184 regmap_read(hdmi->regm, offset, &val); 185 186 return val; 187 } 188 189 static void dw_hdmi_qp_mod(struct dw_hdmi_qp *hdmi, unsigned int data, 190 unsigned int mask, unsigned int reg) 191 { 192 regmap_update_bits(hdmi->regm, reg, mask, data); 193 } 194 195 static struct dw_hdmi_qp *dw_hdmi_qp_from_bridge(struct drm_bridge *bridge) 196 { 197 return container_of(bridge, struct dw_hdmi_qp, bridge); 198 } 199 200 static void dw_hdmi_qp_set_cts_n(struct dw_hdmi_qp *hdmi, unsigned int cts, 201 unsigned int n) 202 { 203 /* Set N */ 204 dw_hdmi_qp_mod(hdmi, n, AUDPKT_ACR_N_VALUE, AUDPKT_ACR_CONTROL0); 205 206 /* Set CTS */ 207 if (cts) 208 dw_hdmi_qp_mod(hdmi, AUDPKT_ACR_CTS_OVR_EN, AUDPKT_ACR_CTS_OVR_EN_MSK, 209 AUDPKT_ACR_CONTROL1); 210 else 211 dw_hdmi_qp_mod(hdmi, 0, AUDPKT_ACR_CTS_OVR_EN_MSK, 212 AUDPKT_ACR_CONTROL1); 213 214 dw_hdmi_qp_mod(hdmi, AUDPKT_ACR_CTS_OVR_VAL(cts), AUDPKT_ACR_CTS_OVR_VAL_MSK, 215 AUDPKT_ACR_CONTROL1); 216 } 217 218 static int dw_hdmi_qp_match_tmds_n_table(struct dw_hdmi_qp *hdmi, 219 unsigned long pixel_clk, 220 unsigned long freq) 221 { 222 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL; 223 int i; 224 225 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) { 226 if (pixel_clk == common_tmds_n_table[i].tmds) { 227 tmds_n = &common_tmds_n_table[i]; 228 break; 229 } 230 } 231 232 if (!tmds_n) 233 return -ENOENT; 234 235 switch (freq) { 236 case 32000: 237 return tmds_n->n_32k; 238 case 44100: 239 case 88200: 240 case 176400: 241 return (freq / 44100) * tmds_n->n_44k1; 242 case 48000: 243 case 96000: 244 case 192000: 245 return (freq / 48000) * tmds_n->n_48k; 246 default: 247 return -ENOENT; 248 } 249 } 250 251 static u32 dw_hdmi_qp_audio_math_diff(unsigned int freq, unsigned int n, 252 unsigned int pixel_clk) 253 { 254 u64 cts = mul_u32_u32(pixel_clk, n); 255 256 return do_div(cts, 128 * freq); 257 } 258 259 static unsigned int dw_hdmi_qp_compute_n(struct dw_hdmi_qp *hdmi, 260 unsigned long pixel_clk, 261 unsigned long freq) 262 { 263 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500); 264 unsigned int max_n = (128 * freq) / 300; 265 unsigned int ideal_n = (128 * freq) / 1000; 266 unsigned int best_n_distance = ideal_n; 267 unsigned int best_n = 0; 268 u64 best_diff = U64_MAX; 269 int n; 270 271 /* If the ideal N could satisfy the audio math, then just take it */ 272 if (dw_hdmi_qp_audio_math_diff(freq, ideal_n, pixel_clk) == 0) 273 return ideal_n; 274 275 for (n = min_n; n <= max_n; n++) { 276 u64 diff = dw_hdmi_qp_audio_math_diff(freq, n, pixel_clk); 277 278 if (diff < best_diff || 279 (diff == best_diff && abs(n - ideal_n) < best_n_distance)) { 280 best_n = n; 281 best_diff = diff; 282 best_n_distance = abs(best_n - ideal_n); 283 } 284 285 /* 286 * The best N already satisfy the audio math, and also be 287 * the closest value to ideal N, so just cut the loop. 288 */ 289 if (best_diff == 0 && (abs(n - ideal_n) > best_n_distance)) 290 break; 291 } 292 293 return best_n; 294 } 295 296 static unsigned int dw_hdmi_qp_find_n(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk, 297 unsigned long sample_rate) 298 { 299 int n = dw_hdmi_qp_match_tmds_n_table(hdmi, pixel_clk, sample_rate); 300 301 if (n > 0) 302 return n; 303 304 dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n", 305 pixel_clk); 306 307 return dw_hdmi_qp_compute_n(hdmi, pixel_clk, sample_rate); 308 } 309 310 static unsigned int dw_hdmi_qp_find_cts(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk, 311 unsigned long sample_rate) 312 { 313 const struct dw_hdmi_audio_tmds_cts *tmds_cts = NULL; 314 int i; 315 316 for (i = 0; common_tmds_cts_table[i].tmds != 0; i++) { 317 if (pixel_clk == common_tmds_cts_table[i].tmds) { 318 tmds_cts = &common_tmds_cts_table[i]; 319 break; 320 } 321 } 322 323 if (!tmds_cts) 324 return 0; 325 326 switch (sample_rate) { 327 case 32000: 328 return tmds_cts->cts_32k; 329 case 44100: 330 case 88200: 331 case 176400: 332 return tmds_cts->cts_44k1; 333 case 48000: 334 case 96000: 335 case 192000: 336 return tmds_cts->cts_48k; 337 default: 338 return -ENOENT; 339 } 340 } 341 342 static void dw_hdmi_qp_set_audio_interface(struct dw_hdmi_qp *hdmi, 343 struct hdmi_codec_daifmt *fmt, 344 struct hdmi_codec_params *hparms) 345 { 346 u32 conf0 = 0; 347 348 /* Reset the audio data path of the AVP */ 349 dw_hdmi_qp_write(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWINIT_P, GLOBAL_SWRESET_REQUEST); 350 351 /* Disable AUDS, ACR, AUDI */ 352 dw_hdmi_qp_mod(hdmi, 0, 353 PKTSCHED_ACR_TX_EN | PKTSCHED_AUDS_TX_EN | PKTSCHED_AUDI_TX_EN, 354 PKTSCHED_PKT_EN); 355 356 /* Clear the audio FIFO */ 357 dw_hdmi_qp_write(hdmi, AUDIO_FIFO_CLR_P, AUDIO_INTERFACE_CONTROL0); 358 359 /* Select I2S interface as the audio source */ 360 dw_hdmi_qp_mod(hdmi, AUD_IF_I2S, AUD_IF_SEL_MSK, AUDIO_INTERFACE_CONFIG0); 361 362 /* Enable the active i2s lanes */ 363 switch (hparms->channels) { 364 case 7 ... 8: 365 conf0 |= I2S_LINES_EN(3); 366 fallthrough; 367 case 5 ... 6: 368 conf0 |= I2S_LINES_EN(2); 369 fallthrough; 370 case 3 ... 4: 371 conf0 |= I2S_LINES_EN(1); 372 fallthrough; 373 default: 374 conf0 |= I2S_LINES_EN(0); 375 break; 376 } 377 378 dw_hdmi_qp_mod(hdmi, conf0, I2S_LINES_EN_MSK, AUDIO_INTERFACE_CONFIG0); 379 380 /* 381 * Enable bpcuv generated internally for L-PCM, or received 382 * from stream for NLPCM/HBR. 383 */ 384 switch (fmt->bit_fmt) { 385 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE: 386 conf0 = (hparms->channels == 8) ? AUD_HBR : AUD_ASP; 387 conf0 |= I2S_BPCUV_RCV_EN; 388 break; 389 default: 390 conf0 = AUD_ASP | I2S_BPCUV_RCV_DIS; 391 break; 392 } 393 394 dw_hdmi_qp_mod(hdmi, conf0, I2S_BPCUV_RCV_MSK | AUD_FORMAT_MSK, 395 AUDIO_INTERFACE_CONFIG0); 396 397 /* Enable audio FIFO auto clear when overflow */ 398 dw_hdmi_qp_mod(hdmi, AUD_FIFO_INIT_ON_OVF_EN, AUD_FIFO_INIT_ON_OVF_MSK, 399 AUDIO_INTERFACE_CONFIG0); 400 } 401 402 /* 403 * When transmitting IEC60958 linear PCM audio, these registers allow to 404 * configure the channel status information of all the channel status 405 * bits in the IEC60958 frame. For the moment this configuration is only 406 * used when the I2S audio interface, General Purpose Audio (GPA), 407 * or AHB audio DMA (AHBAUDDMA) interface is active 408 * (for S/PDIF interface this information comes from the stream). 409 */ 410 static void dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp *hdmi, 411 u8 *channel_status, bool ref2stream) 412 { 413 /* 414 * AUDPKT_CHSTATUS_OVR0: { RSV, RSV, CS1, CS0 } 415 * AUDPKT_CHSTATUS_OVR1: { CS6, CS5, CS4, CS3 } 416 * 417 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 418 * CS0: | Mode | d | c | b | a | 419 * CS1: | Category Code | 420 * CS2: | Channel Number | Source Number | 421 * CS3: | Clock Accuracy | Sample Freq | 422 * CS4: | Ori Sample Freq | Word Length | 423 * CS5: | | CGMS-A | 424 * CS6~CS23: Reserved 425 * 426 * a: use of channel status block 427 * b: linear PCM identification: 0 for lpcm, 1 for nlpcm 428 * c: copyright information 429 * d: additional format information 430 */ 431 432 if (ref2stream) 433 channel_status[0] |= IEC958_AES0_NONAUDIO; 434 435 if ((dw_hdmi_qp_read(hdmi, AUDIO_INTERFACE_CONFIG0) & GENMASK(25, 24)) == AUD_HBR) { 436 /* fixup cs for HBR */ 437 channel_status[3] = (channel_status[3] & 0xf0) | IEC958_AES3_CON_FS_768000; 438 channel_status[4] = (channel_status[4] & 0x0f) | IEC958_AES4_CON_ORIGFS_NOTID; 439 } 440 441 dw_hdmi_qp_write(hdmi, channel_status[0] | (channel_status[1] << 8), 442 AUDPKT_CHSTATUS_OVR0); 443 444 regmap_bulk_write(hdmi->regm, AUDPKT_CHSTATUS_OVR1, &channel_status[3], 1); 445 446 if (ref2stream) 447 dw_hdmi_qp_mod(hdmi, 0, 448 AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK, 449 AUDPKT_CONTROL0); 450 else 451 dw_hdmi_qp_mod(hdmi, AUDPKT_PBIT_FORCE_EN | AUDPKT_CHSTATUS_OVR_EN, 452 AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK, 453 AUDPKT_CONTROL0); 454 } 455 456 static void dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp *hdmi, unsigned long long tmds_char_rate, 457 unsigned int sample_rate) 458 { 459 unsigned int n, cts; 460 461 n = dw_hdmi_qp_find_n(hdmi, tmds_char_rate, sample_rate); 462 cts = dw_hdmi_qp_find_cts(hdmi, tmds_char_rate, sample_rate); 463 464 dw_hdmi_qp_set_cts_n(hdmi, cts, n); 465 } 466 467 static int dw_hdmi_qp_audio_enable(struct drm_bridge *bridge, 468 struct drm_connector *connector) 469 { 470 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 471 472 if (hdmi->tmds_char_rate) 473 dw_hdmi_qp_mod(hdmi, 0, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE); 474 475 return 0; 476 } 477 478 static int dw_hdmi_qp_audio_prepare(struct drm_bridge *bridge, 479 struct drm_connector *connector, 480 struct hdmi_codec_daifmt *fmt, 481 struct hdmi_codec_params *hparms) 482 { 483 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 484 bool ref2stream = false; 485 486 if (!hdmi->tmds_char_rate) 487 return -ENODEV; 488 489 if (fmt->bit_clk_provider | fmt->frame_clk_provider) { 490 dev_err(hdmi->dev, "unsupported clock settings\n"); 491 return -EINVAL; 492 } 493 494 if (fmt->bit_fmt == SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE) 495 ref2stream = true; 496 497 dw_hdmi_qp_set_audio_interface(hdmi, fmt, hparms); 498 dw_hdmi_qp_set_sample_rate(hdmi, hdmi->tmds_char_rate, hparms->sample_rate); 499 dw_hdmi_qp_set_channel_status(hdmi, hparms->iec.status, ref2stream); 500 drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, &hparms->cea); 501 502 return 0; 503 } 504 505 static void dw_hdmi_qp_audio_disable_regs(struct dw_hdmi_qp *hdmi) 506 { 507 /* 508 * Keep ACR, AUDI, AUDS packet always on to make SINK device 509 * active for better compatibility and user experience. 510 * 511 * This also fix POP sound on some SINK devices which wakeup 512 * from suspend to active. 513 */ 514 dw_hdmi_qp_mod(hdmi, I2S_BPCUV_RCV_DIS, I2S_BPCUV_RCV_MSK, 515 AUDIO_INTERFACE_CONFIG0); 516 dw_hdmi_qp_mod(hdmi, AUDPKT_PBIT_FORCE_EN | AUDPKT_CHSTATUS_OVR_EN, 517 AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK, 518 AUDPKT_CONTROL0); 519 520 dw_hdmi_qp_mod(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, 521 AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE); 522 } 523 524 static void dw_hdmi_qp_audio_disable(struct drm_bridge *bridge, 525 struct drm_connector *connector) 526 { 527 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 528 529 drm_atomic_helper_connector_hdmi_clear_audio_infoframe(connector); 530 531 if (hdmi->tmds_char_rate) 532 dw_hdmi_qp_audio_disable_regs(hdmi); 533 } 534 535 static int dw_hdmi_qp_i2c_read(struct dw_hdmi_qp *hdmi, 536 unsigned char *buf, unsigned int length) 537 { 538 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; 539 int stat; 540 541 if (!i2c->is_regaddr) { 542 dev_dbg(hdmi->dev, "set read register address to 0\n"); 543 i2c->slave_reg = 0x00; 544 i2c->is_regaddr = true; 545 } 546 547 while (length--) { 548 reinit_completion(&i2c->cmp); 549 550 dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, 551 I2CM_INTERFACE_CONTROL0); 552 553 if (i2c->is_segment) 554 dw_hdmi_qp_mod(hdmi, I2CM_EXT_READ, I2CM_WR_MASK, 555 I2CM_INTERFACE_CONTROL0); 556 else 557 dw_hdmi_qp_mod(hdmi, I2CM_FM_READ, I2CM_WR_MASK, 558 I2CM_INTERFACE_CONTROL0); 559 560 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 561 if (!stat) { 562 if (hdmi->no_hpd) 563 dev_dbg_ratelimited(hdmi->dev, 564 "i2c read timed out\n"); 565 else 566 dev_err(hdmi->dev, "i2c read timed out\n"); 567 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 568 return -EAGAIN; 569 } 570 571 /* Check for error condition on the bus */ 572 if (i2c->stat & I2CM_NACK_RCVD_IRQ) { 573 if (hdmi->no_hpd) 574 dev_dbg_ratelimited(hdmi->dev, 575 "i2c read error\n"); 576 else 577 dev_err(hdmi->dev, "i2c read error\n"); 578 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 579 return -EIO; 580 } 581 582 *buf++ = dw_hdmi_qp_read(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff; 583 dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 584 } 585 586 i2c->is_segment = false; 587 588 return 0; 589 } 590 591 static int dw_hdmi_qp_i2c_write(struct dw_hdmi_qp *hdmi, 592 unsigned char *buf, unsigned int length) 593 { 594 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; 595 int stat; 596 597 if (!i2c->is_regaddr) { 598 /* Use the first write byte as register address */ 599 i2c->slave_reg = buf[0]; 600 length--; 601 buf++; 602 i2c->is_regaddr = true; 603 } 604 605 while (length--) { 606 reinit_completion(&i2c->cmp); 607 608 dw_hdmi_qp_write(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3); 609 dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, 610 I2CM_INTERFACE_CONTROL0); 611 dw_hdmi_qp_mod(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK, 612 I2CM_INTERFACE_CONTROL0); 613 614 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 615 if (!stat) { 616 dev_err(hdmi->dev, "i2c write time out!\n"); 617 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 618 return -EAGAIN; 619 } 620 621 /* Check for error condition on the bus */ 622 if (i2c->stat & I2CM_NACK_RCVD_IRQ) { 623 dev_err(hdmi->dev, "i2c write nack!\n"); 624 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 625 return -EIO; 626 } 627 628 dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 629 } 630 631 return 0; 632 } 633 634 static int dw_hdmi_qp_i2c_xfer(struct i2c_adapter *adap, 635 struct i2c_msg *msgs, int num) 636 { 637 struct dw_hdmi_qp *hdmi = i2c_get_adapdata(adap); 638 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; 639 u8 addr = msgs[0].addr; 640 int i, ret = 0; 641 642 if (addr == DDC_CI_ADDR) 643 /* 644 * The internal I2C controller does not support the multi-byte 645 * read and write operations needed for DDC/CI. 646 * FIXME: Blacklist the DDC/CI address until we filter out 647 * unsupported I2C operations. 648 */ 649 return -EOPNOTSUPP; 650 651 for (i = 0; i < num; i++) { 652 if (msgs[i].len == 0) { 653 dev_err(hdmi->dev, 654 "unsupported transfer %d/%d, no data\n", 655 i + 1, num); 656 return -EOPNOTSUPP; 657 } 658 } 659 660 guard(mutex)(&i2c->lock); 661 662 /* Unmute DONE and ERROR interrupts */ 663 dw_hdmi_qp_mod(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 664 I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 665 MAINUNIT_1_INT_MASK_N); 666 667 /* Set slave device address taken from the first I2C message */ 668 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 669 addr = DDC_ADDR; 670 671 dw_hdmi_qp_mod(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0); 672 673 /* Set slave device register address on transfer */ 674 i2c->is_regaddr = false; 675 676 /* Set segment pointer for I2C extended read mode operation */ 677 i2c->is_segment = false; 678 679 for (i = 0; i < num; i++) { 680 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 681 i2c->is_segment = true; 682 dw_hdmi_qp_mod(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR, 683 I2CM_INTERFACE_CONTROL1); 684 dw_hdmi_qp_mod(hdmi, *msgs[i].buf << 7, I2CM_SEG_PTR, 685 I2CM_INTERFACE_CONTROL1); 686 } else { 687 if (msgs[i].flags & I2C_M_RD) 688 ret = dw_hdmi_qp_i2c_read(hdmi, msgs[i].buf, 689 msgs[i].len); 690 else 691 ret = dw_hdmi_qp_i2c_write(hdmi, msgs[i].buf, 692 msgs[i].len); 693 } 694 if (ret < 0) 695 break; 696 } 697 698 if (!ret) 699 ret = num; 700 701 /* Mute DONE and ERROR interrupts */ 702 dw_hdmi_qp_mod(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N, 703 MAINUNIT_1_INT_MASK_N); 704 705 return ret; 706 } 707 708 static u32 dw_hdmi_qp_i2c_func(struct i2c_adapter *adapter) 709 { 710 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 711 } 712 713 static const struct i2c_algorithm dw_hdmi_qp_algorithm = { 714 .master_xfer = dw_hdmi_qp_i2c_xfer, 715 .functionality = dw_hdmi_qp_i2c_func, 716 }; 717 718 static struct i2c_adapter *dw_hdmi_qp_i2c_adapter(struct dw_hdmi_qp *hdmi) 719 { 720 struct dw_hdmi_qp_i2c *i2c; 721 struct i2c_adapter *adap; 722 int ret; 723 724 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 725 if (!i2c) 726 return ERR_PTR(-ENOMEM); 727 728 mutex_init(&i2c->lock); 729 init_completion(&i2c->cmp); 730 731 adap = &i2c->adap; 732 adap->owner = THIS_MODULE; 733 adap->dev.parent = hdmi->dev; 734 adap->algo = &dw_hdmi_qp_algorithm; 735 strscpy(adap->name, "DesignWare HDMI QP", sizeof(adap->name)); 736 737 i2c_set_adapdata(adap, hdmi); 738 739 ret = devm_i2c_add_adapter(hdmi->dev, adap); 740 if (ret) { 741 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 742 devm_kfree(hdmi->dev, i2c); 743 return ERR_PTR(ret); 744 } 745 746 hdmi->i2c = i2c; 747 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 748 749 return adap; 750 } 751 752 static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge, 753 struct drm_atomic_state *state) 754 { 755 struct dw_hdmi_qp *hdmi = bridge->driver_private; 756 struct drm_connector_state *conn_state; 757 struct drm_connector *connector; 758 unsigned int op_mode; 759 760 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 761 if (WARN_ON(!connector)) 762 return; 763 764 conn_state = drm_atomic_get_new_connector_state(state, connector); 765 if (WARN_ON(!conn_state)) 766 return; 767 768 if (connector->display_info.is_hdmi) { 769 dev_dbg(hdmi->dev, "%s mode=HDMI %s rate=%llu bpc=%u\n", __func__, 770 drm_hdmi_connector_get_output_format_name(conn_state->hdmi.output_format), 771 conn_state->hdmi.tmds_char_rate, conn_state->hdmi.output_bpc); 772 op_mode = 0; 773 hdmi->tmds_char_rate = conn_state->hdmi.tmds_char_rate; 774 } else { 775 dev_dbg(hdmi->dev, "%s mode=DVI\n", __func__); 776 op_mode = OPMODE_DVI; 777 } 778 779 hdmi->phy.ops->init(hdmi, hdmi->phy.data); 780 781 dw_hdmi_qp_mod(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); 782 dw_hdmi_qp_mod(hdmi, op_mode, OPMODE_DVI, LINK_CONFIG0); 783 784 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 785 } 786 787 static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge, 788 struct drm_atomic_state *state) 789 { 790 struct dw_hdmi_qp *hdmi = bridge->driver_private; 791 792 hdmi->tmds_char_rate = 0; 793 794 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 795 } 796 797 static enum drm_connector_status 798 dw_hdmi_qp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 799 { 800 struct dw_hdmi_qp *hdmi = bridge->driver_private; 801 const struct drm_edid *drm_edid; 802 803 if (hdmi->no_hpd) { 804 drm_edid = drm_edid_read_ddc(connector, bridge->ddc); 805 if (drm_edid) 806 return connector_status_connected; 807 else 808 return connector_status_disconnected; 809 } 810 811 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 812 } 813 814 static const struct drm_edid * 815 dw_hdmi_qp_bridge_edid_read(struct drm_bridge *bridge, 816 struct drm_connector *connector) 817 { 818 struct dw_hdmi_qp *hdmi = bridge->driver_private; 819 const struct drm_edid *drm_edid; 820 821 drm_edid = drm_edid_read_ddc(connector, bridge->ddc); 822 if (!drm_edid) 823 dev_dbg(hdmi->dev, "failed to get edid\n"); 824 825 return drm_edid; 826 } 827 828 static enum drm_mode_status 829 dw_hdmi_qp_bridge_tmds_char_rate_valid(const struct drm_bridge *bridge, 830 const struct drm_display_mode *mode, 831 unsigned long long rate) 832 { 833 struct dw_hdmi_qp *hdmi = bridge->driver_private; 834 835 /* 836 * TODO: when hdmi->no_hpd is 1 we must not support modes that 837 * require scrambling, including every mode with a clock above 838 * HDMI14_MAX_TMDSCLK. 839 */ 840 if (rate > HDMI14_MAX_TMDSCLK) { 841 dev_dbg(hdmi->dev, "Unsupported TMDS char rate: %lld\n", rate); 842 return MODE_CLOCK_HIGH; 843 } 844 845 return MODE_OK; 846 } 847 848 static int dw_hdmi_qp_bridge_clear_avi_infoframe(struct drm_bridge *bridge) 849 { 850 struct dw_hdmi_qp *hdmi = bridge->driver_private; 851 852 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, 853 PKTSCHED_PKT_EN); 854 855 return 0; 856 } 857 858 static int dw_hdmi_qp_bridge_clear_hdmi_infoframe(struct drm_bridge *bridge) 859 { 860 struct dw_hdmi_qp *hdmi = bridge->driver_private; 861 862 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_VSI_TX_EN, PKTSCHED_PKT_EN); 863 864 return 0; 865 } 866 867 static int dw_hdmi_qp_bridge_clear_hdr_drm_infoframe(struct drm_bridge *bridge) 868 { 869 struct dw_hdmi_qp *hdmi = bridge->driver_private; 870 871 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN); 872 873 return 0; 874 } 875 876 static int dw_hdmi_qp_bridge_clear_spd_infoframe(struct drm_bridge *bridge) 877 { 878 struct dw_hdmi_qp *hdmi = bridge->driver_private; 879 880 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_SPDI_TX_EN, PKTSCHED_PKT_EN); 881 882 return 0; 883 } 884 885 static int dw_hdmi_qp_bridge_clear_audio_infoframe(struct drm_bridge *bridge) 886 { 887 struct dw_hdmi_qp *hdmi = bridge->driver_private; 888 889 dw_hdmi_qp_mod(hdmi, 0, 890 PKTSCHED_ACR_TX_EN | 891 PKTSCHED_AUDS_TX_EN | 892 PKTSCHED_AUDI_TX_EN, 893 PKTSCHED_PKT_EN); 894 895 return 0; 896 } 897 898 static void dw_hdmi_qp_write_pkt(struct dw_hdmi_qp *hdmi, const u8 *buffer, 899 size_t start, size_t len, unsigned int reg) 900 { 901 u32 val = 0; 902 size_t i; 903 904 for (i = start; i < start + len; i++) 905 val |= buffer[i] << ((i % 4) * BITS_PER_BYTE); 906 907 dw_hdmi_qp_write(hdmi, val, reg); 908 } 909 910 static void dw_hdmi_qp_write_infoframe(struct dw_hdmi_qp *hdmi, const u8 *buffer, 911 size_t len, unsigned int reg) 912 { 913 size_t i; 914 915 /* InfoFrame packet header */ 916 dw_hdmi_qp_write_pkt(hdmi, buffer, 1, 2, reg); 917 918 /* InfoFrame packet body */ 919 for (i = 0; i < len - 3; i += 4) 920 dw_hdmi_qp_write_pkt(hdmi, buffer + 3, i, min(len - i - 3, 4), 921 reg + i + 4); 922 } 923 924 static int dw_hdmi_qp_bridge_write_avi_infoframe(struct drm_bridge *bridge, 925 const u8 *buffer, size_t len) 926 { 927 struct dw_hdmi_qp *hdmi = bridge->driver_private; 928 929 dw_hdmi_qp_bridge_clear_avi_infoframe(bridge); 930 931 dw_hdmi_qp_write_infoframe(hdmi, buffer, len, PKT_AVI_CONTENTS0); 932 933 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 934 dw_hdmi_qp_mod(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, 935 PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, PKTSCHED_PKT_EN); 936 937 return 0; 938 } 939 940 static int dw_hdmi_qp_bridge_write_hdmi_infoframe(struct drm_bridge *bridge, 941 const u8 *buffer, size_t len) 942 { 943 struct dw_hdmi_qp *hdmi = bridge->driver_private; 944 945 dw_hdmi_qp_bridge_clear_hdmi_infoframe(bridge); 946 947 dw_hdmi_qp_write_infoframe(hdmi, buffer, len, PKT_VSI_CONTENTS0); 948 949 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_VSI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 950 dw_hdmi_qp_mod(hdmi, PKTSCHED_VSI_TX_EN, PKTSCHED_VSI_TX_EN, 951 PKTSCHED_PKT_EN); 952 953 return 0; 954 } 955 956 static int dw_hdmi_qp_bridge_write_hdr_drm_infoframe(struct drm_bridge *bridge, 957 const u8 *buffer, size_t len) 958 { 959 struct dw_hdmi_qp *hdmi = bridge->driver_private; 960 961 dw_hdmi_qp_bridge_clear_hdr_drm_infoframe(bridge); 962 963 dw_hdmi_qp_write_infoframe(hdmi, buffer, len, PKT_DRMI_CONTENTS0); 964 965 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 966 dw_hdmi_qp_mod(hdmi, PKTSCHED_DRMI_TX_EN, PKTSCHED_DRMI_TX_EN, 967 PKTSCHED_PKT_EN); 968 969 return 0; 970 } 971 972 static int dw_hdmi_qp_bridge_write_spd_infoframe(struct drm_bridge *bridge, 973 const u8 *buffer, size_t len) 974 { 975 struct dw_hdmi_qp *hdmi = bridge->driver_private; 976 977 dw_hdmi_qp_bridge_clear_spd_infoframe(bridge); 978 979 dw_hdmi_qp_write_infoframe(hdmi, buffer, len, PKT_SPDI_CONTENTS0); 980 981 dw_hdmi_qp_mod(hdmi, PKTSCHED_SPDI_TX_EN, PKTSCHED_SPDI_TX_EN, 982 PKTSCHED_PKT_EN); 983 984 return 0; 985 } 986 987 static int dw_hdmi_qp_bridge_write_audio_infoframe(struct drm_bridge *bridge, 988 const u8 *buffer, size_t len) 989 { 990 struct dw_hdmi_qp *hdmi = bridge->driver_private; 991 992 dw_hdmi_qp_bridge_clear_audio_infoframe(bridge); 993 994 /* 995 * AUDI_CONTENTS0: { RSV, HB2, HB1, RSV } 996 * AUDI_CONTENTS1: { PB3, PB2, PB1, PB0 } 997 * AUDI_CONTENTS2: { PB7, PB6, PB5, PB4 } 998 * 999 * PB0: CheckSum 1000 * PB1: | CT3 | CT2 | CT1 | CT0 | F13 | CC2 | CC1 | CC0 | 1001 * PB2: | F27 | F26 | F25 | SF2 | SF1 | SF0 | SS1 | SS0 | 1002 * PB3: | F37 | F36 | F35 | F34 | F33 | F32 | F31 | F30 | 1003 * PB4: | CA7 | CA6 | CA5 | CA4 | CA3 | CA2 | CA1 | CA0 | 1004 * PB5: | DM_INH | LSV3 | LSV2 | LSV1 | LSV0 | F52 | F51 | F50 | 1005 * PB6~PB10: Reserved 1006 */ 1007 dw_hdmi_qp_write_infoframe(hdmi, buffer, len, PKT_AUDI_CONTENTS0); 1008 1009 /* Enable ACR, AUDI, AMD */ 1010 dw_hdmi_qp_mod(hdmi, 1011 PKTSCHED_ACR_TX_EN | PKTSCHED_AUDI_TX_EN | PKTSCHED_AMD_TX_EN, 1012 PKTSCHED_ACR_TX_EN | PKTSCHED_AUDI_TX_EN | PKTSCHED_AMD_TX_EN, 1013 PKTSCHED_PKT_EN); 1014 1015 /* Enable AUDS */ 1016 dw_hdmi_qp_mod(hdmi, PKTSCHED_AUDS_TX_EN, PKTSCHED_AUDS_TX_EN, PKTSCHED_PKT_EN); 1017 1018 return 0; 1019 } 1020 1021 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC 1022 static irqreturn_t dw_hdmi_qp_cec_hardirq(int irq, void *dev_id) 1023 { 1024 struct dw_hdmi_qp *hdmi = dev_id; 1025 struct dw_hdmi_qp_cec *cec = hdmi->cec; 1026 irqreturn_t ret = IRQ_HANDLED; 1027 u32 stat; 1028 1029 stat = dw_hdmi_qp_read(hdmi, CEC_INT_STATUS); 1030 if (stat == 0) 1031 return IRQ_NONE; 1032 1033 dw_hdmi_qp_write(hdmi, stat, CEC_INT_CLEAR); 1034 1035 if (stat & CEC_STAT_LINE_ERR) { 1036 cec->tx_status = CEC_TX_STATUS_ERROR; 1037 cec->tx_done = true; 1038 ret = IRQ_WAKE_THREAD; 1039 } else if (stat & CEC_STAT_DONE) { 1040 cec->tx_status = CEC_TX_STATUS_OK; 1041 cec->tx_done = true; 1042 ret = IRQ_WAKE_THREAD; 1043 } else if (stat & CEC_STAT_NACK) { 1044 cec->tx_status = CEC_TX_STATUS_NACK; 1045 cec->tx_done = true; 1046 ret = IRQ_WAKE_THREAD; 1047 } 1048 1049 if (stat & CEC_STAT_EOM) { 1050 unsigned int len, i, val; 1051 1052 val = dw_hdmi_qp_read(hdmi, CEC_RX_COUNT_STATUS); 1053 len = (val & 0xf) + 1; 1054 1055 if (len > sizeof(cec->rx_msg.msg)) 1056 len = sizeof(cec->rx_msg.msg); 1057 1058 for (i = 0; i < 4; i++) { 1059 val = dw_hdmi_qp_read(hdmi, CEC_RX_DATA3_0 + i * 4); 1060 cec->rx_msg.msg[i * 4] = val & 0xff; 1061 cec->rx_msg.msg[i * 4 + 1] = (val >> 8) & 0xff; 1062 cec->rx_msg.msg[i * 4 + 2] = (val >> 16) & 0xff; 1063 cec->rx_msg.msg[i * 4 + 3] = (val >> 24) & 0xff; 1064 } 1065 1066 dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL); 1067 1068 cec->rx_msg.len = len; 1069 cec->rx_done = true; 1070 1071 ret = IRQ_WAKE_THREAD; 1072 } 1073 1074 return ret; 1075 } 1076 1077 static irqreturn_t dw_hdmi_qp_cec_thread(int irq, void *dev_id) 1078 { 1079 struct dw_hdmi_qp *hdmi = dev_id; 1080 struct dw_hdmi_qp_cec *cec = hdmi->cec; 1081 1082 if (cec->tx_done) { 1083 cec->tx_done = false; 1084 drm_connector_hdmi_cec_transmit_attempt_done(cec->connector, 1085 cec->tx_status); 1086 } 1087 1088 if (cec->rx_done) { 1089 cec->rx_done = false; 1090 drm_connector_hdmi_cec_received_msg(cec->connector, &cec->rx_msg); 1091 } 1092 1093 return IRQ_HANDLED; 1094 } 1095 1096 static int dw_hdmi_qp_cec_init(struct drm_bridge *bridge, 1097 struct drm_connector *connector) 1098 { 1099 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 1100 struct dw_hdmi_qp_cec *cec = hdmi->cec; 1101 1102 cec->connector = connector; 1103 1104 dw_hdmi_qp_write(hdmi, 0, CEC_TX_COUNT); 1105 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); 1106 dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N); 1107 1108 return devm_request_threaded_irq(hdmi->dev, cec->irq, 1109 dw_hdmi_qp_cec_hardirq, 1110 dw_hdmi_qp_cec_thread, IRQF_SHARED, 1111 dev_name(hdmi->dev), hdmi); 1112 } 1113 1114 static int dw_hdmi_qp_cec_log_addr(struct drm_bridge *bridge, u8 logical_addr) 1115 { 1116 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 1117 struct dw_hdmi_qp_cec *cec = hdmi->cec; 1118 1119 if (logical_addr == CEC_LOG_ADDR_INVALID) 1120 cec->addresses = 0; 1121 else 1122 cec->addresses |= BIT(logical_addr) | CEC_ADDR_BROADCAST; 1123 1124 dw_hdmi_qp_write(hdmi, cec->addresses, CEC_ADDR); 1125 1126 return 0; 1127 } 1128 1129 static int dw_hdmi_qp_cec_enable(struct drm_bridge *bridge, bool enable) 1130 { 1131 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 1132 unsigned int irqs; 1133 u32 swdisable; 1134 1135 if (!enable) { 1136 dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N); 1137 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); 1138 1139 swdisable = dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE); 1140 swdisable = swdisable | CEC_SWDISABLE; 1141 dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE); 1142 } else { 1143 swdisable = dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE); 1144 swdisable = swdisable & ~CEC_SWDISABLE; 1145 dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE); 1146 1147 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); 1148 dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL); 1149 1150 dw_hdmi_qp_cec_log_addr(bridge, CEC_LOG_ADDR_INVALID); 1151 1152 irqs = CEC_STAT_LINE_ERR | CEC_STAT_NACK | CEC_STAT_EOM | 1153 CEC_STAT_DONE; 1154 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); 1155 dw_hdmi_qp_write(hdmi, irqs, CEC_INT_MASK_N); 1156 } 1157 1158 return 0; 1159 } 1160 1161 static int dw_hdmi_qp_cec_transmit(struct drm_bridge *bridge, u8 attempts, 1162 u32 signal_free_time, struct cec_msg *msg) 1163 { 1164 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 1165 unsigned int i; 1166 u32 val; 1167 1168 for (i = 0; i < msg->len; i++) { 1169 if (!(i % 4)) 1170 val = msg->msg[i]; 1171 if ((i % 4) == 1) 1172 val |= msg->msg[i] << 8; 1173 if ((i % 4) == 2) 1174 val |= msg->msg[i] << 16; 1175 if ((i % 4) == 3) 1176 val |= msg->msg[i] << 24; 1177 1178 if (i == (msg->len - 1) || (i % 4) == 3) 1179 dw_hdmi_qp_write(hdmi, val, CEC_TX_DATA3_0 + (i / 4) * 4); 1180 } 1181 1182 dw_hdmi_qp_write(hdmi, msg->len - 1, CEC_TX_COUNT); 1183 dw_hdmi_qp_write(hdmi, CEC_CTRL_START, CEC_TX_CONTROL); 1184 1185 return 0; 1186 } 1187 #else 1188 #define dw_hdmi_qp_cec_init NULL 1189 #define dw_hdmi_qp_cec_enable NULL 1190 #define dw_hdmi_qp_cec_log_addr NULL 1191 #define dw_hdmi_qp_cec_transmit NULL 1192 #endif /* CONFIG_DRM_DW_HDMI_QP_CEC */ 1193 1194 static const struct drm_bridge_funcs dw_hdmi_qp_bridge_funcs = { 1195 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1196 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1197 .atomic_reset = drm_atomic_helper_bridge_reset, 1198 .atomic_enable = dw_hdmi_qp_bridge_atomic_enable, 1199 .atomic_disable = dw_hdmi_qp_bridge_atomic_disable, 1200 .detect = dw_hdmi_qp_bridge_detect, 1201 .edid_read = dw_hdmi_qp_bridge_edid_read, 1202 .hdmi_tmds_char_rate_valid = dw_hdmi_qp_bridge_tmds_char_rate_valid, 1203 .hdmi_clear_avi_infoframe = dw_hdmi_qp_bridge_clear_avi_infoframe, 1204 .hdmi_write_avi_infoframe = dw_hdmi_qp_bridge_write_avi_infoframe, 1205 .hdmi_clear_hdmi_infoframe = dw_hdmi_qp_bridge_clear_hdmi_infoframe, 1206 .hdmi_write_hdmi_infoframe = dw_hdmi_qp_bridge_write_hdmi_infoframe, 1207 .hdmi_clear_hdr_drm_infoframe = dw_hdmi_qp_bridge_clear_hdr_drm_infoframe, 1208 .hdmi_write_hdr_drm_infoframe = dw_hdmi_qp_bridge_write_hdr_drm_infoframe, 1209 .hdmi_clear_spd_infoframe = dw_hdmi_qp_bridge_clear_spd_infoframe, 1210 .hdmi_write_spd_infoframe = dw_hdmi_qp_bridge_write_spd_infoframe, 1211 .hdmi_clear_audio_infoframe = dw_hdmi_qp_bridge_clear_audio_infoframe, 1212 .hdmi_write_audio_infoframe = dw_hdmi_qp_bridge_write_audio_infoframe, 1213 .hdmi_audio_startup = dw_hdmi_qp_audio_enable, 1214 .hdmi_audio_shutdown = dw_hdmi_qp_audio_disable, 1215 .hdmi_audio_prepare = dw_hdmi_qp_audio_prepare, 1216 .hdmi_cec_init = dw_hdmi_qp_cec_init, 1217 .hdmi_cec_enable = dw_hdmi_qp_cec_enable, 1218 .hdmi_cec_log_addr = dw_hdmi_qp_cec_log_addr, 1219 .hdmi_cec_transmit = dw_hdmi_qp_cec_transmit, 1220 }; 1221 1222 static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id) 1223 { 1224 struct dw_hdmi_qp *hdmi = dev_id; 1225 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; 1226 u32 stat; 1227 1228 stat = dw_hdmi_qp_read(hdmi, MAINUNIT_1_INT_STATUS); 1229 1230 i2c->stat = stat & (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | 1231 I2CM_NACK_RCVD_IRQ); 1232 1233 if (i2c->stat) { 1234 dw_hdmi_qp_write(hdmi, i2c->stat, MAINUNIT_1_INT_CLEAR); 1235 complete(&i2c->cmp); 1236 } 1237 1238 if (stat) 1239 return IRQ_HANDLED; 1240 1241 return IRQ_NONE; 1242 } 1243 1244 static const struct regmap_config dw_hdmi_qp_regmap_config = { 1245 .reg_bits = 32, 1246 .val_bits = 32, 1247 .reg_stride = 4, 1248 .max_register = EARCRX_1_INT_FORCE, 1249 }; 1250 1251 static void dw_hdmi_qp_init_hw(struct dw_hdmi_qp *hdmi) 1252 { 1253 dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N); 1254 dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N); 1255 dw_hdmi_qp_write(hdmi, hdmi->ref_clk_rate, TIMER_BASE_CONFIG0); 1256 1257 /* Software reset */ 1258 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 1259 dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); 1260 dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); 1261 1262 /* Clear DONE and ERROR interrupts */ 1263 dw_hdmi_qp_write(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR, 1264 MAINUNIT_1_INT_CLEAR); 1265 1266 if (hdmi->phy.ops->setup_hpd) 1267 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 1268 } 1269 1270 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, 1271 struct drm_encoder *encoder, 1272 const struct dw_hdmi_qp_plat_data *plat_data) 1273 { 1274 struct device *dev = &pdev->dev; 1275 struct dw_hdmi_qp *hdmi; 1276 void __iomem *regs; 1277 int ret; 1278 1279 if (!plat_data->phy_ops || !plat_data->phy_ops->init || 1280 !plat_data->phy_ops->disable || !plat_data->phy_ops->read_hpd) { 1281 dev_err(dev, "Missing platform PHY ops\n"); 1282 return ERR_PTR(-ENODEV); 1283 } 1284 1285 hdmi = devm_drm_bridge_alloc(dev, struct dw_hdmi_qp, bridge, 1286 &dw_hdmi_qp_bridge_funcs); 1287 if (IS_ERR(hdmi)) 1288 return ERR_CAST(hdmi); 1289 1290 hdmi->dev = dev; 1291 1292 regs = devm_platform_ioremap_resource(pdev, 0); 1293 if (IS_ERR(regs)) 1294 return ERR_CAST(regs); 1295 1296 hdmi->regm = devm_regmap_init_mmio(dev, regs, &dw_hdmi_qp_regmap_config); 1297 if (IS_ERR(hdmi->regm)) { 1298 dev_err(dev, "Failed to configure regmap\n"); 1299 return ERR_CAST(hdmi->regm); 1300 } 1301 1302 hdmi->phy.ops = plat_data->phy_ops; 1303 hdmi->phy.data = plat_data->phy_data; 1304 1305 if (plat_data->ref_clk_rate) { 1306 hdmi->ref_clk_rate = plat_data->ref_clk_rate; 1307 } else { 1308 hdmi->ref_clk_rate = 428571429; 1309 dev_warn(dev, "Set ref_clk_rate to vendor default\n"); 1310 } 1311 1312 dw_hdmi_qp_init_hw(hdmi); 1313 1314 hdmi->main_irq = plat_data->main_irq; 1315 ret = devm_request_threaded_irq(dev, plat_data->main_irq, 1316 dw_hdmi_qp_main_hardirq, NULL, 1317 IRQF_SHARED, dev_name(dev), hdmi); 1318 if (ret) 1319 return ERR_PTR(ret); 1320 1321 hdmi->no_hpd = device_property_read_bool(dev, "no-hpd"); 1322 1323 hdmi->bridge.driver_private = hdmi; 1324 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | 1325 DRM_BRIDGE_OP_EDID | 1326 DRM_BRIDGE_OP_HDMI | 1327 DRM_BRIDGE_OP_HDMI_AUDIO | 1328 DRM_BRIDGE_OP_HDMI_HDR_DRM_INFOFRAME | 1329 DRM_BRIDGE_OP_HDMI_SPD_INFOFRAME; 1330 if (!hdmi->no_hpd) 1331 hdmi->bridge.ops |= DRM_BRIDGE_OP_HPD; 1332 hdmi->bridge.of_node = pdev->dev.of_node; 1333 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 1334 hdmi->bridge.vendor = "Synopsys"; 1335 hdmi->bridge.product = "DW HDMI QP TX"; 1336 1337 if (plat_data->supported_formats) 1338 hdmi->bridge.supported_formats = plat_data->supported_formats; 1339 1340 if (plat_data->max_bpc) 1341 hdmi->bridge.max_bpc = plat_data->max_bpc; 1342 1343 hdmi->bridge.ddc = dw_hdmi_qp_i2c_adapter(hdmi); 1344 if (IS_ERR(hdmi->bridge.ddc)) 1345 return ERR_CAST(hdmi->bridge.ddc); 1346 1347 hdmi->bridge.hdmi_audio_max_i2s_playback_channels = 8; 1348 hdmi->bridge.hdmi_audio_dev = dev; 1349 hdmi->bridge.hdmi_audio_dai_port = 1; 1350 1351 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC 1352 if (plat_data->cec_irq) { 1353 hdmi->bridge.ops |= DRM_BRIDGE_OP_HDMI_CEC_ADAPTER; 1354 hdmi->bridge.hdmi_cec_dev = dev; 1355 hdmi->bridge.hdmi_cec_adapter_name = dev_name(dev); 1356 1357 hdmi->cec = devm_kzalloc(hdmi->dev, sizeof(*hdmi->cec), GFP_KERNEL); 1358 if (!hdmi->cec) 1359 return ERR_PTR(-ENOMEM); 1360 1361 hdmi->cec->irq = plat_data->cec_irq; 1362 } else { 1363 dev_warn(dev, "Disabled CEC support due to missing IRQ\n"); 1364 } 1365 #endif 1366 1367 ret = devm_drm_bridge_add(dev, &hdmi->bridge); 1368 if (ret) 1369 return ERR_PTR(ret); 1370 1371 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 1372 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 1373 if (ret) 1374 return ERR_PTR(ret); 1375 1376 return hdmi; 1377 } 1378 EXPORT_SYMBOL_GPL(dw_hdmi_qp_bind); 1379 1380 void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi) 1381 { 1382 disable_irq(hdmi->main_irq); 1383 } 1384 EXPORT_SYMBOL_GPL(dw_hdmi_qp_suspend); 1385 1386 void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi) 1387 { 1388 dw_hdmi_qp_init_hw(hdmi); 1389 enable_irq(hdmi->main_irq); 1390 } 1391 EXPORT_SYMBOL_GPL(dw_hdmi_qp_resume); 1392 1393 MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>"); 1394 MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@collabora.com>"); 1395 MODULE_DESCRIPTION("DW HDMI QP transmitter library"); 1396 MODULE_LICENSE("GPL"); 1397