1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (c) 2021-2022 Rockchip Electronics Co., Ltd. 4 * Copyright (c) 2024 Collabora Ltd. 5 * 6 * Author: Algea Cao <algea.cao@rock-chips.com> 7 * Author: Cristian Ciocaltea <cristian.ciocaltea@collabora.com> 8 */ 9 #include <linux/completion.h> 10 #include <linux/hdmi.h> 11 #include <linux/export.h> 12 #include <linux/i2c.h> 13 #include <linux/irq.h> 14 #include <linux/module.h> 15 #include <linux/mutex.h> 16 #include <linux/of.h> 17 #include <linux/workqueue.h> 18 19 #include <drm/bridge/dw_hdmi_qp.h> 20 #include <drm/display/drm_hdmi_helper.h> 21 #include <drm/display/drm_hdmi_cec_helper.h> 22 #include <drm/display/drm_hdmi_state_helper.h> 23 #include <drm/drm_atomic.h> 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_connector.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_modes.h> 29 #include <drm/drm_print.h> 30 31 #include <media/cec.h> 32 33 #include <sound/hdmi-codec.h> 34 35 #include "dw-hdmi-qp.h" 36 37 #define DDC_CI_ADDR 0x37 38 #define DDC_SEGMENT_ADDR 0x30 39 40 #define HDMI14_MAX_TMDSCLK 340000000 41 42 #define SCRAMB_POLL_DELAY_MS 3000 43 44 /* 45 * Unless otherwise noted, entries in this table are 100% optimization. 46 * Values can be obtained from dw_hdmi_qp_compute_n() but that function is 47 * slow so we pre-compute values we expect to see. 48 * 49 * The values for TMDS 25175, 25200, 27000, 54000, 74250 and 148500 kHz are 50 * the recommended N values specified in the Audio chapter of the HDMI 51 * specification. 52 */ 53 static const struct dw_hdmi_audio_tmds_n { 54 unsigned long tmds; 55 unsigned int n_32k; 56 unsigned int n_44k1; 57 unsigned int n_48k; 58 } common_tmds_n_table[] = { 59 { .tmds = 25175000, .n_32k = 4576, .n_44k1 = 7007, .n_48k = 6864, }, 60 { .tmds = 25200000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 61 { .tmds = 27000000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 62 { .tmds = 28320000, .n_32k = 4096, .n_44k1 = 5586, .n_48k = 6144, }, 63 { .tmds = 30240000, .n_32k = 4096, .n_44k1 = 5642, .n_48k = 6144, }, 64 { .tmds = 31500000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 65 { .tmds = 32000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 66 { .tmds = 33750000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 67 { .tmds = 36000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 68 { .tmds = 40000000, .n_32k = 4096, .n_44k1 = 5733, .n_48k = 6144, }, 69 { .tmds = 49500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 70 { .tmds = 50000000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 71 { .tmds = 54000000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 72 { .tmds = 65000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 73 { .tmds = 68250000, .n_32k = 4096, .n_44k1 = 5376, .n_48k = 6144, }, 74 { .tmds = 71000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 75 { .tmds = 72000000, .n_32k = 4096, .n_44k1 = 5635, .n_48k = 6144, }, 76 { .tmds = 73250000, .n_32k = 11648, .n_44k1 = 14112, .n_48k = 6144, }, 77 { .tmds = 74250000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 78 { .tmds = 75000000, .n_32k = 4096, .n_44k1 = 5880, .n_48k = 6144, }, 79 { .tmds = 78750000, .n_32k = 4096, .n_44k1 = 5600, .n_48k = 6144, }, 80 { .tmds = 78800000, .n_32k = 4096, .n_44k1 = 5292, .n_48k = 6144, }, 81 { .tmds = 79500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 82 { .tmds = 83500000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 83 { .tmds = 85500000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 84 { .tmds = 88750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 85 { .tmds = 97750000, .n_32k = 4096, .n_44k1 = 14112, .n_48k = 6144, }, 86 { .tmds = 101000000, .n_32k = 4096, .n_44k1 = 7056, .n_48k = 6144, }, 87 { .tmds = 106500000, .n_32k = 4096, .n_44k1 = 4704, .n_48k = 6144, }, 88 { .tmds = 108000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 89 { .tmds = 115500000, .n_32k = 4096, .n_44k1 = 5712, .n_48k = 6144, }, 90 { .tmds = 119000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 91 { .tmds = 135000000, .n_32k = 4096, .n_44k1 = 5488, .n_48k = 6144, }, 92 { .tmds = 146250000, .n_32k = 11648, .n_44k1 = 6272, .n_48k = 6144, }, 93 { .tmds = 148500000, .n_32k = 4096, .n_44k1 = 6272, .n_48k = 6144, }, 94 { .tmds = 154000000, .n_32k = 4096, .n_44k1 = 5544, .n_48k = 6144, }, 95 { .tmds = 162000000, .n_32k = 4096, .n_44k1 = 5684, .n_48k = 6144, }, 96 97 /* For 297 MHz+ HDMI spec have some other rule for setting N */ 98 { .tmds = 297000000, .n_32k = 3073, .n_44k1 = 4704, .n_48k = 5120, }, 99 { .tmds = 594000000, .n_32k = 3073, .n_44k1 = 9408, .n_48k = 10240,}, 100 101 /* End of table */ 102 { .tmds = 0, .n_32k = 0, .n_44k1 = 0, .n_48k = 0, }, 103 }; 104 105 /* 106 * These are the CTS values as recommended in the Audio chapter of the HDMI 107 * specification. 108 */ 109 static const struct dw_hdmi_audio_tmds_cts { 110 unsigned long tmds; 111 unsigned int cts_32k; 112 unsigned int cts_44k1; 113 unsigned int cts_48k; 114 } common_tmds_cts_table[] = { 115 { .tmds = 25175000, .cts_32k = 28125, .cts_44k1 = 31250, .cts_48k = 28125, }, 116 { .tmds = 25200000, .cts_32k = 25200, .cts_44k1 = 28000, .cts_48k = 25200, }, 117 { .tmds = 27000000, .cts_32k = 27000, .cts_44k1 = 30000, .cts_48k = 27000, }, 118 { .tmds = 54000000, .cts_32k = 54000, .cts_44k1 = 60000, .cts_48k = 54000, }, 119 { .tmds = 74250000, .cts_32k = 74250, .cts_44k1 = 82500, .cts_48k = 74250, }, 120 { .tmds = 148500000, .cts_32k = 148500, .cts_44k1 = 165000, .cts_48k = 148500, }, 121 122 /* End of table */ 123 { .tmds = 0, .cts_32k = 0, .cts_44k1 = 0, .cts_48k = 0, }, 124 }; 125 126 struct dw_hdmi_qp_i2c { 127 struct i2c_adapter adap; 128 129 struct mutex lock; /* used to serialize data transfers */ 130 struct completion cmp; 131 u8 stat; 132 133 u8 slave_reg; 134 bool is_regaddr; 135 bool is_segment; 136 }; 137 138 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC 139 struct dw_hdmi_qp_cec { 140 struct drm_connector *connector; 141 int irq; 142 u32 addresses; 143 struct cec_msg rx_msg; 144 u8 tx_status; 145 bool tx_done; 146 bool rx_done; 147 }; 148 #endif 149 150 struct dw_hdmi_qp { 151 struct drm_bridge bridge; 152 153 struct device *dev; 154 struct dw_hdmi_qp_i2c *i2c; 155 156 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC 157 struct dw_hdmi_qp_cec *cec; 158 #endif 159 160 struct { 161 const struct dw_hdmi_qp_phy_ops *ops; 162 void *data; 163 } phy; 164 165 unsigned long ref_clk_rate; 166 struct regmap *regm; 167 int main_irq; 168 169 unsigned long tmds_char_rate; 170 bool no_hpd; 171 }; 172 173 static void dw_hdmi_qp_write(struct dw_hdmi_qp *hdmi, unsigned int val, 174 int offset) 175 { 176 regmap_write(hdmi->regm, offset, val); 177 } 178 179 static unsigned int dw_hdmi_qp_read(struct dw_hdmi_qp *hdmi, int offset) 180 { 181 unsigned int val = 0; 182 183 regmap_read(hdmi->regm, offset, &val); 184 185 return val; 186 } 187 188 static void dw_hdmi_qp_mod(struct dw_hdmi_qp *hdmi, unsigned int data, 189 unsigned int mask, unsigned int reg) 190 { 191 regmap_update_bits(hdmi->regm, reg, mask, data); 192 } 193 194 static struct dw_hdmi_qp *dw_hdmi_qp_from_bridge(struct drm_bridge *bridge) 195 { 196 return container_of(bridge, struct dw_hdmi_qp, bridge); 197 } 198 199 static void dw_hdmi_qp_set_cts_n(struct dw_hdmi_qp *hdmi, unsigned int cts, 200 unsigned int n) 201 { 202 /* Set N */ 203 dw_hdmi_qp_mod(hdmi, n, AUDPKT_ACR_N_VALUE, AUDPKT_ACR_CONTROL0); 204 205 /* Set CTS */ 206 if (cts) 207 dw_hdmi_qp_mod(hdmi, AUDPKT_ACR_CTS_OVR_EN, AUDPKT_ACR_CTS_OVR_EN_MSK, 208 AUDPKT_ACR_CONTROL1); 209 else 210 dw_hdmi_qp_mod(hdmi, 0, AUDPKT_ACR_CTS_OVR_EN_MSK, 211 AUDPKT_ACR_CONTROL1); 212 213 dw_hdmi_qp_mod(hdmi, AUDPKT_ACR_CTS_OVR_VAL(cts), AUDPKT_ACR_CTS_OVR_VAL_MSK, 214 AUDPKT_ACR_CONTROL1); 215 } 216 217 static int dw_hdmi_qp_match_tmds_n_table(struct dw_hdmi_qp *hdmi, 218 unsigned long pixel_clk, 219 unsigned long freq) 220 { 221 const struct dw_hdmi_audio_tmds_n *tmds_n = NULL; 222 int i; 223 224 for (i = 0; common_tmds_n_table[i].tmds != 0; i++) { 225 if (pixel_clk == common_tmds_n_table[i].tmds) { 226 tmds_n = &common_tmds_n_table[i]; 227 break; 228 } 229 } 230 231 if (!tmds_n) 232 return -ENOENT; 233 234 switch (freq) { 235 case 32000: 236 return tmds_n->n_32k; 237 case 44100: 238 case 88200: 239 case 176400: 240 return (freq / 44100) * tmds_n->n_44k1; 241 case 48000: 242 case 96000: 243 case 192000: 244 return (freq / 48000) * tmds_n->n_48k; 245 default: 246 return -ENOENT; 247 } 248 } 249 250 static u32 dw_hdmi_qp_audio_math_diff(unsigned int freq, unsigned int n, 251 unsigned int pixel_clk) 252 { 253 u64 cts = mul_u32_u32(pixel_clk, n); 254 255 return do_div(cts, 128 * freq); 256 } 257 258 static unsigned int dw_hdmi_qp_compute_n(struct dw_hdmi_qp *hdmi, 259 unsigned long pixel_clk, 260 unsigned long freq) 261 { 262 unsigned int min_n = DIV_ROUND_UP((128 * freq), 1500); 263 unsigned int max_n = (128 * freq) / 300; 264 unsigned int ideal_n = (128 * freq) / 1000; 265 unsigned int best_n_distance = ideal_n; 266 unsigned int best_n = 0; 267 u64 best_diff = U64_MAX; 268 int n; 269 270 /* If the ideal N could satisfy the audio math, then just take it */ 271 if (dw_hdmi_qp_audio_math_diff(freq, ideal_n, pixel_clk) == 0) 272 return ideal_n; 273 274 for (n = min_n; n <= max_n; n++) { 275 u64 diff = dw_hdmi_qp_audio_math_diff(freq, n, pixel_clk); 276 277 if (diff < best_diff || 278 (diff == best_diff && abs(n - ideal_n) < best_n_distance)) { 279 best_n = n; 280 best_diff = diff; 281 best_n_distance = abs(best_n - ideal_n); 282 } 283 284 /* 285 * The best N already satisfy the audio math, and also be 286 * the closest value to ideal N, so just cut the loop. 287 */ 288 if (best_diff == 0 && (abs(n - ideal_n) > best_n_distance)) 289 break; 290 } 291 292 return best_n; 293 } 294 295 static unsigned int dw_hdmi_qp_find_n(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk, 296 unsigned long sample_rate) 297 { 298 int n = dw_hdmi_qp_match_tmds_n_table(hdmi, pixel_clk, sample_rate); 299 300 if (n > 0) 301 return n; 302 303 dev_warn(hdmi->dev, "Rate %lu missing; compute N dynamically\n", 304 pixel_clk); 305 306 return dw_hdmi_qp_compute_n(hdmi, pixel_clk, sample_rate); 307 } 308 309 static unsigned int dw_hdmi_qp_find_cts(struct dw_hdmi_qp *hdmi, unsigned long pixel_clk, 310 unsigned long sample_rate) 311 { 312 const struct dw_hdmi_audio_tmds_cts *tmds_cts = NULL; 313 int i; 314 315 for (i = 0; common_tmds_cts_table[i].tmds != 0; i++) { 316 if (pixel_clk == common_tmds_cts_table[i].tmds) { 317 tmds_cts = &common_tmds_cts_table[i]; 318 break; 319 } 320 } 321 322 if (!tmds_cts) 323 return 0; 324 325 switch (sample_rate) { 326 case 32000: 327 return tmds_cts->cts_32k; 328 case 44100: 329 case 88200: 330 case 176400: 331 return tmds_cts->cts_44k1; 332 case 48000: 333 case 96000: 334 case 192000: 335 return tmds_cts->cts_48k; 336 default: 337 return -ENOENT; 338 } 339 } 340 341 static void dw_hdmi_qp_set_audio_interface(struct dw_hdmi_qp *hdmi, 342 struct hdmi_codec_daifmt *fmt, 343 struct hdmi_codec_params *hparms) 344 { 345 u32 conf0 = 0; 346 347 /* Reset the audio data path of the AVP */ 348 dw_hdmi_qp_write(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWINIT_P, GLOBAL_SWRESET_REQUEST); 349 350 /* Disable AUDS, ACR, AUDI */ 351 dw_hdmi_qp_mod(hdmi, 0, 352 PKTSCHED_ACR_TX_EN | PKTSCHED_AUDS_TX_EN | PKTSCHED_AUDI_TX_EN, 353 PKTSCHED_PKT_EN); 354 355 /* Clear the audio FIFO */ 356 dw_hdmi_qp_write(hdmi, AUDIO_FIFO_CLR_P, AUDIO_INTERFACE_CONTROL0); 357 358 /* Select I2S interface as the audio source */ 359 dw_hdmi_qp_mod(hdmi, AUD_IF_I2S, AUD_IF_SEL_MSK, AUDIO_INTERFACE_CONFIG0); 360 361 /* Enable the active i2s lanes */ 362 switch (hparms->channels) { 363 case 7 ... 8: 364 conf0 |= I2S_LINES_EN(3); 365 fallthrough; 366 case 5 ... 6: 367 conf0 |= I2S_LINES_EN(2); 368 fallthrough; 369 case 3 ... 4: 370 conf0 |= I2S_LINES_EN(1); 371 fallthrough; 372 default: 373 conf0 |= I2S_LINES_EN(0); 374 break; 375 } 376 377 dw_hdmi_qp_mod(hdmi, conf0, I2S_LINES_EN_MSK, AUDIO_INTERFACE_CONFIG0); 378 379 /* 380 * Enable bpcuv generated internally for L-PCM, or received 381 * from stream for NLPCM/HBR. 382 */ 383 switch (fmt->bit_fmt) { 384 case SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE: 385 conf0 = (hparms->channels == 8) ? AUD_HBR : AUD_ASP; 386 conf0 |= I2S_BPCUV_RCV_EN; 387 break; 388 default: 389 conf0 = AUD_ASP | I2S_BPCUV_RCV_DIS; 390 break; 391 } 392 393 dw_hdmi_qp_mod(hdmi, conf0, I2S_BPCUV_RCV_MSK | AUD_FORMAT_MSK, 394 AUDIO_INTERFACE_CONFIG0); 395 396 /* Enable audio FIFO auto clear when overflow */ 397 dw_hdmi_qp_mod(hdmi, AUD_FIFO_INIT_ON_OVF_EN, AUD_FIFO_INIT_ON_OVF_MSK, 398 AUDIO_INTERFACE_CONFIG0); 399 } 400 401 /* 402 * When transmitting IEC60958 linear PCM audio, these registers allow to 403 * configure the channel status information of all the channel status 404 * bits in the IEC60958 frame. For the moment this configuration is only 405 * used when the I2S audio interface, General Purpose Audio (GPA), 406 * or AHB audio DMA (AHBAUDDMA) interface is active 407 * (for S/PDIF interface this information comes from the stream). 408 */ 409 static void dw_hdmi_qp_set_channel_status(struct dw_hdmi_qp *hdmi, 410 u8 *channel_status, bool ref2stream) 411 { 412 /* 413 * AUDPKT_CHSTATUS_OVR0: { RSV, RSV, CS1, CS0 } 414 * AUDPKT_CHSTATUS_OVR1: { CS6, CS5, CS4, CS3 } 415 * 416 * | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | 417 * CS0: | Mode | d | c | b | a | 418 * CS1: | Category Code | 419 * CS2: | Channel Number | Source Number | 420 * CS3: | Clock Accuracy | Sample Freq | 421 * CS4: | Ori Sample Freq | Word Length | 422 * CS5: | | CGMS-A | 423 * CS6~CS23: Reserved 424 * 425 * a: use of channel status block 426 * b: linear PCM identification: 0 for lpcm, 1 for nlpcm 427 * c: copyright information 428 * d: additional format information 429 */ 430 431 if (ref2stream) 432 channel_status[0] |= IEC958_AES0_NONAUDIO; 433 434 if ((dw_hdmi_qp_read(hdmi, AUDIO_INTERFACE_CONFIG0) & GENMASK(25, 24)) == AUD_HBR) { 435 /* fixup cs for HBR */ 436 channel_status[3] = (channel_status[3] & 0xf0) | IEC958_AES3_CON_FS_768000; 437 channel_status[4] = (channel_status[4] & 0x0f) | IEC958_AES4_CON_ORIGFS_NOTID; 438 } 439 440 dw_hdmi_qp_write(hdmi, channel_status[0] | (channel_status[1] << 8), 441 AUDPKT_CHSTATUS_OVR0); 442 443 regmap_bulk_write(hdmi->regm, AUDPKT_CHSTATUS_OVR1, &channel_status[3], 1); 444 445 if (ref2stream) 446 dw_hdmi_qp_mod(hdmi, 0, 447 AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK, 448 AUDPKT_CONTROL0); 449 else 450 dw_hdmi_qp_mod(hdmi, AUDPKT_PBIT_FORCE_EN | AUDPKT_CHSTATUS_OVR_EN, 451 AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK, 452 AUDPKT_CONTROL0); 453 } 454 455 static void dw_hdmi_qp_set_sample_rate(struct dw_hdmi_qp *hdmi, unsigned long long tmds_char_rate, 456 unsigned int sample_rate) 457 { 458 unsigned int n, cts; 459 460 n = dw_hdmi_qp_find_n(hdmi, tmds_char_rate, sample_rate); 461 cts = dw_hdmi_qp_find_cts(hdmi, tmds_char_rate, sample_rate); 462 463 dw_hdmi_qp_set_cts_n(hdmi, cts, n); 464 } 465 466 static int dw_hdmi_qp_audio_enable(struct drm_bridge *bridge, 467 struct drm_connector *connector) 468 { 469 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 470 471 if (hdmi->tmds_char_rate) 472 dw_hdmi_qp_mod(hdmi, 0, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE); 473 474 return 0; 475 } 476 477 static int dw_hdmi_qp_audio_prepare(struct drm_bridge *bridge, 478 struct drm_connector *connector, 479 struct hdmi_codec_daifmt *fmt, 480 struct hdmi_codec_params *hparms) 481 { 482 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 483 bool ref2stream = false; 484 485 if (!hdmi->tmds_char_rate) 486 return -ENODEV; 487 488 if (fmt->bit_clk_provider | fmt->frame_clk_provider) { 489 dev_err(hdmi->dev, "unsupported clock settings\n"); 490 return -EINVAL; 491 } 492 493 if (fmt->bit_fmt == SNDRV_PCM_FORMAT_IEC958_SUBFRAME_LE) 494 ref2stream = true; 495 496 dw_hdmi_qp_set_audio_interface(hdmi, fmt, hparms); 497 dw_hdmi_qp_set_sample_rate(hdmi, hdmi->tmds_char_rate, hparms->sample_rate); 498 dw_hdmi_qp_set_channel_status(hdmi, hparms->iec.status, ref2stream); 499 drm_atomic_helper_connector_hdmi_update_audio_infoframe(connector, &hparms->cea); 500 501 return 0; 502 } 503 504 static void dw_hdmi_qp_audio_disable_regs(struct dw_hdmi_qp *hdmi) 505 { 506 /* 507 * Keep ACR, AUDI, AUDS packet always on to make SINK device 508 * active for better compatibility and user experience. 509 * 510 * This also fix POP sound on some SINK devices which wakeup 511 * from suspend to active. 512 */ 513 dw_hdmi_qp_mod(hdmi, I2S_BPCUV_RCV_DIS, I2S_BPCUV_RCV_MSK, 514 AUDIO_INTERFACE_CONFIG0); 515 dw_hdmi_qp_mod(hdmi, AUDPKT_PBIT_FORCE_EN | AUDPKT_CHSTATUS_OVR_EN, 516 AUDPKT_PBIT_FORCE_EN_MASK | AUDPKT_CHSTATUS_OVR_EN_MASK, 517 AUDPKT_CONTROL0); 518 519 dw_hdmi_qp_mod(hdmi, AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, 520 AVP_DATAPATH_PACKET_AUDIO_SWDISABLE, GLOBAL_SWDISABLE); 521 } 522 523 static void dw_hdmi_qp_audio_disable(struct drm_bridge *bridge, 524 struct drm_connector *connector) 525 { 526 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 527 528 drm_atomic_helper_connector_hdmi_clear_audio_infoframe(connector); 529 530 if (hdmi->tmds_char_rate) 531 dw_hdmi_qp_audio_disable_regs(hdmi); 532 } 533 534 static int dw_hdmi_qp_i2c_read(struct dw_hdmi_qp *hdmi, 535 unsigned char *buf, unsigned int length) 536 { 537 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; 538 int stat; 539 540 if (!i2c->is_regaddr) { 541 dev_dbg(hdmi->dev, "set read register address to 0\n"); 542 i2c->slave_reg = 0x00; 543 i2c->is_regaddr = true; 544 } 545 546 while (length--) { 547 reinit_completion(&i2c->cmp); 548 549 dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, 550 I2CM_INTERFACE_CONTROL0); 551 552 if (i2c->is_segment) 553 dw_hdmi_qp_mod(hdmi, I2CM_EXT_READ, I2CM_WR_MASK, 554 I2CM_INTERFACE_CONTROL0); 555 else 556 dw_hdmi_qp_mod(hdmi, I2CM_FM_READ, I2CM_WR_MASK, 557 I2CM_INTERFACE_CONTROL0); 558 559 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 560 if (!stat) { 561 if (hdmi->no_hpd) 562 dev_dbg_ratelimited(hdmi->dev, 563 "i2c read timed out\n"); 564 else 565 dev_err(hdmi->dev, "i2c read timed out\n"); 566 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 567 return -EAGAIN; 568 } 569 570 /* Check for error condition on the bus */ 571 if (i2c->stat & I2CM_NACK_RCVD_IRQ) { 572 if (hdmi->no_hpd) 573 dev_dbg_ratelimited(hdmi->dev, 574 "i2c read error\n"); 575 else 576 dev_err(hdmi->dev, "i2c read error\n"); 577 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 578 return -EIO; 579 } 580 581 *buf++ = dw_hdmi_qp_read(hdmi, I2CM_INTERFACE_RDDATA_0_3) & 0xff; 582 dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 583 } 584 585 i2c->is_segment = false; 586 587 return 0; 588 } 589 590 static int dw_hdmi_qp_i2c_write(struct dw_hdmi_qp *hdmi, 591 unsigned char *buf, unsigned int length) 592 { 593 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; 594 int stat; 595 596 if (!i2c->is_regaddr) { 597 /* Use the first write byte as register address */ 598 i2c->slave_reg = buf[0]; 599 length--; 600 buf++; 601 i2c->is_regaddr = true; 602 } 603 604 while (length--) { 605 reinit_completion(&i2c->cmp); 606 607 dw_hdmi_qp_write(hdmi, *buf++, I2CM_INTERFACE_WRDATA_0_3); 608 dw_hdmi_qp_mod(hdmi, i2c->slave_reg++ << 12, I2CM_ADDR, 609 I2CM_INTERFACE_CONTROL0); 610 dw_hdmi_qp_mod(hdmi, I2CM_FM_WRITE, I2CM_WR_MASK, 611 I2CM_INTERFACE_CONTROL0); 612 613 stat = wait_for_completion_timeout(&i2c->cmp, HZ / 10); 614 if (!stat) { 615 dev_err(hdmi->dev, "i2c write time out!\n"); 616 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 617 return -EAGAIN; 618 } 619 620 /* Check for error condition on the bus */ 621 if (i2c->stat & I2CM_NACK_RCVD_IRQ) { 622 dev_err(hdmi->dev, "i2c write nack!\n"); 623 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 624 return -EIO; 625 } 626 627 dw_hdmi_qp_mod(hdmi, 0, I2CM_WR_MASK, I2CM_INTERFACE_CONTROL0); 628 } 629 630 return 0; 631 } 632 633 static int dw_hdmi_qp_i2c_xfer(struct i2c_adapter *adap, 634 struct i2c_msg *msgs, int num) 635 { 636 struct dw_hdmi_qp *hdmi = i2c_get_adapdata(adap); 637 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; 638 u8 addr = msgs[0].addr; 639 int i, ret = 0; 640 641 if (addr == DDC_CI_ADDR) 642 /* 643 * The internal I2C controller does not support the multi-byte 644 * read and write operations needed for DDC/CI. 645 * FIXME: Blacklist the DDC/CI address until we filter out 646 * unsupported I2C operations. 647 */ 648 return -EOPNOTSUPP; 649 650 for (i = 0; i < num; i++) { 651 if (msgs[i].len == 0) { 652 dev_err(hdmi->dev, 653 "unsupported transfer %d/%d, no data\n", 654 i + 1, num); 655 return -EOPNOTSUPP; 656 } 657 } 658 659 guard(mutex)(&i2c->lock); 660 661 /* Unmute DONE and ERROR interrupts */ 662 dw_hdmi_qp_mod(hdmi, I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 663 I2CM_NACK_RCVD_MASK_N | I2CM_OP_DONE_MASK_N, 664 MAINUNIT_1_INT_MASK_N); 665 666 /* Set slave device address taken from the first I2C message */ 667 if (addr == DDC_SEGMENT_ADDR && msgs[0].len == 1) 668 addr = DDC_ADDR; 669 670 dw_hdmi_qp_mod(hdmi, addr << 5, I2CM_SLVADDR, I2CM_INTERFACE_CONTROL0); 671 672 /* Set slave device register address on transfer */ 673 i2c->is_regaddr = false; 674 675 /* Set segment pointer for I2C extended read mode operation */ 676 i2c->is_segment = false; 677 678 for (i = 0; i < num; i++) { 679 if (msgs[i].addr == DDC_SEGMENT_ADDR && msgs[i].len == 1) { 680 i2c->is_segment = true; 681 dw_hdmi_qp_mod(hdmi, DDC_SEGMENT_ADDR, I2CM_SEG_ADDR, 682 I2CM_INTERFACE_CONTROL1); 683 dw_hdmi_qp_mod(hdmi, *msgs[i].buf << 7, I2CM_SEG_PTR, 684 I2CM_INTERFACE_CONTROL1); 685 } else { 686 if (msgs[i].flags & I2C_M_RD) 687 ret = dw_hdmi_qp_i2c_read(hdmi, msgs[i].buf, 688 msgs[i].len); 689 else 690 ret = dw_hdmi_qp_i2c_write(hdmi, msgs[i].buf, 691 msgs[i].len); 692 } 693 if (ret < 0) 694 break; 695 } 696 697 if (!ret) 698 ret = num; 699 700 /* Mute DONE and ERROR interrupts */ 701 dw_hdmi_qp_mod(hdmi, 0, I2CM_OP_DONE_MASK_N | I2CM_NACK_RCVD_MASK_N, 702 MAINUNIT_1_INT_MASK_N); 703 704 return ret; 705 } 706 707 static u32 dw_hdmi_qp_i2c_func(struct i2c_adapter *adapter) 708 { 709 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 710 } 711 712 static const struct i2c_algorithm dw_hdmi_qp_algorithm = { 713 .master_xfer = dw_hdmi_qp_i2c_xfer, 714 .functionality = dw_hdmi_qp_i2c_func, 715 }; 716 717 static struct i2c_adapter *dw_hdmi_qp_i2c_adapter(struct dw_hdmi_qp *hdmi) 718 { 719 struct dw_hdmi_qp_i2c *i2c; 720 struct i2c_adapter *adap; 721 int ret; 722 723 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 724 if (!i2c) 725 return ERR_PTR(-ENOMEM); 726 727 mutex_init(&i2c->lock); 728 init_completion(&i2c->cmp); 729 730 adap = &i2c->adap; 731 adap->owner = THIS_MODULE; 732 adap->dev.parent = hdmi->dev; 733 adap->algo = &dw_hdmi_qp_algorithm; 734 strscpy(adap->name, "DesignWare HDMI QP", sizeof(adap->name)); 735 736 i2c_set_adapdata(adap, hdmi); 737 738 ret = devm_i2c_add_adapter(hdmi->dev, adap); 739 if (ret) { 740 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 741 devm_kfree(hdmi->dev, i2c); 742 return ERR_PTR(ret); 743 } 744 745 hdmi->i2c = i2c; 746 dev_info(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 747 748 return adap; 749 } 750 751 static int dw_hdmi_qp_config_avi_infoframe(struct dw_hdmi_qp *hdmi, 752 const u8 *buffer, size_t len) 753 { 754 u32 val, i, j; 755 756 if (len != HDMI_INFOFRAME_SIZE(AVI)) { 757 dev_err(hdmi->dev, "failed to configure avi infoframe\n"); 758 return -EINVAL; 759 } 760 761 /* 762 * DW HDMI QP IP uses a different byte format from standard AVI info 763 * frames, though generally the bits are in the correct bytes. 764 */ 765 val = buffer[1] << 8 | buffer[2] << 16; 766 dw_hdmi_qp_write(hdmi, val, PKT_AVI_CONTENTS0); 767 768 for (i = 0; i < 4; i++) { 769 for (j = 0; j < 4; j++) { 770 if (i * 4 + j >= 14) 771 break; 772 if (!j) 773 val = buffer[i * 4 + j + 3]; 774 val |= buffer[i * 4 + j + 3] << (8 * j); 775 } 776 777 dw_hdmi_qp_write(hdmi, val, PKT_AVI_CONTENTS1 + i * 4); 778 } 779 780 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 781 782 dw_hdmi_qp_mod(hdmi, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, 783 PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, PKTSCHED_PKT_EN); 784 785 return 0; 786 } 787 788 static int dw_hdmi_qp_config_drm_infoframe(struct dw_hdmi_qp *hdmi, 789 const u8 *buffer, size_t len) 790 { 791 u32 val, i; 792 793 if (len != HDMI_INFOFRAME_SIZE(DRM)) { 794 dev_err(hdmi->dev, "failed to configure drm infoframe\n"); 795 return -EINVAL; 796 } 797 798 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN); 799 800 val = buffer[1] << 8 | buffer[2] << 16; 801 dw_hdmi_qp_write(hdmi, val, PKT_DRMI_CONTENTS0); 802 803 for (i = 0; i <= buffer[2]; i++) { 804 if (i % 4 == 0) 805 val = buffer[3 + i]; 806 val |= buffer[3 + i] << ((i % 4) * 8); 807 808 if ((i % 4 == 3) || i == buffer[2]) 809 dw_hdmi_qp_write(hdmi, val, 810 PKT_DRMI_CONTENTS1 + ((i / 4) * 4)); 811 } 812 813 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_FIELDRATE, PKTSCHED_PKT_CONFIG1); 814 dw_hdmi_qp_mod(hdmi, PKTSCHED_DRMI_TX_EN, PKTSCHED_DRMI_TX_EN, 815 PKTSCHED_PKT_EN); 816 817 return 0; 818 } 819 820 /* 821 * Static values documented in the TRM 822 * Different values are only used for debug purposes 823 */ 824 #define DW_HDMI_QP_AUDIO_INFOFRAME_HB1 0x1 825 #define DW_HDMI_QP_AUDIO_INFOFRAME_HB2 0xa 826 827 static int dw_hdmi_qp_config_audio_infoframe(struct dw_hdmi_qp *hdmi, 828 const u8 *buffer, size_t len) 829 { 830 /* 831 * AUDI_CONTENTS0: { RSV, HB2, HB1, RSV } 832 * AUDI_CONTENTS1: { PB3, PB2, PB1, PB0 } 833 * AUDI_CONTENTS2: { PB7, PB6, PB5, PB4 } 834 * 835 * PB0: CheckSum 836 * PB1: | CT3 | CT2 | CT1 | CT0 | F13 | CC2 | CC1 | CC0 | 837 * PB2: | F27 | F26 | F25 | SF2 | SF1 | SF0 | SS1 | SS0 | 838 * PB3: | F37 | F36 | F35 | F34 | F33 | F32 | F31 | F30 | 839 * PB4: | CA7 | CA6 | CA5 | CA4 | CA3 | CA2 | CA1 | CA0 | 840 * PB5: | DM_INH | LSV3 | LSV2 | LSV1 | LSV0 | F52 | F51 | F50 | 841 * PB6~PB10: Reserved 842 * 843 * AUDI_CONTENTS0 default value defined by HDMI specification, 844 * and shall only be changed for debug purposes. 845 */ 846 u32 header_bytes = (DW_HDMI_QP_AUDIO_INFOFRAME_HB1 << 8) | 847 (DW_HDMI_QP_AUDIO_INFOFRAME_HB2 << 16); 848 849 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS0, &header_bytes, 1); 850 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS1, &buffer[3], 1); 851 regmap_bulk_write(hdmi->regm, PKT_AUDI_CONTENTS2, &buffer[4], 1); 852 853 /* Enable ACR, AUDI, AMD */ 854 dw_hdmi_qp_mod(hdmi, 855 PKTSCHED_ACR_TX_EN | PKTSCHED_AUDI_TX_EN | PKTSCHED_AMD_TX_EN, 856 PKTSCHED_ACR_TX_EN | PKTSCHED_AUDI_TX_EN | PKTSCHED_AMD_TX_EN, 857 PKTSCHED_PKT_EN); 858 859 /* Enable AUDS */ 860 dw_hdmi_qp_mod(hdmi, PKTSCHED_AUDS_TX_EN, PKTSCHED_AUDS_TX_EN, PKTSCHED_PKT_EN); 861 862 return 0; 863 } 864 865 static void dw_hdmi_qp_bridge_atomic_enable(struct drm_bridge *bridge, 866 struct drm_atomic_state *state) 867 { 868 struct dw_hdmi_qp *hdmi = bridge->driver_private; 869 struct drm_connector_state *conn_state; 870 struct drm_connector *connector; 871 unsigned int op_mode; 872 873 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 874 if (WARN_ON(!connector)) 875 return; 876 877 conn_state = drm_atomic_get_new_connector_state(state, connector); 878 if (WARN_ON(!conn_state)) 879 return; 880 881 if (connector->display_info.is_hdmi) { 882 dev_dbg(hdmi->dev, "%s mode=HDMI %s rate=%llu bpc=%u\n", __func__, 883 drm_hdmi_connector_get_output_format_name(conn_state->hdmi.output_format), 884 conn_state->hdmi.tmds_char_rate, conn_state->hdmi.output_bpc); 885 op_mode = 0; 886 hdmi->tmds_char_rate = conn_state->hdmi.tmds_char_rate; 887 } else { 888 dev_dbg(hdmi->dev, "%s mode=DVI\n", __func__); 889 op_mode = OPMODE_DVI; 890 } 891 892 hdmi->phy.ops->init(hdmi, hdmi->phy.data); 893 894 dw_hdmi_qp_mod(hdmi, HDCP2_BYPASS, HDCP2_BYPASS, HDCP2LOGIC_CONFIG0); 895 dw_hdmi_qp_mod(hdmi, op_mode, OPMODE_DVI, LINK_CONFIG0); 896 897 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 898 } 899 900 static void dw_hdmi_qp_bridge_atomic_disable(struct drm_bridge *bridge, 901 struct drm_atomic_state *state) 902 { 903 struct dw_hdmi_qp *hdmi = bridge->driver_private; 904 905 hdmi->tmds_char_rate = 0; 906 907 hdmi->phy.ops->disable(hdmi, hdmi->phy.data); 908 } 909 910 static enum drm_connector_status 911 dw_hdmi_qp_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 912 { 913 struct dw_hdmi_qp *hdmi = bridge->driver_private; 914 const struct drm_edid *drm_edid; 915 916 if (hdmi->no_hpd) { 917 drm_edid = drm_edid_read_ddc(connector, bridge->ddc); 918 if (drm_edid) 919 return connector_status_connected; 920 else 921 return connector_status_disconnected; 922 } 923 924 return hdmi->phy.ops->read_hpd(hdmi, hdmi->phy.data); 925 } 926 927 static const struct drm_edid * 928 dw_hdmi_qp_bridge_edid_read(struct drm_bridge *bridge, 929 struct drm_connector *connector) 930 { 931 struct dw_hdmi_qp *hdmi = bridge->driver_private; 932 const struct drm_edid *drm_edid; 933 934 drm_edid = drm_edid_read_ddc(connector, bridge->ddc); 935 if (!drm_edid) 936 dev_dbg(hdmi->dev, "failed to get edid\n"); 937 938 return drm_edid; 939 } 940 941 static enum drm_mode_status 942 dw_hdmi_qp_bridge_tmds_char_rate_valid(const struct drm_bridge *bridge, 943 const struct drm_display_mode *mode, 944 unsigned long long rate) 945 { 946 struct dw_hdmi_qp *hdmi = bridge->driver_private; 947 948 /* 949 * TODO: when hdmi->no_hpd is 1 we must not support modes that 950 * require scrambling, including every mode with a clock above 951 * HDMI14_MAX_TMDSCLK. 952 */ 953 if (rate > HDMI14_MAX_TMDSCLK) { 954 dev_dbg(hdmi->dev, "Unsupported TMDS char rate: %lld\n", rate); 955 return MODE_CLOCK_HIGH; 956 } 957 958 return MODE_OK; 959 } 960 961 static int dw_hdmi_qp_bridge_clear_avi_infoframe(struct drm_bridge *bridge) 962 { 963 struct dw_hdmi_qp *hdmi = bridge->driver_private; 964 965 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_AVI_TX_EN | PKTSCHED_GCP_TX_EN, 966 PKTSCHED_PKT_EN); 967 968 return 0; 969 } 970 971 static int dw_hdmi_qp_bridge_clear_hdmi_infoframe(struct drm_bridge *bridge) 972 { 973 /* FIXME: add support for this InfoFrame */ 974 975 drm_warn_once(bridge->encoder->dev, "HDMI VSI not supported\n"); 976 977 return 0; 978 } 979 980 static int dw_hdmi_qp_bridge_clear_hdr_drm_infoframe(struct drm_bridge *bridge) 981 { 982 struct dw_hdmi_qp *hdmi = bridge->driver_private; 983 984 dw_hdmi_qp_mod(hdmi, 0, PKTSCHED_DRMI_TX_EN, PKTSCHED_PKT_EN); 985 986 return 0; 987 } 988 989 static int dw_hdmi_qp_bridge_clear_audio_infoframe(struct drm_bridge *bridge) 990 { 991 struct dw_hdmi_qp *hdmi = bridge->driver_private; 992 993 dw_hdmi_qp_mod(hdmi, 0, 994 PKTSCHED_ACR_TX_EN | 995 PKTSCHED_AUDS_TX_EN | 996 PKTSCHED_AUDI_TX_EN, 997 PKTSCHED_PKT_EN); 998 999 return 0; 1000 } 1001 1002 static int dw_hdmi_qp_bridge_write_avi_infoframe(struct drm_bridge *bridge, 1003 const u8 *buffer, size_t len) 1004 { 1005 struct dw_hdmi_qp *hdmi = bridge->driver_private; 1006 1007 dw_hdmi_qp_bridge_clear_avi_infoframe(bridge); 1008 1009 return dw_hdmi_qp_config_avi_infoframe(hdmi, buffer, len); 1010 } 1011 1012 static int dw_hdmi_qp_bridge_write_hdmi_infoframe(struct drm_bridge *bridge, 1013 const u8 *buffer, size_t len) 1014 { 1015 dw_hdmi_qp_bridge_clear_hdmi_infoframe(bridge); 1016 1017 /* FIXME: add support for the HDMI VSI */ 1018 1019 return 0; 1020 } 1021 1022 static int dw_hdmi_qp_bridge_write_hdr_drm_infoframe(struct drm_bridge *bridge, 1023 const u8 *buffer, size_t len) 1024 { 1025 struct dw_hdmi_qp *hdmi = bridge->driver_private; 1026 1027 dw_hdmi_qp_bridge_clear_hdr_drm_infoframe(bridge); 1028 1029 return dw_hdmi_qp_config_drm_infoframe(hdmi, buffer, len); 1030 } 1031 1032 static int dw_hdmi_qp_bridge_write_audio_infoframe(struct drm_bridge *bridge, 1033 const u8 *buffer, size_t len) 1034 { 1035 struct dw_hdmi_qp *hdmi = bridge->driver_private; 1036 1037 dw_hdmi_qp_bridge_clear_audio_infoframe(bridge); 1038 1039 return dw_hdmi_qp_config_audio_infoframe(hdmi, buffer, len); 1040 } 1041 1042 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC 1043 static irqreturn_t dw_hdmi_qp_cec_hardirq(int irq, void *dev_id) 1044 { 1045 struct dw_hdmi_qp *hdmi = dev_id; 1046 struct dw_hdmi_qp_cec *cec = hdmi->cec; 1047 irqreturn_t ret = IRQ_HANDLED; 1048 u32 stat; 1049 1050 stat = dw_hdmi_qp_read(hdmi, CEC_INT_STATUS); 1051 if (stat == 0) 1052 return IRQ_NONE; 1053 1054 dw_hdmi_qp_write(hdmi, stat, CEC_INT_CLEAR); 1055 1056 if (stat & CEC_STAT_LINE_ERR) { 1057 cec->tx_status = CEC_TX_STATUS_ERROR; 1058 cec->tx_done = true; 1059 ret = IRQ_WAKE_THREAD; 1060 } else if (stat & CEC_STAT_DONE) { 1061 cec->tx_status = CEC_TX_STATUS_OK; 1062 cec->tx_done = true; 1063 ret = IRQ_WAKE_THREAD; 1064 } else if (stat & CEC_STAT_NACK) { 1065 cec->tx_status = CEC_TX_STATUS_NACK; 1066 cec->tx_done = true; 1067 ret = IRQ_WAKE_THREAD; 1068 } 1069 1070 if (stat & CEC_STAT_EOM) { 1071 unsigned int len, i, val; 1072 1073 val = dw_hdmi_qp_read(hdmi, CEC_RX_COUNT_STATUS); 1074 len = (val & 0xf) + 1; 1075 1076 if (len > sizeof(cec->rx_msg.msg)) 1077 len = sizeof(cec->rx_msg.msg); 1078 1079 for (i = 0; i < 4; i++) { 1080 val = dw_hdmi_qp_read(hdmi, CEC_RX_DATA3_0 + i * 4); 1081 cec->rx_msg.msg[i * 4] = val & 0xff; 1082 cec->rx_msg.msg[i * 4 + 1] = (val >> 8) & 0xff; 1083 cec->rx_msg.msg[i * 4 + 2] = (val >> 16) & 0xff; 1084 cec->rx_msg.msg[i * 4 + 3] = (val >> 24) & 0xff; 1085 } 1086 1087 dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL); 1088 1089 cec->rx_msg.len = len; 1090 cec->rx_done = true; 1091 1092 ret = IRQ_WAKE_THREAD; 1093 } 1094 1095 return ret; 1096 } 1097 1098 static irqreturn_t dw_hdmi_qp_cec_thread(int irq, void *dev_id) 1099 { 1100 struct dw_hdmi_qp *hdmi = dev_id; 1101 struct dw_hdmi_qp_cec *cec = hdmi->cec; 1102 1103 if (cec->tx_done) { 1104 cec->tx_done = false; 1105 drm_connector_hdmi_cec_transmit_attempt_done(cec->connector, 1106 cec->tx_status); 1107 } 1108 1109 if (cec->rx_done) { 1110 cec->rx_done = false; 1111 drm_connector_hdmi_cec_received_msg(cec->connector, &cec->rx_msg); 1112 } 1113 1114 return IRQ_HANDLED; 1115 } 1116 1117 static int dw_hdmi_qp_cec_init(struct drm_bridge *bridge, 1118 struct drm_connector *connector) 1119 { 1120 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 1121 struct dw_hdmi_qp_cec *cec = hdmi->cec; 1122 1123 cec->connector = connector; 1124 1125 dw_hdmi_qp_write(hdmi, 0, CEC_TX_COUNT); 1126 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); 1127 dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N); 1128 1129 return devm_request_threaded_irq(hdmi->dev, cec->irq, 1130 dw_hdmi_qp_cec_hardirq, 1131 dw_hdmi_qp_cec_thread, IRQF_SHARED, 1132 dev_name(hdmi->dev), hdmi); 1133 } 1134 1135 static int dw_hdmi_qp_cec_log_addr(struct drm_bridge *bridge, u8 logical_addr) 1136 { 1137 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 1138 struct dw_hdmi_qp_cec *cec = hdmi->cec; 1139 1140 if (logical_addr == CEC_LOG_ADDR_INVALID) 1141 cec->addresses = 0; 1142 else 1143 cec->addresses |= BIT(logical_addr) | CEC_ADDR_BROADCAST; 1144 1145 dw_hdmi_qp_write(hdmi, cec->addresses, CEC_ADDR); 1146 1147 return 0; 1148 } 1149 1150 static int dw_hdmi_qp_cec_enable(struct drm_bridge *bridge, bool enable) 1151 { 1152 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 1153 unsigned int irqs; 1154 u32 swdisable; 1155 1156 if (!enable) { 1157 dw_hdmi_qp_write(hdmi, 0, CEC_INT_MASK_N); 1158 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); 1159 1160 swdisable = dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE); 1161 swdisable = swdisable | CEC_SWDISABLE; 1162 dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE); 1163 } else { 1164 swdisable = dw_hdmi_qp_read(hdmi, GLOBAL_SWDISABLE); 1165 swdisable = swdisable & ~CEC_SWDISABLE; 1166 dw_hdmi_qp_write(hdmi, swdisable, GLOBAL_SWDISABLE); 1167 1168 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); 1169 dw_hdmi_qp_write(hdmi, 1, CEC_LOCK_CONTROL); 1170 1171 dw_hdmi_qp_cec_log_addr(bridge, CEC_LOG_ADDR_INVALID); 1172 1173 irqs = CEC_STAT_LINE_ERR | CEC_STAT_NACK | CEC_STAT_EOM | 1174 CEC_STAT_DONE; 1175 dw_hdmi_qp_write(hdmi, ~0, CEC_INT_CLEAR); 1176 dw_hdmi_qp_write(hdmi, irqs, CEC_INT_MASK_N); 1177 } 1178 1179 return 0; 1180 } 1181 1182 static int dw_hdmi_qp_cec_transmit(struct drm_bridge *bridge, u8 attempts, 1183 u32 signal_free_time, struct cec_msg *msg) 1184 { 1185 struct dw_hdmi_qp *hdmi = dw_hdmi_qp_from_bridge(bridge); 1186 unsigned int i; 1187 u32 val; 1188 1189 for (i = 0; i < msg->len; i++) { 1190 if (!(i % 4)) 1191 val = msg->msg[i]; 1192 if ((i % 4) == 1) 1193 val |= msg->msg[i] << 8; 1194 if ((i % 4) == 2) 1195 val |= msg->msg[i] << 16; 1196 if ((i % 4) == 3) 1197 val |= msg->msg[i] << 24; 1198 1199 if (i == (msg->len - 1) || (i % 4) == 3) 1200 dw_hdmi_qp_write(hdmi, val, CEC_TX_DATA3_0 + (i / 4) * 4); 1201 } 1202 1203 dw_hdmi_qp_write(hdmi, msg->len - 1, CEC_TX_COUNT); 1204 dw_hdmi_qp_write(hdmi, CEC_CTRL_START, CEC_TX_CONTROL); 1205 1206 return 0; 1207 } 1208 #else 1209 #define dw_hdmi_qp_cec_init NULL 1210 #define dw_hdmi_qp_cec_enable NULL 1211 #define dw_hdmi_qp_cec_log_addr NULL 1212 #define dw_hdmi_qp_cec_transmit NULL 1213 #endif /* CONFIG_DRM_DW_HDMI_QP_CEC */ 1214 1215 static const struct drm_bridge_funcs dw_hdmi_qp_bridge_funcs = { 1216 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1217 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1218 .atomic_reset = drm_atomic_helper_bridge_reset, 1219 .atomic_enable = dw_hdmi_qp_bridge_atomic_enable, 1220 .atomic_disable = dw_hdmi_qp_bridge_atomic_disable, 1221 .detect = dw_hdmi_qp_bridge_detect, 1222 .edid_read = dw_hdmi_qp_bridge_edid_read, 1223 .hdmi_tmds_char_rate_valid = dw_hdmi_qp_bridge_tmds_char_rate_valid, 1224 .hdmi_clear_avi_infoframe = dw_hdmi_qp_bridge_clear_avi_infoframe, 1225 .hdmi_write_avi_infoframe = dw_hdmi_qp_bridge_write_avi_infoframe, 1226 .hdmi_clear_hdmi_infoframe = dw_hdmi_qp_bridge_clear_hdmi_infoframe, 1227 .hdmi_write_hdmi_infoframe = dw_hdmi_qp_bridge_write_hdmi_infoframe, 1228 .hdmi_clear_hdr_drm_infoframe = dw_hdmi_qp_bridge_clear_hdr_drm_infoframe, 1229 .hdmi_write_hdr_drm_infoframe = dw_hdmi_qp_bridge_write_hdr_drm_infoframe, 1230 .hdmi_clear_audio_infoframe = dw_hdmi_qp_bridge_clear_audio_infoframe, 1231 .hdmi_write_audio_infoframe = dw_hdmi_qp_bridge_write_audio_infoframe, 1232 .hdmi_audio_startup = dw_hdmi_qp_audio_enable, 1233 .hdmi_audio_shutdown = dw_hdmi_qp_audio_disable, 1234 .hdmi_audio_prepare = dw_hdmi_qp_audio_prepare, 1235 .hdmi_cec_init = dw_hdmi_qp_cec_init, 1236 .hdmi_cec_enable = dw_hdmi_qp_cec_enable, 1237 .hdmi_cec_log_addr = dw_hdmi_qp_cec_log_addr, 1238 .hdmi_cec_transmit = dw_hdmi_qp_cec_transmit, 1239 }; 1240 1241 static irqreturn_t dw_hdmi_qp_main_hardirq(int irq, void *dev_id) 1242 { 1243 struct dw_hdmi_qp *hdmi = dev_id; 1244 struct dw_hdmi_qp_i2c *i2c = hdmi->i2c; 1245 u32 stat; 1246 1247 stat = dw_hdmi_qp_read(hdmi, MAINUNIT_1_INT_STATUS); 1248 1249 i2c->stat = stat & (I2CM_OP_DONE_IRQ | I2CM_READ_REQUEST_IRQ | 1250 I2CM_NACK_RCVD_IRQ); 1251 1252 if (i2c->stat) { 1253 dw_hdmi_qp_write(hdmi, i2c->stat, MAINUNIT_1_INT_CLEAR); 1254 complete(&i2c->cmp); 1255 } 1256 1257 if (stat) 1258 return IRQ_HANDLED; 1259 1260 return IRQ_NONE; 1261 } 1262 1263 static const struct regmap_config dw_hdmi_qp_regmap_config = { 1264 .reg_bits = 32, 1265 .val_bits = 32, 1266 .reg_stride = 4, 1267 .max_register = EARCRX_1_INT_FORCE, 1268 }; 1269 1270 static void dw_hdmi_qp_init_hw(struct dw_hdmi_qp *hdmi) 1271 { 1272 dw_hdmi_qp_write(hdmi, 0, MAINUNIT_0_INT_MASK_N); 1273 dw_hdmi_qp_write(hdmi, 0, MAINUNIT_1_INT_MASK_N); 1274 dw_hdmi_qp_write(hdmi, hdmi->ref_clk_rate, TIMER_BASE_CONFIG0); 1275 1276 /* Software reset */ 1277 dw_hdmi_qp_write(hdmi, 0x01, I2CM_CONTROL0); 1278 dw_hdmi_qp_write(hdmi, 0x085c085c, I2CM_FM_SCL_CONFIG0); 1279 dw_hdmi_qp_mod(hdmi, 0, I2CM_FM_EN, I2CM_INTERFACE_CONTROL0); 1280 1281 /* Clear DONE and ERROR interrupts */ 1282 dw_hdmi_qp_write(hdmi, I2CM_OP_DONE_CLEAR | I2CM_NACK_RCVD_CLEAR, 1283 MAINUNIT_1_INT_CLEAR); 1284 1285 if (hdmi->phy.ops->setup_hpd) 1286 hdmi->phy.ops->setup_hpd(hdmi, hdmi->phy.data); 1287 } 1288 1289 struct dw_hdmi_qp *dw_hdmi_qp_bind(struct platform_device *pdev, 1290 struct drm_encoder *encoder, 1291 const struct dw_hdmi_qp_plat_data *plat_data) 1292 { 1293 struct device *dev = &pdev->dev; 1294 struct dw_hdmi_qp *hdmi; 1295 void __iomem *regs; 1296 int ret; 1297 1298 if (!plat_data->phy_ops || !plat_data->phy_ops->init || 1299 !plat_data->phy_ops->disable || !plat_data->phy_ops->read_hpd) { 1300 dev_err(dev, "Missing platform PHY ops\n"); 1301 return ERR_PTR(-ENODEV); 1302 } 1303 1304 hdmi = devm_drm_bridge_alloc(dev, struct dw_hdmi_qp, bridge, 1305 &dw_hdmi_qp_bridge_funcs); 1306 if (IS_ERR(hdmi)) 1307 return ERR_CAST(hdmi); 1308 1309 hdmi->dev = dev; 1310 1311 regs = devm_platform_ioremap_resource(pdev, 0); 1312 if (IS_ERR(regs)) 1313 return ERR_CAST(regs); 1314 1315 hdmi->regm = devm_regmap_init_mmio(dev, regs, &dw_hdmi_qp_regmap_config); 1316 if (IS_ERR(hdmi->regm)) { 1317 dev_err(dev, "Failed to configure regmap\n"); 1318 return ERR_CAST(hdmi->regm); 1319 } 1320 1321 hdmi->phy.ops = plat_data->phy_ops; 1322 hdmi->phy.data = plat_data->phy_data; 1323 1324 if (plat_data->ref_clk_rate) { 1325 hdmi->ref_clk_rate = plat_data->ref_clk_rate; 1326 } else { 1327 hdmi->ref_clk_rate = 428571429; 1328 dev_warn(dev, "Set ref_clk_rate to vendor default\n"); 1329 } 1330 1331 dw_hdmi_qp_init_hw(hdmi); 1332 1333 hdmi->main_irq = plat_data->main_irq; 1334 ret = devm_request_threaded_irq(dev, plat_data->main_irq, 1335 dw_hdmi_qp_main_hardirq, NULL, 1336 IRQF_SHARED, dev_name(dev), hdmi); 1337 if (ret) 1338 return ERR_PTR(ret); 1339 1340 hdmi->no_hpd = device_property_read_bool(dev, "no-hpd"); 1341 1342 hdmi->bridge.driver_private = hdmi; 1343 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | 1344 DRM_BRIDGE_OP_EDID | 1345 DRM_BRIDGE_OP_HDMI | 1346 DRM_BRIDGE_OP_HDMI_AUDIO | 1347 DRM_BRIDGE_OP_HDMI_HDR_DRM_INFOFRAME; 1348 if (!hdmi->no_hpd) 1349 hdmi->bridge.ops |= DRM_BRIDGE_OP_HPD; 1350 hdmi->bridge.of_node = pdev->dev.of_node; 1351 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 1352 hdmi->bridge.vendor = "Synopsys"; 1353 hdmi->bridge.product = "DW HDMI QP TX"; 1354 1355 if (plat_data->supported_formats) 1356 hdmi->bridge.supported_formats = plat_data->supported_formats; 1357 1358 if (plat_data->max_bpc) 1359 hdmi->bridge.max_bpc = plat_data->max_bpc; 1360 1361 hdmi->bridge.ddc = dw_hdmi_qp_i2c_adapter(hdmi); 1362 if (IS_ERR(hdmi->bridge.ddc)) 1363 return ERR_CAST(hdmi->bridge.ddc); 1364 1365 hdmi->bridge.hdmi_audio_max_i2s_playback_channels = 8; 1366 hdmi->bridge.hdmi_audio_dev = dev; 1367 hdmi->bridge.hdmi_audio_dai_port = 1; 1368 1369 #ifdef CONFIG_DRM_DW_HDMI_QP_CEC 1370 if (plat_data->cec_irq) { 1371 hdmi->bridge.ops |= DRM_BRIDGE_OP_HDMI_CEC_ADAPTER; 1372 hdmi->bridge.hdmi_cec_dev = dev; 1373 hdmi->bridge.hdmi_cec_adapter_name = dev_name(dev); 1374 1375 hdmi->cec = devm_kzalloc(hdmi->dev, sizeof(*hdmi->cec), GFP_KERNEL); 1376 if (!hdmi->cec) 1377 return ERR_PTR(-ENOMEM); 1378 1379 hdmi->cec->irq = plat_data->cec_irq; 1380 } else { 1381 dev_warn(dev, "Disabled CEC support due to missing IRQ\n"); 1382 } 1383 #endif 1384 1385 ret = devm_drm_bridge_add(dev, &hdmi->bridge); 1386 if (ret) 1387 return ERR_PTR(ret); 1388 1389 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, 1390 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 1391 if (ret) 1392 return ERR_PTR(ret); 1393 1394 return hdmi; 1395 } 1396 EXPORT_SYMBOL_GPL(dw_hdmi_qp_bind); 1397 1398 void dw_hdmi_qp_suspend(struct device *dev, struct dw_hdmi_qp *hdmi) 1399 { 1400 disable_irq(hdmi->main_irq); 1401 } 1402 EXPORT_SYMBOL_GPL(dw_hdmi_qp_suspend); 1403 1404 void dw_hdmi_qp_resume(struct device *dev, struct dw_hdmi_qp *hdmi) 1405 { 1406 dw_hdmi_qp_init_hw(hdmi); 1407 enable_irq(hdmi->main_irq); 1408 } 1409 EXPORT_SYMBOL_GPL(dw_hdmi_qp_resume); 1410 1411 MODULE_AUTHOR("Algea Cao <algea.cao@rock-chips.com>"); 1412 MODULE_AUTHOR("Cristian Ciocaltea <cristian.ciocaltea@collabora.com>"); 1413 MODULE_DESCRIPTION("DW HDMI QP transmitter library"); 1414 MODULE_LICENSE("GPL"); 1415