1 // SPDX-License-Identifier: GPL-2.0 2 3 #include <linux/clk.h> 4 #include <linux/delay.h> 5 #include <linux/device.h> 6 #include <linux/err.h> 7 #include <linux/kernel.h> 8 #include <linux/module.h> 9 #include <linux/mutex.h> 10 #include <linux/of.h> 11 #include <linux/regulator/consumer.h> 12 #include <linux/spi/spi.h> 13 #include <linux/units.h> 14 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_bridge.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_mipi_dsi.h> 19 #include <drm/drm_of.h> 20 #include <drm/drm_panel.h> 21 #include <video/mipi_display.h> 22 23 #define SSD2825_DEVICE_ID_REG 0xb0 24 #define SSD2825_RGB_INTERFACE_CTRL_REG_1 0xb1 25 #define SSD2825_RGB_INTERFACE_CTRL_REG_2 0xb2 26 #define SSD2825_RGB_INTERFACE_CTRL_REG_3 0xb3 27 #define SSD2825_RGB_INTERFACE_CTRL_REG_4 0xb4 28 #define SSD2825_RGB_INTERFACE_CTRL_REG_5 0xb5 29 #define SSD2825_RGB_INTERFACE_CTRL_REG_6 0xb6 30 #define SSD2825_NON_BURST_EV BIT(2) 31 #define SSD2825_BURST BIT(3) 32 #define SSD2825_PCKL_HIGH BIT(13) 33 #define SSD2825_HSYNC_HIGH BIT(14) 34 #define SSD2825_VSYNC_HIGH BIT(15) 35 #define SSD2825_CONFIGURATION_REG 0xb7 36 #define SSD2825_CONF_REG_HS BIT(0) 37 #define SSD2825_CONF_REG_CKE BIT(1) 38 #define SSD2825_CONF_REG_SLP BIT(2) 39 #define SSD2825_CONF_REG_VEN BIT(3) 40 #define SSD2825_CONF_REG_HCLK BIT(4) 41 #define SSD2825_CONF_REG_CSS BIT(5) 42 #define SSD2825_CONF_REG_DCS BIT(6) 43 #define SSD2825_CONF_REG_REN BIT(7) 44 #define SSD2825_CONF_REG_ECD BIT(8) 45 #define SSD2825_CONF_REG_EOT BIT(9) 46 #define SSD2825_CONF_REG_LPE BIT(10) 47 #define SSD2825_VC_CTRL_REG 0xb8 48 #define SSD2825_PLL_CTRL_REG 0xb9 49 #define SSD2825_PLL_CONFIGURATION_REG 0xba 50 #define SSD2825_CLOCK_CTRL_REG 0xbb 51 #define SSD2825_PACKET_SIZE_CTRL_REG_1 0xbc 52 #define SSD2825_PACKET_SIZE_CTRL_REG_2 0xbd 53 #define SSD2825_PACKET_SIZE_CTRL_REG_3 0xbe 54 #define SSD2825_PACKET_DROP_REG 0xbf 55 #define SSD2825_OPERATION_CTRL_REG 0xc0 56 #define SSD2825_MAX_RETURN_SIZE_REG 0xc1 57 #define SSD2825_RETURN_DATA_COUNT_REG 0xc2 58 #define SSD2825_ACK_RESPONSE_REG 0xc3 59 #define SSD2825_LINE_CTRL_REG 0xc4 60 #define SSD2825_INTERRUPT_CTRL_REG 0xc5 61 #define SSD2825_INTERRUPT_STATUS_REG 0xc6 62 #define SSD2825_ERROR_STATUS_REG 0xc7 63 #define SSD2825_DATA_FORMAT_REG 0xc8 64 #define SSD2825_DELAY_ADJ_REG_1 0xc9 65 #define SSD2825_DELAY_ADJ_REG_2 0xca 66 #define SSD2825_DELAY_ADJ_REG_3 0xcb 67 #define SSD2825_DELAY_ADJ_REG_4 0xcc 68 #define SSD2825_DELAY_ADJ_REG_5 0xcd 69 #define SSD2825_DELAY_ADJ_REG_6 0xce 70 #define SSD2825_HS_TX_TIMER_REG_1 0xcf 71 #define SSD2825_HS_TX_TIMER_REG_2 0xd0 72 #define SSD2825_LP_RX_TIMER_REG_1 0xd1 73 #define SSD2825_LP_RX_TIMER_REG_2 0xd2 74 #define SSD2825_TE_STATUS_REG 0xd3 75 #define SSD2825_SPI_READ_REG 0xd4 76 #define SSD2825_SPI_READ_REG_RESET 0xfa 77 #define SSD2825_PLL_LOCK_REG 0xd5 78 #define SSD2825_TEST_REG 0xd6 79 #define SSD2825_TE_COUNT_REG 0xd7 80 #define SSD2825_ANALOG_CTRL_REG_1 0xd8 81 #define SSD2825_ANALOG_CTRL_REG_2 0xd9 82 #define SSD2825_ANALOG_CTRL_REG_3 0xda 83 #define SSD2825_ANALOG_CTRL_REG_4 0xdb 84 #define SSD2825_INTERRUPT_OUT_CTRL_REG 0xdc 85 #define SSD2825_RGB_INTERFACE_CTRL_REG_7 0xdd 86 #define SSD2825_LANE_CONFIGURATION_REG 0xde 87 #define SSD2825_DELAY_ADJ_REG_7 0xdf 88 #define SSD2825_INPUT_PIN_CTRL_REG_1 0xe0 89 #define SSD2825_INPUT_PIN_CTRL_REG_2 0xe1 90 #define SSD2825_BIDIR_PIN_CTRL_REG_1 0xe2 91 #define SSD2825_BIDIR_PIN_CTRL_REG_2 0xe3 92 #define SSD2825_BIDIR_PIN_CTRL_REG_3 0xe4 93 #define SSD2825_BIDIR_PIN_CTRL_REG_4 0xe5 94 #define SSD2825_BIDIR_PIN_CTRL_REG_5 0xe6 95 #define SSD2825_BIDIR_PIN_CTRL_REG_6 0xe7 96 #define SSD2825_BIDIR_PIN_CTRL_REG_7 0xe8 97 #define SSD2825_CABC_BRIGHTNESS_CTRL_REG_1 0xe9 98 #define SSD2825_CABC_BRIGHTNESS_CTRL_REG_2 0xea 99 #define SSD2825_CABC_BRIGHTNESS_STATUS_REG 0xeb 100 #define SSD2825_READ_REG 0xff 101 102 #define SSD2825_COM_BYTE 0x00 103 #define SSD2825_DAT_BYTE 0x01 104 105 #define SSD2828_LP_CLOCK_DIVIDER(n) (((n) - 1) & 0x3f) 106 #define SSD2825_LP_MIN_CLK 5000 /* KHz */ 107 #define SSD2825_REF_MIN_CLK 2000 /* KHz */ 108 109 static const struct regulator_bulk_data ssd2825_supplies[] = { 110 { .supply = "dvdd" }, 111 { .supply = "avdd" }, 112 { .supply = "vddio" }, 113 }; 114 115 struct ssd2825_dsi_output { 116 struct mipi_dsi_device *dev; 117 struct drm_panel *panel; 118 struct drm_bridge *bridge; 119 }; 120 121 struct ssd2825_priv { 122 struct spi_device *spi; 123 struct device *dev; 124 125 struct gpio_desc *reset_gpio; 126 struct regulator_bulk_data *supplies; 127 128 struct clk *tx_clk; 129 130 struct mipi_dsi_host dsi_host; 131 struct drm_bridge bridge; 132 struct ssd2825_dsi_output output; 133 134 struct mutex mlock; /* for host transfer operations */ 135 136 u32 pd_lines; /* number of Parallel Port Input Data Lines */ 137 u32 dsi_lanes; /* number of DSI Lanes */ 138 139 /* Parameters for PLL programming */ 140 u32 pll_freq_kbps; /* PLL in kbps */ 141 u32 nibble_freq_khz; /* PLL div by 4 */ 142 143 u32 hzd; /* HS Zero Delay in ns*/ 144 u32 hpd; /* HS Prepare Delay is ns */ 145 }; 146 147 static inline struct ssd2825_priv *dsi_host_to_ssd2825(struct mipi_dsi_host *host) 148 { 149 return container_of(host, struct ssd2825_priv, dsi_host); 150 } 151 152 static inline struct ssd2825_priv *bridge_to_ssd2825(struct drm_bridge *bridge) 153 { 154 return container_of(bridge, struct ssd2825_priv, bridge); 155 } 156 157 static int ssd2825_write_raw(struct ssd2825_priv *priv, u8 high_byte, u8 low_byte) 158 { 159 struct spi_device *spi = priv->spi; 160 u8 tx_buf[2]; 161 162 /* 163 * Low byte is the value, high byte defines type of 164 * write cycle, 0 for command and 1 for data. 165 */ 166 tx_buf[0] = low_byte; 167 tx_buf[1] = high_byte; 168 169 return spi_write(spi, tx_buf, 2); 170 } 171 172 static int ssd2825_write_reg(struct ssd2825_priv *priv, u8 reg, u16 command) 173 { 174 u8 datal = (command & 0x00FF); 175 u8 datah = (command & 0xFF00) >> 8; 176 int ret; 177 178 /* Command write cycle */ 179 ret = ssd2825_write_raw(priv, SSD2825_COM_BYTE, reg); 180 if (ret) 181 return ret; 182 183 /* Data write cycle bits 7-0 */ 184 ret = ssd2825_write_raw(priv, SSD2825_DAT_BYTE, datal); 185 if (ret) 186 return ret; 187 188 /* Data write cycle bits 15-8 */ 189 ret = ssd2825_write_raw(priv, SSD2825_DAT_BYTE, datah); 190 if (ret) 191 return ret; 192 193 return 0; 194 } 195 196 static int ssd2825_write_dsi(struct ssd2825_priv *priv, const u8 *command, int len) 197 { 198 int ret, i; 199 200 ret = ssd2825_write_reg(priv, SSD2825_PACKET_SIZE_CTRL_REG_1, len); 201 if (ret) 202 return ret; 203 204 ret = ssd2825_write_raw(priv, SSD2825_COM_BYTE, SSD2825_PACKET_DROP_REG); 205 if (ret) 206 return ret; 207 208 for (i = 0; i < len; i++) { 209 ret = ssd2825_write_raw(priv, SSD2825_DAT_BYTE, command[i]); 210 if (ret) 211 return ret; 212 } 213 214 return 0; 215 } 216 217 static int ssd2825_read_raw(struct ssd2825_priv *priv, u8 cmd, u16 *data) 218 { 219 struct spi_device *spi = priv->spi; 220 struct spi_message msg; 221 struct spi_transfer xfer[2]; 222 u8 tx_buf[2]; 223 u8 rx_buf[2]; 224 int ret; 225 226 memset(&xfer, 0, sizeof(xfer)); 227 228 tx_buf[1] = (cmd & 0xFF00) >> 8; 229 tx_buf[0] = (cmd & 0x00FF); 230 231 xfer[0].tx_buf = tx_buf; 232 xfer[0].bits_per_word = 9; 233 xfer[0].len = 2; 234 235 xfer[1].rx_buf = rx_buf; 236 xfer[1].bits_per_word = 16; 237 xfer[1].len = 2; 238 239 spi_message_init(&msg); 240 spi_message_add_tail(&xfer[0], &msg); 241 spi_message_add_tail(&xfer[1], &msg); 242 243 ret = spi_sync(spi, &msg); 244 if (ret) { 245 dev_err(&spi->dev, "ssd2825 read raw failed %d\n", ret); 246 return ret; 247 } 248 249 *data = rx_buf[1] | (rx_buf[0] << 8); 250 251 return 0; 252 } 253 254 static int ssd2825_read_reg(struct ssd2825_priv *priv, u8 reg, u16 *data) 255 { 256 int ret; 257 258 /* Reset the read register */ 259 ret = ssd2825_write_reg(priv, SSD2825_SPI_READ_REG, SSD2825_SPI_READ_REG_RESET); 260 if (ret) 261 return ret; 262 263 /* Push the address to read */ 264 ret = ssd2825_write_raw(priv, SSD2825_COM_BYTE, reg); 265 if (ret) 266 return ret; 267 268 /* Perform a reading cycle */ 269 ret = ssd2825_read_raw(priv, SSD2825_SPI_READ_REG_RESET, data); 270 if (ret) 271 return ret; 272 273 return 0; 274 } 275 276 static int ssd2825_dsi_host_attach(struct mipi_dsi_host *host, struct mipi_dsi_device *dev) 277 { 278 struct ssd2825_priv *priv = dsi_host_to_ssd2825(host); 279 struct drm_bridge *bridge; 280 struct drm_panel *panel; 281 struct device_node *ep; 282 int ret; 283 284 if (dev->lanes > 4) { 285 dev_err(priv->dev, "unsupported number of data lanes(%u)\n", dev->lanes); 286 return -EINVAL; 287 } 288 289 /* 290 * ssd2825 supports both Video and Pulse mode, but the driver only 291 * implements Video (event) mode currently 292 */ 293 if (!(dev->mode_flags & MIPI_DSI_MODE_VIDEO)) { 294 dev_err(priv->dev, "Only MIPI_DSI_MODE_VIDEO is supported\n"); 295 return -EOPNOTSUPP; 296 } 297 298 ret = drm_of_find_panel_or_bridge(host->dev->of_node, 1, 0, &panel, &bridge); 299 if (ret) 300 return ret; 301 302 if (panel) { 303 bridge = drm_panel_bridge_add_typed(panel, DRM_MODE_CONNECTOR_DSI); 304 if (IS_ERR(bridge)) 305 return PTR_ERR(bridge); 306 } 307 308 priv->output.dev = dev; 309 priv->output.bridge = bridge; 310 priv->output.panel = panel; 311 312 priv->dsi_lanes = dev->lanes; 313 314 /* get input ep (port0/endpoint0) */ 315 ret = -EINVAL; 316 ep = of_graph_get_endpoint_by_regs(host->dev->of_node, 0, 0); 317 if (ep) { 318 ret = of_property_read_u32(ep, "bus-width", &priv->pd_lines); 319 of_node_put(ep); 320 } 321 322 if (ret) 323 priv->pd_lines = mipi_dsi_pixel_format_to_bpp(dev->format); 324 325 drm_bridge_add(&priv->bridge); 326 327 return 0; 328 } 329 330 static int ssd2825_dsi_host_detach(struct mipi_dsi_host *host, struct mipi_dsi_device *dev) 331 { 332 struct ssd2825_priv *priv = dsi_host_to_ssd2825(host); 333 334 drm_bridge_remove(&priv->bridge); 335 if (priv->output.panel) 336 drm_panel_bridge_remove(priv->output.bridge); 337 338 return 0; 339 } 340 341 static ssize_t ssd2825_dsi_host_transfer(struct mipi_dsi_host *host, 342 const struct mipi_dsi_msg *msg) 343 { 344 struct ssd2825_priv *priv = dsi_host_to_ssd2825(host); 345 u16 config; 346 int ret; 347 348 if (msg->rx_len) { 349 dev_warn(priv->dev, "MIPI rx is not supported\n"); 350 return -EOPNOTSUPP; 351 } 352 353 guard(mutex)(&priv->mlock); 354 355 ret = ssd2825_read_reg(priv, SSD2825_CONFIGURATION_REG, &config); 356 if (ret) 357 return ret; 358 359 switch (msg->type) { 360 case MIPI_DSI_DCS_SHORT_WRITE: 361 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 362 case MIPI_DSI_DCS_LONG_WRITE: 363 config |= SSD2825_CONF_REG_DCS; 364 break; 365 case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: 366 case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: 367 case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: 368 case MIPI_DSI_GENERIC_LONG_WRITE: 369 config &= ~SSD2825_CONF_REG_DCS; 370 break; 371 case MIPI_DSI_DCS_READ: 372 case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: 373 case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: 374 case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: 375 default: 376 return 0; 377 } 378 379 ret = ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG, config); 380 if (ret) 381 return ret; 382 383 ret = ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0x0000); 384 if (ret) 385 return ret; 386 387 ret = ssd2825_write_dsi(priv, msg->tx_buf, msg->tx_len); 388 if (ret) 389 return ret; 390 391 return 0; 392 } 393 394 static const struct mipi_dsi_host_ops ssd2825_dsi_host_ops = { 395 .attach = ssd2825_dsi_host_attach, 396 .detach = ssd2825_dsi_host_detach, 397 .transfer = ssd2825_dsi_host_transfer, 398 }; 399 400 static void ssd2825_hw_reset(struct ssd2825_priv *priv) 401 { 402 gpiod_set_value_cansleep(priv->reset_gpio, 1); 403 usleep_range(5000, 6000); 404 gpiod_set_value_cansleep(priv->reset_gpio, 0); 405 usleep_range(5000, 6000); 406 } 407 408 /* 409 * PLL configuration register settings. 410 * 411 * See the "PLL Configuration Register Description" in the SSD2825 datasheet. 412 */ 413 static u16 construct_pll_config(struct ssd2825_priv *priv, 414 u32 desired_pll_freq_kbps, u32 reference_freq_khz) 415 { 416 u32 div_factor = 1, mul_factor, fr = 0; 417 418 while (reference_freq_khz / (div_factor + 1) >= SSD2825_REF_MIN_CLK) 419 div_factor++; 420 if (div_factor > 31) 421 div_factor = 31; 422 423 mul_factor = DIV_ROUND_UP(desired_pll_freq_kbps * div_factor, 424 reference_freq_khz); 425 426 priv->pll_freq_kbps = reference_freq_khz * mul_factor / div_factor; 427 priv->nibble_freq_khz = priv->pll_freq_kbps / 4; 428 429 if (priv->pll_freq_kbps >= 501000) 430 fr = 3; 431 else if (priv->pll_freq_kbps >= 251000) 432 fr = 2; 433 else if (priv->pll_freq_kbps >= 126000) 434 fr = 1; 435 436 return (fr << 14) | (div_factor << 8) | mul_factor; 437 } 438 439 static int ssd2825_setup_pll(struct ssd2825_priv *priv, 440 const struct drm_display_mode *mode) 441 { 442 u16 pll_config, lp_div; 443 u32 nibble_delay, pclk_mult, tx_freq_khz; 444 u8 hzd, hpd; 445 446 tx_freq_khz = clk_get_rate(priv->tx_clk) / KILO; 447 if (!tx_freq_khz) 448 tx_freq_khz = SSD2825_REF_MIN_CLK; 449 450 pclk_mult = priv->pd_lines / priv->dsi_lanes + 1; 451 pll_config = construct_pll_config(priv, pclk_mult * mode->clock, 452 tx_freq_khz); 453 454 lp_div = priv->pll_freq_kbps / (SSD2825_LP_MIN_CLK * 8); 455 456 /* nibble_delay in nanoseconds */ 457 nibble_delay = MICRO / priv->nibble_freq_khz; 458 459 hzd = priv->hzd / nibble_delay; 460 hpd = (priv->hpd - 4 * nibble_delay) / nibble_delay; 461 462 /* Disable PLL */ 463 ssd2825_write_reg(priv, SSD2825_PLL_CTRL_REG, 0x0000); 464 ssd2825_write_reg(priv, SSD2825_LINE_CTRL_REG, 0x0001); 465 466 /* Set delays */ 467 ssd2825_write_reg(priv, SSD2825_DELAY_ADJ_REG_1, (hzd << 8) | hpd); 468 469 /* Set PLL coefficients */ 470 ssd2825_write_reg(priv, SSD2825_PLL_CONFIGURATION_REG, pll_config); 471 472 /* Clock Control Register */ 473 ssd2825_write_reg(priv, SSD2825_CLOCK_CTRL_REG, 474 SSD2828_LP_CLOCK_DIVIDER(lp_div)); 475 476 /* Enable PLL */ 477 ssd2825_write_reg(priv, SSD2825_PLL_CTRL_REG, 0x0001); 478 ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0); 479 480 return 0; 481 } 482 483 static void ssd2825_bridge_atomic_pre_enable(struct drm_bridge *bridge, 484 struct drm_atomic_commit *state) 485 { 486 struct ssd2825_priv *priv = bridge_to_ssd2825(bridge); 487 struct mipi_dsi_device *dsi_dev = priv->output.dev; 488 const struct drm_crtc_state *crtc_state; 489 const struct drm_display_mode *mode; 490 struct drm_connector *connector; 491 struct drm_crtc *crtc; 492 u32 input_bus_flags = bridge->timings->input_bus_flags; 493 u16 flags = 0, config; 494 u8 pixel_format; 495 int ret; 496 497 /* Power Sequence */ 498 ret = clk_prepare_enable(priv->tx_clk); 499 if (ret) 500 dev_err(priv->dev, "error enabling tx_clk (%d)\n", ret); 501 502 ret = regulator_bulk_enable(ARRAY_SIZE(ssd2825_supplies), priv->supplies); 503 if (ret) 504 dev_err(priv->dev, "error enabling regulators (%d)\n", ret); 505 506 usleep_range(1000, 2000); 507 508 ssd2825_hw_reset(priv); 509 510 /* Perform SW reset */ 511 ssd2825_write_reg(priv, SSD2825_OPERATION_CTRL_REG, 0x0100); 512 513 /* Set pixel format */ 514 switch (dsi_dev->format) { 515 case MIPI_DSI_FMT_RGB565: 516 pixel_format = 0x00; 517 break; 518 case MIPI_DSI_FMT_RGB666_PACKED: 519 pixel_format = 0x01; 520 break; 521 case MIPI_DSI_FMT_RGB666: 522 pixel_format = 0x02; 523 break; 524 case MIPI_DSI_FMT_RGB888: 525 default: 526 pixel_format = 0x03; 527 break; 528 } 529 530 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 531 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 532 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 533 mode = &crtc_state->adjusted_mode; 534 535 /* Set panel timings */ 536 ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_1, 537 ((mode->vtotal - mode->vsync_end) << 8) | 538 (mode->htotal - mode->hsync_end)); 539 ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_2, 540 ((mode->vtotal - mode->vsync_start) << 8) | 541 (mode->htotal - mode->hsync_start)); 542 ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_3, 543 ((mode->vsync_start - mode->vdisplay) << 8) | 544 (mode->hsync_start - mode->hdisplay)); 545 ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_4, mode->hdisplay); 546 ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_5, mode->vdisplay); 547 548 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 549 flags |= SSD2825_HSYNC_HIGH; 550 551 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 552 flags |= SSD2825_VSYNC_HIGH; 553 554 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO) 555 flags |= SSD2825_NON_BURST_EV; 556 557 if (input_bus_flags & DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE) 558 flags |= SSD2825_PCKL_HIGH; 559 560 ssd2825_write_reg(priv, SSD2825_RGB_INTERFACE_CTRL_REG_6, flags | pixel_format); 561 ssd2825_write_reg(priv, SSD2825_LANE_CONFIGURATION_REG, dsi_dev->lanes - 1); 562 ssd2825_write_reg(priv, SSD2825_TEST_REG, 0x0004); 563 564 /* Call PLL configuration */ 565 ssd2825_setup_pll(priv, mode); 566 567 usleep_range(10000, 11000); 568 569 config = SSD2825_CONF_REG_HS | SSD2825_CONF_REG_CKE | SSD2825_CONF_REG_DCS | 570 SSD2825_CONF_REG_ECD | SSD2825_CONF_REG_EOT; 571 572 if (dsi_dev->mode_flags & MIPI_DSI_MODE_LPM) 573 config &= ~SSD2825_CONF_REG_HS; 574 575 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 576 config &= ~SSD2825_CONF_REG_EOT; 577 578 /* Initial DSI configuration register set */ 579 ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG, config); 580 ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0); 581 582 if (priv->output.panel) 583 drm_panel_enable(priv->output.panel); 584 } 585 586 static void ssd2825_bridge_atomic_enable(struct drm_bridge *bridge, 587 struct drm_atomic_commit *state) 588 { 589 struct ssd2825_priv *priv = bridge_to_ssd2825(bridge); 590 struct mipi_dsi_device *dsi_dev = priv->output.dev; 591 u16 config; 592 593 config = SSD2825_CONF_REG_HS | SSD2825_CONF_REG_DCS | 594 SSD2825_CONF_REG_ECD | SSD2825_CONF_REG_EOT; 595 596 if (dsi_dev->mode_flags & MIPI_DSI_MODE_VIDEO) 597 config |= SSD2825_CONF_REG_VEN; 598 599 if (dsi_dev->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 600 config &= ~SSD2825_CONF_REG_EOT; 601 602 /* Complete configuration after DSI commands were sent */ 603 ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG, config); 604 ssd2825_write_reg(priv, SSD2825_PLL_CTRL_REG, 0x0001); 605 ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0x0000); 606 } 607 608 static void ssd2825_bridge_atomic_disable(struct drm_bridge *bridge, 609 struct drm_atomic_commit *state) 610 { 611 struct ssd2825_priv *priv = bridge_to_ssd2825(bridge); 612 int ret; 613 614 msleep(100); 615 616 /* Exit DSI configuration register set */ 617 ssd2825_write_reg(priv, SSD2825_CONFIGURATION_REG, 618 SSD2825_CONF_REG_ECD | SSD2825_CONF_REG_EOT); 619 ssd2825_write_reg(priv, SSD2825_VC_CTRL_REG, 0); 620 621 /* HW disable */ 622 gpiod_set_value_cansleep(priv->reset_gpio, 1); 623 usleep_range(5000, 6000); 624 625 ret = regulator_bulk_disable(ARRAY_SIZE(ssd2825_supplies), 626 priv->supplies); 627 if (ret < 0) 628 dev_err(priv->dev, "error disabling regulators (%d)\n", ret); 629 630 clk_disable_unprepare(priv->tx_clk); 631 } 632 633 static int ssd2825_bridge_attach(struct drm_bridge *bridge, struct drm_encoder *encoder, 634 enum drm_bridge_attach_flags flags) 635 { 636 struct ssd2825_priv *priv = bridge_to_ssd2825(bridge); 637 638 return drm_bridge_attach(bridge->encoder, priv->output.bridge, bridge, 639 flags); 640 } 641 642 static enum drm_mode_status 643 ssd2825_bridge_mode_valid(struct drm_bridge *bridge, 644 const struct drm_display_info *info, 645 const struct drm_display_mode *mode) 646 { 647 if (mode->hdisplay > 1366) 648 return MODE_H_ILLEGAL; 649 650 if (mode->vdisplay > 1366) 651 return MODE_V_ILLEGAL; 652 653 return MODE_OK; 654 } 655 656 static bool ssd2825_mode_fixup(struct drm_bridge *bridge, 657 const struct drm_display_mode *mode, 658 struct drm_display_mode *adjusted_mode) 659 { 660 /* Default to positive sync */ 661 662 if (!(adjusted_mode->flags & 663 (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_NHSYNC))) 664 adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC; 665 666 if (!(adjusted_mode->flags & 667 (DRM_MODE_FLAG_PVSYNC | DRM_MODE_FLAG_NVSYNC))) 668 adjusted_mode->flags |= DRM_MODE_FLAG_PVSYNC; 669 670 return true; 671 } 672 673 static const struct drm_bridge_funcs ssd2825_bridge_funcs = { 674 .attach = ssd2825_bridge_attach, 675 .mode_valid = ssd2825_bridge_mode_valid, 676 .mode_fixup = ssd2825_mode_fixup, 677 678 .atomic_pre_enable = ssd2825_bridge_atomic_pre_enable, 679 .atomic_enable = ssd2825_bridge_atomic_enable, 680 .atomic_disable = ssd2825_bridge_atomic_disable, 681 682 .atomic_reset = drm_atomic_helper_bridge_reset, 683 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 684 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 685 }; 686 687 static const struct drm_bridge_timings default_ssd2825_timings = { 688 .input_bus_flags = DRM_BUS_FLAG_PIXDATA_SAMPLE_POSEDGE 689 | DRM_BUS_FLAG_SYNC_SAMPLE_NEGEDGE 690 | DRM_BUS_FLAG_DE_HIGH, 691 }; 692 693 static int ssd2825_probe(struct spi_device *spi) 694 { 695 struct ssd2825_priv *priv; 696 struct device *dev = &spi->dev; 697 struct device_node *np = dev->of_node; 698 int ret; 699 700 /* Driver supports only 8 bit 3 Wire mode */ 701 spi->bits_per_word = 9; 702 703 ret = spi_setup(spi); 704 if (ret) 705 return ret; 706 707 priv = devm_drm_bridge_alloc(dev, struct ssd2825_priv, bridge, &ssd2825_bridge_funcs); 708 if (IS_ERR(priv)) 709 return PTR_ERR(priv); 710 711 spi_set_drvdata(spi, priv); 712 713 priv->spi = spi; 714 priv->dev = dev; 715 716 mutex_init(&priv->mlock); 717 718 priv->tx_clk = devm_clk_get_optional(dev, NULL); 719 if (IS_ERR(priv->tx_clk)) 720 return dev_err_probe(dev, PTR_ERR(priv->tx_clk), 721 "can't retrieve bridge tx_clk\n"); 722 723 priv->reset_gpio = devm_gpiod_get_optional(dev, "reset", 724 GPIOD_OUT_HIGH); 725 if (IS_ERR(priv->reset_gpio)) 726 return dev_err_probe(dev, PTR_ERR(priv->reset_gpio), 727 "failed to get reset GPIO\n"); 728 729 ret = devm_regulator_bulk_get_const(dev, ARRAY_SIZE(ssd2825_supplies), 730 ssd2825_supplies, &priv->supplies); 731 if (ret) 732 return dev_err_probe(dev, ret, "failed to get regulators\n"); 733 734 priv->hzd = 133; /* ns */ 735 device_property_read_u32(dev, "solomon,hs-zero-delay-ns", &priv->hzd); 736 737 priv->hpd = 40; /* ns */ 738 device_property_read_u32(dev, "solomon,hs-prep-delay-ns", &priv->hpd); 739 740 priv->dsi_host.dev = dev; 741 priv->dsi_host.ops = &ssd2825_dsi_host_ops; 742 743 priv->bridge.timings = &default_ssd2825_timings; 744 priv->bridge.of_node = np; 745 746 return mipi_dsi_host_register(&priv->dsi_host); 747 } 748 749 static void ssd2825_remove(struct spi_device *spi) 750 { 751 struct ssd2825_priv *priv = spi_get_drvdata(spi); 752 753 mipi_dsi_host_unregister(&priv->dsi_host); 754 } 755 756 static const struct of_device_id ssd2825_of_match[] = { 757 { .compatible = "solomon,ssd2825" }, 758 { /* sentinel */ } 759 }; 760 MODULE_DEVICE_TABLE(of, ssd2825_of_match); 761 762 static struct spi_driver ssd2825_driver = { 763 .driver = { 764 .name = "ssd2825", 765 .of_match_table = ssd2825_of_match, 766 }, 767 .probe = ssd2825_probe, 768 .remove = ssd2825_remove, 769 }; 770 module_spi_driver(ssd2825_driver); 771 772 MODULE_AUTHOR("Svyatoslav Ryhel <clamor95@gmail.com>"); 773 MODULE_DESCRIPTION("Solomon SSD2825 RGB to MIPI-DSI bridge driver SPI"); 774 MODULE_LICENSE("GPL"); 775