1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Silicon Image SiI8620 HDMI/MHL bridge driver 4 * 5 * Copyright (C) 2015, Samsung Electronics Co., Ltd. 6 * Andrzej Hajda <a.hajda@samsung.com> 7 */ 8 9 #include <linux/unaligned.h> 10 11 #include <drm/bridge/mhl.h> 12 #include <drm/drm_atomic_state_helper.h> 13 #include <drm/drm_bridge.h> 14 #include <drm/drm_crtc.h> 15 #include <drm/drm_edid.h> 16 #include <drm/drm_encoder.h> 17 18 #include <linux/clk.h> 19 #include <linux/delay.h> 20 #include <linux/extcon.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/i2c.h> 23 #include <linux/interrupt.h> 24 #include <linux/irq.h> 25 #include <linux/kernel.h> 26 #include <linux/list.h> 27 #include <linux/module.h> 28 #include <linux/mutex.h> 29 #include <linux/of_graph.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/slab.h> 32 33 #include <media/rc-core.h> 34 35 #include "sil-sii8620.h" 36 37 #define SII8620_BURST_BUF_LEN 288 38 #define VAL_RX_HDMI_CTRL2_DEFVAL VAL_RX_HDMI_CTRL2_IDLE_CNT(3) 39 40 #define MHL1_MAX_PCLK 75000 41 #define MHL1_MAX_PCLK_PP_MODE 150000 42 #define MHL3_MAX_PCLK 200000 43 #define MHL3_MAX_PCLK_PP_MODE 300000 44 45 enum sii8620_mode { 46 CM_DISCONNECTED, 47 CM_DISCOVERY, 48 CM_MHL1, 49 CM_MHL3, 50 CM_ECBUS_S 51 }; 52 53 enum sii8620_sink_type { 54 SINK_NONE, 55 SINK_HDMI, 56 SINK_DVI 57 }; 58 59 enum sii8620_mt_state { 60 MT_STATE_READY, 61 MT_STATE_BUSY, 62 MT_STATE_DONE 63 }; 64 65 struct sii8620 { 66 struct drm_bridge bridge; 67 struct device *dev; 68 struct rc_dev *rc_dev; 69 struct clk *clk_xtal; 70 struct gpio_desc *gpio_reset; 71 struct gpio_desc *gpio_int; 72 struct regulator_bulk_data supplies[2]; 73 struct mutex lock; /* context lock, protects fields below */ 74 int error; 75 unsigned int use_packed_pixel:1; 76 enum sii8620_mode mode; 77 enum sii8620_sink_type sink_type; 78 u8 cbus_status; 79 u8 stat[MHL_DST_SIZE]; 80 u8 xstat[MHL_XDS_SIZE]; 81 u8 devcap[MHL_DCAP_SIZE]; 82 u8 xdevcap[MHL_XDC_SIZE]; 83 bool feature_complete; 84 bool devcap_read; 85 bool sink_detected; 86 struct edid *edid; 87 unsigned int gen2_write_burst:1; 88 enum sii8620_mt_state mt_state; 89 struct extcon_dev *extcon; 90 struct notifier_block extcon_nb; 91 struct work_struct extcon_wq; 92 int cable_state; 93 struct list_head mt_queue; 94 struct { 95 int r_size; 96 int r_count; 97 int rx_ack; 98 int rx_count; 99 u8 rx_buf[32]; 100 int tx_count; 101 u8 tx_buf[32]; 102 } burst; 103 }; 104 105 struct sii8620_mt_msg; 106 107 typedef void (*sii8620_mt_msg_cb)(struct sii8620 *ctx, 108 struct sii8620_mt_msg *msg); 109 110 typedef void (*sii8620_cb)(struct sii8620 *ctx, int ret); 111 112 struct sii8620_mt_msg { 113 struct list_head node; 114 u8 reg[4]; 115 u8 ret; 116 sii8620_mt_msg_cb send; 117 sii8620_mt_msg_cb recv; 118 sii8620_cb continuation; 119 }; 120 121 static const u8 sii8620_i2c_page[] = { 122 0x39, /* Main System */ 123 0x3d, /* TDM and HSIC */ 124 0x49, /* TMDS Receiver, MHL EDID */ 125 0x4d, /* eMSC, HDCP, HSIC */ 126 0x5d, /* MHL Spec */ 127 0x64, /* MHL CBUS */ 128 0x59, /* Hardware TPI (Transmitter Programming Interface) */ 129 0x61, /* eCBUS-S, eCBUS-D */ 130 }; 131 132 static void sii8620_fetch_edid(struct sii8620 *ctx); 133 static void sii8620_set_upstream_edid(struct sii8620 *ctx); 134 static void sii8620_enable_hpd(struct sii8620 *ctx); 135 static void sii8620_mhl_disconnected(struct sii8620 *ctx); 136 static void sii8620_disconnect(struct sii8620 *ctx); 137 138 static int sii8620_clear_error(struct sii8620 *ctx) 139 { 140 int ret = ctx->error; 141 142 ctx->error = 0; 143 return ret; 144 } 145 146 static void sii8620_read_buf(struct sii8620 *ctx, u16 addr, u8 *buf, int len) 147 { 148 struct device *dev = ctx->dev; 149 struct i2c_client *client = to_i2c_client(dev); 150 u8 data = addr; 151 struct i2c_msg msg[] = { 152 { 153 .addr = sii8620_i2c_page[addr >> 8], 154 .flags = client->flags, 155 .len = 1, 156 .buf = &data 157 }, 158 { 159 .addr = sii8620_i2c_page[addr >> 8], 160 .flags = client->flags | I2C_M_RD, 161 .len = len, 162 .buf = buf 163 }, 164 }; 165 int ret; 166 167 if (ctx->error) 168 return; 169 170 ret = i2c_transfer(client->adapter, msg, 2); 171 dev_dbg(dev, "read at %04x: %*ph, %d\n", addr, len, buf, ret); 172 173 if (ret != 2) { 174 dev_err(dev, "Read at %#06x of %d bytes failed with code %d.\n", 175 addr, len, ret); 176 ctx->error = ret < 0 ? ret : -EIO; 177 } 178 } 179 180 static u8 sii8620_readb(struct sii8620 *ctx, u16 addr) 181 { 182 u8 ret = 0; 183 184 sii8620_read_buf(ctx, addr, &ret, 1); 185 return ret; 186 } 187 188 static void sii8620_write_buf(struct sii8620 *ctx, u16 addr, const u8 *buf, 189 int len) 190 { 191 struct device *dev = ctx->dev; 192 struct i2c_client *client = to_i2c_client(dev); 193 u8 data[2]; 194 struct i2c_msg msg = { 195 .addr = sii8620_i2c_page[addr >> 8], 196 .flags = client->flags, 197 .len = len + 1, 198 }; 199 int ret; 200 201 if (ctx->error) 202 return; 203 204 if (len > 1) { 205 msg.buf = kmalloc(len + 1, GFP_KERNEL); 206 if (!msg.buf) { 207 ctx->error = -ENOMEM; 208 return; 209 } 210 memcpy(msg.buf + 1, buf, len); 211 } else { 212 msg.buf = data; 213 msg.buf[1] = *buf; 214 } 215 216 msg.buf[0] = addr; 217 218 ret = i2c_transfer(client->adapter, &msg, 1); 219 dev_dbg(dev, "write at %04x: %*ph, %d\n", addr, len, buf, ret); 220 221 if (ret != 1) { 222 dev_err(dev, "Write at %#06x of %*ph failed with code %d.\n", 223 addr, len, buf, ret); 224 ctx->error = ret ?: -EIO; 225 } 226 227 if (len > 1) 228 kfree(msg.buf); 229 } 230 231 #define sii8620_write(ctx, addr, arr...) \ 232 ({\ 233 u8 d[] = { arr }; \ 234 sii8620_write_buf(ctx, addr, d, ARRAY_SIZE(d)); \ 235 }) 236 237 static void __sii8620_write_seq(struct sii8620 *ctx, const u16 *seq, int len) 238 { 239 int i; 240 241 for (i = 0; i < len; i += 2) 242 sii8620_write(ctx, seq[i], seq[i + 1]); 243 } 244 245 #define sii8620_write_seq(ctx, seq...) \ 246 ({\ 247 const u16 d[] = { seq }; \ 248 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \ 249 }) 250 251 #define sii8620_write_seq_static(ctx, seq...) \ 252 ({\ 253 static const u16 d[] = { seq }; \ 254 __sii8620_write_seq(ctx, d, ARRAY_SIZE(d)); \ 255 }) 256 257 static void sii8620_setbits(struct sii8620 *ctx, u16 addr, u8 mask, u8 val) 258 { 259 val = (val & mask) | (sii8620_readb(ctx, addr) & ~mask); 260 sii8620_write(ctx, addr, val); 261 } 262 263 static inline bool sii8620_is_mhl3(struct sii8620 *ctx) 264 { 265 return ctx->mode >= CM_MHL3; 266 } 267 268 static void sii8620_mt_cleanup(struct sii8620 *ctx) 269 { 270 struct sii8620_mt_msg *msg, *n; 271 272 list_for_each_entry_safe(msg, n, &ctx->mt_queue, node) { 273 list_del(&msg->node); 274 kfree(msg); 275 } 276 ctx->mt_state = MT_STATE_READY; 277 } 278 279 static void sii8620_mt_work(struct sii8620 *ctx) 280 { 281 struct sii8620_mt_msg *msg; 282 283 if (ctx->error) 284 return; 285 if (ctx->mt_state == MT_STATE_BUSY || list_empty(&ctx->mt_queue)) 286 return; 287 288 if (ctx->mt_state == MT_STATE_DONE) { 289 ctx->mt_state = MT_STATE_READY; 290 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, 291 node); 292 list_del(&msg->node); 293 if (msg->recv) 294 msg->recv(ctx, msg); 295 if (msg->continuation) 296 msg->continuation(ctx, msg->ret); 297 kfree(msg); 298 } 299 300 if (ctx->mt_state != MT_STATE_READY || list_empty(&ctx->mt_queue)) 301 return; 302 303 ctx->mt_state = MT_STATE_BUSY; 304 msg = list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 305 if (msg->send) 306 msg->send(ctx, msg); 307 } 308 309 static void sii8620_enable_gen2_write_burst(struct sii8620 *ctx) 310 { 311 u8 ctrl = BIT_MDT_RCV_CTRL_MDT_RCV_EN; 312 313 if (ctx->gen2_write_burst) 314 return; 315 316 if (ctx->mode >= CM_MHL1) 317 ctrl |= BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN; 318 319 sii8620_write_seq(ctx, 320 REG_MDT_RCV_TIMEOUT, 100, 321 REG_MDT_RCV_CTRL, ctrl 322 ); 323 ctx->gen2_write_burst = 1; 324 } 325 326 static void sii8620_disable_gen2_write_burst(struct sii8620 *ctx) 327 { 328 if (!ctx->gen2_write_burst) 329 return; 330 331 sii8620_write_seq_static(ctx, 332 REG_MDT_XMIT_CTRL, 0, 333 REG_MDT_RCV_CTRL, 0 334 ); 335 ctx->gen2_write_burst = 0; 336 } 337 338 static void sii8620_start_gen2_write_burst(struct sii8620 *ctx) 339 { 340 sii8620_write_seq_static(ctx, 341 REG_MDT_INT_1_MASK, BIT_MDT_RCV_TIMEOUT 342 | BIT_MDT_RCV_SM_ABORT_PKT_RCVD | BIT_MDT_RCV_SM_ERROR 343 | BIT_MDT_XMIT_TIMEOUT | BIT_MDT_XMIT_SM_ABORT_PKT_RCVD 344 | BIT_MDT_XMIT_SM_ERROR, 345 REG_MDT_INT_0_MASK, BIT_MDT_XFIFO_EMPTY 346 | BIT_MDT_IDLE_AFTER_HAWB_DISABLE 347 | BIT_MDT_RFIFO_DATA_RDY 348 ); 349 sii8620_enable_gen2_write_burst(ctx); 350 } 351 352 static void sii8620_mt_msc_cmd_send(struct sii8620 *ctx, 353 struct sii8620_mt_msg *msg) 354 { 355 if (msg->reg[0] == MHL_SET_INT && 356 msg->reg[1] == MHL_INT_REG(RCHANGE) && 357 msg->reg[2] == MHL_INT_RC_FEAT_REQ) 358 sii8620_enable_gen2_write_burst(ctx); 359 else 360 sii8620_disable_gen2_write_burst(ctx); 361 362 switch (msg->reg[0]) { 363 case MHL_WRITE_STAT: 364 case MHL_SET_INT: 365 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg + 1, 2); 366 sii8620_write(ctx, REG_MSC_COMMAND_START, 367 BIT_MSC_COMMAND_START_WRITE_STAT); 368 break; 369 case MHL_MSC_MSG: 370 sii8620_write_buf(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg, 3); 371 sii8620_write(ctx, REG_MSC_COMMAND_START, 372 BIT_MSC_COMMAND_START_MSC_MSG); 373 break; 374 case MHL_READ_DEVCAP_REG: 375 case MHL_READ_XDEVCAP_REG: 376 sii8620_write(ctx, REG_MSC_CMD_OR_OFFSET, msg->reg[1]); 377 sii8620_write(ctx, REG_MSC_COMMAND_START, 378 BIT_MSC_COMMAND_START_READ_DEVCAP); 379 break; 380 default: 381 dev_err(ctx->dev, "%s: command %#x not supported\n", __func__, 382 msg->reg[0]); 383 } 384 } 385 386 static struct sii8620_mt_msg *sii8620_mt_msg_new(struct sii8620 *ctx) 387 { 388 struct sii8620_mt_msg *msg = kzalloc_obj(*msg); 389 390 if (!msg) 391 ctx->error = -ENOMEM; 392 else 393 list_add_tail(&msg->node, &ctx->mt_queue); 394 395 return msg; 396 } 397 398 static void sii8620_mt_set_cont(struct sii8620 *ctx, sii8620_cb cont) 399 { 400 struct sii8620_mt_msg *msg; 401 402 if (ctx->error) 403 return; 404 405 if (list_empty(&ctx->mt_queue)) { 406 ctx->error = -EINVAL; 407 return; 408 } 409 msg = list_last_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 410 msg->continuation = cont; 411 } 412 413 static void sii8620_mt_msc_cmd(struct sii8620 *ctx, u8 cmd, u8 arg1, u8 arg2) 414 { 415 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 416 417 if (!msg) 418 return; 419 420 msg->reg[0] = cmd; 421 msg->reg[1] = arg1; 422 msg->reg[2] = arg2; 423 msg->send = sii8620_mt_msc_cmd_send; 424 } 425 426 static void sii8620_mt_write_stat(struct sii8620 *ctx, u8 reg, u8 val) 427 { 428 sii8620_mt_msc_cmd(ctx, MHL_WRITE_STAT, reg, val); 429 } 430 431 static inline void sii8620_mt_set_int(struct sii8620 *ctx, u8 irq, u8 mask) 432 { 433 sii8620_mt_msc_cmd(ctx, MHL_SET_INT, irq, mask); 434 } 435 436 static void sii8620_mt_msc_msg(struct sii8620 *ctx, u8 cmd, u8 data) 437 { 438 sii8620_mt_msc_cmd(ctx, MHL_MSC_MSG, cmd, data); 439 } 440 441 static void sii8620_mt_rap(struct sii8620 *ctx, u8 code) 442 { 443 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RAP, code); 444 } 445 446 static void sii8620_mt_rcpk(struct sii8620 *ctx, u8 code) 447 { 448 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPK, code); 449 } 450 451 static void sii8620_mt_rcpe(struct sii8620 *ctx, u8 code) 452 { 453 sii8620_mt_msc_msg(ctx, MHL_MSC_MSG_RCPE, code); 454 } 455 456 static void sii8620_mt_read_devcap_send(struct sii8620 *ctx, 457 struct sii8620_mt_msg *msg) 458 { 459 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP 460 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 461 | BIT_EDID_CTRL_EDID_MODE_EN; 462 463 if (msg->reg[0] == MHL_READ_XDEVCAP) 464 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN; 465 466 sii8620_write_seq(ctx, 467 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE, 468 REG_EDID_CTRL, ctrl, 469 REG_TPI_CBUS_START, BIT_TPI_CBUS_START_GET_DEVCAP_START 470 ); 471 } 472 473 /* copy src to dst and set changed bits in src */ 474 static void sii8620_update_array(u8 *dst, u8 *src, int count) 475 { 476 while (--count >= 0) { 477 *src ^= *dst; 478 *dst++ ^= *src++; 479 } 480 } 481 482 static void sii8620_identify_sink(struct sii8620 *ctx) 483 { 484 static const char * const sink_str[] = { 485 [SINK_NONE] = "NONE", 486 [SINK_HDMI] = "HDMI", 487 [SINK_DVI] = "DVI" 488 }; 489 490 char sink_name[20]; 491 struct device *dev = ctx->dev; 492 493 if (!ctx->sink_detected || !ctx->devcap_read) 494 return; 495 496 sii8620_fetch_edid(ctx); 497 if (!ctx->edid) { 498 dev_err(ctx->dev, "Cannot fetch EDID\n"); 499 sii8620_mhl_disconnected(ctx); 500 return; 501 } 502 sii8620_set_upstream_edid(ctx); 503 504 if (drm_detect_hdmi_monitor(ctx->edid)) 505 ctx->sink_type = SINK_HDMI; 506 else 507 ctx->sink_type = SINK_DVI; 508 509 drm_edid_get_monitor_name(ctx->edid, sink_name, ARRAY_SIZE(sink_name)); 510 511 dev_info(dev, "detected sink(type: %s): %s\n", 512 sink_str[ctx->sink_type], sink_name); 513 } 514 515 static void sii8620_mr_devcap(struct sii8620 *ctx) 516 { 517 u8 dcap[MHL_DCAP_SIZE]; 518 struct device *dev = ctx->dev; 519 520 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, dcap, MHL_DCAP_SIZE); 521 if (ctx->error < 0) 522 return; 523 524 dev_info(dev, "detected dongle MHL %d.%d, ChipID %02x%02x:%02x%02x\n", 525 dcap[MHL_DCAP_MHL_VERSION] / 16, 526 dcap[MHL_DCAP_MHL_VERSION] % 16, 527 dcap[MHL_DCAP_ADOPTER_ID_H], dcap[MHL_DCAP_ADOPTER_ID_L], 528 dcap[MHL_DCAP_DEVICE_ID_H], dcap[MHL_DCAP_DEVICE_ID_L]); 529 sii8620_update_array(ctx->devcap, dcap, MHL_DCAP_SIZE); 530 ctx->devcap_read = true; 531 sii8620_identify_sink(ctx); 532 } 533 534 static void sii8620_mr_xdevcap(struct sii8620 *ctx) 535 { 536 sii8620_read_buf(ctx, REG_EDID_FIFO_RD_DATA, ctx->xdevcap, 537 MHL_XDC_SIZE); 538 } 539 540 static void sii8620_mt_read_devcap_recv(struct sii8620 *ctx, 541 struct sii8620_mt_msg *msg) 542 { 543 u8 ctrl = BIT_EDID_CTRL_DEVCAP_SELECT_DEVCAP 544 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 545 | BIT_EDID_CTRL_EDID_MODE_EN; 546 547 if (msg->reg[0] == MHL_READ_XDEVCAP) 548 ctrl |= BIT_EDID_CTRL_XDEVCAP_EN; 549 550 sii8620_write_seq(ctx, 551 REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE | BIT_INTR9_EDID_DONE 552 | BIT_INTR9_EDID_ERROR, 553 REG_EDID_CTRL, ctrl, 554 REG_EDID_FIFO_ADDR, 0 555 ); 556 557 if (msg->reg[0] == MHL_READ_XDEVCAP) 558 sii8620_mr_xdevcap(ctx); 559 else 560 sii8620_mr_devcap(ctx); 561 } 562 563 static void sii8620_mt_read_devcap(struct sii8620 *ctx, bool xdevcap) 564 { 565 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 566 567 if (!msg) 568 return; 569 570 msg->reg[0] = xdevcap ? MHL_READ_XDEVCAP : MHL_READ_DEVCAP; 571 msg->send = sii8620_mt_read_devcap_send; 572 msg->recv = sii8620_mt_read_devcap_recv; 573 } 574 575 static void sii8620_mt_read_devcap_reg_recv(struct sii8620 *ctx, 576 struct sii8620_mt_msg *msg) 577 { 578 u8 reg = msg->reg[1] & 0x7f; 579 580 if (msg->reg[1] & 0x80) 581 ctx->xdevcap[reg] = msg->ret; 582 else 583 ctx->devcap[reg] = msg->ret; 584 } 585 586 static void sii8620_mt_read_devcap_reg(struct sii8620 *ctx, u8 reg) 587 { 588 struct sii8620_mt_msg *msg = sii8620_mt_msg_new(ctx); 589 590 if (!msg) 591 return; 592 593 msg->reg[0] = (reg & 0x80) ? MHL_READ_XDEVCAP_REG : MHL_READ_DEVCAP_REG; 594 msg->reg[1] = reg; 595 msg->send = sii8620_mt_msc_cmd_send; 596 msg->recv = sii8620_mt_read_devcap_reg_recv; 597 } 598 599 static inline void sii8620_mt_read_xdevcap_reg(struct sii8620 *ctx, u8 reg) 600 { 601 sii8620_mt_read_devcap_reg(ctx, reg | 0x80); 602 } 603 604 static void *sii8620_burst_get_tx_buf(struct sii8620 *ctx, int len) 605 { 606 u8 *buf = &ctx->burst.tx_buf[ctx->burst.tx_count]; 607 int size = len + 2; 608 609 if (ctx->burst.tx_count + size >= ARRAY_SIZE(ctx->burst.tx_buf)) { 610 dev_err(ctx->dev, "TX-BLK buffer exhausted\n"); 611 ctx->error = -EINVAL; 612 return NULL; 613 } 614 615 ctx->burst.tx_count += size; 616 buf[1] = len; 617 618 return buf + 2; 619 } 620 621 static u8 *sii8620_burst_get_rx_buf(struct sii8620 *ctx, int len) 622 { 623 u8 *buf = &ctx->burst.rx_buf[ctx->burst.rx_count]; 624 int size = len + 1; 625 626 if (ctx->burst.rx_count + size >= ARRAY_SIZE(ctx->burst.rx_buf)) { 627 dev_err(ctx->dev, "RX-BLK buffer exhausted\n"); 628 ctx->error = -EINVAL; 629 return NULL; 630 } 631 632 ctx->burst.rx_count += size; 633 buf[0] = len; 634 635 return buf + 1; 636 } 637 638 static void sii8620_burst_send(struct sii8620 *ctx) 639 { 640 int tx_left = ctx->burst.tx_count; 641 u8 *d = ctx->burst.tx_buf; 642 643 while (tx_left > 0) { 644 int len = d[1] + 2; 645 646 if (ctx->burst.r_count + len > ctx->burst.r_size) 647 break; 648 d[0] = min(ctx->burst.rx_ack, 255); 649 ctx->burst.rx_ack -= d[0]; 650 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, d, len); 651 ctx->burst.r_count += len; 652 tx_left -= len; 653 d += len; 654 } 655 656 ctx->burst.tx_count = tx_left; 657 658 while (ctx->burst.rx_ack > 0) { 659 u8 b[2] = { min(ctx->burst.rx_ack, 255), 0 }; 660 661 if (ctx->burst.r_count + 2 > ctx->burst.r_size) 662 break; 663 ctx->burst.rx_ack -= b[0]; 664 sii8620_write_buf(ctx, REG_EMSC_XMIT_WRITE_PORT, b, 2); 665 ctx->burst.r_count += 2; 666 } 667 } 668 669 static void sii8620_burst_receive(struct sii8620 *ctx) 670 { 671 u8 buf[3], *d; 672 int count; 673 674 sii8620_read_buf(ctx, REG_EMSCRFIFOBCNTL, buf, 2); 675 count = get_unaligned_le16(buf); 676 while (count > 0) { 677 int len = min(count, 3); 678 679 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, buf, len); 680 count -= len; 681 ctx->burst.rx_ack += len - 1; 682 ctx->burst.r_count -= buf[1]; 683 if (ctx->burst.r_count < 0) 684 ctx->burst.r_count = 0; 685 686 if (len < 3 || !buf[2]) 687 continue; 688 689 len = buf[2]; 690 d = sii8620_burst_get_rx_buf(ctx, len); 691 if (!d) 692 continue; 693 sii8620_read_buf(ctx, REG_EMSC_RCV_READ_PORT, d, len); 694 count -= len; 695 ctx->burst.rx_ack += len; 696 } 697 } 698 699 static void sii8620_burst_tx_rbuf_info(struct sii8620 *ctx, int size) 700 { 701 struct mhl_burst_blk_rcv_buffer_info *d = 702 sii8620_burst_get_tx_buf(ctx, sizeof(*d)); 703 if (!d) 704 return; 705 706 d->id = cpu_to_be16(MHL_BURST_ID_BLK_RCV_BUFFER_INFO); 707 d->size = cpu_to_le16(size); 708 } 709 710 static u8 sii8620_checksum(void *ptr, int size) 711 { 712 u8 *d = ptr, sum = 0; 713 714 while (size--) 715 sum += *d++; 716 717 return sum; 718 } 719 720 static void sii8620_mhl_burst_hdr_set(struct mhl3_burst_header *h, 721 enum mhl_burst_id id) 722 { 723 h->id = cpu_to_be16(id); 724 h->total_entries = 1; 725 h->sequence_index = 1; 726 } 727 728 static void sii8620_burst_tx_bits_per_pixel_fmt(struct sii8620 *ctx, u8 fmt) 729 { 730 struct mhl_burst_bits_per_pixel_fmt *d; 731 const int size = sizeof(*d) + sizeof(d->desc[0]); 732 733 d = sii8620_burst_get_tx_buf(ctx, size); 734 if (!d) 735 return; 736 737 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_BITS_PER_PIXEL_FMT); 738 d->num_entries = 1; 739 d->desc[0].stream_id = 0; 740 d->desc[0].pixel_format = fmt; 741 d->hdr.checksum -= sii8620_checksum(d, size); 742 } 743 744 static void sii8620_burst_rx_all(struct sii8620 *ctx) 745 { 746 u8 *d = ctx->burst.rx_buf; 747 int count = ctx->burst.rx_count; 748 749 while (count-- > 0) { 750 int len = *d++; 751 int id = get_unaligned_be16(&d[0]); 752 753 switch (id) { 754 case MHL_BURST_ID_BLK_RCV_BUFFER_INFO: 755 ctx->burst.r_size = get_unaligned_le16(&d[2]); 756 break; 757 default: 758 break; 759 } 760 count -= len; 761 d += len; 762 } 763 ctx->burst.rx_count = 0; 764 } 765 766 static void sii8620_fetch_edid(struct sii8620 *ctx) 767 { 768 u8 lm_ddc, ddc_cmd, int3, cbus; 769 unsigned long timeout; 770 int fetched, i; 771 int edid_len = EDID_LENGTH; 772 u8 *edid; 773 774 sii8620_readb(ctx, REG_CBUS_STATUS); 775 lm_ddc = sii8620_readb(ctx, REG_LM_DDC); 776 ddc_cmd = sii8620_readb(ctx, REG_DDC_CMD); 777 778 sii8620_write_seq(ctx, 779 REG_INTR9_MASK, 0, 780 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO, 781 REG_HDCP2X_POLL_CS, 0x71, 782 REG_HDCP2X_CTRL_0, BIT_HDCP2X_CTRL_0_HDCP2X_HDCPTX, 783 REG_LM_DDC, lm_ddc | BIT_LM_DDC_SW_TPI_EN_DISABLED, 784 ); 785 786 for (i = 0; i < 256; ++i) { 787 u8 ddc_stat = sii8620_readb(ctx, REG_DDC_STATUS); 788 789 if (!(ddc_stat & BIT_DDC_STATUS_DDC_I2C_IN_PROG)) 790 break; 791 sii8620_write(ctx, REG_DDC_STATUS, 792 BIT_DDC_STATUS_DDC_FIFO_EMPTY); 793 } 794 795 sii8620_write(ctx, REG_DDC_ADDR, 0x50 << 1); 796 797 edid = kmalloc(EDID_LENGTH, GFP_KERNEL); 798 if (!edid) { 799 ctx->error = -ENOMEM; 800 return; 801 } 802 803 #define FETCH_SIZE 16 804 for (fetched = 0; fetched < edid_len; fetched += FETCH_SIZE) { 805 sii8620_readb(ctx, REG_DDC_STATUS); 806 sii8620_write_seq(ctx, 807 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_ABORT, 808 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_DDC_CMD_CLEAR_FIFO, 809 REG_DDC_STATUS, BIT_DDC_STATUS_DDC_FIFO_EMPTY 810 ); 811 sii8620_write_seq(ctx, 812 REG_DDC_SEGM, fetched >> 8, 813 REG_DDC_OFFSET, fetched & 0xff, 814 REG_DDC_DIN_CNT1, FETCH_SIZE, 815 REG_DDC_DIN_CNT2, 0, 816 REG_DDC_CMD, ddc_cmd | VAL_DDC_CMD_ENH_DDC_READ_NO_ACK 817 ); 818 819 int3 = 0; 820 timeout = jiffies + msecs_to_jiffies(200); 821 for (;;) { 822 cbus = sii8620_readb(ctx, REG_CBUS_STATUS); 823 if (~cbus & BIT_CBUS_STATUS_CBUS_CONNECTED) { 824 kfree(edid); 825 edid = NULL; 826 goto end; 827 } 828 if (int3 & BIT_DDC_CMD_DONE) { 829 if (sii8620_readb(ctx, REG_DDC_DOUT_CNT) 830 >= FETCH_SIZE) 831 break; 832 } else { 833 int3 = sii8620_readb(ctx, REG_INTR3); 834 } 835 if (time_is_before_jiffies(timeout)) { 836 ctx->error = -ETIMEDOUT; 837 dev_err(ctx->dev, "timeout during EDID read\n"); 838 kfree(edid); 839 edid = NULL; 840 goto end; 841 } 842 usleep_range(10, 20); 843 } 844 845 sii8620_read_buf(ctx, REG_DDC_DATA, edid + fetched, FETCH_SIZE); 846 if (fetched + FETCH_SIZE == EDID_LENGTH) { 847 u8 ext = ((struct edid *)edid)->extensions; 848 849 if (ext) { 850 u8 *new_edid; 851 852 edid_len += ext * EDID_LENGTH; 853 new_edid = krealloc(edid, edid_len, GFP_KERNEL); 854 if (!new_edid) { 855 kfree(edid); 856 ctx->error = -ENOMEM; 857 return; 858 } 859 edid = new_edid; 860 } 861 } 862 } 863 864 sii8620_write_seq(ctx, 865 REG_INTR3_MASK, BIT_DDC_CMD_DONE, 866 REG_LM_DDC, lm_ddc 867 ); 868 869 end: 870 kfree(ctx->edid); 871 ctx->edid = (struct edid *)edid; 872 } 873 874 static void sii8620_set_upstream_edid(struct sii8620 *ctx) 875 { 876 sii8620_setbits(ctx, REG_DPD, BIT_DPD_PDNRX12 | BIT_DPD_PDIDCK_N 877 | BIT_DPD_PD_MHL_CLK_N, 0xff); 878 879 sii8620_write_seq_static(ctx, 880 REG_RX_HDMI_CTRL3, 0x00, 881 REG_PKT_FILTER_0, 0xFF, 882 REG_PKT_FILTER_1, 0xFF, 883 REG_ALICE0_BW_I2C, 0x06 884 ); 885 886 sii8620_setbits(ctx, REG_RX_HDMI_CLR_BUFFER, 887 BIT_RX_HDMI_CLR_BUFFER_VSI_CLR_EN, 0xff); 888 889 sii8620_write_seq_static(ctx, 890 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 891 | BIT_EDID_CTRL_EDID_MODE_EN, 892 REG_EDID_FIFO_ADDR, 0, 893 ); 894 895 sii8620_write_buf(ctx, REG_EDID_FIFO_WR_DATA, (u8 *)ctx->edid, 896 (ctx->edid->extensions + 1) * EDID_LENGTH); 897 898 sii8620_write_seq_static(ctx, 899 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID 900 | BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO 901 | BIT_EDID_CTRL_EDID_MODE_EN, 902 REG_INTR5_MASK, BIT_INTR_SCDT_CHANGE, 903 REG_INTR9_MASK, 0 904 ); 905 } 906 907 static void sii8620_xtal_set_rate(struct sii8620 *ctx) 908 { 909 static const struct { 910 unsigned int rate; 911 u8 div; 912 u8 tp1; 913 } rates[] = { 914 { 19200, 0x04, 0x53 }, 915 { 20000, 0x04, 0x62 }, 916 { 24000, 0x05, 0x75 }, 917 { 30000, 0x06, 0x92 }, 918 { 38400, 0x0c, 0xbc }, 919 }; 920 unsigned long rate = clk_get_rate(ctx->clk_xtal) / 1000; 921 int i; 922 923 for (i = 0; i < ARRAY_SIZE(rates) - 1; ++i) 924 if (rate <= rates[i].rate) 925 break; 926 927 if (rate != rates[i].rate) 928 dev_err(ctx->dev, "xtal clock rate(%lukHz) not supported, setting MHL for %ukHz.\n", 929 rate, rates[i].rate); 930 931 sii8620_write(ctx, REG_DIV_CTL_MAIN, rates[i].div); 932 sii8620_write(ctx, REG_HDCP2X_TP1, rates[i].tp1); 933 } 934 935 static int sii8620_hw_on(struct sii8620 *ctx) 936 { 937 int ret; 938 939 ret = regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 940 if (ret) 941 return ret; 942 943 usleep_range(10000, 20000); 944 ret = clk_prepare_enable(ctx->clk_xtal); 945 if (ret) 946 return ret; 947 948 msleep(100); 949 gpiod_set_value(ctx->gpio_reset, 0); 950 msleep(100); 951 952 return 0; 953 } 954 955 static int sii8620_hw_off(struct sii8620 *ctx) 956 { 957 clk_disable_unprepare(ctx->clk_xtal); 958 gpiod_set_value(ctx->gpio_reset, 1); 959 return regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 960 } 961 962 static void sii8620_cbus_reset(struct sii8620 *ctx) 963 { 964 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST 965 | BIT_PWD_SRST_CBUS_RST_SW_EN); 966 usleep_range(10000, 20000); 967 sii8620_write(ctx, REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN); 968 } 969 970 static void sii8620_set_auto_zone(struct sii8620 *ctx) 971 { 972 if (ctx->mode != CM_MHL1) { 973 sii8620_write_seq_static(ctx, 974 REG_TX_ZONE_CTL1, 0x0, 975 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 976 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 977 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE 978 ); 979 } else { 980 sii8620_write_seq_static(ctx, 981 REG_TX_ZONE_CTL1, VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE, 982 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 983 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE 984 ); 985 } 986 } 987 988 static void sii8620_stop_video(struct sii8620 *ctx) 989 { 990 u8 val; 991 992 sii8620_write_seq_static(ctx, 993 REG_TPI_INTR_EN, 0, 994 REG_HDCP2X_INTR0_MASK, 0, 995 REG_TPI_COPP_DATA2, 0, 996 REG_TPI_INTR_ST0, ~0, 997 ); 998 999 switch (ctx->sink_type) { 1000 case SINK_DVI: 1001 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN 1002 | BIT_TPI_SC_TPI_AV_MUTE; 1003 break; 1004 case SINK_HDMI: 1005 default: 1006 val = BIT_TPI_SC_REG_TMDS_OE_POWER_DOWN 1007 | BIT_TPI_SC_TPI_AV_MUTE 1008 | BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI; 1009 break; 1010 } 1011 1012 sii8620_write(ctx, REG_TPI_SC, val); 1013 } 1014 1015 static void sii8620_set_format(struct sii8620 *ctx) 1016 { 1017 u8 out_fmt; 1018 1019 if (sii8620_is_mhl3(ctx)) { 1020 sii8620_setbits(ctx, REG_M3_P0CTRL, 1021 BIT_M3_P0CTRL_MHL3_P0_PIXEL_MODE_PACKED, 1022 ctx->use_packed_pixel ? ~0 : 0); 1023 } else { 1024 if (ctx->use_packed_pixel) { 1025 sii8620_write_seq_static(ctx, 1026 REG_VID_MODE, BIT_VID_MODE_M1080P, 1027 REG_MHL_TOP_CTL, BIT_MHL_TOP_CTL_MHL_PP_SEL | 1, 1028 REG_MHLTX_CTL6, 0x60 1029 ); 1030 } else { 1031 sii8620_write_seq_static(ctx, 1032 REG_VID_MODE, 0, 1033 REG_MHL_TOP_CTL, 1, 1034 REG_MHLTX_CTL6, 0xa0 1035 ); 1036 } 1037 } 1038 1039 if (ctx->use_packed_pixel) 1040 out_fmt = VAL_TPI_FORMAT(YCBCR422, FULL); 1041 else 1042 out_fmt = VAL_TPI_FORMAT(RGB, FULL); 1043 1044 sii8620_write_seq(ctx, 1045 REG_TPI_INPUT, VAL_TPI_FORMAT(RGB, FULL), 1046 REG_TPI_OUTPUT, out_fmt, 1047 ); 1048 } 1049 1050 static int mhl3_infoframe_init(struct mhl3_infoframe *frame) 1051 { 1052 memset(frame, 0, sizeof(*frame)); 1053 1054 frame->version = 3; 1055 frame->hev_format = -1; 1056 return 0; 1057 } 1058 1059 static ssize_t mhl3_infoframe_pack(struct mhl3_infoframe *frame, 1060 void *buffer, size_t size) 1061 { 1062 const int frm_len = HDMI_INFOFRAME_HEADER_SIZE + MHL3_INFOFRAME_SIZE; 1063 u8 *ptr = buffer; 1064 1065 if (size < frm_len) 1066 return -ENOSPC; 1067 1068 memset(buffer, 0, size); 1069 ptr[0] = HDMI_INFOFRAME_TYPE_VENDOR; 1070 ptr[1] = frame->version; 1071 ptr[2] = MHL3_INFOFRAME_SIZE; 1072 ptr[4] = MHL3_IEEE_OUI & 0xff; 1073 ptr[5] = (MHL3_IEEE_OUI >> 8) & 0xff; 1074 ptr[6] = (MHL3_IEEE_OUI >> 16) & 0xff; 1075 ptr[7] = frame->video_format & 0x3; 1076 ptr[7] |= (frame->format_type & 0x7) << 2; 1077 ptr[7] |= frame->sep_audio ? BIT(5) : 0; 1078 if (frame->hev_format >= 0) { 1079 ptr[9] = 1; 1080 ptr[10] = (frame->hev_format >> 8) & 0xff; 1081 ptr[11] = frame->hev_format & 0xff; 1082 } 1083 if (frame->av_delay) { 1084 bool sign = frame->av_delay < 0; 1085 int delay = sign ? -frame->av_delay : frame->av_delay; 1086 1087 ptr[12] = (delay >> 16) & 0xf; 1088 if (sign) 1089 ptr[12] |= BIT(4); 1090 ptr[13] = (delay >> 8) & 0xff; 1091 ptr[14] = delay & 0xff; 1092 } 1093 ptr[3] -= sii8620_checksum(buffer, frm_len); 1094 return frm_len; 1095 } 1096 1097 static void sii8620_set_infoframes(struct sii8620 *ctx, 1098 struct drm_display_mode *mode) 1099 { 1100 struct mhl3_infoframe mhl_frm; 1101 union hdmi_infoframe frm; 1102 u8 buf[31]; 1103 int ret; 1104 1105 ret = drm_hdmi_avi_infoframe_from_display_mode(&frm.avi, 1106 NULL, mode); 1107 if (ctx->use_packed_pixel) 1108 frm.avi.colorspace = HDMI_COLORSPACE_YUV422; 1109 1110 if (!ret) 1111 ret = hdmi_avi_infoframe_pack(&frm.avi, buf, ARRAY_SIZE(buf)); 1112 if (ret > 0) 1113 sii8620_write_buf(ctx, REG_TPI_AVI_CHSUM, buf + 3, ret - 3); 1114 1115 if (!sii8620_is_mhl3(ctx) || !ctx->use_packed_pixel) { 1116 sii8620_write(ctx, REG_TPI_SC, 1117 BIT_TPI_SC_TPI_OUTPUT_MODE_0_HDMI); 1118 sii8620_write(ctx, REG_PKT_FILTER_0, 1119 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT | 1120 BIT_PKT_FILTER_0_DROP_MPEG_PKT | 1121 BIT_PKT_FILTER_0_DROP_GCP_PKT, 1122 BIT_PKT_FILTER_1_DROP_GEN_PKT); 1123 return; 1124 } 1125 1126 sii8620_write(ctx, REG_PKT_FILTER_0, 1127 BIT_PKT_FILTER_0_DROP_CEA_GAMUT_PKT | 1128 BIT_PKT_FILTER_0_DROP_MPEG_PKT | 1129 BIT_PKT_FILTER_0_DROP_AVI_PKT | 1130 BIT_PKT_FILTER_0_DROP_GCP_PKT, 1131 BIT_PKT_FILTER_1_VSI_OVERRIDE_DIS | 1132 BIT_PKT_FILTER_1_DROP_GEN_PKT | 1133 BIT_PKT_FILTER_1_DROP_VSIF_PKT); 1134 1135 sii8620_write(ctx, REG_TPI_INFO_FSEL, BIT_TPI_INFO_FSEL_EN 1136 | BIT_TPI_INFO_FSEL_RPT | VAL_TPI_INFO_FSEL_VSI); 1137 ret = mhl3_infoframe_init(&mhl_frm); 1138 if (!ret) 1139 ret = mhl3_infoframe_pack(&mhl_frm, buf, ARRAY_SIZE(buf)); 1140 sii8620_write_buf(ctx, REG_TPI_INFO_B0, buf, ret); 1141 } 1142 1143 static void sii8620_start_video(struct sii8620 *ctx) 1144 { 1145 struct drm_display_mode *mode = 1146 &ctx->bridge.encoder->crtc->state->adjusted_mode; 1147 1148 if (!sii8620_is_mhl3(ctx)) 1149 sii8620_stop_video(ctx); 1150 1151 if (ctx->sink_type == SINK_DVI && !sii8620_is_mhl3(ctx)) { 1152 sii8620_write(ctx, REG_RX_HDMI_CTRL2, 1153 VAL_RX_HDMI_CTRL2_DEFVAL); 1154 sii8620_write(ctx, REG_TPI_SC, 0); 1155 return; 1156 } 1157 1158 sii8620_write_seq_static(ctx, 1159 REG_RX_HDMI_CTRL2, VAL_RX_HDMI_CTRL2_DEFVAL 1160 | BIT_RX_HDMI_CTRL2_USE_AV_MUTE, 1161 REG_VID_OVRRD, BIT_VID_OVRRD_PP_AUTO_DISABLE 1162 | BIT_VID_OVRRD_M1080P_OVRRD); 1163 sii8620_set_format(ctx); 1164 1165 if (!sii8620_is_mhl3(ctx)) { 1166 u8 link_mode = MHL_DST_LM_PATH_ENABLED; 1167 1168 if (ctx->use_packed_pixel) 1169 link_mode |= MHL_DST_LM_CLK_MODE_PACKED_PIXEL; 1170 else 1171 link_mode |= MHL_DST_LM_CLK_MODE_NORMAL; 1172 1173 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), link_mode); 1174 sii8620_set_auto_zone(ctx); 1175 } else { 1176 static const struct { 1177 int max_clk; 1178 u8 zone; 1179 u8 link_rate; 1180 u8 rrp_decode; 1181 } clk_spec[] = { 1182 { 150000, VAL_TX_ZONE_CTL3_TX_ZONE_1_5GBPS, 1183 MHL_XDS_LINK_RATE_1_5_GBPS, 0x38 }, 1184 { 300000, VAL_TX_ZONE_CTL3_TX_ZONE_3GBPS, 1185 MHL_XDS_LINK_RATE_3_0_GBPS, 0x40 }, 1186 { 600000, VAL_TX_ZONE_CTL3_TX_ZONE_6GBPS, 1187 MHL_XDS_LINK_RATE_6_0_GBPS, 0x40 }, 1188 }; 1189 u8 p0_ctrl = BIT_M3_P0CTRL_MHL3_P0_PORT_EN; 1190 int clk = mode->clock * (ctx->use_packed_pixel ? 2 : 3); 1191 int i; 1192 1193 for (i = 0; i < ARRAY_SIZE(clk_spec) - 1; ++i) 1194 if (clk < clk_spec[i].max_clk) 1195 break; 1196 1197 if (100 * clk >= 98 * clk_spec[i].max_clk) 1198 p0_ctrl |= BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN; 1199 1200 sii8620_burst_tx_bits_per_pixel_fmt(ctx, ctx->use_packed_pixel); 1201 sii8620_burst_send(ctx); 1202 sii8620_write_seq(ctx, 1203 REG_MHL_DP_CTL0, 0xf0, 1204 REG_MHL3_TX_ZONE_CTL, clk_spec[i].zone); 1205 sii8620_setbits(ctx, REG_M3_P0CTRL, 1206 BIT_M3_P0CTRL_MHL3_P0_PORT_EN 1207 | BIT_M3_P0CTRL_MHL3_P0_UNLIMIT_EN, p0_ctrl); 1208 sii8620_setbits(ctx, REG_M3_POSTM, MSK_M3_POSTM_RRP_DECODE, 1209 clk_spec[i].rrp_decode); 1210 sii8620_write_seq_static(ctx, 1211 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE 1212 | BIT_M3_CTRL_H2M_SWRST, 1213 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE 1214 ); 1215 sii8620_mt_write_stat(ctx, MHL_XDS_REG(AVLINK_MODE_CONTROL), 1216 clk_spec[i].link_rate); 1217 } 1218 1219 sii8620_set_infoframes(ctx, mode); 1220 } 1221 1222 static void sii8620_disable_hpd(struct sii8620 *ctx) 1223 { 1224 sii8620_setbits(ctx, REG_EDID_CTRL, BIT_EDID_CTRL_EDID_PRIME_VALID, 0); 1225 sii8620_write_seq_static(ctx, 1226 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN, 1227 REG_INTR8_MASK, 0 1228 ); 1229 } 1230 1231 static void sii8620_enable_hpd(struct sii8620 *ctx) 1232 { 1233 sii8620_setbits(ctx, REG_TMDS_CSTAT_P3, 1234 BIT_TMDS_CSTAT_P3_SCDT_CLR_AVI_DIS 1235 | BIT_TMDS_CSTAT_P3_CLR_AVI, ~0); 1236 sii8620_write_seq_static(ctx, 1237 REG_HPD_CTRL, BIT_HPD_CTRL_HPD_OUT_OVR_EN 1238 | BIT_HPD_CTRL_HPD_HIGH, 1239 ); 1240 } 1241 1242 static void sii8620_mhl_discover(struct sii8620 *ctx) 1243 { 1244 sii8620_write_seq_static(ctx, 1245 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1246 | BIT_DISC_CTRL9_DISC_PULSE_PROCEED, 1247 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_5K, VAL_PUP_20K), 1248 REG_CBUS_DISC_INTR0_MASK, BIT_MHL3_EST_INT 1249 | BIT_MHL_EST_INT 1250 | BIT_NOT_MHL_EST_INT 1251 | BIT_CBUS_MHL3_DISCON_INT 1252 | BIT_CBUS_MHL12_DISCON_INT 1253 | BIT_RGND_READY_INT, 1254 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1255 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1256 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE, 1257 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE 1258 | BIT_MHL_DP_CTL0_TX_OE_OVR, 1259 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE, 1260 REG_MHL_DP_CTL1, 0xA2, 1261 REG_MHL_DP_CTL2, 0x03, 1262 REG_MHL_DP_CTL3, 0x35, 1263 REG_MHL_DP_CTL5, 0x02, 1264 REG_MHL_DP_CTL6, 0x02, 1265 REG_MHL_DP_CTL7, 0x03, 1266 REG_COC_CTLC, 0xFF, 1267 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 1268 | BIT_DPD_OSC_EN | BIT_DPD_PWRON_HSIC, 1269 REG_COC_INTR_MASK, BIT_COC_PLL_LOCK_STATUS_CHANGE 1270 | BIT_COC_CALIBRATION_DONE, 1271 REG_CBUS_INT_1_MASK, BIT_CBUS_MSC_ABORT_RCVD 1272 | BIT_CBUS_CMD_ABORT, 1273 REG_CBUS_INT_0_MASK, BIT_CBUS_MSC_MT_DONE 1274 | BIT_CBUS_HPD_CHG 1275 | BIT_CBUS_MSC_MR_WRITE_STAT 1276 | BIT_CBUS_MSC_MR_MSC_MSG 1277 | BIT_CBUS_MSC_MR_WRITE_BURST 1278 | BIT_CBUS_MSC_MR_SET_INT 1279 | BIT_CBUS_MSC_MT_DONE_NACK 1280 ); 1281 } 1282 1283 static void sii8620_peer_specific_init(struct sii8620 *ctx) 1284 { 1285 if (sii8620_is_mhl3(ctx)) 1286 sii8620_write_seq_static(ctx, 1287 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD, 1288 REG_EMSCINTRMASK1, 1289 BIT_EMSCINTR1_EMSC_TRAINING_COMMA_ERR 1290 ); 1291 else 1292 sii8620_write_seq_static(ctx, 1293 REG_HDCP2X_INTR0_MASK, 0x00, 1294 REG_EMSCINTRMASK1, 0x00, 1295 REG_HDCP2X_INTR0, 0xFF, 1296 REG_INTR1, 0xFF, 1297 REG_SYS_CTRL1, BIT_SYS_CTRL1_BLOCK_DDC_BY_HPD 1298 | BIT_SYS_CTRL1_TX_CTRL_HDMI 1299 ); 1300 } 1301 1302 #define SII8620_MHL_VERSION 0x32 1303 #define SII8620_SCRATCHPAD_SIZE 16 1304 #define SII8620_INT_STAT_SIZE 0x33 1305 1306 static void sii8620_set_dev_cap(struct sii8620 *ctx) 1307 { 1308 static const u8 devcap[MHL_DCAP_SIZE] = { 1309 [MHL_DCAP_MHL_VERSION] = SII8620_MHL_VERSION, 1310 [MHL_DCAP_CAT] = MHL_DCAP_CAT_SOURCE | MHL_DCAP_CAT_POWER, 1311 [MHL_DCAP_ADOPTER_ID_H] = 0x01, 1312 [MHL_DCAP_ADOPTER_ID_L] = 0x41, 1313 [MHL_DCAP_VID_LINK_MODE] = MHL_DCAP_VID_LINK_RGB444 1314 | MHL_DCAP_VID_LINK_PPIXEL 1315 | MHL_DCAP_VID_LINK_16BPP, 1316 [MHL_DCAP_AUD_LINK_MODE] = MHL_DCAP_AUD_LINK_2CH, 1317 [MHL_DCAP_VIDEO_TYPE] = MHL_DCAP_VT_GRAPHICS, 1318 [MHL_DCAP_LOG_DEV_MAP] = MHL_DCAP_LD_GUI, 1319 [MHL_DCAP_BANDWIDTH] = 0x0f, 1320 [MHL_DCAP_FEATURE_FLAG] = MHL_DCAP_FEATURE_RCP_SUPPORT 1321 | MHL_DCAP_FEATURE_RAP_SUPPORT 1322 | MHL_DCAP_FEATURE_SP_SUPPORT, 1323 [MHL_DCAP_SCRATCHPAD_SIZE] = SII8620_SCRATCHPAD_SIZE, 1324 [MHL_DCAP_INT_STAT_SIZE] = SII8620_INT_STAT_SIZE, 1325 }; 1326 static const u8 xdcap[MHL_XDC_SIZE] = { 1327 [MHL_XDC_ECBUS_SPEEDS] = MHL_XDC_ECBUS_S_075 1328 | MHL_XDC_ECBUS_S_8BIT, 1329 [MHL_XDC_TMDS_SPEEDS] = MHL_XDC_TMDS_150 1330 | MHL_XDC_TMDS_300 | MHL_XDC_TMDS_600, 1331 [MHL_XDC_ECBUS_ROLES] = MHL_XDC_DEV_HOST, 1332 [MHL_XDC_LOG_DEV_MAPX] = MHL_XDC_LD_PHONE, 1333 }; 1334 1335 sii8620_write_buf(ctx, REG_MHL_DEVCAP_0, devcap, ARRAY_SIZE(devcap)); 1336 sii8620_write_buf(ctx, REG_MHL_EXTDEVCAP_0, xdcap, ARRAY_SIZE(xdcap)); 1337 } 1338 1339 static void sii8620_mhl_init(struct sii8620 *ctx) 1340 { 1341 sii8620_write_seq_static(ctx, 1342 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1343 REG_CBUS_MSC_COMPAT_CTRL, 1344 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN, 1345 ); 1346 1347 sii8620_peer_specific_init(ctx); 1348 1349 sii8620_disable_hpd(ctx); 1350 1351 sii8620_write_seq_static(ctx, 1352 REG_EDID_CTRL, BIT_EDID_CTRL_EDID_FIFO_ADDR_AUTO, 1353 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1354 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1355 REG_TMDS0_CCTRL1, 0x90, 1356 REG_TMDS_CLK_EN, 0x01, 1357 REG_TMDS_CH_EN, 0x11, 1358 REG_BGR_BIAS, 0x87, 1359 REG_ALICE0_ZONE_CTRL, 0xE8, 1360 REG_ALICE0_MODE_CTRL, 0x04, 1361 ); 1362 sii8620_setbits(ctx, REG_LM_DDC, BIT_LM_DDC_SW_TPI_EN_DISABLED, 0); 1363 sii8620_write_seq_static(ctx, 1364 REG_TPI_HW_OPT3, 0x76, 1365 REG_TMDS_CCTRL, BIT_TMDS_CCTRL_TMDS_OE, 1366 REG_TPI_DTD_B2, 79, 1367 ); 1368 sii8620_set_dev_cap(ctx); 1369 sii8620_write_seq_static(ctx, 1370 REG_MDT_XMIT_TIMEOUT, 100, 1371 REG_MDT_XMIT_CTRL, 0x03, 1372 REG_MDT_XFIFO_STAT, 0x00, 1373 REG_MDT_RCV_TIMEOUT, 100, 1374 REG_CBUS_LINK_CTRL_8, 0x1D, 1375 ); 1376 1377 sii8620_start_gen2_write_burst(ctx); 1378 sii8620_write_seq_static(ctx, 1379 REG_BIST_CTRL, 0x00, 1380 REG_COC_CTL1, 0x10, 1381 REG_COC_CTL2, 0x18, 1382 REG_COC_CTLF, 0x07, 1383 REG_COC_CTL11, 0xF8, 1384 REG_COC_CTL17, 0x61, 1385 REG_COC_CTL18, 0x46, 1386 REG_COC_CTL19, 0x15, 1387 REG_COC_CTL1A, 0x01, 1388 REG_MHL_COC_CTL3, BIT_MHL_COC_CTL3_COC_AECHO_EN, 1389 REG_MHL_COC_CTL4, 0x2D, 1390 REG_MHL_COC_CTL5, 0xF9, 1391 REG_MSC_HEARTBEAT_CTRL, 0x27, 1392 ); 1393 sii8620_disable_gen2_write_burst(ctx); 1394 1395 sii8620_mt_write_stat(ctx, MHL_DST_REG(VERSION), SII8620_MHL_VERSION); 1396 sii8620_mt_write_stat(ctx, MHL_DST_REG(CONNECTED_RDY), 1397 MHL_DST_CONN_DCAP_RDY | MHL_DST_CONN_XDEVCAPP_SUPP 1398 | MHL_DST_CONN_POW_STAT); 1399 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), MHL_INT_RC_DCAP_CHG); 1400 } 1401 1402 static void sii8620_emsc_enable(struct sii8620 *ctx) 1403 { 1404 u8 reg; 1405 1406 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_EMSC_EN 1407 | BIT_GENCTL_CLR_EMSC_RFIFO 1408 | BIT_GENCTL_CLR_EMSC_XFIFO, ~0); 1409 sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_CLR_EMSC_RFIFO 1410 | BIT_GENCTL_CLR_EMSC_XFIFO, 0); 1411 sii8620_setbits(ctx, REG_COMMECNT, BIT_COMMECNT_I2C_TO_EMSC_EN, ~0); 1412 reg = sii8620_readb(ctx, REG_EMSCINTR); 1413 sii8620_write(ctx, REG_EMSCINTR, reg); 1414 sii8620_write(ctx, REG_EMSCINTRMASK, BIT_EMSCINTR_SPI_DVLD); 1415 } 1416 1417 static int sii8620_wait_for_fsm_state(struct sii8620 *ctx, u8 state) 1418 { 1419 int i; 1420 1421 for (i = 0; i < 10; ++i) { 1422 u8 s = sii8620_readb(ctx, REG_COC_STAT_0); 1423 1424 if ((s & MSK_COC_STAT_0_FSM_STATE) == state) 1425 return 0; 1426 if (!(s & BIT_COC_STAT_0_PLL_LOCKED)) 1427 return -EBUSY; 1428 usleep_range(4000, 6000); 1429 } 1430 return -ETIMEDOUT; 1431 } 1432 1433 static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode) 1434 { 1435 int ret; 1436 1437 if (ctx->mode == mode) 1438 return; 1439 1440 switch (mode) { 1441 case CM_MHL1: 1442 sii8620_write_seq_static(ctx, 1443 REG_CBUS_MSC_COMPAT_CTRL, 0x02, 1444 REG_M3_CTRL, VAL_M3_CTRL_MHL1_2_VALUE, 1445 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 1446 | BIT_DPD_OSC_EN, 1447 REG_COC_INTR_MASK, 0 1448 ); 1449 ctx->mode = mode; 1450 break; 1451 case CM_MHL3: 1452 sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE); 1453 ctx->mode = mode; 1454 return; 1455 case CM_ECBUS_S: 1456 sii8620_emsc_enable(ctx); 1457 sii8620_write_seq_static(ctx, 1458 REG_TTXSPINUMS, 4, 1459 REG_TRXSPINUMS, 4, 1460 REG_TTXHSICNUMS, 0x14, 1461 REG_TRXHSICNUMS, 0x14, 1462 REG_TTXTOTNUMS, 0x18, 1463 REG_TRXTOTNUMS, 0x18, 1464 REG_PWD_SRST, BIT_PWD_SRST_COC_DOC_RST 1465 | BIT_PWD_SRST_CBUS_RST_SW_EN, 1466 REG_MHL_COC_CTL1, 0xbd, 1467 REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN, 1468 REG_COC_CTLB, 0x01, 1469 REG_COC_CTL0, 0x5c, 1470 REG_COC_CTL14, 0x03, 1471 REG_COC_CTL15, 0x80, 1472 REG_MHL_DP_CTL6, BIT_MHL_DP_CTL6_DP_TAP1_SGN 1473 | BIT_MHL_DP_CTL6_DP_TAP1_EN 1474 | BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN, 1475 REG_MHL_DP_CTL8, 0x03 1476 ); 1477 ret = sii8620_wait_for_fsm_state(ctx, 0x03); 1478 sii8620_write_seq_static(ctx, 1479 REG_COC_CTL14, 0x00, 1480 REG_COC_CTL15, 0x80 1481 ); 1482 if (!ret) 1483 sii8620_write(ctx, REG_CBUS3_CNVT, 0x85); 1484 else 1485 sii8620_disconnect(ctx); 1486 return; 1487 case CM_DISCONNECTED: 1488 ctx->mode = mode; 1489 break; 1490 default: 1491 dev_err(ctx->dev, "%s mode %d not supported\n", __func__, mode); 1492 break; 1493 } 1494 1495 sii8620_set_auto_zone(ctx); 1496 1497 if (mode != CM_MHL1) 1498 return; 1499 1500 sii8620_write_seq_static(ctx, 1501 REG_MHL_DP_CTL0, 0xBC, 1502 REG_MHL_DP_CTL1, 0xBB, 1503 REG_MHL_DP_CTL3, 0x48, 1504 REG_MHL_DP_CTL5, 0x39, 1505 REG_MHL_DP_CTL2, 0x2A, 1506 REG_MHL_DP_CTL6, 0x2A, 1507 REG_MHL_DP_CTL7, 0x08 1508 ); 1509 } 1510 1511 static void sii8620_hpd_unplugged(struct sii8620 *ctx) 1512 { 1513 sii8620_disable_hpd(ctx); 1514 ctx->sink_type = SINK_NONE; 1515 ctx->sink_detected = false; 1516 ctx->feature_complete = false; 1517 kfree(ctx->edid); 1518 ctx->edid = NULL; 1519 } 1520 1521 static void sii8620_disconnect(struct sii8620 *ctx) 1522 { 1523 sii8620_disable_gen2_write_burst(ctx); 1524 sii8620_stop_video(ctx); 1525 msleep(100); 1526 sii8620_cbus_reset(ctx); 1527 sii8620_set_mode(ctx, CM_DISCONNECTED); 1528 sii8620_write_seq_static(ctx, 1529 REG_TX_ZONE_CTL1, 0, 1530 REG_MHL_PLL_CTL0, 0x07, 1531 REG_COC_CTL0, 0x40, 1532 REG_CBUS3_CNVT, 0x84, 1533 REG_COC_CTL14, 0x00, 1534 REG_COC_CTL0, 0x40, 1535 REG_HRXCTRL3, 0x07, 1536 REG_MHL_PLL_CTL0, VAL_MHL_PLL_CTL0_HDMI_CLK_RATIO_1X 1537 | BIT_MHL_PLL_CTL0_CRYSTAL_CLK_SEL 1538 | BIT_MHL_PLL_CTL0_ZONE_MASK_OE, 1539 REG_MHL_DP_CTL0, BIT_MHL_DP_CTL0_DP_OE 1540 | BIT_MHL_DP_CTL0_TX_OE_OVR, 1541 REG_MHL_DP_CTL1, 0xBB, 1542 REG_MHL_DP_CTL3, 0x48, 1543 REG_MHL_DP_CTL5, 0x3F, 1544 REG_MHL_DP_CTL2, 0x2F, 1545 REG_MHL_DP_CTL6, 0x2A, 1546 REG_MHL_DP_CTL7, 0x03 1547 ); 1548 sii8620_hpd_unplugged(ctx); 1549 sii8620_write_seq_static(ctx, 1550 REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE, 1551 REG_MHL_COC_CTL1, 0x07, 1552 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1553 REG_DISC_CTRL8, 0x00, 1554 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1555 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1556 REG_INT_CTRL, 0x00, 1557 REG_MSC_HEARTBEAT_CTRL, 0x27, 1558 REG_DISC_CTRL1, 0x25, 1559 REG_CBUS_DISC_INTR0, (u8)~BIT_RGND_READY_INT, 1560 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT, 1561 REG_MDT_INT_1, 0xff, 1562 REG_MDT_INT_1_MASK, 0x00, 1563 REG_MDT_INT_0, 0xff, 1564 REG_MDT_INT_0_MASK, 0x00, 1565 REG_COC_INTR, 0xff, 1566 REG_COC_INTR_MASK, 0x00, 1567 REG_TRXINTH, 0xff, 1568 REG_TRXINTMH, 0x00, 1569 REG_CBUS_INT_0, 0xff, 1570 REG_CBUS_INT_0_MASK, 0x00, 1571 REG_CBUS_INT_1, 0xff, 1572 REG_CBUS_INT_1_MASK, 0x00, 1573 REG_EMSCINTR, 0xff, 1574 REG_EMSCINTRMASK, 0x00, 1575 REG_EMSCINTR1, 0xff, 1576 REG_EMSCINTRMASK1, 0x00, 1577 REG_INTR8, 0xff, 1578 REG_INTR8_MASK, 0x00, 1579 REG_TPI_INTR_ST0, 0xff, 1580 REG_TPI_INTR_EN, 0x00, 1581 REG_HDCP2X_INTR0, 0xff, 1582 REG_HDCP2X_INTR0_MASK, 0x00, 1583 REG_INTR9, 0xff, 1584 REG_INTR9_MASK, 0x00, 1585 REG_INTR3, 0xff, 1586 REG_INTR3_MASK, 0x00, 1587 REG_INTR5, 0xff, 1588 REG_INTR5_MASK, 0x00, 1589 REG_INTR2, 0xff, 1590 REG_INTR2_MASK, 0x00, 1591 ); 1592 memset(ctx->stat, 0, sizeof(ctx->stat)); 1593 memset(ctx->xstat, 0, sizeof(ctx->xstat)); 1594 memset(ctx->devcap, 0, sizeof(ctx->devcap)); 1595 memset(ctx->xdevcap, 0, sizeof(ctx->xdevcap)); 1596 ctx->devcap_read = false; 1597 ctx->cbus_status = 0; 1598 sii8620_mt_cleanup(ctx); 1599 } 1600 1601 static void sii8620_mhl_disconnected(struct sii8620 *ctx) 1602 { 1603 sii8620_write_seq_static(ctx, 1604 REG_DISC_CTRL4, VAL_DISC_CTRL4(VAL_PUP_OFF, VAL_PUP_20K), 1605 REG_CBUS_MSC_COMPAT_CTRL, 1606 BIT_CBUS_MSC_COMPAT_CTRL_XDEVCAP_EN 1607 ); 1608 sii8620_disconnect(ctx); 1609 } 1610 1611 static void sii8620_irq_disc(struct sii8620 *ctx) 1612 { 1613 u8 stat = sii8620_readb(ctx, REG_CBUS_DISC_INTR0); 1614 1615 if (stat & VAL_CBUS_MHL_DISCON) 1616 sii8620_mhl_disconnected(ctx); 1617 1618 if (stat & BIT_RGND_READY_INT) { 1619 u8 stat2 = sii8620_readb(ctx, REG_DISC_STAT2); 1620 1621 if ((stat2 & MSK_DISC_STAT2_RGND) == VAL_RGND_1K) { 1622 sii8620_mhl_discover(ctx); 1623 } else { 1624 sii8620_write_seq_static(ctx, 1625 REG_DISC_CTRL9, BIT_DISC_CTRL9_WAKE_DRVFLT 1626 | BIT_DISC_CTRL9_NOMHL_EST 1627 | BIT_DISC_CTRL9_WAKE_PULSE_BYPASS, 1628 REG_CBUS_DISC_INTR0_MASK, BIT_RGND_READY_INT 1629 | BIT_CBUS_MHL3_DISCON_INT 1630 | BIT_CBUS_MHL12_DISCON_INT 1631 | BIT_NOT_MHL_EST_INT 1632 ); 1633 } 1634 } 1635 if (stat & BIT_MHL_EST_INT) 1636 sii8620_mhl_init(ctx); 1637 1638 sii8620_write(ctx, REG_CBUS_DISC_INTR0, stat); 1639 } 1640 1641 static void sii8620_read_burst(struct sii8620 *ctx) 1642 { 1643 u8 buf[17]; 1644 1645 sii8620_read_buf(ctx, REG_MDT_RCV_READ_PORT, buf, ARRAY_SIZE(buf)); 1646 sii8620_write(ctx, REG_MDT_RCV_CTRL, BIT_MDT_RCV_CTRL_MDT_RCV_EN | 1647 BIT_MDT_RCV_CTRL_MDT_DELAY_RCV_EN | 1648 BIT_MDT_RCV_CTRL_MDT_RFIFO_CLR_CUR); 1649 sii8620_readb(ctx, REG_MDT_RFIFO_STAT); 1650 } 1651 1652 static void sii8620_irq_g2wb(struct sii8620 *ctx) 1653 { 1654 u8 stat = sii8620_readb(ctx, REG_MDT_INT_0); 1655 1656 if (stat & BIT_MDT_IDLE_AFTER_HAWB_DISABLE) 1657 if (sii8620_is_mhl3(ctx)) 1658 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), 1659 MHL_INT_RC_FEAT_COMPLETE); 1660 1661 if (stat & BIT_MDT_RFIFO_DATA_RDY) 1662 sii8620_read_burst(ctx); 1663 1664 if (stat & BIT_MDT_XFIFO_EMPTY) 1665 sii8620_write(ctx, REG_MDT_XMIT_CTRL, 0); 1666 1667 sii8620_write(ctx, REG_MDT_INT_0, stat); 1668 } 1669 1670 static void sii8620_status_dcap_ready(struct sii8620 *ctx) 1671 { 1672 enum sii8620_mode mode; 1673 1674 mode = ctx->stat[MHL_DST_VERSION] >= 0x30 ? CM_MHL3 : CM_MHL1; 1675 if (mode > ctx->mode) 1676 sii8620_set_mode(ctx, mode); 1677 sii8620_peer_specific_init(ctx); 1678 sii8620_write(ctx, REG_INTR9_MASK, BIT_INTR9_DEVCAP_DONE 1679 | BIT_INTR9_EDID_DONE | BIT_INTR9_EDID_ERROR); 1680 } 1681 1682 static void sii8620_status_changed_path(struct sii8620 *ctx) 1683 { 1684 u8 link_mode; 1685 1686 if (ctx->use_packed_pixel) 1687 link_mode = MHL_DST_LM_CLK_MODE_PACKED_PIXEL; 1688 else 1689 link_mode = MHL_DST_LM_CLK_MODE_NORMAL; 1690 1691 if (ctx->stat[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) 1692 link_mode |= MHL_DST_LM_PATH_ENABLED; 1693 1694 sii8620_mt_write_stat(ctx, MHL_DST_REG(LINK_MODE), 1695 link_mode); 1696 } 1697 1698 static void sii8620_msc_mr_write_stat(struct sii8620 *ctx) 1699 { 1700 u8 st[MHL_DST_SIZE], xst[MHL_XDS_SIZE]; 1701 1702 sii8620_read_buf(ctx, REG_MHL_STAT_0, st, MHL_DST_SIZE); 1703 sii8620_read_buf(ctx, REG_MHL_EXTSTAT_0, xst, MHL_XDS_SIZE); 1704 1705 sii8620_update_array(ctx->stat, st, MHL_DST_SIZE); 1706 sii8620_update_array(ctx->xstat, xst, MHL_XDS_SIZE); 1707 1708 if (ctx->stat[MHL_DST_CONNECTED_RDY] & st[MHL_DST_CONNECTED_RDY] & 1709 MHL_DST_CONN_DCAP_RDY) { 1710 sii8620_status_dcap_ready(ctx); 1711 1712 if (!sii8620_is_mhl3(ctx)) 1713 sii8620_mt_read_devcap(ctx, false); 1714 } 1715 1716 if (st[MHL_DST_LINK_MODE] & MHL_DST_LM_PATH_ENABLED) 1717 sii8620_status_changed_path(ctx); 1718 } 1719 1720 static void sii8620_ecbus_up(struct sii8620 *ctx, int ret) 1721 { 1722 if (ret < 0) 1723 return; 1724 1725 sii8620_set_mode(ctx, CM_ECBUS_S); 1726 } 1727 1728 static void sii8620_got_ecbus_speed(struct sii8620 *ctx, int ret) 1729 { 1730 if (ret < 0) 1731 return; 1732 1733 sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE), 1734 MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT); 1735 sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP); 1736 sii8620_mt_set_cont(ctx, sii8620_ecbus_up); 1737 } 1738 1739 static void sii8620_mhl_burst_emsc_support_set(struct mhl_burst_emsc_support *d, 1740 enum mhl_burst_id id) 1741 { 1742 sii8620_mhl_burst_hdr_set(&d->hdr, MHL_BURST_ID_EMSC_SUPPORT); 1743 d->num_entries = 1; 1744 d->burst_id[0] = cpu_to_be16(id); 1745 } 1746 1747 static void sii8620_send_features(struct sii8620 *ctx) 1748 { 1749 u8 buf[16]; 1750 1751 sii8620_write(ctx, REG_MDT_XMIT_CTRL, BIT_MDT_XMIT_CTRL_EN 1752 | BIT_MDT_XMIT_CTRL_FIXED_BURST_LEN); 1753 sii8620_mhl_burst_emsc_support_set((void *)buf, 1754 MHL_BURST_ID_HID_PAYLOAD); 1755 sii8620_write_buf(ctx, REG_MDT_XMIT_WRITE_PORT, buf, ARRAY_SIZE(buf)); 1756 } 1757 1758 static bool sii8620_rcp_consume(struct sii8620 *ctx, u8 scancode) 1759 { 1760 bool pressed = !(scancode & MHL_RCP_KEY_RELEASED_MASK); 1761 1762 scancode &= MHL_RCP_KEY_ID_MASK; 1763 1764 if (!IS_ENABLED(CONFIG_RC_CORE) || !ctx->rc_dev) 1765 return false; 1766 1767 if (pressed) 1768 rc_keydown(ctx->rc_dev, RC_PROTO_CEC, scancode, 0); 1769 else 1770 rc_keyup(ctx->rc_dev); 1771 1772 return true; 1773 } 1774 1775 static void sii8620_msc_mr_set_int(struct sii8620 *ctx) 1776 { 1777 u8 ints[MHL_INT_SIZE]; 1778 1779 sii8620_read_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); 1780 sii8620_write_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); 1781 1782 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_DCAP_CHG) { 1783 switch (ctx->mode) { 1784 case CM_MHL3: 1785 sii8620_mt_read_xdevcap_reg(ctx, MHL_XDC_ECBUS_SPEEDS); 1786 sii8620_mt_set_cont(ctx, sii8620_got_ecbus_speed); 1787 break; 1788 case CM_ECBUS_S: 1789 sii8620_mt_read_devcap(ctx, true); 1790 break; 1791 default: 1792 break; 1793 } 1794 } 1795 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_REQ) 1796 sii8620_send_features(ctx); 1797 if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_FEAT_COMPLETE) { 1798 ctx->feature_complete = true; 1799 if (ctx->edid) 1800 sii8620_enable_hpd(ctx); 1801 } 1802 } 1803 1804 static struct sii8620_mt_msg *sii8620_msc_msg_first(struct sii8620 *ctx) 1805 { 1806 struct device *dev = ctx->dev; 1807 1808 if (list_empty(&ctx->mt_queue)) { 1809 dev_err(dev, "unexpected MSC MT response\n"); 1810 return NULL; 1811 } 1812 1813 return list_first_entry(&ctx->mt_queue, struct sii8620_mt_msg, node); 1814 } 1815 1816 static void sii8620_msc_mt_done(struct sii8620 *ctx) 1817 { 1818 struct sii8620_mt_msg *msg = sii8620_msc_msg_first(ctx); 1819 1820 if (!msg) 1821 return; 1822 1823 msg->ret = sii8620_readb(ctx, REG_MSC_MT_RCVD_DATA0); 1824 ctx->mt_state = MT_STATE_DONE; 1825 } 1826 1827 static void sii8620_msc_mr_msc_msg(struct sii8620 *ctx) 1828 { 1829 struct sii8620_mt_msg *msg; 1830 u8 buf[2]; 1831 1832 sii8620_read_buf(ctx, REG_MSC_MR_MSC_MSG_RCVD_1ST_DATA, buf, 2); 1833 1834 switch (buf[0]) { 1835 case MHL_MSC_MSG_RAPK: 1836 msg = sii8620_msc_msg_first(ctx); 1837 if (!msg) 1838 return; 1839 msg->ret = buf[1]; 1840 ctx->mt_state = MT_STATE_DONE; 1841 break; 1842 case MHL_MSC_MSG_RCP: 1843 if (!sii8620_rcp_consume(ctx, buf[1])) 1844 sii8620_mt_rcpe(ctx, 1845 MHL_RCPE_STATUS_INEFFECTIVE_KEY_CODE); 1846 sii8620_mt_rcpk(ctx, buf[1]); 1847 break; 1848 default: 1849 dev_err(ctx->dev, "%s message type %d,%d not supported", 1850 __func__, buf[0], buf[1]); 1851 } 1852 } 1853 1854 static void sii8620_irq_msc(struct sii8620 *ctx) 1855 { 1856 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_0); 1857 1858 if (stat & ~BIT_CBUS_HPD_CHG) 1859 sii8620_write(ctx, REG_CBUS_INT_0, stat & ~BIT_CBUS_HPD_CHG); 1860 1861 if (stat & BIT_CBUS_HPD_CHG) { 1862 u8 cbus_stat = sii8620_readb(ctx, REG_CBUS_STATUS); 1863 1864 if ((cbus_stat ^ ctx->cbus_status) & BIT_CBUS_STATUS_CBUS_HPD) { 1865 sii8620_write(ctx, REG_CBUS_INT_0, BIT_CBUS_HPD_CHG); 1866 } else { 1867 stat ^= BIT_CBUS_STATUS_CBUS_HPD; 1868 cbus_stat ^= BIT_CBUS_STATUS_CBUS_HPD; 1869 } 1870 ctx->cbus_status = cbus_stat; 1871 } 1872 1873 if (stat & BIT_CBUS_MSC_MR_WRITE_STAT) 1874 sii8620_msc_mr_write_stat(ctx); 1875 1876 if (stat & BIT_CBUS_HPD_CHG) { 1877 if (ctx->cbus_status & BIT_CBUS_STATUS_CBUS_HPD) { 1878 ctx->sink_detected = true; 1879 sii8620_identify_sink(ctx); 1880 } else { 1881 sii8620_hpd_unplugged(ctx); 1882 } 1883 } 1884 1885 if (stat & BIT_CBUS_MSC_MR_SET_INT) 1886 sii8620_msc_mr_set_int(ctx); 1887 1888 if (stat & BIT_CBUS_MSC_MT_DONE) 1889 sii8620_msc_mt_done(ctx); 1890 1891 if (stat & BIT_CBUS_MSC_MR_MSC_MSG) 1892 sii8620_msc_mr_msc_msg(ctx); 1893 } 1894 1895 static void sii8620_irq_coc(struct sii8620 *ctx) 1896 { 1897 u8 stat = sii8620_readb(ctx, REG_COC_INTR); 1898 1899 if (stat & BIT_COC_CALIBRATION_DONE) { 1900 u8 cstat = sii8620_readb(ctx, REG_COC_STAT_0); 1901 1902 cstat &= BIT_COC_STAT_0_PLL_LOCKED | MSK_COC_STAT_0_FSM_STATE; 1903 if (cstat == (BIT_COC_STAT_0_PLL_LOCKED | 0x02)) { 1904 sii8620_write_seq_static(ctx, 1905 REG_COC_CTLB, 0, 1906 REG_TRXINTMH, BIT_TDM_INTR_SYNC_DATA 1907 | BIT_TDM_INTR_SYNC_WAIT 1908 ); 1909 } 1910 } 1911 1912 sii8620_write(ctx, REG_COC_INTR, stat); 1913 } 1914 1915 static void sii8620_irq_merr(struct sii8620 *ctx) 1916 { 1917 u8 stat = sii8620_readb(ctx, REG_CBUS_INT_1); 1918 1919 sii8620_write(ctx, REG_CBUS_INT_1, stat); 1920 } 1921 1922 static void sii8620_irq_edid(struct sii8620 *ctx) 1923 { 1924 u8 stat = sii8620_readb(ctx, REG_INTR9); 1925 1926 sii8620_write(ctx, REG_INTR9, stat); 1927 1928 if (stat & BIT_INTR9_DEVCAP_DONE) 1929 ctx->mt_state = MT_STATE_DONE; 1930 } 1931 1932 static void sii8620_irq_scdt(struct sii8620 *ctx) 1933 { 1934 u8 stat = sii8620_readb(ctx, REG_INTR5); 1935 1936 if (stat & BIT_INTR_SCDT_CHANGE) { 1937 u8 cstat = sii8620_readb(ctx, REG_TMDS_CSTAT_P3); 1938 1939 if (cstat & BIT_TMDS_CSTAT_P3_SCDT) 1940 sii8620_start_video(ctx); 1941 } 1942 1943 sii8620_write(ctx, REG_INTR5, stat); 1944 } 1945 1946 static void sii8620_got_xdevcap(struct sii8620 *ctx, int ret) 1947 { 1948 if (ret < 0) 1949 return; 1950 1951 sii8620_mt_read_devcap(ctx, false); 1952 } 1953 1954 static void sii8620_irq_tdm(struct sii8620 *ctx) 1955 { 1956 u8 stat = sii8620_readb(ctx, REG_TRXINTH); 1957 u8 tdm = sii8620_readb(ctx, REG_TRXSTA2); 1958 1959 if ((tdm & MSK_TDM_SYNCHRONIZED) == VAL_TDM_SYNCHRONIZED) { 1960 ctx->mode = CM_ECBUS_S; 1961 ctx->burst.rx_ack = 0; 1962 ctx->burst.r_size = SII8620_BURST_BUF_LEN; 1963 sii8620_burst_tx_rbuf_info(ctx, SII8620_BURST_BUF_LEN); 1964 sii8620_mt_read_devcap(ctx, true); 1965 sii8620_mt_set_cont(ctx, sii8620_got_xdevcap); 1966 } else { 1967 sii8620_write_seq_static(ctx, 1968 REG_MHL_PLL_CTL2, 0, 1969 REG_MHL_PLL_CTL2, BIT_MHL_PLL_CTL2_CLKDETECT_EN 1970 ); 1971 } 1972 1973 sii8620_write(ctx, REG_TRXINTH, stat); 1974 } 1975 1976 static void sii8620_irq_block(struct sii8620 *ctx) 1977 { 1978 u8 stat = sii8620_readb(ctx, REG_EMSCINTR); 1979 1980 if (stat & BIT_EMSCINTR_SPI_DVLD) { 1981 u8 bstat = sii8620_readb(ctx, REG_SPIBURSTSTAT); 1982 1983 if (bstat & BIT_SPIBURSTSTAT_EMSC_NORMAL_MODE) 1984 sii8620_burst_receive(ctx); 1985 } 1986 1987 sii8620_write(ctx, REG_EMSCINTR, stat); 1988 } 1989 1990 static void sii8620_irq_ddc(struct sii8620 *ctx) 1991 { 1992 u8 stat = sii8620_readb(ctx, REG_INTR3); 1993 1994 if (stat & BIT_DDC_CMD_DONE) { 1995 sii8620_write(ctx, REG_INTR3_MASK, 0); 1996 if (sii8620_is_mhl3(ctx) && !ctx->feature_complete) 1997 sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), 1998 MHL_INT_RC_FEAT_REQ); 1999 else 2000 sii8620_enable_hpd(ctx); 2001 } 2002 sii8620_write(ctx, REG_INTR3, stat); 2003 } 2004 2005 /* endian agnostic, non-volatile version of test_bit */ 2006 static bool sii8620_test_bit(unsigned int nr, const u8 *addr) 2007 { 2008 return 1 & (addr[nr / BITS_PER_BYTE] >> (nr % BITS_PER_BYTE)); 2009 } 2010 2011 static irqreturn_t sii8620_irq_thread(int irq, void *data) 2012 { 2013 static const struct { 2014 int bit; 2015 void (*handler)(struct sii8620 *ctx); 2016 } irq_vec[] = { 2017 { BIT_FAST_INTR_STAT_DISC, sii8620_irq_disc }, 2018 { BIT_FAST_INTR_STAT_G2WB, sii8620_irq_g2wb }, 2019 { BIT_FAST_INTR_STAT_COC, sii8620_irq_coc }, 2020 { BIT_FAST_INTR_STAT_TDM, sii8620_irq_tdm }, 2021 { BIT_FAST_INTR_STAT_MSC, sii8620_irq_msc }, 2022 { BIT_FAST_INTR_STAT_MERR, sii8620_irq_merr }, 2023 { BIT_FAST_INTR_STAT_BLOCK, sii8620_irq_block }, 2024 { BIT_FAST_INTR_STAT_EDID, sii8620_irq_edid }, 2025 { BIT_FAST_INTR_STAT_DDC, sii8620_irq_ddc }, 2026 { BIT_FAST_INTR_STAT_SCDT, sii8620_irq_scdt }, 2027 }; 2028 struct sii8620 *ctx = data; 2029 u8 stats[LEN_FAST_INTR_STAT]; 2030 int i, ret; 2031 2032 mutex_lock(&ctx->lock); 2033 2034 sii8620_read_buf(ctx, REG_FAST_INTR_STAT, stats, ARRAY_SIZE(stats)); 2035 for (i = 0; i < ARRAY_SIZE(irq_vec); ++i) 2036 if (sii8620_test_bit(irq_vec[i].bit, stats)) 2037 irq_vec[i].handler(ctx); 2038 2039 sii8620_burst_rx_all(ctx); 2040 sii8620_mt_work(ctx); 2041 sii8620_burst_send(ctx); 2042 2043 ret = sii8620_clear_error(ctx); 2044 if (ret) { 2045 dev_err(ctx->dev, "Error during IRQ handling, %d.\n", ret); 2046 sii8620_mhl_disconnected(ctx); 2047 } 2048 mutex_unlock(&ctx->lock); 2049 2050 return IRQ_HANDLED; 2051 } 2052 2053 static void sii8620_cable_in(struct sii8620 *ctx) 2054 { 2055 struct device *dev = ctx->dev; 2056 u8 ver[5]; 2057 int ret; 2058 2059 ret = sii8620_hw_on(ctx); 2060 if (ret) { 2061 dev_err(dev, "Error powering on, %d.\n", ret); 2062 return; 2063 } 2064 2065 sii8620_read_buf(ctx, REG_VND_IDL, ver, ARRAY_SIZE(ver)); 2066 ret = sii8620_clear_error(ctx); 2067 if (ret) { 2068 dev_err(dev, "Error accessing I2C bus, %d.\n", ret); 2069 return; 2070 } 2071 2072 dev_info(dev, "ChipID %02x%02x:%02x%02x rev %02x.\n", ver[1], ver[0], 2073 ver[3], ver[2], ver[4]); 2074 2075 sii8620_write(ctx, REG_DPD, 2076 BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN); 2077 2078 sii8620_xtal_set_rate(ctx); 2079 sii8620_disconnect(ctx); 2080 2081 sii8620_write_seq_static(ctx, 2082 REG_MHL_CBUS_CTL0, VAL_MHL_CBUS_CTL0_CBUS_DRV_SEL_STRONG 2083 | VAL_MHL_CBUS_CTL0_CBUS_RGND_VBIAS_734, 2084 REG_MHL_CBUS_CTL1, VAL_MHL_CBUS_CTL1_1115_OHM, 2085 REG_DPD, BIT_DPD_PWRON_PLL | BIT_DPD_PDNTX12 | BIT_DPD_OSC_EN, 2086 ); 2087 2088 ret = sii8620_clear_error(ctx); 2089 if (ret) { 2090 dev_err(dev, "Error accessing I2C bus, %d.\n", ret); 2091 return; 2092 } 2093 2094 enable_irq(to_i2c_client(ctx->dev)->irq); 2095 } 2096 2097 static void sii8620_init_rcp_input_dev(struct sii8620 *ctx) 2098 { 2099 struct rc_dev *rc_dev; 2100 int ret; 2101 2102 if (!IS_ENABLED(CONFIG_RC_CORE)) 2103 return; 2104 2105 rc_dev = rc_allocate_device(RC_DRIVER_SCANCODE); 2106 if (!rc_dev) { 2107 dev_err(ctx->dev, "Failed to allocate RC device\n"); 2108 ctx->error = -ENOMEM; 2109 return; 2110 } 2111 2112 rc_dev->input_phys = "sii8620/input0"; 2113 rc_dev->input_id.bustype = BUS_VIRTUAL; 2114 rc_dev->map_name = RC_MAP_CEC; 2115 rc_dev->allowed_protocols = RC_PROTO_BIT_CEC; 2116 rc_dev->driver_name = "sii8620"; 2117 rc_dev->device_name = "sii8620"; 2118 2119 ret = rc_register_device(rc_dev); 2120 2121 if (ret) { 2122 dev_err(ctx->dev, "Failed to register RC device\n"); 2123 ctx->error = ret; 2124 rc_free_device(rc_dev); 2125 return; 2126 } 2127 ctx->rc_dev = rc_dev; 2128 } 2129 2130 static void sii8620_cable_out(struct sii8620 *ctx) 2131 { 2132 disable_irq(to_i2c_client(ctx->dev)->irq); 2133 sii8620_hw_off(ctx); 2134 } 2135 2136 static void sii8620_extcon_work(struct work_struct *work) 2137 { 2138 struct sii8620 *ctx = 2139 container_of(work, struct sii8620, extcon_wq); 2140 int state = extcon_get_state(ctx->extcon, EXTCON_DISP_MHL); 2141 2142 if (state == ctx->cable_state) 2143 return; 2144 2145 ctx->cable_state = state; 2146 2147 if (state > 0) 2148 sii8620_cable_in(ctx); 2149 else 2150 sii8620_cable_out(ctx); 2151 } 2152 2153 static int sii8620_extcon_notifier(struct notifier_block *self, 2154 unsigned long event, void *ptr) 2155 { 2156 struct sii8620 *ctx = 2157 container_of(self, struct sii8620, extcon_nb); 2158 2159 schedule_work(&ctx->extcon_wq); 2160 2161 return NOTIFY_DONE; 2162 } 2163 2164 static int sii8620_extcon_init(struct sii8620 *ctx) 2165 { 2166 struct extcon_dev *edev; 2167 struct device_node *musb, *muic; 2168 int ret; 2169 2170 /* get micro-USB connector node */ 2171 musb = of_graph_get_remote_node(ctx->dev->of_node, 1, -1); 2172 /* next get micro-USB Interface Controller node */ 2173 muic = of_get_next_parent(musb); 2174 2175 if (!muic) { 2176 dev_info(ctx->dev, "no extcon found, switching to 'always on' mode\n"); 2177 return 0; 2178 } 2179 2180 edev = extcon_find_edev_by_node(muic); 2181 of_node_put(muic); 2182 if (IS_ERR(edev)) { 2183 if (PTR_ERR(edev) == -EPROBE_DEFER) 2184 return -EPROBE_DEFER; 2185 dev_err(ctx->dev, "Invalid or missing extcon\n"); 2186 return PTR_ERR(edev); 2187 } 2188 2189 ctx->extcon = edev; 2190 ctx->extcon_nb.notifier_call = sii8620_extcon_notifier; 2191 INIT_WORK(&ctx->extcon_wq, sii8620_extcon_work); 2192 ret = extcon_register_notifier(edev, EXTCON_DISP_MHL, &ctx->extcon_nb); 2193 if (ret) { 2194 dev_err(ctx->dev, "failed to register notifier for MHL\n"); 2195 return ret; 2196 } 2197 2198 return 0; 2199 } 2200 2201 static inline struct sii8620 *bridge_to_sii8620(struct drm_bridge *bridge) 2202 { 2203 return container_of(bridge, struct sii8620, bridge); 2204 } 2205 2206 static int sii8620_attach(struct drm_bridge *bridge, 2207 struct drm_encoder *encoder, 2208 enum drm_bridge_attach_flags flags) 2209 { 2210 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2211 2212 sii8620_init_rcp_input_dev(ctx); 2213 2214 return sii8620_clear_error(ctx); 2215 } 2216 2217 static void sii8620_detach(struct drm_bridge *bridge) 2218 { 2219 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2220 2221 if (!IS_ENABLED(CONFIG_RC_CORE)) 2222 return; 2223 2224 rc_unregister_device(ctx->rc_dev); 2225 rc_free_device(ctx->rc_dev); 2226 } 2227 2228 static int sii8620_is_packing_required(struct sii8620 *ctx, 2229 const struct drm_display_mode *mode) 2230 { 2231 int max_pclk, max_pclk_pp_mode; 2232 2233 if (sii8620_is_mhl3(ctx)) { 2234 max_pclk = MHL3_MAX_PCLK; 2235 max_pclk_pp_mode = MHL3_MAX_PCLK_PP_MODE; 2236 } else { 2237 max_pclk = MHL1_MAX_PCLK; 2238 max_pclk_pp_mode = MHL1_MAX_PCLK_PP_MODE; 2239 } 2240 2241 if (mode->clock < max_pclk) 2242 return 0; 2243 else if (mode->clock < max_pclk_pp_mode) 2244 return 1; 2245 else 2246 return -1; 2247 } 2248 2249 static enum drm_mode_status sii8620_mode_valid(struct drm_bridge *bridge, 2250 const struct drm_display_info *info, 2251 const struct drm_display_mode *mode) 2252 { 2253 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2254 int pack_required = sii8620_is_packing_required(ctx, mode); 2255 bool can_pack = ctx->devcap[MHL_DCAP_VID_LINK_MODE] & 2256 MHL_DCAP_VID_LINK_PPIXEL; 2257 2258 switch (pack_required) { 2259 case 0: 2260 return MODE_OK; 2261 case 1: 2262 return (can_pack) ? MODE_OK : MODE_CLOCK_HIGH; 2263 default: 2264 return MODE_CLOCK_HIGH; 2265 } 2266 } 2267 2268 static bool sii8620_mode_fixup(struct drm_bridge *bridge, 2269 const struct drm_display_mode *mode, 2270 struct drm_display_mode *adjusted_mode) 2271 { 2272 struct sii8620 *ctx = bridge_to_sii8620(bridge); 2273 2274 mutex_lock(&ctx->lock); 2275 2276 ctx->use_packed_pixel = sii8620_is_packing_required(ctx, adjusted_mode); 2277 2278 mutex_unlock(&ctx->lock); 2279 2280 return true; 2281 } 2282 2283 static const struct drm_bridge_funcs sii8620_bridge_funcs = { 2284 .atomic_create_state = drm_atomic_helper_bridge_create_state, 2285 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2286 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2287 .attach = sii8620_attach, 2288 .detach = sii8620_detach, 2289 .mode_fixup = sii8620_mode_fixup, 2290 .mode_valid = sii8620_mode_valid, 2291 }; 2292 2293 static int sii8620_probe(struct i2c_client *client) 2294 { 2295 struct device *dev = &client->dev; 2296 struct sii8620 *ctx; 2297 int ret; 2298 2299 ctx = devm_drm_bridge_alloc(dev, struct sii8620, bridge, 2300 &sii8620_bridge_funcs); 2301 if (IS_ERR(ctx)) 2302 return PTR_ERR(ctx); 2303 2304 ctx->dev = dev; 2305 mutex_init(&ctx->lock); 2306 INIT_LIST_HEAD(&ctx->mt_queue); 2307 2308 ctx->clk_xtal = devm_clk_get(dev, "xtal"); 2309 if (IS_ERR(ctx->clk_xtal)) 2310 return dev_err_probe(dev, PTR_ERR(ctx->clk_xtal), 2311 "failed to get xtal clock from DT\n"); 2312 2313 if (!client->irq) { 2314 dev_err(dev, "no irq provided\n"); 2315 return -EINVAL; 2316 } 2317 irq_set_status_flags(client->irq, IRQ_NOAUTOEN); 2318 ret = devm_request_threaded_irq(dev, client->irq, NULL, 2319 sii8620_irq_thread, 2320 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 2321 "sii8620", ctx); 2322 if (ret < 0) 2323 return dev_err_probe(dev, ret, 2324 "failed to install IRQ handler\n"); 2325 2326 ctx->gpio_reset = devm_gpiod_get(dev, "reset", GPIOD_OUT_HIGH); 2327 if (IS_ERR(ctx->gpio_reset)) 2328 return dev_err_probe(dev, PTR_ERR(ctx->gpio_reset), 2329 "failed to get reset gpio from DT\n"); 2330 2331 ctx->supplies[0].supply = "cvcc10"; 2332 ctx->supplies[1].supply = "iovcc18"; 2333 ret = devm_regulator_bulk_get(dev, 2, ctx->supplies); 2334 if (ret) 2335 return ret; 2336 2337 ret = sii8620_extcon_init(ctx); 2338 if (ret < 0) { 2339 dev_err(ctx->dev, "failed to initialize EXTCON\n"); 2340 return ret; 2341 } 2342 2343 i2c_set_clientdata(client, ctx); 2344 2345 ctx->bridge.of_node = dev->of_node; 2346 drm_bridge_add(&ctx->bridge); 2347 2348 if (!ctx->extcon) 2349 sii8620_cable_in(ctx); 2350 2351 return 0; 2352 } 2353 2354 static void sii8620_remove(struct i2c_client *client) 2355 { 2356 struct sii8620 *ctx = i2c_get_clientdata(client); 2357 2358 if (ctx->extcon) { 2359 extcon_unregister_notifier(ctx->extcon, EXTCON_DISP_MHL, 2360 &ctx->extcon_nb); 2361 flush_work(&ctx->extcon_wq); 2362 if (ctx->cable_state > 0) 2363 sii8620_cable_out(ctx); 2364 } else { 2365 sii8620_cable_out(ctx); 2366 } 2367 drm_bridge_remove(&ctx->bridge); 2368 } 2369 2370 static const struct of_device_id sii8620_dt_match[] = { 2371 { .compatible = "sil,sii8620" }, 2372 { }, 2373 }; 2374 MODULE_DEVICE_TABLE(of, sii8620_dt_match); 2375 2376 static const struct i2c_device_id sii8620_id[] = { 2377 { .name = "sii8620" }, 2378 { } 2379 }; 2380 2381 MODULE_DEVICE_TABLE(i2c, sii8620_id); 2382 static struct i2c_driver sii8620_driver = { 2383 .driver = { 2384 .name = "sii8620", 2385 .of_match_table = sii8620_dt_match, 2386 }, 2387 .probe = sii8620_probe, 2388 .remove = sii8620_remove, 2389 .id_table = sii8620_id, 2390 }; 2391 2392 module_i2c_driver(sii8620_driver); 2393 MODULE_DESCRIPTION("Silicon Image SiI8620 HDMI/MHL bridge driver"); 2394 MODULE_LICENSE("GPL v2"); 2395