1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2017 Samsung Electronics 4 * 5 * Authors: 6 * Tomasz Stanislawski <t.stanislaws@samsung.com> 7 * Maciej Purski <m.purski@samsung.com> 8 * 9 * Based on sii9234 driver created by: 10 * Adam Hampson <ahampson@sta.samsung.com> 11 * Erik Gilling <konkers@android.com> 12 * Shankar Bandal <shankar.b@samsung.com> 13 * Dharam Kumar <dharam.kr@samsung.com> 14 */ 15 #include <drm/bridge/mhl.h> 16 #include <drm/drm_atomic_state_helper.h> 17 #include <drm/drm_bridge.h> 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_edid.h> 20 21 #include <linux/delay.h> 22 #include <linux/err.h> 23 #include <linux/gpio/consumer.h> 24 #include <linux/i2c.h> 25 #include <linux/interrupt.h> 26 #include <linux/irq.h> 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/mutex.h> 30 #include <linux/regulator/consumer.h> 31 #include <linux/slab.h> 32 33 #define CBUS_DEVCAP_OFFSET 0x80 34 35 #define SII9234_MHL_VERSION 0x11 36 #define SII9234_SCRATCHPAD_SIZE 0x10 37 #define SII9234_INT_STAT_SIZE 0x33 38 39 #define BIT_TMDS_CCTRL_TMDS_OE BIT(4) 40 #define MHL_HPD_OUT_OVR_EN BIT(4) 41 #define MHL_HPD_OUT_OVR_VAL BIT(5) 42 #define MHL_INIT_TIMEOUT 0x0C 43 44 /* MHL Tx registers and bits */ 45 #define MHL_TX_SRST 0x05 46 #define MHL_TX_SYSSTAT_REG 0x09 47 #define MHL_TX_INTR1_REG 0x71 48 #define MHL_TX_INTR4_REG 0x74 49 #define MHL_TX_INTR1_ENABLE_REG 0x75 50 #define MHL_TX_INTR4_ENABLE_REG 0x78 51 #define MHL_TX_INT_CTRL_REG 0x79 52 #define MHL_TX_TMDS_CCTRL 0x80 53 #define MHL_TX_DISC_CTRL1_REG 0x90 54 #define MHL_TX_DISC_CTRL2_REG 0x91 55 #define MHL_TX_DISC_CTRL3_REG 0x92 56 #define MHL_TX_DISC_CTRL4_REG 0x93 57 #define MHL_TX_DISC_CTRL5_REG 0x94 58 #define MHL_TX_DISC_CTRL6_REG 0x95 59 #define MHL_TX_DISC_CTRL7_REG 0x96 60 #define MHL_TX_DISC_CTRL8_REG 0x97 61 #define MHL_TX_STAT2_REG 0x99 62 #define MHL_TX_MHLTX_CTL1_REG 0xA0 63 #define MHL_TX_MHLTX_CTL2_REG 0xA1 64 #define MHL_TX_MHLTX_CTL4_REG 0xA3 65 #define MHL_TX_MHLTX_CTL6_REG 0xA5 66 #define MHL_TX_MHLTX_CTL7_REG 0xA6 67 68 #define RSEN_STATUS BIT(2) 69 #define HPD_CHANGE_INT BIT(6) 70 #define RSEN_CHANGE_INT BIT(5) 71 #define RGND_READY_INT BIT(6) 72 #define VBUS_LOW_INT BIT(5) 73 #define CBUS_LKOUT_INT BIT(4) 74 #define MHL_DISC_FAIL_INT BIT(3) 75 #define MHL_EST_INT BIT(2) 76 #define HPD_CHANGE_INT_MASK BIT(6) 77 #define RSEN_CHANGE_INT_MASK BIT(5) 78 79 #define RGND_READY_MASK BIT(6) 80 #define CBUS_LKOUT_MASK BIT(4) 81 #define MHL_DISC_FAIL_MASK BIT(3) 82 #define MHL_EST_MASK BIT(2) 83 84 #define SKIP_GND BIT(6) 85 86 #define ATT_THRESH_SHIFT 0x04 87 #define ATT_THRESH_MASK (0x03 << ATT_THRESH_SHIFT) 88 #define USB_D_OEN BIT(3) 89 #define DEGLITCH_TIME_MASK 0x07 90 #define DEGLITCH_TIME_2MS 0 91 #define DEGLITCH_TIME_4MS 1 92 #define DEGLITCH_TIME_8MS 2 93 #define DEGLITCH_TIME_16MS 3 94 #define DEGLITCH_TIME_40MS 4 95 #define DEGLITCH_TIME_50MS 5 96 #define DEGLITCH_TIME_60MS 6 97 #define DEGLITCH_TIME_128MS 7 98 99 #define USB_D_OVR BIT(7) 100 #define USB_ID_OVR BIT(6) 101 #define DVRFLT_SEL BIT(5) 102 #define BLOCK_RGND_INT BIT(4) 103 #define SKIP_DEG BIT(3) 104 #define CI2CA_POL BIT(2) 105 #define CI2CA_WKUP BIT(1) 106 #define SINGLE_ATT BIT(0) 107 108 #define USB_D_ODN BIT(5) 109 #define VBUS_CHECK BIT(2) 110 #define RGND_INTP_MASK 0x03 111 #define RGND_INTP_OPEN 0 112 #define RGND_INTP_2K 1 113 #define RGND_INTP_1K 2 114 #define RGND_INTP_SHORT 3 115 116 /* HDMI registers */ 117 #define HDMI_RX_TMDS0_CCTRL1_REG 0x10 118 #define HDMI_RX_TMDS_CLK_EN_REG 0x11 119 #define HDMI_RX_TMDS_CH_EN_REG 0x12 120 #define HDMI_RX_PLL_CALREFSEL_REG 0x17 121 #define HDMI_RX_PLL_VCOCAL_REG 0x1A 122 #define HDMI_RX_EQ_DATA0_REG 0x22 123 #define HDMI_RX_EQ_DATA1_REG 0x23 124 #define HDMI_RX_EQ_DATA2_REG 0x24 125 #define HDMI_RX_EQ_DATA3_REG 0x25 126 #define HDMI_RX_EQ_DATA4_REG 0x26 127 #define HDMI_RX_TMDS_ZONE_CTRL_REG 0x4C 128 #define HDMI_RX_TMDS_MODE_CTRL_REG 0x4D 129 130 /* CBUS registers */ 131 #define CBUS_INT_STATUS_1_REG 0x08 132 #define CBUS_INTR1_ENABLE_REG 0x09 133 #define CBUS_MSC_REQ_ABORT_REASON_REG 0x0D 134 #define CBUS_INT_STATUS_2_REG 0x1E 135 #define CBUS_INTR2_ENABLE_REG 0x1F 136 #define CBUS_LINK_CONTROL_2_REG 0x31 137 #define CBUS_MHL_STATUS_REG_0 0xB0 138 #define CBUS_MHL_STATUS_REG_1 0xB1 139 140 #define BIT_CBUS_RESET BIT(3) 141 #define SET_HPD_DOWNSTREAM BIT(6) 142 143 /* TPI registers */ 144 #define TPI_DPD_REG 0x3D 145 146 /* Timeouts in msec */ 147 #define T_SRC_VBUS_CBUS_TO_STABLE 200 148 #define T_SRC_CBUS_FLOAT 100 149 #define T_SRC_CBUS_DEGLITCH 2 150 #define T_SRC_RXSENSE_DEGLITCH 110 151 152 #define MHL1_MAX_CLK 75000 /* in kHz */ 153 154 #define I2C_TPI_ADDR 0x3D 155 #define I2C_HDMI_ADDR 0x49 156 #define I2C_CBUS_ADDR 0x64 157 158 enum sii9234_state { 159 ST_OFF, 160 ST_D3, 161 ST_RGND_INIT, 162 ST_RGND_1K, 163 ST_RSEN_HIGH, 164 ST_MHL_ESTABLISHED, 165 ST_FAILURE_DISCOVERY, 166 ST_FAILURE, 167 }; 168 169 struct sii9234 { 170 struct i2c_client *client[4]; 171 struct drm_bridge bridge; 172 struct device *dev; 173 struct gpio_desc *gpio_reset; 174 int i2c_error; 175 struct regulator_bulk_data supplies[4]; 176 177 struct mutex lock; /* Protects fields below and device registers */ 178 enum sii9234_state state; 179 }; 180 181 enum sii9234_client_id { 182 I2C_MHL, 183 I2C_TPI, 184 I2C_HDMI, 185 I2C_CBUS, 186 }; 187 188 static const char * const sii9234_client_name[] = { 189 [I2C_MHL] = "MHL", 190 [I2C_TPI] = "TPI", 191 [I2C_HDMI] = "HDMI", 192 [I2C_CBUS] = "CBUS", 193 }; 194 195 static int sii9234_writeb(struct sii9234 *ctx, int id, int offset, 196 int value) 197 { 198 int ret; 199 struct i2c_client *client = ctx->client[id]; 200 201 if (ctx->i2c_error) 202 return ctx->i2c_error; 203 204 ret = i2c_smbus_write_byte_data(client, offset, value); 205 if (ret < 0) 206 dev_err(ctx->dev, "writeb: %4s[0x%02x] <- 0x%02x\n", 207 sii9234_client_name[id], offset, value); 208 ctx->i2c_error = ret; 209 210 return ret; 211 } 212 213 static int sii9234_writebm(struct sii9234 *ctx, int id, int offset, 214 int value, int mask) 215 { 216 int ret; 217 struct i2c_client *client = ctx->client[id]; 218 219 if (ctx->i2c_error) 220 return ctx->i2c_error; 221 222 ret = i2c_smbus_write_byte(client, offset); 223 if (ret < 0) { 224 dev_err(ctx->dev, "writebm: %4s[0x%02x] <- 0x%02x\n", 225 sii9234_client_name[id], offset, value); 226 ctx->i2c_error = ret; 227 return ret; 228 } 229 230 ret = i2c_smbus_read_byte(client); 231 if (ret < 0) { 232 dev_err(ctx->dev, "writebm: %4s[0x%02x] <- 0x%02x\n", 233 sii9234_client_name[id], offset, value); 234 ctx->i2c_error = ret; 235 return ret; 236 } 237 238 value = (value & mask) | (ret & ~mask); 239 240 ret = i2c_smbus_write_byte_data(client, offset, value); 241 if (ret < 0) { 242 dev_err(ctx->dev, "writebm: %4s[0x%02x] <- 0x%02x\n", 243 sii9234_client_name[id], offset, value); 244 ctx->i2c_error = ret; 245 } 246 247 return ret; 248 } 249 250 static int sii9234_readb(struct sii9234 *ctx, int id, int offset) 251 { 252 int ret; 253 struct i2c_client *client = ctx->client[id]; 254 255 if (ctx->i2c_error) 256 return ctx->i2c_error; 257 258 ret = i2c_smbus_write_byte(client, offset); 259 if (ret < 0) { 260 dev_err(ctx->dev, "readb: %4s[0x%02x]\n", 261 sii9234_client_name[id], offset); 262 ctx->i2c_error = ret; 263 return ret; 264 } 265 266 ret = i2c_smbus_read_byte(client); 267 if (ret < 0) { 268 dev_err(ctx->dev, "readb: %4s[0x%02x]\n", 269 sii9234_client_name[id], offset); 270 ctx->i2c_error = ret; 271 } 272 273 return ret; 274 } 275 276 static int sii9234_clear_error(struct sii9234 *ctx) 277 { 278 int ret = ctx->i2c_error; 279 280 ctx->i2c_error = 0; 281 282 return ret; 283 } 284 285 #define mhl_tx_writeb(sii9234, offset, value) \ 286 sii9234_writeb(sii9234, I2C_MHL, offset, value) 287 #define mhl_tx_writebm(sii9234, offset, value, mask) \ 288 sii9234_writebm(sii9234, I2C_MHL, offset, value, mask) 289 #define mhl_tx_readb(sii9234, offset) \ 290 sii9234_readb(sii9234, I2C_MHL, offset) 291 #define cbus_writeb(sii9234, offset, value) \ 292 sii9234_writeb(sii9234, I2C_CBUS, offset, value) 293 #define cbus_writebm(sii9234, offset, value, mask) \ 294 sii9234_writebm(sii9234, I2C_CBUS, offset, value, mask) 295 #define cbus_readb(sii9234, offset) \ 296 sii9234_readb(sii9234, I2C_CBUS, offset) 297 #define hdmi_writeb(sii9234, offset, value) \ 298 sii9234_writeb(sii9234, I2C_HDMI, offset, value) 299 #define hdmi_writebm(sii9234, offset, value, mask) \ 300 sii9234_writebm(sii9234, I2C_HDMI, offset, value, mask) 301 #define hdmi_readb(sii9234, offset) \ 302 sii9234_readb(sii9234, I2C_HDMI, offset) 303 #define tpi_writeb(sii9234, offset, value) \ 304 sii9234_writeb(sii9234, I2C_TPI, offset, value) 305 #define tpi_writebm(sii9234, offset, value, mask) \ 306 sii9234_writebm(sii9234, I2C_TPI, offset, value, mask) 307 #define tpi_readb(sii9234, offset) \ 308 sii9234_readb(sii9234, I2C_TPI, offset) 309 310 static u8 sii9234_tmds_control(struct sii9234 *ctx, bool enable) 311 { 312 mhl_tx_writebm(ctx, MHL_TX_TMDS_CCTRL, enable ? ~0 : 0, 313 BIT_TMDS_CCTRL_TMDS_OE); 314 mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, enable ? ~0 : 0, 315 MHL_HPD_OUT_OVR_EN | MHL_HPD_OUT_OVR_VAL); 316 return sii9234_clear_error(ctx); 317 } 318 319 static int sii9234_cbus_reset(struct sii9234 *ctx) 320 { 321 int i; 322 323 mhl_tx_writebm(ctx, MHL_TX_SRST, ~0, BIT_CBUS_RESET); 324 msleep(T_SRC_CBUS_DEGLITCH); 325 mhl_tx_writebm(ctx, MHL_TX_SRST, 0, BIT_CBUS_RESET); 326 327 for (i = 0; i < 4; i++) { 328 /* 329 * Enable WRITE_STAT interrupt for writes to all 330 * 4 MSC Status registers. 331 */ 332 cbus_writeb(ctx, 0xE0 + i, 0xF2); 333 /* 334 * Enable SET_INT interrupt for writes to all 335 * 4 MSC Interrupt registers. 336 */ 337 cbus_writeb(ctx, 0xF0 + i, 0xF2); 338 } 339 340 return sii9234_clear_error(ctx); 341 } 342 343 /* Require to check mhl information of samsung in cbus_init_register */ 344 static int sii9234_cbus_init(struct sii9234 *ctx) 345 { 346 cbus_writeb(ctx, 0x07, 0xF2); 347 cbus_writeb(ctx, 0x40, 0x03); 348 cbus_writeb(ctx, 0x42, 0x06); 349 cbus_writeb(ctx, 0x36, 0x0C); 350 cbus_writeb(ctx, 0x3D, 0xFD); 351 cbus_writeb(ctx, 0x1C, 0x01); 352 cbus_writeb(ctx, 0x1D, 0x0F); 353 cbus_writeb(ctx, 0x44, 0x02); 354 /* Setup our devcap */ 355 cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEV_STATE, 0x00); 356 cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_MHL_VERSION, 357 SII9234_MHL_VERSION); 358 cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_CAT, 359 MHL_DCAP_CAT_SOURCE); 360 cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_H, 0x01); 361 cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_ADOPTER_ID_L, 0x41); 362 cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VID_LINK_MODE, 363 MHL_DCAP_VID_LINK_RGB444 | MHL_DCAP_VID_LINK_YCBCR444); 364 cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_VIDEO_TYPE, 365 MHL_DCAP_VT_GRAPHICS); 366 cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_LOG_DEV_MAP, 367 MHL_DCAP_LD_GUI); 368 cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_BANDWIDTH, 0x0F); 369 cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_FEATURE_FLAG, 370 MHL_DCAP_FEATURE_RCP_SUPPORT | MHL_DCAP_FEATURE_RAP_SUPPORT 371 | MHL_DCAP_FEATURE_SP_SUPPORT); 372 cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_H, 0x0); 373 cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_DEVICE_ID_L, 0x0); 374 cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_SCRATCHPAD_SIZE, 375 SII9234_SCRATCHPAD_SIZE); 376 cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_INT_STAT_SIZE, 377 SII9234_INT_STAT_SIZE); 378 cbus_writeb(ctx, CBUS_DEVCAP_OFFSET + MHL_DCAP_RESERVED, 0); 379 cbus_writebm(ctx, 0x31, 0x0C, 0x0C); 380 cbus_writeb(ctx, 0x30, 0x01); 381 cbus_writebm(ctx, 0x3C, 0x30, 0x38); 382 cbus_writebm(ctx, 0x22, 0x0D, 0x0F); 383 cbus_writebm(ctx, 0x2E, 0x15, 0x15); 384 cbus_writeb(ctx, CBUS_INTR1_ENABLE_REG, 0); 385 cbus_writeb(ctx, CBUS_INTR2_ENABLE_REG, 0); 386 387 return sii9234_clear_error(ctx); 388 } 389 390 static void force_usb_id_switch_open(struct sii9234 *ctx) 391 { 392 /* Disable CBUS discovery */ 393 mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, 0, 0x01); 394 /* Force USB ID switch to open */ 395 mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, ~0, USB_ID_OVR); 396 mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL3_REG, ~0, 0x86); 397 /* Force upstream HPD to 0 when not in MHL mode. */ 398 mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, 0, 0x30); 399 } 400 401 static void release_usb_id_switch_open(struct sii9234 *ctx) 402 { 403 msleep(T_SRC_CBUS_FLOAT); 404 /* Clear USB ID switch to open */ 405 mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, 0, USB_ID_OVR); 406 /* Enable CBUS discovery */ 407 mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, ~0, 0x01); 408 } 409 410 static int sii9234_power_init(struct sii9234 *ctx) 411 { 412 /* Force the SiI9234 into the D0 state. */ 413 tpi_writeb(ctx, TPI_DPD_REG, 0x3F); 414 /* Enable TxPLL Clock */ 415 hdmi_writeb(ctx, HDMI_RX_TMDS_CLK_EN_REG, 0x01); 416 /* Enable Tx Clock Path & Equalizer */ 417 hdmi_writeb(ctx, HDMI_RX_TMDS_CH_EN_REG, 0x15); 418 /* Power Up TMDS */ 419 mhl_tx_writeb(ctx, 0x08, 0x35); 420 return sii9234_clear_error(ctx); 421 } 422 423 static int sii9234_hdmi_init(struct sii9234 *ctx) 424 { 425 hdmi_writeb(ctx, HDMI_RX_TMDS0_CCTRL1_REG, 0xC1); 426 hdmi_writeb(ctx, HDMI_RX_PLL_CALREFSEL_REG, 0x03); 427 hdmi_writeb(ctx, HDMI_RX_PLL_VCOCAL_REG, 0x20); 428 hdmi_writeb(ctx, HDMI_RX_EQ_DATA0_REG, 0x8A); 429 hdmi_writeb(ctx, HDMI_RX_EQ_DATA1_REG, 0x6A); 430 hdmi_writeb(ctx, HDMI_RX_EQ_DATA2_REG, 0xAA); 431 hdmi_writeb(ctx, HDMI_RX_EQ_DATA3_REG, 0xCA); 432 hdmi_writeb(ctx, HDMI_RX_EQ_DATA4_REG, 0xEA); 433 hdmi_writeb(ctx, HDMI_RX_TMDS_ZONE_CTRL_REG, 0xA0); 434 hdmi_writeb(ctx, HDMI_RX_TMDS_MODE_CTRL_REG, 0x00); 435 mhl_tx_writeb(ctx, MHL_TX_TMDS_CCTRL, 0x34); 436 hdmi_writeb(ctx, 0x45, 0x44); 437 hdmi_writeb(ctx, 0x31, 0x0A); 438 hdmi_writeb(ctx, HDMI_RX_TMDS0_CCTRL1_REG, 0xC1); 439 440 return sii9234_clear_error(ctx); 441 } 442 443 static int sii9234_mhl_tx_ctl_int(struct sii9234 *ctx) 444 { 445 mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL1_REG, 0xD0); 446 mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL2_REG, 0xFC); 447 mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL4_REG, 0xEB); 448 mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL7_REG, 0x0C); 449 450 return sii9234_clear_error(ctx); 451 } 452 453 static int sii9234_reset(struct sii9234 *ctx) 454 { 455 int ret; 456 457 sii9234_clear_error(ctx); 458 459 ret = sii9234_power_init(ctx); 460 if (ret < 0) 461 return ret; 462 ret = sii9234_cbus_reset(ctx); 463 if (ret < 0) 464 return ret; 465 ret = sii9234_hdmi_init(ctx); 466 if (ret < 0) 467 return ret; 468 ret = sii9234_mhl_tx_ctl_int(ctx); 469 if (ret < 0) 470 return ret; 471 472 /* Enable HDCP Compliance safety */ 473 mhl_tx_writeb(ctx, 0x2B, 0x01); 474 /* CBUS discovery cycle time for each drive and float = 150us */ 475 mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, 0x04, 0x06); 476 /* Clear bit 6 (reg_skip_rgnd) */ 477 mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL2_REG, (1 << 7) /* Reserved */ 478 | 2 << ATT_THRESH_SHIFT | DEGLITCH_TIME_50MS); 479 /* 480 * Changed from 66 to 65 for 94[1:0] = 01 = 5k reg_cbusmhl_pup_sel 481 * 1.8V CBUS VTH & GND threshold 482 * to meet CTS 3.3.7.2 spec 483 */ 484 mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL5_REG, 0x77); 485 cbus_writebm(ctx, CBUS_LINK_CONTROL_2_REG, ~0, MHL_INIT_TIMEOUT); 486 mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL6_REG, 0xA0); 487 /* RGND & single discovery attempt (RGND blocking) */ 488 mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL6_REG, BLOCK_RGND_INT | 489 DVRFLT_SEL | SINGLE_ATT); 490 /* Use VBUS path of discovery state machine */ 491 mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL8_REG, 0); 492 /* 0x92[3] sets the CBUS / ID switch */ 493 mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, ~0, USB_ID_OVR); 494 /* 495 * To allow RGND engine to operate correctly. 496 * When moving the chip from D2 to D0 (power up, init regs) 497 * the values should be 498 * 94[1:0] = 01 reg_cbusmhl_pup_sel[1:0] should be set for 5k 499 * 93[7:6] = 10 reg_cbusdisc_pup_sel[1:0] should be 500 * set for 10k (default) 501 * 93[5:4] = 00 reg_cbusidle_pup_sel[1:0] = open (default) 502 */ 503 mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL3_REG, ~0, 0x86); 504 /* 505 * Change from CC to 8C to match 5K 506 * to meet CTS 3.3.72 spec 507 */ 508 mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL4_REG, ~0, 0x8C); 509 /* Configure the interrupt as active high */ 510 mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, 0, 0x06); 511 512 msleep(25); 513 514 /* Release usb_id switch */ 515 mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, 0, USB_ID_OVR); 516 mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL1_REG, 0x27); 517 518 ret = sii9234_clear_error(ctx); 519 if (ret < 0) 520 return ret; 521 ret = sii9234_cbus_init(ctx); 522 if (ret < 0) 523 return ret; 524 525 /* Enable Auto soft reset on SCDT = 0 */ 526 mhl_tx_writeb(ctx, 0x05, 0x04); 527 /* HDMI Transcode mode enable */ 528 mhl_tx_writeb(ctx, 0x0D, 0x1C); 529 mhl_tx_writeb(ctx, MHL_TX_INTR4_ENABLE_REG, 530 RGND_READY_MASK | CBUS_LKOUT_MASK 531 | MHL_DISC_FAIL_MASK | MHL_EST_MASK); 532 mhl_tx_writeb(ctx, MHL_TX_INTR1_ENABLE_REG, 0x60); 533 534 /* This point is very important before measure RGND impedance */ 535 force_usb_id_switch_open(ctx); 536 mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL4_REG, 0, 0xF0); 537 mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL5_REG, 0, 0x03); 538 release_usb_id_switch_open(ctx); 539 540 /* Force upstream HPD to 0 when not in MHL mode */ 541 mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, 0, 1 << 5); 542 mhl_tx_writebm(ctx, MHL_TX_INT_CTRL_REG, ~0, 1 << 4); 543 544 return sii9234_clear_error(ctx); 545 } 546 547 static int sii9234_goto_d3(struct sii9234 *ctx) 548 { 549 int ret; 550 551 dev_dbg(ctx->dev, "sii9234: detection started d3\n"); 552 553 ret = sii9234_reset(ctx); 554 if (ret < 0) 555 goto exit; 556 557 hdmi_writeb(ctx, 0x01, 0x03); 558 tpi_writebm(ctx, TPI_DPD_REG, 0, 1); 559 /* I2C above is expected to fail because power goes down */ 560 sii9234_clear_error(ctx); 561 562 ctx->state = ST_D3; 563 564 return 0; 565 exit: 566 dev_err(ctx->dev, "%s failed\n", __func__); 567 return -1; 568 } 569 570 static int sii9234_hw_on(struct sii9234 *ctx) 571 { 572 return regulator_bulk_enable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 573 } 574 575 static void sii9234_hw_off(struct sii9234 *ctx) 576 { 577 gpiod_set_value(ctx->gpio_reset, 1); 578 msleep(20); 579 regulator_bulk_disable(ARRAY_SIZE(ctx->supplies), ctx->supplies); 580 } 581 582 static void sii9234_hw_reset(struct sii9234 *ctx) 583 { 584 gpiod_set_value(ctx->gpio_reset, 1); 585 msleep(20); 586 gpiod_set_value(ctx->gpio_reset, 0); 587 } 588 589 static void sii9234_cable_in(struct sii9234 *ctx) 590 { 591 int ret; 592 593 mutex_lock(&ctx->lock); 594 if (ctx->state != ST_OFF) 595 goto unlock; 596 ret = sii9234_hw_on(ctx); 597 if (ret < 0) 598 goto unlock; 599 600 sii9234_hw_reset(ctx); 601 sii9234_goto_d3(ctx); 602 /* To avoid irq storm, when hw is in meta state */ 603 enable_irq(to_i2c_client(ctx->dev)->irq); 604 605 unlock: 606 mutex_unlock(&ctx->lock); 607 } 608 609 static void sii9234_cable_out(struct sii9234 *ctx) 610 { 611 mutex_lock(&ctx->lock); 612 613 if (ctx->state == ST_OFF) 614 goto unlock; 615 616 disable_irq(to_i2c_client(ctx->dev)->irq); 617 tpi_writeb(ctx, TPI_DPD_REG, 0); 618 /* Turn on&off hpd feature for only QCT HDMI */ 619 sii9234_hw_off(ctx); 620 621 ctx->state = ST_OFF; 622 623 unlock: 624 mutex_unlock(&ctx->lock); 625 } 626 627 static enum sii9234_state sii9234_rgnd_ready_irq(struct sii9234 *ctx) 628 { 629 int value; 630 631 if (ctx->state == ST_D3) { 632 int ret; 633 634 dev_dbg(ctx->dev, "RGND_READY_INT\n"); 635 sii9234_hw_reset(ctx); 636 637 ret = sii9234_reset(ctx); 638 if (ret < 0) { 639 dev_err(ctx->dev, "sii9234_reset() failed\n"); 640 return ST_FAILURE; 641 } 642 643 return ST_RGND_INIT; 644 } 645 646 /* Got interrupt in inappropriate state */ 647 if (ctx->state != ST_RGND_INIT) 648 return ST_FAILURE; 649 650 value = mhl_tx_readb(ctx, MHL_TX_STAT2_REG); 651 if (sii9234_clear_error(ctx)) 652 return ST_FAILURE; 653 654 if ((value & RGND_INTP_MASK) != RGND_INTP_1K) { 655 dev_warn(ctx->dev, "RGND is not 1k\n"); 656 return ST_RGND_INIT; 657 } 658 dev_dbg(ctx->dev, "RGND 1K!!\n"); 659 mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL4_REG, ~0, 0x8C); 660 mhl_tx_writeb(ctx, MHL_TX_DISC_CTRL5_REG, 0x77); 661 mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL6_REG, ~0, 0x05); 662 if (sii9234_clear_error(ctx)) 663 return ST_FAILURE; 664 665 msleep(T_SRC_VBUS_CBUS_TO_STABLE); 666 return ST_RGND_1K; 667 } 668 669 static enum sii9234_state sii9234_mhl_established(struct sii9234 *ctx) 670 { 671 dev_dbg(ctx->dev, "mhl est interrupt\n"); 672 673 /* Discovery override */ 674 mhl_tx_writeb(ctx, MHL_TX_MHLTX_CTL1_REG, 0x10); 675 /* Increase DDC translation layer timer (byte mode) */ 676 cbus_writeb(ctx, 0x07, 0x32); 677 cbus_writebm(ctx, 0x44, ~0, 1 << 1); 678 /* Keep the discovery enabled. Need RGND interrupt */ 679 mhl_tx_writebm(ctx, MHL_TX_DISC_CTRL1_REG, ~0, 1); 680 mhl_tx_writeb(ctx, MHL_TX_INTR1_ENABLE_REG, 681 RSEN_CHANGE_INT_MASK | HPD_CHANGE_INT_MASK); 682 683 if (sii9234_clear_error(ctx)) 684 return ST_FAILURE; 685 686 return ST_MHL_ESTABLISHED; 687 } 688 689 static enum sii9234_state sii9234_hpd_change(struct sii9234 *ctx) 690 { 691 int value; 692 693 value = cbus_readb(ctx, CBUS_MSC_REQ_ABORT_REASON_REG); 694 if (sii9234_clear_error(ctx)) 695 return ST_FAILURE; 696 697 if (value & SET_HPD_DOWNSTREAM) { 698 /* Downstream HPD High, Enable TMDS */ 699 sii9234_tmds_control(ctx, true); 700 } else { 701 /* Downstream HPD Low, Disable TMDS */ 702 sii9234_tmds_control(ctx, false); 703 } 704 705 return ctx->state; 706 } 707 708 static enum sii9234_state sii9234_rsen_change(struct sii9234 *ctx) 709 { 710 int value; 711 712 /* Workaround code to handle wrong interrupt */ 713 if (ctx->state != ST_RGND_1K) { 714 dev_err(ctx->dev, "RSEN_HIGH without RGND_1K\n"); 715 return ST_FAILURE; 716 } 717 value = mhl_tx_readb(ctx, MHL_TX_SYSSTAT_REG); 718 if (value < 0) 719 return ST_FAILURE; 720 721 if (value & RSEN_STATUS) { 722 dev_dbg(ctx->dev, "MHL cable connected.. RSEN High\n"); 723 return ST_RSEN_HIGH; 724 } 725 dev_dbg(ctx->dev, "RSEN lost\n"); 726 /* 727 * Once RSEN loss is confirmed, we need to check 728 * based on cable status and chip power status, whether 729 * it is SINK Loss (HDMI cable not connected, TV Off) 730 * or MHL cable disconnection 731 * TODO: Define the below mhl_disconnection() 732 */ 733 msleep(T_SRC_RXSENSE_DEGLITCH); 734 value = mhl_tx_readb(ctx, MHL_TX_SYSSTAT_REG); 735 if (value < 0) 736 return ST_FAILURE; 737 dev_dbg(ctx->dev, "sys_stat: %x\n", value); 738 739 if (value & RSEN_STATUS) { 740 dev_dbg(ctx->dev, "RSEN recovery\n"); 741 return ST_RSEN_HIGH; 742 } 743 dev_dbg(ctx->dev, "RSEN Really LOW\n"); 744 /* To meet CTS 3.3.22.2 spec */ 745 sii9234_tmds_control(ctx, false); 746 force_usb_id_switch_open(ctx); 747 release_usb_id_switch_open(ctx); 748 749 return ST_FAILURE; 750 } 751 752 static irqreturn_t sii9234_irq_thread(int irq, void *data) 753 { 754 struct sii9234 *ctx = data; 755 int intr1, intr4; 756 int intr1_en, intr4_en; 757 int cbus_intr1, cbus_intr2; 758 759 dev_dbg(ctx->dev, "%s\n", __func__); 760 761 mutex_lock(&ctx->lock); 762 763 intr1 = mhl_tx_readb(ctx, MHL_TX_INTR1_REG); 764 intr4 = mhl_tx_readb(ctx, MHL_TX_INTR4_REG); 765 intr1_en = mhl_tx_readb(ctx, MHL_TX_INTR1_ENABLE_REG); 766 intr4_en = mhl_tx_readb(ctx, MHL_TX_INTR4_ENABLE_REG); 767 cbus_intr1 = cbus_readb(ctx, CBUS_INT_STATUS_1_REG); 768 cbus_intr2 = cbus_readb(ctx, CBUS_INT_STATUS_2_REG); 769 770 if (sii9234_clear_error(ctx)) 771 goto done; 772 773 dev_dbg(ctx->dev, "irq %02x/%02x %02x/%02x %02x/%02x\n", 774 intr1, intr1_en, intr4, intr4_en, cbus_intr1, cbus_intr2); 775 776 if (intr4 & RGND_READY_INT) 777 ctx->state = sii9234_rgnd_ready_irq(ctx); 778 if (intr1 & RSEN_CHANGE_INT) 779 ctx->state = sii9234_rsen_change(ctx); 780 if (intr4 & MHL_EST_INT) 781 ctx->state = sii9234_mhl_established(ctx); 782 if (intr1 & HPD_CHANGE_INT) 783 ctx->state = sii9234_hpd_change(ctx); 784 if (intr4 & CBUS_LKOUT_INT) 785 ctx->state = ST_FAILURE; 786 if (intr4 & MHL_DISC_FAIL_INT) 787 ctx->state = ST_FAILURE_DISCOVERY; 788 789 done: 790 /* Clean interrupt status and pending flags */ 791 mhl_tx_writeb(ctx, MHL_TX_INTR1_REG, intr1); 792 mhl_tx_writeb(ctx, MHL_TX_INTR4_REG, intr4); 793 cbus_writeb(ctx, CBUS_MHL_STATUS_REG_0, 0xFF); 794 cbus_writeb(ctx, CBUS_MHL_STATUS_REG_1, 0xFF); 795 cbus_writeb(ctx, CBUS_INT_STATUS_1_REG, cbus_intr1); 796 cbus_writeb(ctx, CBUS_INT_STATUS_2_REG, cbus_intr2); 797 798 sii9234_clear_error(ctx); 799 800 if (ctx->state == ST_FAILURE) { 801 dev_dbg(ctx->dev, "try to reset after failure\n"); 802 sii9234_hw_reset(ctx); 803 sii9234_goto_d3(ctx); 804 } 805 806 if (ctx->state == ST_FAILURE_DISCOVERY) { 807 dev_err(ctx->dev, "discovery failed, no power for MHL?\n"); 808 tpi_writebm(ctx, TPI_DPD_REG, 0, 1); 809 ctx->state = ST_D3; 810 } 811 812 mutex_unlock(&ctx->lock); 813 814 return IRQ_HANDLED; 815 } 816 817 static int sii9234_init_resources(struct sii9234 *ctx, 818 struct i2c_client *client) 819 { 820 struct i2c_adapter *adapter = client->adapter; 821 int ret; 822 823 if (!ctx->dev->of_node) { 824 dev_err(ctx->dev, "no DT device\n"); 825 return -ENODEV; 826 } 827 828 ctx->gpio_reset = devm_gpiod_get(ctx->dev, "reset", GPIOD_OUT_LOW); 829 if (IS_ERR(ctx->gpio_reset)) 830 return dev_err_probe(ctx->dev, PTR_ERR(ctx->gpio_reset), 831 "failed to get reset gpio from DT\n"); 832 833 ctx->supplies[0].supply = "avcc12"; 834 ctx->supplies[1].supply = "avcc33"; 835 ctx->supplies[2].supply = "iovcc18"; 836 ctx->supplies[3].supply = "cvcc12"; 837 ret = devm_regulator_bulk_get(ctx->dev, 4, ctx->supplies); 838 if (ret) 839 return dev_err_probe(ctx->dev, ret, "regulator_bulk failed\n"); 840 841 ctx->client[I2C_MHL] = client; 842 843 ctx->client[I2C_TPI] = devm_i2c_new_dummy_device(&client->dev, adapter, 844 I2C_TPI_ADDR); 845 if (IS_ERR(ctx->client[I2C_TPI])) { 846 dev_err(ctx->dev, "failed to create TPI client\n"); 847 return PTR_ERR(ctx->client[I2C_TPI]); 848 } 849 850 ctx->client[I2C_HDMI] = devm_i2c_new_dummy_device(&client->dev, adapter, 851 I2C_HDMI_ADDR); 852 if (IS_ERR(ctx->client[I2C_HDMI])) { 853 dev_err(ctx->dev, "failed to create HDMI RX client\n"); 854 return PTR_ERR(ctx->client[I2C_HDMI]); 855 } 856 857 ctx->client[I2C_CBUS] = devm_i2c_new_dummy_device(&client->dev, adapter, 858 I2C_CBUS_ADDR); 859 if (IS_ERR(ctx->client[I2C_CBUS])) { 860 dev_err(ctx->dev, "failed to create CBUS client\n"); 861 return PTR_ERR(ctx->client[I2C_CBUS]); 862 } 863 864 return 0; 865 } 866 867 static enum drm_mode_status sii9234_mode_valid(struct drm_bridge *bridge, 868 const struct drm_display_info *info, 869 const struct drm_display_mode *mode) 870 { 871 if (mode->clock > MHL1_MAX_CLK) 872 return MODE_CLOCK_HIGH; 873 874 return MODE_OK; 875 } 876 877 static const struct drm_bridge_funcs sii9234_bridge_funcs = { 878 .atomic_create_state = drm_atomic_helper_bridge_create_state, 879 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 880 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 881 .mode_valid = sii9234_mode_valid, 882 }; 883 884 static int sii9234_probe(struct i2c_client *client) 885 { 886 struct i2c_adapter *adapter = client->adapter; 887 struct sii9234 *ctx; 888 struct device *dev = &client->dev; 889 int ret; 890 891 ctx = devm_drm_bridge_alloc(dev, struct sii9234, bridge, 892 &sii9234_bridge_funcs); 893 if (IS_ERR(ctx)) 894 return PTR_ERR(ctx); 895 896 ctx->dev = dev; 897 mutex_init(&ctx->lock); 898 899 if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA)) { 900 dev_err(dev, "I2C adapter lacks SMBUS feature\n"); 901 return -EIO; 902 } 903 904 if (!client->irq) { 905 dev_err(dev, "no irq provided\n"); 906 return -EINVAL; 907 } 908 909 irq_set_status_flags(client->irq, IRQ_NOAUTOEN); 910 ret = devm_request_threaded_irq(dev, client->irq, NULL, 911 sii9234_irq_thread, 912 IRQF_TRIGGER_HIGH | IRQF_ONESHOT, 913 "sii9234", ctx); 914 if (ret < 0) 915 return dev_err_probe(dev, ret, 916 "failed to install IRQ handler\n"); 917 918 ret = sii9234_init_resources(ctx, client); 919 if (ret < 0) 920 return ret; 921 922 i2c_set_clientdata(client, ctx); 923 924 ctx->bridge.of_node = dev->of_node; 925 drm_bridge_add(&ctx->bridge); 926 927 sii9234_cable_in(ctx); 928 929 return 0; 930 } 931 932 static void sii9234_remove(struct i2c_client *client) 933 { 934 struct sii9234 *ctx = i2c_get_clientdata(client); 935 936 sii9234_cable_out(ctx); 937 drm_bridge_remove(&ctx->bridge); 938 } 939 940 static const struct of_device_id sii9234_dt_match[] = { 941 { .compatible = "sil,sii9234" }, 942 { }, 943 }; 944 MODULE_DEVICE_TABLE(of, sii9234_dt_match); 945 946 static const struct i2c_device_id sii9234_id[] = { 947 { .name = "SII9234" }, 948 { } 949 }; 950 MODULE_DEVICE_TABLE(i2c, sii9234_id); 951 952 static struct i2c_driver sii9234_driver = { 953 .driver = { 954 .name = "sii9234", 955 .of_match_table = sii9234_dt_match, 956 }, 957 .probe = sii9234_probe, 958 .remove = sii9234_remove, 959 .id_table = sii9234_id, 960 }; 961 962 module_i2c_driver(sii9234_driver); 963 MODULE_DESCRIPTION("Silicon Image SII9234 HDMI/MHL bridge driver"); 964 MODULE_LICENSE("GPL"); 965