1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Samsung MIPI DSIM bridge driver. 4 * 5 * Copyright (C) 2021 Amarula Solutions(India) 6 * Copyright (c) 2014 Samsung Electronics Co., Ltd 7 * Author: Jagan Teki <jagan@amarulasolutions.com> 8 * 9 * Based on exynos_drm_dsi from 10 * Tomasz Figa <t.figa@samsung.com> 11 */ 12 13 #include <linux/unaligned.h> 14 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/export.h> 18 #include <linux/irq.h> 19 #include <linux/media-bus-format.h> 20 #include <linux/of.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 24 #include <video/mipi_display.h> 25 26 #include <drm/bridge/samsung-dsim.h> 27 #include <drm/drm_panel.h> 28 #include <drm/drm_print.h> 29 30 /* returns true iff both arguments logically differs */ 31 #define NEQV(a, b) (!(a) ^ !(b)) 32 33 /* DSIM_STATUS */ 34 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 35 #define DSIM_STOP_STATE_CLK BIT(8) 36 #define DSIM_TX_READY_HS_CLK BIT(10) 37 #define DSIM_PLL_STABLE BIT(31) 38 39 /* DSIM_SWRST */ 40 #define DSIM_FUNCRST BIT(16) 41 #define DSIM_SWRST BIT(0) 42 43 /* DSIM_TIMEOUT */ 44 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 45 #define DSIM_BTA_TIMEOUT(x) ((x) << 16) 46 47 /* DSIM_CLKCTRL */ 48 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 49 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 50 #define DSIM_LANE_ESC_CLK_EN_CLK BIT(19) 51 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) 52 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) 53 #define DSIM_BYTE_CLKEN BIT(24) 54 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 55 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 56 #define DSIM_PLL_BYPASS BIT(27) 57 #define DSIM_ESC_CLKEN BIT(28) 58 #define DSIM_TX_REQUEST_HSCLK BIT(31) 59 60 /* DSIM_CONFIG */ 61 #define DSIM_LANE_EN_CLK BIT(0) 62 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 63 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 64 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 65 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 66 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 67 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 68 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 69 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 70 #define DSIM_SUB_VC (((x) & 0x3) << 16) 71 #define DSIM_MAIN_VC (((x) & 0x3) << 18) 72 #define DSIM_HSA_DISABLE_MODE BIT(20) 73 #define DSIM_HBP_DISABLE_MODE BIT(21) 74 #define DSIM_HFP_DISABLE_MODE BIT(22) 75 /* 76 * The i.MX 8M Mini Applications Processor Reference Manual, 77 * Rev. 3, 11/2020 Page 4091 78 * The i.MX 8M Nano Applications Processor Reference Manual, 79 * Rev. 2, 07/2022 Page 3058 80 * The i.MX 8M Plus Applications Processor Reference Manual, 81 * Rev. 1, 06/2021 Page 5436 82 * all claims this bit is 'HseDisableMode' with the definition 83 * 0 = Disables transfer 84 * 1 = Enables transfer 85 * 86 * This clearly states that HSE is not a disabled bit. 87 * 88 * The naming convention follows as per the manual and the 89 * driver logic is based on the MIPI_DSI_MODE_VIDEO_HSE flag. 90 */ 91 #define DSIM_HSE_DISABLE_MODE BIT(23) 92 #define DSIM_AUTO_MODE BIT(24) 93 #define DSIM_VIDEO_MODE BIT(25) 94 #define DSIM_BURST_MODE BIT(26) 95 #define DSIM_SYNC_INFORM BIT(27) 96 #define DSIM_EOT_DISABLE BIT(28) 97 #define DSIM_MFLUSH_VS BIT(29) 98 /* This flag is valid only for exynos3250/3472/5260/5430 */ 99 #define DSIM_CLKLANE_STOP BIT(30) 100 #define DSIM_NON_CONTINUOUS_CLKLANE BIT(31) 101 102 /* DSIM_ESCMODE */ 103 #define DSIM_TX_TRIGGER_RST BIT(4) 104 #define DSIM_TX_LPDT_LP BIT(6) 105 #define DSIM_CMD_LPDT_LP BIT(7) 106 #define DSIM_FORCE_BTA BIT(16) 107 #define DSIM_FORCE_STOP_STATE BIT(20) 108 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 109 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 110 111 /* DSIM_MDRESOL */ 112 #define DSIM_MAIN_STAND_BY BIT(31) 113 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) 114 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) 115 116 /* DSIM_MVPORCH */ 117 #define DSIM_CMD_ALLOW(x) ((x) << 28) 118 #define DSIM_STABLE_VFP(x) ((x) << 16) 119 #define DSIM_MAIN_VBP(x) ((x) << 0) 120 #define DSIM_CMD_ALLOW_MASK (0xf << 28) 121 #define DSIM_STABLE_VFP_MASK (0x7ff << 16) 122 #define DSIM_MAIN_VBP_MASK (0x7ff << 0) 123 124 /* DSIM_MHPORCH */ 125 #define DSIM_MAIN_HFP(x) ((x) << 16) 126 #define DSIM_MAIN_HBP(x) ((x) << 0) 127 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 128 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 129 130 /* DSIM_MSYNC */ 131 #define DSIM_MAIN_VSA(x) ((x) << 22) 132 #define DSIM_MAIN_HSA(x) ((x) << 0) 133 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 134 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 135 136 /* DSIM_SDRESOL */ 137 #define DSIM_SUB_STANDY(x) ((x) << 31) 138 #define DSIM_SUB_VRESOL(x) ((x) << 16) 139 #define DSIM_SUB_HRESOL(x) ((x) << 0) 140 #define DSIM_SUB_STANDY_MASK ((0x1) << 31) 141 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 142 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 143 144 /* DSIM_INTSRC */ 145 #define DSIM_INT_PLL_STABLE BIT(31) 146 #define DSIM_INT_SW_RST_RELEASE BIT(30) 147 #define DSIM_INT_SFR_FIFO_EMPTY BIT(29) 148 #define DSIM_INT_SFR_HDR_FIFO_EMPTY BIT(28) 149 #define DSIM_INT_BTA BIT(25) 150 #define DSIM_INT_FRAME_DONE BIT(24) 151 #define DSIM_INT_RX_TIMEOUT BIT(21) 152 #define DSIM_INT_BTA_TIMEOUT BIT(20) 153 #define DSIM_INT_RX_DONE BIT(18) 154 #define DSIM_INT_RX_TE BIT(17) 155 #define DSIM_INT_RX_ACK BIT(16) 156 #define DSIM_INT_RX_ECC_ERR BIT(15) 157 #define DSIM_INT_RX_CRC_ERR BIT(14) 158 159 /* DSIM_FIFOCTRL */ 160 #define DSIM_RX_DATA_FULL BIT(25) 161 #define DSIM_RX_DATA_EMPTY BIT(24) 162 #define DSIM_SFR_HEADER_FULL BIT(23) 163 #define DSIM_SFR_HEADER_EMPTY BIT(22) 164 #define DSIM_SFR_PAYLOAD_FULL BIT(21) 165 #define DSIM_SFR_PAYLOAD_EMPTY BIT(20) 166 #define DSIM_I80_HEADER_FULL BIT(19) 167 #define DSIM_I80_HEADER_EMPTY BIT(18) 168 #define DSIM_I80_PAYLOAD_FULL BIT(17) 169 #define DSIM_I80_PAYLOAD_EMPTY BIT(16) 170 #define DSIM_SD_HEADER_FULL BIT(15) 171 #define DSIM_SD_HEADER_EMPTY BIT(14) 172 #define DSIM_SD_PAYLOAD_FULL BIT(13) 173 #define DSIM_SD_PAYLOAD_EMPTY BIT(12) 174 #define DSIM_MD_HEADER_FULL BIT(11) 175 #define DSIM_MD_HEADER_EMPTY BIT(10) 176 #define DSIM_MD_PAYLOAD_FULL BIT(9) 177 #define DSIM_MD_PAYLOAD_EMPTY BIT(8) 178 #define DSIM_RX_FIFO BIT(4) 179 #define DSIM_SFR_FIFO BIT(3) 180 #define DSIM_I80_FIFO BIT(2) 181 #define DSIM_SD_FIFO BIT(1) 182 #define DSIM_MD_FIFO BIT(0) 183 184 /* DSIM_PHYACCHR */ 185 #define DSIM_AFC_EN BIT(14) 186 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 187 188 /* DSIM_PLLCTRL */ 189 #define DSIM_PLL_DPDNSWAP_CLK (1 << 25) 190 #define DSIM_PLL_DPDNSWAP_DAT (1 << 24) 191 #define DSIM_FREQ_BAND(x) ((x) << 24) 192 #define DSIM_PLL_EN BIT(23) 193 #define DSIM_PLL_P(x, offset) ((x) << (offset)) 194 #define DSIM_PLL_M(x) ((x) << 4) 195 #define DSIM_PLL_S(x) ((x) << 1) 196 197 /* DSIM_PHYCTRL */ 198 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 199 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP BIT(30) 200 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP BIT(14) 201 202 /* DSIM_PHYTIMING */ 203 #define DSIM_PHYTIMING_LPX(x) ((x) << 8) 204 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 205 206 /* DSIM_PHYTIMING1 */ 207 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 208 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 209 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 210 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 211 212 /* DSIM_PHYTIMING2 */ 213 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 214 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 215 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 216 217 #define DSI_MAX_BUS_WIDTH 4 218 #define DSI_NUM_VIRTUAL_CHANNELS 4 219 #define DSI_TX_FIFO_SIZE 2048 220 #define DSI_RX_FIFO_SIZE 256 221 #define DSI_XFER_TIMEOUT_MS 100 222 #define DSI_RX_FIFO_EMPTY 0x30800002 223 224 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" 225 226 #define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000000000ULL) 227 228 static const char *const clk_names[5] = { 229 "bus_clk", 230 "sclk_mipi", 231 "phyclk_mipidphy0_bitclkdiv8", 232 "phyclk_mipidphy0_rxclkesc0", 233 "sclk_rgb_vclk_to_dsim0" 234 }; 235 236 enum samsung_dsim_transfer_type { 237 EXYNOS_DSI_TX, 238 EXYNOS_DSI_RX, 239 }; 240 241 enum reg_idx { 242 DSIM_STATUS_REG, /* Status register */ 243 DSIM_SWRST_REG, /* Software reset register */ 244 DSIM_CLKCTRL_REG, /* Clock control register */ 245 DSIM_TIMEOUT_REG, /* Time out register */ 246 DSIM_CONFIG_REG, /* Configuration register */ 247 DSIM_ESCMODE_REG, /* Escape mode register */ 248 DSIM_MDRESOL_REG, 249 DSIM_MVPORCH_REG, /* Main display Vporch register */ 250 DSIM_MHPORCH_REG, /* Main display Hporch register */ 251 DSIM_MSYNC_REG, /* Main display sync area register */ 252 DSIM_INTSRC_REG, /* Interrupt source register */ 253 DSIM_INTMSK_REG, /* Interrupt mask register */ 254 DSIM_PKTHDR_REG, /* Packet Header FIFO register */ 255 DSIM_PAYLOAD_REG, /* Payload FIFO register */ 256 DSIM_RXFIFO_REG, /* Read FIFO register */ 257 DSIM_FIFOCTRL_REG, /* FIFO status and control register */ 258 DSIM_PLLCTRL_REG, /* PLL control register */ 259 DSIM_PHYCTRL_REG, 260 DSIM_PHYTIMING_REG, 261 DSIM_PHYTIMING1_REG, 262 DSIM_PHYTIMING2_REG, 263 NUM_REGS 264 }; 265 266 static const unsigned int exynos_reg_ofs[] = { 267 [DSIM_STATUS_REG] = 0x00, 268 [DSIM_SWRST_REG] = 0x04, 269 [DSIM_CLKCTRL_REG] = 0x08, 270 [DSIM_TIMEOUT_REG] = 0x0c, 271 [DSIM_CONFIG_REG] = 0x10, 272 [DSIM_ESCMODE_REG] = 0x14, 273 [DSIM_MDRESOL_REG] = 0x18, 274 [DSIM_MVPORCH_REG] = 0x1c, 275 [DSIM_MHPORCH_REG] = 0x20, 276 [DSIM_MSYNC_REG] = 0x24, 277 [DSIM_INTSRC_REG] = 0x2c, 278 [DSIM_INTMSK_REG] = 0x30, 279 [DSIM_PKTHDR_REG] = 0x34, 280 [DSIM_PAYLOAD_REG] = 0x38, 281 [DSIM_RXFIFO_REG] = 0x3c, 282 [DSIM_FIFOCTRL_REG] = 0x44, 283 [DSIM_PLLCTRL_REG] = 0x4c, 284 [DSIM_PHYCTRL_REG] = 0x5c, 285 [DSIM_PHYTIMING_REG] = 0x64, 286 [DSIM_PHYTIMING1_REG] = 0x68, 287 [DSIM_PHYTIMING2_REG] = 0x6c, 288 }; 289 290 static const unsigned int exynos5433_reg_ofs[] = { 291 [DSIM_STATUS_REG] = 0x04, 292 [DSIM_SWRST_REG] = 0x0C, 293 [DSIM_CLKCTRL_REG] = 0x10, 294 [DSIM_TIMEOUT_REG] = 0x14, 295 [DSIM_CONFIG_REG] = 0x18, 296 [DSIM_ESCMODE_REG] = 0x1C, 297 [DSIM_MDRESOL_REG] = 0x20, 298 [DSIM_MVPORCH_REG] = 0x24, 299 [DSIM_MHPORCH_REG] = 0x28, 300 [DSIM_MSYNC_REG] = 0x2C, 301 [DSIM_INTSRC_REG] = 0x34, 302 [DSIM_INTMSK_REG] = 0x38, 303 [DSIM_PKTHDR_REG] = 0x3C, 304 [DSIM_PAYLOAD_REG] = 0x40, 305 [DSIM_RXFIFO_REG] = 0x44, 306 [DSIM_FIFOCTRL_REG] = 0x4C, 307 [DSIM_PLLCTRL_REG] = 0x94, 308 [DSIM_PHYCTRL_REG] = 0xA4, 309 [DSIM_PHYTIMING_REG] = 0xB4, 310 [DSIM_PHYTIMING1_REG] = 0xB8, 311 [DSIM_PHYTIMING2_REG] = 0xBC, 312 }; 313 314 enum reg_value_idx { 315 RESET_TYPE, 316 PLL_TIMER, 317 STOP_STATE_CNT, 318 PHYCTRL_ULPS_EXIT, 319 PHYCTRL_VREG_LP, 320 PHYCTRL_SLEW_UP, 321 PHYTIMING_LPX, 322 PHYTIMING_HS_EXIT, 323 PHYTIMING_CLK_PREPARE, 324 PHYTIMING_CLK_ZERO, 325 PHYTIMING_CLK_POST, 326 PHYTIMING_CLK_TRAIL, 327 PHYTIMING_HS_PREPARE, 328 PHYTIMING_HS_ZERO, 329 PHYTIMING_HS_TRAIL 330 }; 331 332 static const unsigned int reg_values[] = { 333 [RESET_TYPE] = DSIM_SWRST, 334 [PLL_TIMER] = 500, 335 [STOP_STATE_CNT] = 0xf, 336 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), 337 [PHYCTRL_VREG_LP] = 0, 338 [PHYCTRL_SLEW_UP] = 0, 339 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 340 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 341 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 342 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), 343 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 344 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 345 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 346 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 347 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 348 }; 349 350 static const unsigned int exynos5422_reg_values[] = { 351 [RESET_TYPE] = DSIM_SWRST, 352 [PLL_TIMER] = 500, 353 [STOP_STATE_CNT] = 0xf, 354 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 355 [PHYCTRL_VREG_LP] = 0, 356 [PHYCTRL_SLEW_UP] = 0, 357 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), 358 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), 359 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 360 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), 361 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 362 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), 363 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), 364 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), 365 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), 366 }; 367 368 static const unsigned int exynos5433_reg_values[] = { 369 [RESET_TYPE] = DSIM_FUNCRST, 370 [PLL_TIMER] = 22200, 371 [STOP_STATE_CNT] = 0xa, 372 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), 373 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, 374 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, 375 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), 376 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), 377 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 378 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), 379 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 380 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), 381 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), 382 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), 383 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), 384 }; 385 386 static const unsigned int imx8mm_dsim_reg_values[] = { 387 [RESET_TYPE] = DSIM_SWRST, 388 [PLL_TIMER] = 500, 389 [STOP_STATE_CNT] = 0xf, 390 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 391 [PHYCTRL_VREG_LP] = 0, 392 [PHYCTRL_SLEW_UP] = 0, 393 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 394 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 395 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 396 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26), 397 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 398 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 399 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08), 400 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 401 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 402 }; 403 404 static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { 405 .reg_ofs = exynos_reg_ofs, 406 .plltmr_reg = 0x50, 407 .has_freqband = 1, 408 .has_clklane_stop = 1, 409 .num_clks = 2, 410 .max_freq = 1000, 411 .wait_for_reset = 1, 412 .num_bits_resol = 11, 413 .pll_p_offset = 13, 414 .reg_values = reg_values, 415 .pll_fin_min = 6, 416 .pll_fin_max = 12, 417 .m_min = 41, 418 .m_max = 125, 419 .min_freq = 500, 420 .has_broken_fifoctrl_emptyhdr = 1, 421 }; 422 423 static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { 424 .reg_ofs = exynos_reg_ofs, 425 .plltmr_reg = 0x50, 426 .has_freqband = 1, 427 .has_clklane_stop = 1, 428 .num_clks = 2, 429 .max_freq = 1000, 430 .wait_for_reset = 1, 431 .num_bits_resol = 11, 432 .pll_p_offset = 13, 433 .reg_values = reg_values, 434 .pll_fin_min = 6, 435 .pll_fin_max = 12, 436 .m_min = 41, 437 .m_max = 125, 438 .min_freq = 500, 439 .has_broken_fifoctrl_emptyhdr = 1, 440 }; 441 442 static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { 443 .reg_ofs = exynos_reg_ofs, 444 .plltmr_reg = 0x58, 445 .num_clks = 2, 446 .max_freq = 1000, 447 .wait_for_reset = 1, 448 .num_bits_resol = 11, 449 .pll_p_offset = 13, 450 .reg_values = reg_values, 451 .pll_fin_min = 6, 452 .pll_fin_max = 12, 453 .m_min = 41, 454 .m_max = 125, 455 .min_freq = 500, 456 }; 457 458 static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { 459 .reg_ofs = exynos5433_reg_ofs, 460 .plltmr_reg = 0xa0, 461 .has_clklane_stop = 1, 462 .num_clks = 5, 463 .max_freq = 1500, 464 .wait_for_reset = 0, 465 .num_bits_resol = 12, 466 .pll_p_offset = 13, 467 .reg_values = exynos5433_reg_values, 468 .pll_fin_min = 6, 469 .pll_fin_max = 12, 470 .m_min = 41, 471 .m_max = 125, 472 .min_freq = 500, 473 }; 474 475 static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { 476 .reg_ofs = exynos5433_reg_ofs, 477 .plltmr_reg = 0xa0, 478 .has_clklane_stop = 1, 479 .num_clks = 2, 480 .max_freq = 1500, 481 .wait_for_reset = 1, 482 .num_bits_resol = 12, 483 .pll_p_offset = 13, 484 .reg_values = exynos5422_reg_values, 485 .pll_fin_min = 6, 486 .pll_fin_max = 12, 487 .m_min = 41, 488 .m_max = 125, 489 .min_freq = 500, 490 }; 491 492 static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { 493 .reg_ofs = exynos5433_reg_ofs, 494 .plltmr_reg = 0xa0, 495 .has_clklane_stop = 1, 496 .num_clks = 2, 497 .max_freq = 2100, 498 .wait_for_reset = 0, 499 .num_bits_resol = 12, 500 /* 501 * Unlike Exynos, PLL_P(PMS_P) offset 14 is used in i.MX8M Mini/Nano/Plus 502 * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c 503 */ 504 .pll_p_offset = 14, 505 .reg_values = imx8mm_dsim_reg_values, 506 .pll_fin_min = 2, 507 .pll_fin_max = 30, 508 .m_min = 64, 509 .m_max = 1023, 510 .min_freq = 1050, 511 }; 512 513 static const struct samsung_dsim_driver_data * 514 samsung_dsim_types[DSIM_TYPE_COUNT] = { 515 [DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data, 516 [DSIM_TYPE_EXYNOS4210] = &exynos4_dsi_driver_data, 517 [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data, 518 [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data, 519 [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data, 520 [DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data, 521 [DSIM_TYPE_IMX8MP] = &imx8mm_dsi_driver_data, 522 }; 523 524 static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h) 525 { 526 return container_of(h, struct samsung_dsim, dsi_host); 527 } 528 529 static inline struct samsung_dsim *bridge_to_dsi(struct drm_bridge *b) 530 { 531 return container_of(b, struct samsung_dsim, bridge); 532 } 533 534 static inline void samsung_dsim_write(struct samsung_dsim *dsi, 535 enum reg_idx idx, u32 val) 536 { 537 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 538 } 539 540 static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx) 541 { 542 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 543 } 544 545 static void samsung_dsim_wait_for_reset(struct samsung_dsim *dsi) 546 { 547 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 548 return; 549 550 dev_err(dsi->dev, "timeout waiting for reset\n"); 551 } 552 553 static void samsung_dsim_reset(struct samsung_dsim *dsi) 554 { 555 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; 556 557 reinit_completion(&dsi->completed); 558 samsung_dsim_write(dsi, DSIM_SWRST_REG, reset_val); 559 } 560 561 #ifndef MHZ 562 #define MHZ (1000 * 1000) 563 #endif 564 565 static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi, 566 unsigned long fin, 567 unsigned long fout, 568 u8 *p, u16 *m, u8 *s) 569 { 570 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 571 unsigned long best_freq = 0; 572 u32 min_delta = 0xffffffff; 573 u8 p_min, p_max; 574 u8 _p, best_p; 575 u16 _m, best_m; 576 u8 _s, best_s; 577 578 p_min = DIV_ROUND_UP(fin, (driver_data->pll_fin_max * MHZ)); 579 p_max = fin / (driver_data->pll_fin_min * MHZ); 580 581 for (_p = p_min; _p <= p_max; ++_p) { 582 for (_s = 0; _s <= 5; ++_s) { 583 u64 tmp; 584 u32 delta; 585 586 tmp = (u64)fout * (_p << _s); 587 do_div(tmp, fin); 588 _m = tmp; 589 if (_m < driver_data->m_min || _m > driver_data->m_max) 590 continue; 591 592 tmp = (u64)_m * fin; 593 do_div(tmp, _p); 594 if (tmp < driver_data->min_freq * MHZ || 595 tmp > driver_data->max_freq * MHZ) 596 continue; 597 598 tmp = (u64)_m * fin; 599 do_div(tmp, _p << _s); 600 601 delta = abs(fout - tmp); 602 if (delta < min_delta) { 603 best_p = _p; 604 best_m = _m; 605 best_s = _s; 606 min_delta = delta; 607 best_freq = tmp; 608 } 609 } 610 } 611 612 if (best_freq) { 613 *p = best_p; 614 *m = best_m; 615 *s = best_s; 616 } 617 618 return best_freq; 619 } 620 621 static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, 622 unsigned long freq) 623 { 624 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 625 unsigned long fin, fout; 626 int timeout; 627 u8 p, s; 628 u16 m; 629 u32 reg; 630 631 if (dsi->pll_clk) { 632 /* 633 * Ensure that the reference clock is generated with a power of 634 * two divider from its parent, but close to the PLLs upper 635 * limit. 636 */ 637 fin = clk_get_rate(clk_get_parent(dsi->pll_clk)); 638 while (fin > driver_data->pll_fin_max * MHZ) 639 fin /= 2; 640 clk_set_rate(dsi->pll_clk, fin); 641 642 fin = clk_get_rate(dsi->pll_clk); 643 } else { 644 fin = dsi->pll_clk_rate; 645 } 646 dev_dbg(dsi->dev, "PLL ref clock freq %lu\n", fin); 647 648 fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s); 649 if (!fout) { 650 dev_err(dsi->dev, 651 "failed to find PLL PMS for requested frequency\n"); 652 return 0; 653 } 654 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 655 656 writel(driver_data->reg_values[PLL_TIMER], 657 dsi->reg_base + driver_data->plltmr_reg); 658 659 reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | 660 DSIM_PLL_M(m) | DSIM_PLL_S(s); 661 662 if (driver_data->has_freqband) { 663 static const unsigned long freq_bands[] = { 664 100 * MHZ, 120 * MHZ, 160 * MHZ, 200 * MHZ, 665 270 * MHZ, 320 * MHZ, 390 * MHZ, 450 * MHZ, 666 510 * MHZ, 560 * MHZ, 640 * MHZ, 690 * MHZ, 667 770 * MHZ, 870 * MHZ, 950 * MHZ, 668 }; 669 int band; 670 671 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 672 if (fout < freq_bands[band]) 673 break; 674 675 dev_dbg(dsi->dev, "band %d\n", band); 676 677 reg |= DSIM_FREQ_BAND(band); 678 } 679 680 if (dsi->swap_dn_dp_clk) 681 reg |= DSIM_PLL_DPDNSWAP_CLK; 682 if (dsi->swap_dn_dp_data) 683 reg |= DSIM_PLL_DPDNSWAP_DAT; 684 685 samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg); 686 687 timeout = 1000; 688 do { 689 if (timeout-- == 0) { 690 dev_err(dsi->dev, "PLL failed to stabilize\n"); 691 return 0; 692 } 693 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG); 694 } while ((reg & DSIM_PLL_STABLE) == 0); 695 696 dsi->hs_clock = fout; 697 698 return fout; 699 } 700 701 static int samsung_dsim_enable_clock(struct samsung_dsim *dsi) 702 { 703 unsigned long hs_clk, byte_clk, esc_clk, pix_clk; 704 unsigned long esc_div; 705 u32 reg; 706 struct drm_display_mode *m = &dsi->mode; 707 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 708 709 /* m->clock is in KHz */ 710 pix_clk = m->clock * 1000; 711 712 /* Use burst_clk_rate if available, otherwise use the pix_clk */ 713 if (dsi->burst_clk_rate) 714 hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); 715 else 716 hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes)); 717 718 if (!hs_clk) { 719 dev_err(dsi->dev, "failed to configure DSI PLL\n"); 720 return -EFAULT; 721 } 722 723 byte_clk = hs_clk / 8; 724 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 725 esc_clk = byte_clk / esc_div; 726 727 if (esc_clk > 20 * MHZ) { 728 ++esc_div; 729 esc_clk = byte_clk / esc_div; 730 } 731 732 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 733 hs_clk, byte_clk, esc_clk); 734 735 reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG); 736 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK 737 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS 738 | DSIM_BYTE_CLK_SRC_MASK); 739 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN 740 | DSIM_ESC_PRESCALER(esc_div) 741 | DSIM_LANE_ESC_CLK_EN_CLK 742 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) 743 | DSIM_BYTE_CLK_SRC(0) 744 | DSIM_TX_REQUEST_HSCLK; 745 samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg); 746 747 return 0; 748 } 749 750 static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi) 751 { 752 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 753 const unsigned int *reg_values = driver_data->reg_values; 754 u32 reg; 755 struct phy_configure_opts_mipi_dphy cfg; 756 int clk_prepare, lpx, clk_zero, clk_post, clk_trail; 757 int hs_exit, hs_prepare, hs_zero, hs_trail; 758 unsigned long long byte_clock = dsi->hs_clock / 8; 759 760 if (driver_data->has_freqband) 761 return; 762 763 phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock, 764 dsi->lanes, &cfg); 765 766 /* 767 * TODO: 768 * The tech Applications Processor manuals for i.MX8M Mini, Nano, 769 * and Plus don't state what the definition of the PHYTIMING 770 * bits are beyond their address and bit position. 771 * After reviewing NXP's downstream code, it appears 772 * that the various PHYTIMING registers take the number 773 * of cycles and use various dividers on them. This 774 * calculation does not result in an exact match to the 775 * downstream code, but it is very close to the values 776 * generated by their lookup table, and it appears 777 * to sync at a variety of resolutions. If someone 778 * can get a more accurate mathematical equation needed 779 * for these registers, this should be updated. 780 */ 781 782 lpx = PS_TO_CYCLE(cfg.lpx, byte_clock); 783 hs_exit = PS_TO_CYCLE(cfg.hs_exit, byte_clock); 784 clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, byte_clock); 785 clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock); 786 clk_post = PS_TO_CYCLE(cfg.clk_post, byte_clock); 787 clk_trail = PS_TO_CYCLE(cfg.clk_trail, byte_clock); 788 hs_prepare = PS_TO_CYCLE(cfg.hs_prepare, byte_clock); 789 hs_zero = PS_TO_CYCLE(cfg.hs_zero, byte_clock); 790 hs_trail = PS_TO_CYCLE(cfg.hs_trail, byte_clock); 791 792 /* B D-PHY: D-PHY Master & Slave Analog Block control */ 793 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | 794 reg_values[PHYCTRL_SLEW_UP]; 795 796 samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg); 797 798 /* 799 * T LPX: Transmitted length of any Low-Power state period 800 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 801 * burst 802 */ 803 804 reg = DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit); 805 806 samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg); 807 808 /* 809 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 810 * Line state immediately before the HS-0 Line state starting the 811 * HS transmission 812 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 813 * transmitting the Clock. 814 * T CLK_POST: Time that the transmitter continues to send HS clock 815 * after the last associated Data Lane has transitioned to LP Mode 816 * Interval is defined as the period from the end of T HS-TRAIL to 817 * the beginning of T CLK-TRAIL 818 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 819 * the last payload clock bit of a HS transmission burst 820 */ 821 822 reg = DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare) | 823 DSIM_PHYTIMING1_CLK_ZERO(clk_zero) | 824 DSIM_PHYTIMING1_CLK_POST(clk_post) | 825 DSIM_PHYTIMING1_CLK_TRAIL(clk_trail); 826 827 samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg); 828 829 /* 830 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 831 * Line state immediately before the HS-0 Line state starting the 832 * HS transmission 833 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 834 * transmitting the Sync sequence. 835 * T HS-TRAIL: Time that the transmitter drives the flipped differential 836 * state after last payload data bit of a HS transmission burst 837 */ 838 839 reg = DSIM_PHYTIMING2_HS_PREPARE(hs_prepare) | 840 DSIM_PHYTIMING2_HS_ZERO(hs_zero) | 841 DSIM_PHYTIMING2_HS_TRAIL(hs_trail); 842 843 samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg); 844 } 845 846 static void samsung_dsim_disable_clock(struct samsung_dsim *dsi) 847 { 848 u32 reg; 849 850 reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG); 851 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK 852 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); 853 samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg); 854 855 reg = samsung_dsim_read(dsi, DSIM_PLLCTRL_REG); 856 reg &= ~DSIM_PLL_EN; 857 samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg); 858 } 859 860 static void samsung_dsim_enable_lane(struct samsung_dsim *dsi, u32 lane) 861 { 862 u32 reg = samsung_dsim_read(dsi, DSIM_CONFIG_REG); 863 864 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | 865 DSIM_LANE_EN(lane)); 866 samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg); 867 } 868 869 static int samsung_dsim_init_link(struct samsung_dsim *dsi) 870 { 871 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 872 int timeout; 873 u32 reg; 874 u32 lanes_mask; 875 876 /* Initialize FIFO pointers */ 877 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG); 878 reg &= ~0x1f; 879 samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg); 880 881 usleep_range(9000, 11000); 882 883 reg |= 0x1f; 884 samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg); 885 usleep_range(9000, 11000); 886 887 /* DSI configuration */ 888 reg = 0; 889 890 /* 891 * The first bit of mode_flags specifies display configuration. 892 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 893 * mode, otherwise it will support command mode. 894 */ 895 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 896 reg |= DSIM_VIDEO_MODE; 897 898 /* 899 * The user manual describes that following bits are ignored in 900 * command mode. 901 */ 902 if (!(dsi->mode_flags & MIPI_DSI_MODE_VSYNC_FLUSH)) 903 reg |= DSIM_MFLUSH_VS; 904 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 905 reg |= DSIM_SYNC_INFORM; 906 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 907 reg |= DSIM_BURST_MODE; 908 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 909 reg |= DSIM_AUTO_MODE; 910 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 911 reg |= DSIM_HSE_DISABLE_MODE; 912 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 913 reg |= DSIM_HFP_DISABLE_MODE; 914 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 915 reg |= DSIM_HBP_DISABLE_MODE; 916 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 917 reg |= DSIM_HSA_DISABLE_MODE; 918 } 919 920 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 921 reg |= DSIM_EOT_DISABLE; 922 923 switch (dsi->format) { 924 case MIPI_DSI_FMT_RGB888: 925 reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 926 break; 927 case MIPI_DSI_FMT_RGB666: 928 reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 929 break; 930 case MIPI_DSI_FMT_RGB666_PACKED: 931 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 932 break; 933 case MIPI_DSI_FMT_RGB565: 934 reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 935 break; 936 default: 937 dev_err(dsi->dev, "invalid pixel format\n"); 938 return -EINVAL; 939 } 940 941 /* 942 * Use non-continuous clock mode if the periparal wants and 943 * host controller supports 944 * 945 * In non-continous clock mode, host controller will turn off 946 * the HS clock between high-speed transmissions to reduce 947 * power consumption. 948 */ 949 if (driver_data->has_clklane_stop && 950 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 951 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) 952 reg |= DSIM_NON_CONTINUOUS_CLKLANE; 953 954 reg |= DSIM_CLKLANE_STOP; 955 } 956 samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg); 957 958 lanes_mask = BIT(dsi->lanes) - 1; 959 samsung_dsim_enable_lane(dsi, lanes_mask); 960 961 /* Check clock and data lane state are stop state */ 962 timeout = 100; 963 do { 964 if (timeout-- == 0) { 965 dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 966 return -EFAULT; 967 } 968 969 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG); 970 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 971 != DSIM_STOP_STATE_DAT(lanes_mask)) 972 continue; 973 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 974 975 reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); 976 reg &= ~DSIM_STOP_STATE_CNT_MASK; 977 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); 978 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg); 979 980 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 981 samsung_dsim_write(dsi, DSIM_TIMEOUT_REG, reg); 982 983 return 0; 984 } 985 986 static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) 987 { 988 struct drm_display_mode *m = &dsi->mode; 989 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; 990 u32 reg; 991 992 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 993 u64 byte_clk = dsi->hs_clock / 8; 994 u64 pix_clk = m->clock * 1000; 995 996 int hfp = DIV64_U64_ROUND_UP((m->hsync_start - m->hdisplay) * byte_clk, pix_clk); 997 int hbp = DIV64_U64_ROUND_UP((m->htotal - m->hsync_end) * byte_clk, pix_clk); 998 int hsa = DIV64_U64_ROUND_UP((m->hsync_end - m->hsync_start) * byte_clk, pix_clk); 999 1000 /* remove packet overhead when possible */ 1001 hfp = max(hfp - 6, 0); 1002 hbp = max(hbp - 6, 0); 1003 hsa = max(hsa - 6, 0); 1004 1005 dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u", 1006 hfp, hbp, hsa); 1007 1008 reg = DSIM_CMD_ALLOW(0xf) 1009 | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) 1010 | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); 1011 samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg); 1012 1013 reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp); 1014 samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg); 1015 1016 reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) 1017 | DSIM_MAIN_HSA(hsa); 1018 samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg); 1019 } 1020 reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | 1021 DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol); 1022 1023 samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg); 1024 1025 dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay); 1026 } 1027 1028 static void samsung_dsim_set_display_enable(struct samsung_dsim *dsi, bool enable) 1029 { 1030 u32 reg; 1031 1032 reg = samsung_dsim_read(dsi, DSIM_MDRESOL_REG); 1033 if (enable) 1034 reg |= DSIM_MAIN_STAND_BY; 1035 else 1036 reg &= ~DSIM_MAIN_STAND_BY; 1037 samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg); 1038 } 1039 1040 static int samsung_dsim_wait_for_hdr_fifo(struct samsung_dsim *dsi) 1041 { 1042 int timeout = 2000; 1043 1044 do { 1045 u32 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG); 1046 1047 if (!dsi->driver_data->has_broken_fifoctrl_emptyhdr) { 1048 if (reg & DSIM_SFR_HEADER_EMPTY) 1049 return 0; 1050 } else { 1051 if (!(reg & DSIM_SFR_HEADER_FULL)) { 1052 /* 1053 * Wait a little bit, so the pending data can 1054 * actually leave the FIFO to avoid overflow. 1055 */ 1056 if (!cond_resched()) 1057 usleep_range(950, 1050); 1058 return 0; 1059 } 1060 } 1061 1062 if (!cond_resched()) 1063 usleep_range(950, 1050); 1064 } while (--timeout); 1065 1066 return -ETIMEDOUT; 1067 } 1068 1069 static void samsung_dsim_set_cmd_lpm(struct samsung_dsim *dsi, bool lpm) 1070 { 1071 u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); 1072 1073 if (lpm) 1074 v |= DSIM_CMD_LPDT_LP; 1075 else 1076 v &= ~DSIM_CMD_LPDT_LP; 1077 1078 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v); 1079 } 1080 1081 static void samsung_dsim_force_bta(struct samsung_dsim *dsi) 1082 { 1083 u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); 1084 1085 v |= DSIM_FORCE_BTA; 1086 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v); 1087 } 1088 1089 static void samsung_dsim_send_to_fifo(struct samsung_dsim *dsi, 1090 struct samsung_dsim_transfer *xfer) 1091 { 1092 struct device *dev = dsi->dev; 1093 struct mipi_dsi_packet *pkt = &xfer->packet; 1094 const u8 *payload = pkt->payload + xfer->tx_done; 1095 u16 length = pkt->payload_length - xfer->tx_done; 1096 bool first = !xfer->tx_done; 1097 u32 reg; 1098 1099 dev_dbg(dev, "< xfer %pK: tx len %u, done %u, rx len %u, done %u\n", 1100 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done); 1101 1102 if (length > DSI_TX_FIFO_SIZE) 1103 length = DSI_TX_FIFO_SIZE; 1104 1105 xfer->tx_done += length; 1106 1107 /* Send payload */ 1108 while (length >= 4) { 1109 reg = get_unaligned_le32(payload); 1110 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg); 1111 payload += 4; 1112 length -= 4; 1113 } 1114 1115 reg = 0; 1116 switch (length) { 1117 case 3: 1118 reg |= payload[2] << 16; 1119 fallthrough; 1120 case 2: 1121 reg |= payload[1] << 8; 1122 fallthrough; 1123 case 1: 1124 reg |= payload[0]; 1125 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg); 1126 break; 1127 } 1128 1129 /* Send packet header */ 1130 if (!first) 1131 return; 1132 1133 reg = get_unaligned_le32(pkt->header); 1134 if (samsung_dsim_wait_for_hdr_fifo(dsi)) { 1135 dev_err(dev, "waiting for header FIFO timed out\n"); 1136 return; 1137 } 1138 1139 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 1140 dsi->state & DSIM_STATE_CMD_LPM)) { 1141 samsung_dsim_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 1142 dsi->state ^= DSIM_STATE_CMD_LPM; 1143 } 1144 1145 samsung_dsim_write(dsi, DSIM_PKTHDR_REG, reg); 1146 1147 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 1148 samsung_dsim_force_bta(dsi); 1149 } 1150 1151 static void samsung_dsim_read_from_fifo(struct samsung_dsim *dsi, 1152 struct samsung_dsim_transfer *xfer) 1153 { 1154 u8 *payload = xfer->rx_payload + xfer->rx_done; 1155 bool first = !xfer->rx_done; 1156 struct device *dev = dsi->dev; 1157 u16 length; 1158 u32 reg; 1159 1160 if (first) { 1161 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1162 1163 switch (reg & 0x3f) { 1164 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 1165 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1166 if (xfer->rx_len >= 2) { 1167 payload[1] = reg >> 16; 1168 ++xfer->rx_done; 1169 } 1170 fallthrough; 1171 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 1172 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1173 payload[0] = reg >> 8; 1174 ++xfer->rx_done; 1175 xfer->rx_len = xfer->rx_done; 1176 xfer->result = 0; 1177 goto clear_fifo; 1178 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1179 dev_err(dev, "DSI Error Report: 0x%04x\n", (reg >> 8) & 0xffff); 1180 xfer->result = 0; 1181 goto clear_fifo; 1182 } 1183 1184 length = (reg >> 8) & 0xffff; 1185 if (length > xfer->rx_len) { 1186 dev_err(dev, 1187 "response too long (%u > %u bytes), stripping\n", 1188 xfer->rx_len, length); 1189 length = xfer->rx_len; 1190 } else if (length < xfer->rx_len) { 1191 xfer->rx_len = length; 1192 } 1193 } 1194 1195 length = xfer->rx_len - xfer->rx_done; 1196 xfer->rx_done += length; 1197 1198 /* Receive payload */ 1199 while (length >= 4) { 1200 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1201 payload[0] = (reg >> 0) & 0xff; 1202 payload[1] = (reg >> 8) & 0xff; 1203 payload[2] = (reg >> 16) & 0xff; 1204 payload[3] = (reg >> 24) & 0xff; 1205 payload += 4; 1206 length -= 4; 1207 } 1208 1209 if (length) { 1210 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1211 switch (length) { 1212 case 3: 1213 payload[2] = (reg >> 16) & 0xff; 1214 fallthrough; 1215 case 2: 1216 payload[1] = (reg >> 8) & 0xff; 1217 fallthrough; 1218 case 1: 1219 payload[0] = reg & 0xff; 1220 } 1221 } 1222 1223 if (xfer->rx_done == xfer->rx_len) 1224 xfer->result = 0; 1225 1226 clear_fifo: 1227 length = DSI_RX_FIFO_SIZE / 4; 1228 do { 1229 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1230 if (reg == DSI_RX_FIFO_EMPTY) 1231 break; 1232 } while (--length); 1233 } 1234 1235 static void samsung_dsim_transfer_start(struct samsung_dsim *dsi) 1236 { 1237 unsigned long flags; 1238 struct samsung_dsim_transfer *xfer; 1239 bool start = false; 1240 1241 again: 1242 spin_lock_irqsave(&dsi->transfer_lock, flags); 1243 1244 if (list_empty(&dsi->transfer_list)) { 1245 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1246 return; 1247 } 1248 1249 xfer = list_first_entry(&dsi->transfer_list, 1250 struct samsung_dsim_transfer, list); 1251 1252 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1253 1254 if (xfer->packet.payload_length && 1255 xfer->tx_done == xfer->packet.payload_length) 1256 /* waiting for RX */ 1257 return; 1258 1259 samsung_dsim_send_to_fifo(dsi, xfer); 1260 1261 if (xfer->packet.payload_length || xfer->rx_len) 1262 return; 1263 1264 xfer->result = 0; 1265 complete(&xfer->completed); 1266 1267 spin_lock_irqsave(&dsi->transfer_lock, flags); 1268 1269 list_del_init(&xfer->list); 1270 start = !list_empty(&dsi->transfer_list); 1271 1272 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1273 1274 if (start) 1275 goto again; 1276 } 1277 1278 static bool samsung_dsim_transfer_finish(struct samsung_dsim *dsi) 1279 { 1280 struct samsung_dsim_transfer *xfer; 1281 unsigned long flags; 1282 bool start = true; 1283 1284 spin_lock_irqsave(&dsi->transfer_lock, flags); 1285 1286 if (list_empty(&dsi->transfer_list)) { 1287 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1288 return false; 1289 } 1290 1291 xfer = list_first_entry(&dsi->transfer_list, 1292 struct samsung_dsim_transfer, list); 1293 1294 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1295 1296 dev_dbg(dsi->dev, 1297 "> xfer %pK, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n", 1298 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len, 1299 xfer->rx_done); 1300 1301 if (xfer->tx_done != xfer->packet.payload_length) 1302 return true; 1303 1304 if (xfer->rx_done != xfer->rx_len) 1305 samsung_dsim_read_from_fifo(dsi, xfer); 1306 1307 if (xfer->rx_done != xfer->rx_len) 1308 return true; 1309 1310 spin_lock_irqsave(&dsi->transfer_lock, flags); 1311 1312 list_del_init(&xfer->list); 1313 start = !list_empty(&dsi->transfer_list); 1314 1315 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1316 1317 if (!xfer->rx_len) 1318 xfer->result = 0; 1319 complete(&xfer->completed); 1320 1321 return start; 1322 } 1323 1324 static void samsung_dsim_remove_transfer(struct samsung_dsim *dsi, 1325 struct samsung_dsim_transfer *xfer) 1326 { 1327 unsigned long flags; 1328 bool start; 1329 1330 spin_lock_irqsave(&dsi->transfer_lock, flags); 1331 1332 if (!list_empty(&dsi->transfer_list) && 1333 xfer == list_first_entry(&dsi->transfer_list, 1334 struct samsung_dsim_transfer, list)) { 1335 list_del_init(&xfer->list); 1336 start = !list_empty(&dsi->transfer_list); 1337 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1338 if (start) 1339 samsung_dsim_transfer_start(dsi); 1340 return; 1341 } 1342 1343 list_del_init(&xfer->list); 1344 1345 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1346 } 1347 1348 static int samsung_dsim_transfer(struct samsung_dsim *dsi, 1349 struct samsung_dsim_transfer *xfer) 1350 { 1351 unsigned long flags; 1352 bool stopped; 1353 1354 xfer->tx_done = 0; 1355 xfer->rx_done = 0; 1356 xfer->result = -ETIMEDOUT; 1357 init_completion(&xfer->completed); 1358 1359 spin_lock_irqsave(&dsi->transfer_lock, flags); 1360 1361 stopped = list_empty(&dsi->transfer_list); 1362 list_add_tail(&xfer->list, &dsi->transfer_list); 1363 1364 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1365 1366 if (stopped) 1367 samsung_dsim_transfer_start(dsi); 1368 1369 wait_for_completion_timeout(&xfer->completed, 1370 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 1371 if (xfer->result == -ETIMEDOUT) { 1372 struct mipi_dsi_packet *pkt = &xfer->packet; 1373 1374 samsung_dsim_remove_transfer(dsi, xfer); 1375 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header, 1376 (int)pkt->payload_length, pkt->payload); 1377 return -ETIMEDOUT; 1378 } 1379 1380 /* Also covers hardware timeout condition */ 1381 return xfer->result; 1382 } 1383 1384 static irqreturn_t samsung_dsim_irq(int irq, void *dev_id) 1385 { 1386 struct samsung_dsim *dsi = dev_id; 1387 u32 status; 1388 1389 status = samsung_dsim_read(dsi, DSIM_INTSRC_REG); 1390 if (!status) { 1391 static unsigned long j; 1392 1393 if (printk_timed_ratelimit(&j, 500)) 1394 dev_warn(dsi->dev, "spurious interrupt\n"); 1395 return IRQ_HANDLED; 1396 } 1397 samsung_dsim_write(dsi, DSIM_INTSRC_REG, status); 1398 1399 if (status & DSIM_INT_SW_RST_RELEASE) { 1400 unsigned long mask = ~(DSIM_INT_RX_DONE | 1401 DSIM_INT_SFR_FIFO_EMPTY | 1402 DSIM_INT_SFR_HDR_FIFO_EMPTY | 1403 DSIM_INT_RX_ECC_ERR | 1404 DSIM_INT_SW_RST_RELEASE); 1405 samsung_dsim_write(dsi, DSIM_INTMSK_REG, mask); 1406 complete(&dsi->completed); 1407 return IRQ_HANDLED; 1408 } 1409 1410 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1411 DSIM_INT_PLL_STABLE))) 1412 return IRQ_HANDLED; 1413 1414 if (samsung_dsim_transfer_finish(dsi)) 1415 samsung_dsim_transfer_start(dsi); 1416 1417 return IRQ_HANDLED; 1418 } 1419 1420 static void samsung_dsim_enable_irq(struct samsung_dsim *dsi) 1421 { 1422 enable_irq(dsi->irq); 1423 1424 if (dsi->te_gpio) 1425 enable_irq(gpiod_to_irq(dsi->te_gpio)); 1426 } 1427 1428 static void samsung_dsim_disable_irq(struct samsung_dsim *dsi) 1429 { 1430 if (dsi->te_gpio) 1431 disable_irq(gpiod_to_irq(dsi->te_gpio)); 1432 1433 disable_irq(dsi->irq); 1434 } 1435 1436 static int samsung_dsim_init(struct samsung_dsim *dsi) 1437 { 1438 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 1439 1440 if (dsi->state & DSIM_STATE_INITIALIZED) 1441 return 0; 1442 1443 samsung_dsim_reset(dsi); 1444 samsung_dsim_enable_irq(dsi); 1445 1446 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) 1447 samsung_dsim_enable_lane(dsi, BIT(dsi->lanes) - 1); 1448 1449 samsung_dsim_enable_clock(dsi); 1450 if (driver_data->wait_for_reset) 1451 samsung_dsim_wait_for_reset(dsi); 1452 samsung_dsim_set_phy_ctrl(dsi); 1453 samsung_dsim_init_link(dsi); 1454 1455 dsi->state |= DSIM_STATE_INITIALIZED; 1456 1457 return 0; 1458 } 1459 1460 static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge, 1461 struct drm_atomic_state *state) 1462 { 1463 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1464 int ret; 1465 1466 if (dsi->state & DSIM_STATE_ENABLED) 1467 return; 1468 1469 ret = pm_runtime_resume_and_get(dsi->dev); 1470 if (ret < 0) { 1471 dev_err(dsi->dev, "failed to enable DSI device.\n"); 1472 return; 1473 } 1474 1475 dsi->state |= DSIM_STATE_ENABLED; 1476 1477 /* 1478 * For Exynos-DSIM the downstream bridge, or panel are expecting 1479 * the host initialization during DSI transfer. 1480 */ 1481 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) { 1482 ret = samsung_dsim_init(dsi); 1483 if (ret) 1484 return; 1485 } 1486 } 1487 1488 static void samsung_dsim_atomic_enable(struct drm_bridge *bridge, 1489 struct drm_atomic_state *state) 1490 { 1491 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1492 1493 samsung_dsim_set_display_mode(dsi); 1494 samsung_dsim_set_display_enable(dsi, true); 1495 1496 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; 1497 } 1498 1499 static void samsung_dsim_atomic_disable(struct drm_bridge *bridge, 1500 struct drm_atomic_state *state) 1501 { 1502 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1503 1504 if (!(dsi->state & DSIM_STATE_ENABLED)) 1505 return; 1506 1507 samsung_dsim_set_display_enable(dsi, false); 1508 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; 1509 } 1510 1511 static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge, 1512 struct drm_atomic_state *state) 1513 { 1514 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1515 1516 dsi->state &= ~DSIM_STATE_ENABLED; 1517 pm_runtime_put_sync(dsi->dev); 1518 } 1519 1520 /* 1521 * This pixel output formats list referenced from, 1522 * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022 1523 * 3.7.4 Pixel formats 1524 * Table 14. DSI pixel packing formats 1525 */ 1526 static const u32 samsung_dsim_pixel_output_fmts[] = { 1527 MEDIA_BUS_FMT_YUYV10_1X20, 1528 MEDIA_BUS_FMT_YUYV12_1X24, 1529 MEDIA_BUS_FMT_UYVY8_1X16, 1530 MEDIA_BUS_FMT_RGB101010_1X30, 1531 MEDIA_BUS_FMT_RGB121212_1X36, 1532 MEDIA_BUS_FMT_RGB565_1X16, 1533 MEDIA_BUS_FMT_RGB666_1X18, 1534 MEDIA_BUS_FMT_RGB888_1X24, 1535 }; 1536 1537 static bool samsung_dsim_pixel_output_fmt_supported(u32 fmt) 1538 { 1539 int i; 1540 1541 if (fmt == MEDIA_BUS_FMT_FIXED) 1542 return false; 1543 1544 for (i = 0; i < ARRAY_SIZE(samsung_dsim_pixel_output_fmts); i++) { 1545 if (samsung_dsim_pixel_output_fmts[i] == fmt) 1546 return true; 1547 } 1548 1549 return false; 1550 } 1551 1552 static u32 * 1553 samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 1554 struct drm_bridge_state *bridge_state, 1555 struct drm_crtc_state *crtc_state, 1556 struct drm_connector_state *conn_state, 1557 u32 output_fmt, 1558 unsigned int *num_input_fmts) 1559 { 1560 u32 *input_fmts; 1561 1562 input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); 1563 if (!input_fmts) 1564 return NULL; 1565 1566 if (!samsung_dsim_pixel_output_fmt_supported(output_fmt)) 1567 /* 1568 * Some bridge/display drivers are still not able to pass the 1569 * correct format, so handle those pipelines by falling back 1570 * to the default format till the supported formats finalized. 1571 */ 1572 output_fmt = MEDIA_BUS_FMT_RGB888_1X24; 1573 1574 input_fmts[0] = output_fmt; 1575 *num_input_fmts = 1; 1576 1577 return input_fmts; 1578 } 1579 1580 static int samsung_dsim_atomic_check(struct drm_bridge *bridge, 1581 struct drm_bridge_state *bridge_state, 1582 struct drm_crtc_state *crtc_state, 1583 struct drm_connector_state *conn_state) 1584 { 1585 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1586 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 1587 1588 /* 1589 * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM 1590 * inverts HS/VS/DE sync signals polarity, therefore, while 1591 * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 1592 * 13.6.3.5.2 RGB interface 1593 * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 1594 * 13.6.2.7.2 RGB interface 1595 * both claim "Vsync, Hsync, and VDEN are active high signals.", the 1596 * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. 1597 * 1598 * The i.MX8M Plus glue logic between LCDIFv3 and DSIM does not 1599 * implement the same behavior, therefore LCDIFv3 must generate 1600 * HS/VS/DE signals active HIGH. 1601 */ 1602 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) { 1603 adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1604 adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1605 } else if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MP) { 1606 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1607 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1608 } 1609 1610 /* 1611 * When using video sync pulses, the HFP, HBP, and HSA are divided between 1612 * the available lanes if there is more than one lane. For certain 1613 * timings and lane configurations, the HFP may not be evenly divisible. 1614 * If the HFP is rounded down, it ends up being too small which can cause 1615 * some monitors to not sync properly. In these instances, adjust htotal 1616 * and hsync to round the HFP up, and recalculate the htotal. Through trial 1617 * and error, it appears that the HBP and HSA do not appearto need the same 1618 * correction that HFP does. 1619 */ 1620 if (dsi->lanes > 1) { 1621 int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay; 1622 int remainder = hfp % dsi->lanes; 1623 1624 if (remainder) { 1625 adjusted_mode->hsync_start += remainder; 1626 adjusted_mode->hsync_end += remainder; 1627 adjusted_mode->htotal += remainder; 1628 } 1629 } 1630 1631 return 0; 1632 } 1633 1634 static void samsung_dsim_mode_set(struct drm_bridge *bridge, 1635 const struct drm_display_mode *mode, 1636 const struct drm_display_mode *adjusted_mode) 1637 { 1638 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1639 1640 drm_mode_copy(&dsi->mode, adjusted_mode); 1641 } 1642 1643 static int samsung_dsim_attach(struct drm_bridge *bridge, 1644 struct drm_encoder *encoder, 1645 enum drm_bridge_attach_flags flags) 1646 { 1647 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1648 1649 return drm_bridge_attach(encoder, dsi->out_bridge, bridge, 1650 flags); 1651 } 1652 1653 static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = { 1654 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1655 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1656 .atomic_reset = drm_atomic_helper_bridge_reset, 1657 .atomic_get_input_bus_fmts = samsung_dsim_atomic_get_input_bus_fmts, 1658 .atomic_check = samsung_dsim_atomic_check, 1659 .atomic_pre_enable = samsung_dsim_atomic_pre_enable, 1660 .atomic_enable = samsung_dsim_atomic_enable, 1661 .atomic_disable = samsung_dsim_atomic_disable, 1662 .atomic_post_disable = samsung_dsim_atomic_post_disable, 1663 .mode_set = samsung_dsim_mode_set, 1664 .attach = samsung_dsim_attach, 1665 }; 1666 1667 static irqreturn_t samsung_dsim_te_irq_handler(int irq, void *dev_id) 1668 { 1669 struct samsung_dsim *dsi = (struct samsung_dsim *)dev_id; 1670 const struct samsung_dsim_plat_data *pdata = dsi->plat_data; 1671 1672 if (pdata->host_ops && pdata->host_ops->te_irq_handler) 1673 return pdata->host_ops->te_irq_handler(dsi); 1674 1675 return IRQ_HANDLED; 1676 } 1677 1678 static int samsung_dsim_register_te_irq(struct samsung_dsim *dsi, struct device *dev) 1679 { 1680 int te_gpio_irq; 1681 int ret; 1682 1683 dsi->te_gpio = devm_gpiod_get_optional(dev, "te", GPIOD_IN); 1684 if (!dsi->te_gpio) 1685 return 0; 1686 else if (IS_ERR(dsi->te_gpio)) 1687 return dev_err_probe(dev, PTR_ERR(dsi->te_gpio), "failed to get te GPIO\n"); 1688 1689 te_gpio_irq = gpiod_to_irq(dsi->te_gpio); 1690 1691 ret = request_threaded_irq(te_gpio_irq, samsung_dsim_te_irq_handler, NULL, 1692 IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi); 1693 if (ret) { 1694 dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1695 gpiod_put(dsi->te_gpio); 1696 return ret; 1697 } 1698 1699 return 0; 1700 } 1701 1702 static int samsung_dsim_host_attach(struct mipi_dsi_host *host, 1703 struct mipi_dsi_device *device) 1704 { 1705 struct samsung_dsim *dsi = host_to_dsi(host); 1706 const struct samsung_dsim_plat_data *pdata = dsi->plat_data; 1707 struct device *dev = dsi->dev; 1708 struct device_node *np = dev->of_node; 1709 struct device_node *remote; 1710 struct drm_panel *panel; 1711 int ret; 1712 1713 /* 1714 * Devices can also be child nodes when we also control that device 1715 * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device). 1716 * 1717 * Lookup for a child node of the given parent that isn't either port 1718 * or ports. 1719 */ 1720 for_each_available_child_of_node(np, remote) { 1721 if (of_node_name_eq(remote, "port") || 1722 of_node_name_eq(remote, "ports")) 1723 continue; 1724 1725 goto of_find_panel_or_bridge; 1726 } 1727 1728 /* 1729 * of_graph_get_remote_node() produces a noisy error message if port 1730 * node isn't found and the absence of the port is a legit case here, 1731 * so at first we silently check whether graph presents in the 1732 * device-tree node. 1733 */ 1734 if (!of_graph_is_present(np)) 1735 return -ENODEV; 1736 1737 remote = of_graph_get_remote_node(np, 1, 0); 1738 1739 of_find_panel_or_bridge: 1740 if (!remote) 1741 return -ENODEV; 1742 1743 panel = of_drm_find_panel(remote); 1744 if (!IS_ERR(panel)) { 1745 dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel); 1746 } else { 1747 dsi->out_bridge = of_drm_find_bridge(remote); 1748 if (!dsi->out_bridge) 1749 dsi->out_bridge = ERR_PTR(-EINVAL); 1750 } 1751 1752 of_node_put(remote); 1753 1754 if (IS_ERR(dsi->out_bridge)) { 1755 ret = PTR_ERR(dsi->out_bridge); 1756 DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret); 1757 return ret; 1758 } 1759 1760 DRM_DEV_INFO(dev, "Attached %s device (lanes:%d bpp:%d mode-flags:0x%lx)\n", 1761 device->name, device->lanes, 1762 mipi_dsi_pixel_format_to_bpp(device->format), 1763 device->mode_flags); 1764 1765 drm_bridge_add(&dsi->bridge); 1766 1767 /* 1768 * This is a temporary solution and should be made by more generic way. 1769 * 1770 * If attached panel device is for command mode one, dsi should register 1771 * TE interrupt handler. 1772 */ 1773 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1774 ret = samsung_dsim_register_te_irq(dsi, &device->dev); 1775 if (ret) 1776 return ret; 1777 } 1778 1779 if (pdata->host_ops && pdata->host_ops->attach) { 1780 ret = pdata->host_ops->attach(dsi, device); 1781 if (ret) 1782 return ret; 1783 } 1784 1785 dsi->lanes = device->lanes; 1786 dsi->format = device->format; 1787 dsi->mode_flags = device->mode_flags; 1788 1789 return 0; 1790 } 1791 1792 static void samsung_dsim_unregister_te_irq(struct samsung_dsim *dsi) 1793 { 1794 if (dsi->te_gpio) { 1795 free_irq(gpiod_to_irq(dsi->te_gpio), dsi); 1796 gpiod_put(dsi->te_gpio); 1797 } 1798 } 1799 1800 static int samsung_dsim_host_detach(struct mipi_dsi_host *host, 1801 struct mipi_dsi_device *device) 1802 { 1803 struct samsung_dsim *dsi = host_to_dsi(host); 1804 const struct samsung_dsim_plat_data *pdata = dsi->plat_data; 1805 1806 dsi->out_bridge = NULL; 1807 1808 if (pdata->host_ops && pdata->host_ops->detach) 1809 pdata->host_ops->detach(dsi, device); 1810 1811 samsung_dsim_unregister_te_irq(dsi); 1812 1813 drm_bridge_remove(&dsi->bridge); 1814 1815 return 0; 1816 } 1817 1818 static ssize_t samsung_dsim_host_transfer(struct mipi_dsi_host *host, 1819 const struct mipi_dsi_msg *msg) 1820 { 1821 struct samsung_dsim *dsi = host_to_dsi(host); 1822 struct samsung_dsim_transfer xfer; 1823 int ret; 1824 1825 if (!(dsi->state & DSIM_STATE_ENABLED)) 1826 return -EINVAL; 1827 1828 ret = samsung_dsim_init(dsi); 1829 if (ret) 1830 return ret; 1831 1832 ret = mipi_dsi_create_packet(&xfer.packet, msg); 1833 if (ret < 0) 1834 return ret; 1835 1836 xfer.rx_len = msg->rx_len; 1837 xfer.rx_payload = msg->rx_buf; 1838 xfer.flags = msg->flags; 1839 1840 ret = samsung_dsim_transfer(dsi, &xfer); 1841 return (ret < 0) ? ret : xfer.rx_done; 1842 } 1843 1844 static const struct mipi_dsi_host_ops samsung_dsim_ops = { 1845 .attach = samsung_dsim_host_attach, 1846 .detach = samsung_dsim_host_detach, 1847 .transfer = samsung_dsim_host_transfer, 1848 }; 1849 1850 static int samsung_dsim_of_read_u32(const struct device_node *np, 1851 const char *propname, u32 *out_value, bool optional) 1852 { 1853 int ret = of_property_read_u32(np, propname, out_value); 1854 1855 if (ret < 0 && !optional) 1856 pr_err("%pOF: failed to get '%s' property\n", np, propname); 1857 1858 return ret; 1859 } 1860 1861 static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) 1862 { 1863 struct device *dev = dsi->dev; 1864 struct device_node *node = dev->of_node; 1865 u32 lane_polarities[5] = { 0 }; 1866 struct device_node *endpoint; 1867 int i, nr_lanes, ret; 1868 1869 ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency", 1870 &dsi->pll_clk_rate, 1); 1871 /* If it doesn't exist, read it from the clock instead of failing */ 1872 if (ret < 0) { 1873 dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n"); 1874 dsi->pll_clk = devm_clk_get(dev, "sclk_mipi"); 1875 if (IS_ERR(dsi->pll_clk)) 1876 return PTR_ERR(dsi->pll_clk); 1877 } 1878 1879 /* If it doesn't exist, use pixel clock instead of failing */ 1880 ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", 1881 &dsi->burst_clk_rate, 1); 1882 if (ret < 0) { 1883 dev_dbg(dev, "Using pixel clock for HS clock frequency\n"); 1884 dsi->burst_clk_rate = 0; 1885 } 1886 1887 ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", 1888 &dsi->esc_clk_rate, 0); 1889 if (ret < 0) 1890 return ret; 1891 1892 endpoint = of_graph_get_endpoint_by_regs(node, 1, -1); 1893 nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); 1894 if (nr_lanes > 0 && nr_lanes <= 4) { 1895 /* Polarity 0 is clock lane, 1..4 are data lanes. */ 1896 of_property_read_u32_array(endpoint, "lane-polarities", 1897 lane_polarities, nr_lanes + 1); 1898 for (i = 1; i <= nr_lanes; i++) { 1899 if (lane_polarities[1] != lane_polarities[i]) 1900 DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match"); 1901 } 1902 if (lane_polarities[0]) 1903 dsi->swap_dn_dp_clk = true; 1904 if (lane_polarities[1]) 1905 dsi->swap_dn_dp_data = true; 1906 } 1907 1908 return 0; 1909 } 1910 1911 static int generic_dsim_register_host(struct samsung_dsim *dsi) 1912 { 1913 return mipi_dsi_host_register(&dsi->dsi_host); 1914 } 1915 1916 static void generic_dsim_unregister_host(struct samsung_dsim *dsi) 1917 { 1918 mipi_dsi_host_unregister(&dsi->dsi_host); 1919 } 1920 1921 static const struct samsung_dsim_host_ops generic_dsim_host_ops = { 1922 .register_host = generic_dsim_register_host, 1923 .unregister_host = generic_dsim_unregister_host, 1924 }; 1925 1926 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_high = { 1927 .input_bus_flags = DRM_BUS_FLAG_DE_HIGH, 1928 }; 1929 1930 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_low = { 1931 .input_bus_flags = DRM_BUS_FLAG_DE_LOW, 1932 }; 1933 1934 int samsung_dsim_probe(struct platform_device *pdev) 1935 { 1936 struct device *dev = &pdev->dev; 1937 struct samsung_dsim *dsi; 1938 int ret, i; 1939 1940 dsi = devm_drm_bridge_alloc(dev, struct samsung_dsim, bridge, &samsung_dsim_bridge_funcs); 1941 if (IS_ERR(dsi)) 1942 return PTR_ERR(dsi); 1943 1944 init_completion(&dsi->completed); 1945 spin_lock_init(&dsi->transfer_lock); 1946 INIT_LIST_HEAD(&dsi->transfer_list); 1947 1948 dsi->dsi_host.ops = &samsung_dsim_ops; 1949 dsi->dsi_host.dev = dev; 1950 1951 dsi->dev = dev; 1952 dsi->plat_data = of_device_get_match_data(dev); 1953 dsi->driver_data = samsung_dsim_types[dsi->plat_data->hw_type]; 1954 1955 dsi->supplies[0].supply = "vddcore"; 1956 dsi->supplies[1].supply = "vddio"; 1957 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), 1958 dsi->supplies); 1959 if (ret) 1960 return dev_err_probe(dev, ret, "failed to get regulators\n"); 1961 1962 dsi->clks = devm_kcalloc(dev, dsi->driver_data->num_clks, 1963 sizeof(*dsi->clks), GFP_KERNEL); 1964 if (!dsi->clks) 1965 return -ENOMEM; 1966 1967 for (i = 0; i < dsi->driver_data->num_clks; i++) { 1968 dsi->clks[i] = devm_clk_get(dev, clk_names[i]); 1969 if (IS_ERR(dsi->clks[i])) { 1970 if (strcmp(clk_names[i], "sclk_mipi") == 0) { 1971 dsi->clks[i] = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME); 1972 if (!IS_ERR(dsi->clks[i])) 1973 continue; 1974 } 1975 1976 dev_info(dev, "failed to get the clock: %s\n", clk_names[i]); 1977 return PTR_ERR(dsi->clks[i]); 1978 } 1979 } 1980 1981 dsi->reg_base = devm_platform_ioremap_resource(pdev, 0); 1982 if (IS_ERR(dsi->reg_base)) 1983 return PTR_ERR(dsi->reg_base); 1984 1985 dsi->phy = devm_phy_optional_get(dev, "dsim"); 1986 if (IS_ERR(dsi->phy)) { 1987 dev_info(dev, "failed to get dsim phy\n"); 1988 return PTR_ERR(dsi->phy); 1989 } 1990 1991 dsi->irq = platform_get_irq(pdev, 0); 1992 if (dsi->irq < 0) 1993 return dsi->irq; 1994 1995 ret = devm_request_threaded_irq(dev, dsi->irq, NULL, 1996 samsung_dsim_irq, 1997 IRQF_ONESHOT | IRQF_NO_AUTOEN, 1998 dev_name(dev), dsi); 1999 if (ret) { 2000 dev_err(dev, "failed to request dsi irq\n"); 2001 return ret; 2002 } 2003 2004 ret = samsung_dsim_parse_dt(dsi); 2005 if (ret) 2006 return ret; 2007 2008 platform_set_drvdata(pdev, dsi); 2009 2010 pm_runtime_enable(dev); 2011 2012 dsi->bridge.of_node = dev->of_node; 2013 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 2014 2015 /* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */ 2016 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) 2017 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_low; 2018 else 2019 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_high; 2020 2021 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host) { 2022 ret = dsi->plat_data->host_ops->register_host(dsi); 2023 if (ret) 2024 goto err_disable_runtime; 2025 } 2026 2027 return 0; 2028 2029 err_disable_runtime: 2030 pm_runtime_disable(dev); 2031 2032 return ret; 2033 } 2034 EXPORT_SYMBOL_GPL(samsung_dsim_probe); 2035 2036 void samsung_dsim_remove(struct platform_device *pdev) 2037 { 2038 struct samsung_dsim *dsi = platform_get_drvdata(pdev); 2039 2040 pm_runtime_disable(&pdev->dev); 2041 2042 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->unregister_host) 2043 dsi->plat_data->host_ops->unregister_host(dsi); 2044 } 2045 EXPORT_SYMBOL_GPL(samsung_dsim_remove); 2046 2047 static int samsung_dsim_suspend(struct device *dev) 2048 { 2049 struct samsung_dsim *dsi = dev_get_drvdata(dev); 2050 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 2051 int ret, i; 2052 2053 usleep_range(10000, 20000); 2054 2055 if (dsi->state & DSIM_STATE_INITIALIZED) { 2056 dsi->state &= ~DSIM_STATE_INITIALIZED; 2057 2058 samsung_dsim_disable_clock(dsi); 2059 2060 samsung_dsim_disable_irq(dsi); 2061 } 2062 2063 dsi->state &= ~DSIM_STATE_CMD_LPM; 2064 2065 phy_power_off(dsi->phy); 2066 2067 for (i = driver_data->num_clks - 1; i > -1; i--) 2068 clk_disable_unprepare(dsi->clks[i]); 2069 2070 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 2071 if (ret < 0) 2072 dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 2073 2074 return 0; 2075 } 2076 2077 static int samsung_dsim_resume(struct device *dev) 2078 { 2079 struct samsung_dsim *dsi = dev_get_drvdata(dev); 2080 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 2081 int ret, i; 2082 2083 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 2084 if (ret < 0) { 2085 dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 2086 return ret; 2087 } 2088 2089 for (i = 0; i < driver_data->num_clks; i++) { 2090 ret = clk_prepare_enable(dsi->clks[i]); 2091 if (ret < 0) 2092 goto err_clk; 2093 } 2094 2095 ret = phy_power_on(dsi->phy); 2096 if (ret < 0) { 2097 dev_err(dsi->dev, "cannot enable phy %d\n", ret); 2098 goto err_clk; 2099 } 2100 2101 return 0; 2102 2103 err_clk: 2104 while (--i > -1) 2105 clk_disable_unprepare(dsi->clks[i]); 2106 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 2107 2108 return ret; 2109 } 2110 2111 const struct dev_pm_ops samsung_dsim_pm_ops = { 2112 RUNTIME_PM_OPS(samsung_dsim_suspend, samsung_dsim_resume, NULL) 2113 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2114 pm_runtime_force_resume) 2115 }; 2116 EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops); 2117 2118 static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = { 2119 .hw_type = DSIM_TYPE_IMX8MM, 2120 .host_ops = &generic_dsim_host_ops, 2121 }; 2122 2123 static const struct samsung_dsim_plat_data samsung_dsim_imx8mp_pdata = { 2124 .hw_type = DSIM_TYPE_IMX8MP, 2125 .host_ops = &generic_dsim_host_ops, 2126 }; 2127 2128 static const struct of_device_id samsung_dsim_of_match[] = { 2129 { 2130 .compatible = "fsl,imx8mm-mipi-dsim", 2131 .data = &samsung_dsim_imx8mm_pdata, 2132 }, 2133 { 2134 .compatible = "fsl,imx8mp-mipi-dsim", 2135 .data = &samsung_dsim_imx8mp_pdata, 2136 }, 2137 { /* sentinel. */ } 2138 }; 2139 MODULE_DEVICE_TABLE(of, samsung_dsim_of_match); 2140 2141 static struct platform_driver samsung_dsim_driver = { 2142 .probe = samsung_dsim_probe, 2143 .remove = samsung_dsim_remove, 2144 .driver = { 2145 .name = "samsung-dsim", 2146 .pm = pm_ptr(&samsung_dsim_pm_ops), 2147 .of_match_table = samsung_dsim_of_match, 2148 }, 2149 }; 2150 2151 module_platform_driver(samsung_dsim_driver); 2152 2153 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>"); 2154 MODULE_DESCRIPTION("Samsung MIPI DSIM controller bridge"); 2155 MODULE_LICENSE("GPL"); 2156