1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Samsung MIPI DSIM bridge driver. 4 * 5 * Copyright (C) 2021 Amarula Solutions(India) 6 * Copyright (c) 2014 Samsung Electronics Co., Ltd 7 * Author: Jagan Teki <jagan@amarulasolutions.com> 8 * 9 * Based on exynos_drm_dsi from 10 * Tomasz Figa <t.figa@samsung.com> 11 */ 12 13 #include <linux/unaligned.h> 14 15 #include <linux/clk.h> 16 #include <linux/delay.h> 17 #include <linux/export.h> 18 #include <linux/irq.h> 19 #include <linux/media-bus-format.h> 20 #include <linux/of.h> 21 #include <linux/phy/phy.h> 22 #include <linux/platform_device.h> 23 #include <linux/units.h> 24 25 #include <video/mipi_display.h> 26 27 #include <drm/bridge/samsung-dsim.h> 28 #include <drm/drm_panel.h> 29 #include <drm/drm_print.h> 30 31 /* returns true iff both arguments logically differs */ 32 #define NEQV(a, b) (!(a) ^ !(b)) 33 34 /* DSIM_STATUS */ 35 #define DSIM_STOP_STATE_DAT(x) (((x) & 0xf) << 0) 36 #define DSIM_STOP_STATE_CLK BIT(8) 37 #define DSIM_TX_READY_HS_CLK BIT(10) 38 #define DSIM_PLL_STABLE BIT(31) 39 40 /* DSIM_SWRST */ 41 #define DSIM_FUNCRST BIT(16) 42 #define DSIM_SWRST BIT(0) 43 44 /* DSIM_TIMEOUT */ 45 #define DSIM_LPDR_TIMEOUT(x) ((x) << 0) 46 #define DSIM_BTA_TIMEOUT(x) ((x) << 16) 47 48 /* DSIM_CLKCTRL */ 49 #define DSIM_ESC_PRESCALER(x) (((x) & 0xffff) << 0) 50 #define DSIM_ESC_PRESCALER_MASK (0xffff << 0) 51 #define DSIM_LANE_ESC_CLK_EN_CLK BIT(19) 52 #define DSIM_LANE_ESC_CLK_EN_DATA(x) (((x) & 0xf) << 20) 53 #define DSIM_LANE_ESC_CLK_EN_DATA_MASK (0xf << 20) 54 #define DSIM_BYTE_CLKEN BIT(24) 55 #define DSIM_BYTE_CLK_SRC(x) (((x) & 0x3) << 25) 56 #define DSIM_BYTE_CLK_SRC_MASK (0x3 << 25) 57 #define DSIM_PLL_BYPASS BIT(27) 58 #define DSIM_ESC_CLKEN BIT(28) 59 #define DSIM_TX_REQUEST_HSCLK BIT(31) 60 61 /* DSIM_CONFIG */ 62 #define DSIM_LANE_EN_CLK BIT(0) 63 #define DSIM_LANE_EN(x) (((x) & 0xf) << 1) 64 #define DSIM_NUM_OF_DATA_LANE(x) (((x) & 0x3) << 5) 65 #define DSIM_SUB_PIX_FORMAT(x) (((x) & 0x7) << 8) 66 #define DSIM_MAIN_PIX_FORMAT_MASK (0x7 << 12) 67 #define DSIM_MAIN_PIX_FORMAT_RGB888 (0x7 << 12) 68 #define DSIM_MAIN_PIX_FORMAT_RGB666 (0x6 << 12) 69 #define DSIM_MAIN_PIX_FORMAT_RGB666_P (0x5 << 12) 70 #define DSIM_MAIN_PIX_FORMAT_RGB565 (0x4 << 12) 71 #define DSIM_SUB_VC (((x) & 0x3) << 16) 72 #define DSIM_MAIN_VC (((x) & 0x3) << 18) 73 #define DSIM_HSA_DISABLE_MODE BIT(20) 74 #define DSIM_HBP_DISABLE_MODE BIT(21) 75 #define DSIM_HFP_DISABLE_MODE BIT(22) 76 /* 77 * The i.MX 8M Mini Applications Processor Reference Manual, 78 * Rev. 3, 11/2020 Page 4091 79 * The i.MX 8M Nano Applications Processor Reference Manual, 80 * Rev. 2, 07/2022 Page 3058 81 * The i.MX 8M Plus Applications Processor Reference Manual, 82 * Rev. 1, 06/2021 Page 5436 83 * all claims this bit is 'HseDisableMode' with the definition 84 * 0 = Disables transfer 85 * 1 = Enables transfer 86 * 87 * This clearly states that HSE is not a disabled bit. 88 * 89 * The naming convention follows as per the manual and the 90 * driver logic is based on the MIPI_DSI_MODE_VIDEO_HSE flag. 91 */ 92 #define DSIM_HSE_DISABLE_MODE BIT(23) 93 #define DSIM_AUTO_MODE BIT(24) 94 #define DSIM_VIDEO_MODE BIT(25) 95 #define DSIM_BURST_MODE BIT(26) 96 #define DSIM_SYNC_INFORM BIT(27) 97 #define DSIM_EOT_DISABLE BIT(28) 98 #define DSIM_MFLUSH_VS BIT(29) 99 /* This flag is valid only for exynos3250/3472/5260/5430 */ 100 #define DSIM_CLKLANE_STOP BIT(30) 101 #define DSIM_NON_CONTINUOUS_CLKLANE BIT(31) 102 103 /* DSIM_ESCMODE */ 104 #define DSIM_TX_TRIGGER_RST BIT(4) 105 #define DSIM_TX_LPDT_LP BIT(6) 106 #define DSIM_CMD_LPDT_LP BIT(7) 107 #define DSIM_FORCE_BTA BIT(16) 108 #define DSIM_FORCE_STOP_STATE BIT(20) 109 #define DSIM_STOP_STATE_CNT(x) (((x) & 0x7ff) << 21) 110 #define DSIM_STOP_STATE_CNT_MASK (0x7ff << 21) 111 112 /* DSIM_MDRESOL */ 113 #define DSIM_MAIN_STAND_BY BIT(31) 114 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16) 115 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0) 116 117 /* DSIM_MVPORCH */ 118 #define DSIM_CMD_ALLOW(x) ((x) << 28) 119 #define DSIM_STABLE_VFP(x) ((x) << 16) 120 #define DSIM_MAIN_VBP(x) ((x) << 0) 121 #define DSIM_CMD_ALLOW_MASK (0xf << 28) 122 #define DSIM_STABLE_VFP_MASK (0x7ff << 16) 123 #define DSIM_MAIN_VBP_MASK (0x7ff << 0) 124 125 /* DSIM_MHPORCH */ 126 #define DSIM_MAIN_HFP(x) ((x) << 16) 127 #define DSIM_MAIN_HBP(x) ((x) << 0) 128 #define DSIM_MAIN_HFP_MASK ((0xffff) << 16) 129 #define DSIM_MAIN_HBP_MASK ((0xffff) << 0) 130 131 /* DSIM_MSYNC */ 132 #define DSIM_MAIN_VSA(x) ((x) << 22) 133 #define DSIM_MAIN_HSA(x) ((x) << 0) 134 #define DSIM_MAIN_VSA_MASK ((0x3ff) << 22) 135 #define DSIM_MAIN_HSA_MASK ((0xffff) << 0) 136 137 /* DSIM_SDRESOL */ 138 #define DSIM_SUB_STANDY(x) ((x) << 31) 139 #define DSIM_SUB_VRESOL(x) ((x) << 16) 140 #define DSIM_SUB_HRESOL(x) ((x) << 0) 141 #define DSIM_SUB_STANDY_MASK ((0x1) << 31) 142 #define DSIM_SUB_VRESOL_MASK ((0x7ff) << 16) 143 #define DSIM_SUB_HRESOL_MASK ((0x7ff) << 0) 144 145 /* DSIM_INTSRC */ 146 #define DSIM_INT_PLL_STABLE BIT(31) 147 #define DSIM_INT_SW_RST_RELEASE BIT(30) 148 #define DSIM_INT_SFR_FIFO_EMPTY BIT(29) 149 #define DSIM_INT_SFR_HDR_FIFO_EMPTY BIT(28) 150 #define DSIM_INT_BTA BIT(25) 151 #define DSIM_INT_FRAME_DONE BIT(24) 152 #define DSIM_INT_RX_TIMEOUT BIT(21) 153 #define DSIM_INT_BTA_TIMEOUT BIT(20) 154 #define DSIM_INT_RX_DONE BIT(18) 155 #define DSIM_INT_RX_TE BIT(17) 156 #define DSIM_INT_RX_ACK BIT(16) 157 #define DSIM_INT_RX_ECC_ERR BIT(15) 158 #define DSIM_INT_RX_CRC_ERR BIT(14) 159 160 /* DSIM_FIFOCTRL */ 161 #define DSIM_RX_DATA_FULL BIT(25) 162 #define DSIM_RX_DATA_EMPTY BIT(24) 163 #define DSIM_SFR_HEADER_FULL BIT(23) 164 #define DSIM_SFR_HEADER_EMPTY BIT(22) 165 #define DSIM_SFR_PAYLOAD_FULL BIT(21) 166 #define DSIM_SFR_PAYLOAD_EMPTY BIT(20) 167 #define DSIM_I80_HEADER_FULL BIT(19) 168 #define DSIM_I80_HEADER_EMPTY BIT(18) 169 #define DSIM_I80_PAYLOAD_FULL BIT(17) 170 #define DSIM_I80_PAYLOAD_EMPTY BIT(16) 171 #define DSIM_SD_HEADER_FULL BIT(15) 172 #define DSIM_SD_HEADER_EMPTY BIT(14) 173 #define DSIM_SD_PAYLOAD_FULL BIT(13) 174 #define DSIM_SD_PAYLOAD_EMPTY BIT(12) 175 #define DSIM_MD_HEADER_FULL BIT(11) 176 #define DSIM_MD_HEADER_EMPTY BIT(10) 177 #define DSIM_MD_PAYLOAD_FULL BIT(9) 178 #define DSIM_MD_PAYLOAD_EMPTY BIT(8) 179 #define DSIM_RX_FIFO BIT(4) 180 #define DSIM_SFR_FIFO BIT(3) 181 #define DSIM_I80_FIFO BIT(2) 182 #define DSIM_SD_FIFO BIT(1) 183 #define DSIM_MD_FIFO BIT(0) 184 185 /* DSIM_PHYACCHR */ 186 #define DSIM_AFC_EN BIT(14) 187 #define DSIM_AFC_CTL(x) (((x) & 0x7) << 5) 188 189 /* DSIM_PLLCTRL */ 190 #define DSIM_PLL_DPDNSWAP_CLK (1 << 25) 191 #define DSIM_PLL_DPDNSWAP_DAT (1 << 24) 192 #define DSIM_FREQ_BAND(x) ((x) << 24) 193 #define DSIM_PLL_EN BIT(23) 194 #define DSIM_PLL_P(x, offset) ((x) << (offset)) 195 #define DSIM_PLL_M(x) ((x) << 4) 196 #define DSIM_PLL_S(x) ((x) << 1) 197 198 /* DSIM_PHYCTRL */ 199 #define DSIM_PHYCTRL_ULPS_EXIT(x) (((x) & 0x1ff) << 0) 200 #define DSIM_PHYCTRL_B_DPHYCTL_VREG_LP BIT(30) 201 #define DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP BIT(14) 202 203 /* DSIM_PHYTIMING */ 204 #define DSIM_PHYTIMING_LPX(x) ((x) << 8) 205 #define DSIM_PHYTIMING_HS_EXIT(x) ((x) << 0) 206 207 /* DSIM_PHYTIMING1 */ 208 #define DSIM_PHYTIMING1_CLK_PREPARE(x) ((x) << 24) 209 #define DSIM_PHYTIMING1_CLK_ZERO(x) ((x) << 16) 210 #define DSIM_PHYTIMING1_CLK_POST(x) ((x) << 8) 211 #define DSIM_PHYTIMING1_CLK_TRAIL(x) ((x) << 0) 212 213 /* DSIM_PHYTIMING2 */ 214 #define DSIM_PHYTIMING2_HS_PREPARE(x) ((x) << 16) 215 #define DSIM_PHYTIMING2_HS_ZERO(x) ((x) << 8) 216 #define DSIM_PHYTIMING2_HS_TRAIL(x) ((x) << 0) 217 218 #define DSI_MAX_BUS_WIDTH 4 219 #define DSI_NUM_VIRTUAL_CHANNELS 4 220 #define DSI_TX_FIFO_SIZE 2048 221 #define DSI_RX_FIFO_SIZE 256 222 #define DSI_XFER_TIMEOUT_MS 100 223 #define DSI_RX_FIFO_EMPTY 0x30800002 224 225 #define OLD_SCLK_MIPI_CLK_NAME "pll_clk" 226 227 #define PS_TO_CYCLE(ps, hz) DIV64_U64_ROUND_CLOSEST(((ps) * (hz)), 1000000000000ULL) 228 229 static const char *const clk_names[5] = { 230 "bus_clk", 231 "sclk_mipi", 232 "phyclk_mipidphy0_bitclkdiv8", 233 "phyclk_mipidphy0_rxclkesc0", 234 "sclk_rgb_vclk_to_dsim0" 235 }; 236 237 enum samsung_dsim_transfer_type { 238 EXYNOS_DSI_TX, 239 EXYNOS_DSI_RX, 240 }; 241 242 enum reg_idx { 243 DSIM_STATUS_REG, /* Status register */ 244 DSIM_SWRST_REG, /* Software reset register */ 245 DSIM_CLKCTRL_REG, /* Clock control register */ 246 DSIM_TIMEOUT_REG, /* Time out register */ 247 DSIM_CONFIG_REG, /* Configuration register */ 248 DSIM_ESCMODE_REG, /* Escape mode register */ 249 DSIM_MDRESOL_REG, 250 DSIM_MVPORCH_REG, /* Main display Vporch register */ 251 DSIM_MHPORCH_REG, /* Main display Hporch register */ 252 DSIM_MSYNC_REG, /* Main display sync area register */ 253 DSIM_INTSRC_REG, /* Interrupt source register */ 254 DSIM_INTMSK_REG, /* Interrupt mask register */ 255 DSIM_PKTHDR_REG, /* Packet Header FIFO register */ 256 DSIM_PAYLOAD_REG, /* Payload FIFO register */ 257 DSIM_RXFIFO_REG, /* Read FIFO register */ 258 DSIM_FIFOCTRL_REG, /* FIFO status and control register */ 259 DSIM_PLLCTRL_REG, /* PLL control register */ 260 DSIM_PHYCTRL_REG, 261 DSIM_PHYTIMING_REG, 262 DSIM_PHYTIMING1_REG, 263 DSIM_PHYTIMING2_REG, 264 NUM_REGS 265 }; 266 267 static const unsigned int exynos_reg_ofs[] = { 268 [DSIM_STATUS_REG] = 0x00, 269 [DSIM_SWRST_REG] = 0x04, 270 [DSIM_CLKCTRL_REG] = 0x08, 271 [DSIM_TIMEOUT_REG] = 0x0c, 272 [DSIM_CONFIG_REG] = 0x10, 273 [DSIM_ESCMODE_REG] = 0x14, 274 [DSIM_MDRESOL_REG] = 0x18, 275 [DSIM_MVPORCH_REG] = 0x1c, 276 [DSIM_MHPORCH_REG] = 0x20, 277 [DSIM_MSYNC_REG] = 0x24, 278 [DSIM_INTSRC_REG] = 0x2c, 279 [DSIM_INTMSK_REG] = 0x30, 280 [DSIM_PKTHDR_REG] = 0x34, 281 [DSIM_PAYLOAD_REG] = 0x38, 282 [DSIM_RXFIFO_REG] = 0x3c, 283 [DSIM_FIFOCTRL_REG] = 0x44, 284 [DSIM_PLLCTRL_REG] = 0x4c, 285 [DSIM_PHYCTRL_REG] = 0x5c, 286 [DSIM_PHYTIMING_REG] = 0x64, 287 [DSIM_PHYTIMING1_REG] = 0x68, 288 [DSIM_PHYTIMING2_REG] = 0x6c, 289 }; 290 291 static const unsigned int exynos5433_reg_ofs[] = { 292 [DSIM_STATUS_REG] = 0x04, 293 [DSIM_SWRST_REG] = 0x0C, 294 [DSIM_CLKCTRL_REG] = 0x10, 295 [DSIM_TIMEOUT_REG] = 0x14, 296 [DSIM_CONFIG_REG] = 0x18, 297 [DSIM_ESCMODE_REG] = 0x1C, 298 [DSIM_MDRESOL_REG] = 0x20, 299 [DSIM_MVPORCH_REG] = 0x24, 300 [DSIM_MHPORCH_REG] = 0x28, 301 [DSIM_MSYNC_REG] = 0x2C, 302 [DSIM_INTSRC_REG] = 0x34, 303 [DSIM_INTMSK_REG] = 0x38, 304 [DSIM_PKTHDR_REG] = 0x3C, 305 [DSIM_PAYLOAD_REG] = 0x40, 306 [DSIM_RXFIFO_REG] = 0x44, 307 [DSIM_FIFOCTRL_REG] = 0x4C, 308 [DSIM_PLLCTRL_REG] = 0x94, 309 [DSIM_PHYCTRL_REG] = 0xA4, 310 [DSIM_PHYTIMING_REG] = 0xB4, 311 [DSIM_PHYTIMING1_REG] = 0xB8, 312 [DSIM_PHYTIMING2_REG] = 0xBC, 313 }; 314 315 enum reg_value_idx { 316 RESET_TYPE, 317 PLL_TIMER, 318 STOP_STATE_CNT, 319 PHYCTRL_ULPS_EXIT, 320 PHYCTRL_VREG_LP, 321 PHYCTRL_SLEW_UP, 322 PHYTIMING_LPX, 323 PHYTIMING_HS_EXIT, 324 PHYTIMING_CLK_PREPARE, 325 PHYTIMING_CLK_ZERO, 326 PHYTIMING_CLK_POST, 327 PHYTIMING_CLK_TRAIL, 328 PHYTIMING_HS_PREPARE, 329 PHYTIMING_HS_ZERO, 330 PHYTIMING_HS_TRAIL 331 }; 332 333 static const unsigned int reg_values[] = { 334 [RESET_TYPE] = DSIM_SWRST, 335 [PLL_TIMER] = 500, 336 [STOP_STATE_CNT] = 0xf, 337 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x0af), 338 [PHYCTRL_VREG_LP] = 0, 339 [PHYCTRL_SLEW_UP] = 0, 340 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 341 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 342 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 343 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x27), 344 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 345 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 346 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x09), 347 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 348 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 349 }; 350 351 static const unsigned int exynos5422_reg_values[] = { 352 [RESET_TYPE] = DSIM_SWRST, 353 [PLL_TIMER] = 500, 354 [STOP_STATE_CNT] = 0xf, 355 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 356 [PHYCTRL_VREG_LP] = 0, 357 [PHYCTRL_SLEW_UP] = 0, 358 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x08), 359 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0d), 360 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 361 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x30), 362 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 363 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x0a), 364 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0c), 365 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x11), 366 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0d), 367 }; 368 369 static const unsigned int exynos5433_reg_values[] = { 370 [RESET_TYPE] = DSIM_FUNCRST, 371 [PLL_TIMER] = 22200, 372 [STOP_STATE_CNT] = 0xa, 373 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0x190), 374 [PHYCTRL_VREG_LP] = DSIM_PHYCTRL_B_DPHYCTL_VREG_LP, 375 [PHYCTRL_SLEW_UP] = DSIM_PHYCTRL_B_DPHYCTL_SLEW_UP, 376 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x07), 377 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0c), 378 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x09), 379 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x2d), 380 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0e), 381 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x09), 382 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x0b), 383 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x10), 384 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0c), 385 }; 386 387 static const unsigned int imx8mm_dsim_reg_values[] = { 388 [RESET_TYPE] = DSIM_SWRST, 389 [PLL_TIMER] = 500, 390 [STOP_STATE_CNT] = 0xf, 391 [PHYCTRL_ULPS_EXIT] = DSIM_PHYCTRL_ULPS_EXIT(0xaf), 392 [PHYCTRL_VREG_LP] = 0, 393 [PHYCTRL_SLEW_UP] = 0, 394 [PHYTIMING_LPX] = DSIM_PHYTIMING_LPX(0x06), 395 [PHYTIMING_HS_EXIT] = DSIM_PHYTIMING_HS_EXIT(0x0b), 396 [PHYTIMING_CLK_PREPARE] = DSIM_PHYTIMING1_CLK_PREPARE(0x07), 397 [PHYTIMING_CLK_ZERO] = DSIM_PHYTIMING1_CLK_ZERO(0x26), 398 [PHYTIMING_CLK_POST] = DSIM_PHYTIMING1_CLK_POST(0x0d), 399 [PHYTIMING_CLK_TRAIL] = DSIM_PHYTIMING1_CLK_TRAIL(0x08), 400 [PHYTIMING_HS_PREPARE] = DSIM_PHYTIMING2_HS_PREPARE(0x08), 401 [PHYTIMING_HS_ZERO] = DSIM_PHYTIMING2_HS_ZERO(0x0d), 402 [PHYTIMING_HS_TRAIL] = DSIM_PHYTIMING2_HS_TRAIL(0x0b), 403 }; 404 405 static const struct samsung_dsim_driver_data exynos3_dsi_driver_data = { 406 .reg_ofs = exynos_reg_ofs, 407 .plltmr_reg = 0x50, 408 .has_freqband = 1, 409 .has_clklane_stop = 1, 410 .num_clks = 2, 411 .max_freq = 1000, 412 .wait_for_reset = 1, 413 .num_bits_resol = 11, 414 .pll_p_offset = 13, 415 .reg_values = reg_values, 416 .pll_fin_min = 6, 417 .pll_fin_max = 12, 418 .m_min = 41, 419 .m_max = 125, 420 .min_freq = 500, 421 .has_broken_fifoctrl_emptyhdr = 1, 422 }; 423 424 static const struct samsung_dsim_driver_data exynos4_dsi_driver_data = { 425 .reg_ofs = exynos_reg_ofs, 426 .plltmr_reg = 0x50, 427 .has_freqband = 1, 428 .has_clklane_stop = 1, 429 .num_clks = 2, 430 .max_freq = 1000, 431 .wait_for_reset = 1, 432 .num_bits_resol = 11, 433 .pll_p_offset = 13, 434 .reg_values = reg_values, 435 .pll_fin_min = 6, 436 .pll_fin_max = 12, 437 .m_min = 41, 438 .m_max = 125, 439 .min_freq = 500, 440 .has_broken_fifoctrl_emptyhdr = 1, 441 }; 442 443 static const struct samsung_dsim_driver_data exynos5_dsi_driver_data = { 444 .reg_ofs = exynos_reg_ofs, 445 .plltmr_reg = 0x58, 446 .num_clks = 2, 447 .max_freq = 1000, 448 .wait_for_reset = 1, 449 .num_bits_resol = 11, 450 .pll_p_offset = 13, 451 .reg_values = reg_values, 452 .pll_fin_min = 6, 453 .pll_fin_max = 12, 454 .m_min = 41, 455 .m_max = 125, 456 .min_freq = 500, 457 }; 458 459 static const struct samsung_dsim_driver_data exynos5433_dsi_driver_data = { 460 .reg_ofs = exynos5433_reg_ofs, 461 .plltmr_reg = 0xa0, 462 .has_clklane_stop = 1, 463 .num_clks = 5, 464 .max_freq = 1500, 465 .wait_for_reset = 0, 466 .num_bits_resol = 12, 467 .pll_p_offset = 13, 468 .reg_values = exynos5433_reg_values, 469 .pll_fin_min = 6, 470 .pll_fin_max = 12, 471 .m_min = 41, 472 .m_max = 125, 473 .min_freq = 500, 474 }; 475 476 static const struct samsung_dsim_driver_data exynos5422_dsi_driver_data = { 477 .reg_ofs = exynos5433_reg_ofs, 478 .plltmr_reg = 0xa0, 479 .has_clklane_stop = 1, 480 .num_clks = 2, 481 .max_freq = 1500, 482 .wait_for_reset = 1, 483 .num_bits_resol = 12, 484 .pll_p_offset = 13, 485 .reg_values = exynos5422_reg_values, 486 .pll_fin_min = 6, 487 .pll_fin_max = 12, 488 .m_min = 41, 489 .m_max = 125, 490 .min_freq = 500, 491 }; 492 493 static const struct samsung_dsim_driver_data imx8mm_dsi_driver_data = { 494 .reg_ofs = exynos5433_reg_ofs, 495 .plltmr_reg = 0xa0, 496 .has_clklane_stop = 1, 497 .num_clks = 2, 498 .max_freq = 2100, 499 .wait_for_reset = 0, 500 .num_bits_resol = 12, 501 /* 502 * Unlike Exynos, PLL_P(PMS_P) offset 14 is used in i.MX8M Mini/Nano/Plus 503 * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c 504 */ 505 .pll_p_offset = 14, 506 .reg_values = imx8mm_dsim_reg_values, 507 .pll_fin_min = 2, 508 .pll_fin_max = 30, 509 .m_min = 64, 510 .m_max = 1023, 511 .min_freq = 1050, 512 }; 513 514 static const struct samsung_dsim_driver_data * 515 samsung_dsim_types[DSIM_TYPE_COUNT] = { 516 [DSIM_TYPE_EXYNOS3250] = &exynos3_dsi_driver_data, 517 [DSIM_TYPE_EXYNOS4210] = &exynos4_dsi_driver_data, 518 [DSIM_TYPE_EXYNOS5410] = &exynos5_dsi_driver_data, 519 [DSIM_TYPE_EXYNOS5422] = &exynos5422_dsi_driver_data, 520 [DSIM_TYPE_EXYNOS5433] = &exynos5433_dsi_driver_data, 521 [DSIM_TYPE_IMX8MM] = &imx8mm_dsi_driver_data, 522 [DSIM_TYPE_IMX8MP] = &imx8mm_dsi_driver_data, 523 }; 524 525 static inline struct samsung_dsim *host_to_dsi(struct mipi_dsi_host *h) 526 { 527 return container_of(h, struct samsung_dsim, dsi_host); 528 } 529 530 static inline struct samsung_dsim *bridge_to_dsi(struct drm_bridge *b) 531 { 532 return container_of(b, struct samsung_dsim, bridge); 533 } 534 535 static inline void samsung_dsim_write(struct samsung_dsim *dsi, 536 enum reg_idx idx, u32 val) 537 { 538 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 539 } 540 541 static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx) 542 { 543 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); 544 } 545 546 static void samsung_dsim_wait_for_reset(struct samsung_dsim *dsi) 547 { 548 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) 549 return; 550 551 dev_err(dsi->dev, "timeout waiting for reset\n"); 552 } 553 554 static void samsung_dsim_reset(struct samsung_dsim *dsi) 555 { 556 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; 557 558 reinit_completion(&dsi->completed); 559 samsung_dsim_write(dsi, DSIM_SWRST_REG, reset_val); 560 } 561 562 static unsigned long samsung_dsim_pll_find_pms(struct samsung_dsim *dsi, 563 unsigned long fin, 564 unsigned long fout, 565 u8 *p, u16 *m, u8 *s) 566 { 567 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 568 unsigned long best_freq = 0; 569 u32 min_delta = 0xffffffff; 570 u8 p_min, p_max; 571 u8 _p, best_p; 572 u16 _m, best_m; 573 u8 _s, best_s; 574 575 p_min = DIV_ROUND_UP(fin, (driver_data->pll_fin_max * HZ_PER_MHZ)); 576 p_max = fin / (driver_data->pll_fin_min * HZ_PER_MHZ); 577 578 for (_p = p_min; _p <= p_max; ++_p) { 579 for (_s = 0; _s <= 5; ++_s) { 580 u64 tmp; 581 u32 delta; 582 583 tmp = (u64)fout * (_p << _s); 584 do_div(tmp, fin); 585 _m = tmp; 586 if (_m < driver_data->m_min || _m > driver_data->m_max) 587 continue; 588 589 tmp = (u64)_m * fin; 590 do_div(tmp, _p); 591 if (tmp < driver_data->min_freq * HZ_PER_MHZ || 592 tmp > driver_data->max_freq * HZ_PER_MHZ) 593 continue; 594 595 tmp = (u64)_m * fin; 596 do_div(tmp, _p << _s); 597 598 delta = abs(fout - tmp); 599 if (delta < min_delta) { 600 best_p = _p; 601 best_m = _m; 602 best_s = _s; 603 min_delta = delta; 604 best_freq = tmp; 605 } 606 } 607 } 608 609 if (best_freq) { 610 *p = best_p; 611 *m = best_m; 612 *s = best_s; 613 } 614 615 return best_freq; 616 } 617 618 static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi, 619 unsigned long freq) 620 { 621 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 622 unsigned long fin, fout; 623 int timeout; 624 u8 p, s; 625 u16 m; 626 u32 reg; 627 628 if (dsi->pll_clk) { 629 /* 630 * Ensure that the reference clock is generated with a power of 631 * two divider from its parent, but close to the PLLs upper 632 * limit. 633 */ 634 fin = clk_get_rate(clk_get_parent(dsi->pll_clk)); 635 while (fin > driver_data->pll_fin_max * HZ_PER_MHZ) 636 fin /= 2; 637 clk_set_rate(dsi->pll_clk, fin); 638 639 fin = clk_get_rate(dsi->pll_clk); 640 } else { 641 fin = dsi->pll_clk_rate; 642 } 643 dev_dbg(dsi->dev, "PLL ref clock freq %lu\n", fin); 644 645 fout = samsung_dsim_pll_find_pms(dsi, fin, freq, &p, &m, &s); 646 if (!fout) { 647 dev_err(dsi->dev, 648 "failed to find PLL PMS for requested frequency\n"); 649 return 0; 650 } 651 dev_dbg(dsi->dev, "PLL freq %lu, (p %d, m %d, s %d)\n", fout, p, m, s); 652 653 writel(driver_data->reg_values[PLL_TIMER], 654 dsi->reg_base + driver_data->plltmr_reg); 655 656 reg = DSIM_PLL_EN | DSIM_PLL_P(p, driver_data->pll_p_offset) | 657 DSIM_PLL_M(m) | DSIM_PLL_S(s); 658 659 if (driver_data->has_freqband) { 660 static const unsigned long freq_bands[] = { 661 100 * HZ_PER_MHZ, 120 * HZ_PER_MHZ, 160 * HZ_PER_MHZ, 662 200 * HZ_PER_MHZ, 270 * HZ_PER_MHZ, 320 * HZ_PER_MHZ, 663 390 * HZ_PER_MHZ, 450 * HZ_PER_MHZ, 510 * HZ_PER_MHZ, 664 560 * HZ_PER_MHZ, 640 * HZ_PER_MHZ, 690 * HZ_PER_MHZ, 665 770 * HZ_PER_MHZ, 870 * HZ_PER_MHZ, 950 * HZ_PER_MHZ, 666 }; 667 int band; 668 669 for (band = 0; band < ARRAY_SIZE(freq_bands); ++band) 670 if (fout < freq_bands[band]) 671 break; 672 673 dev_dbg(dsi->dev, "band %d\n", band); 674 675 reg |= DSIM_FREQ_BAND(band); 676 } 677 678 if (dsi->swap_dn_dp_clk) 679 reg |= DSIM_PLL_DPDNSWAP_CLK; 680 if (dsi->swap_dn_dp_data) 681 reg |= DSIM_PLL_DPDNSWAP_DAT; 682 683 samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg); 684 685 timeout = 1000; 686 do { 687 if (timeout-- == 0) { 688 dev_err(dsi->dev, "PLL failed to stabilize\n"); 689 return 0; 690 } 691 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG); 692 } while ((reg & DSIM_PLL_STABLE) == 0); 693 694 dsi->hs_clock = fout; 695 696 return fout; 697 } 698 699 static int samsung_dsim_enable_clock(struct samsung_dsim *dsi) 700 { 701 unsigned long hs_clk, byte_clk, esc_clk, pix_clk; 702 unsigned long esc_div; 703 u32 reg; 704 struct drm_display_mode *m = &dsi->mode; 705 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 706 707 /* m->clock is in KHz */ 708 pix_clk = m->clock * 1000; 709 710 /* Use burst_clk_rate if available, otherwise use the pix_clk */ 711 if (dsi->burst_clk_rate) 712 hs_clk = samsung_dsim_set_pll(dsi, dsi->burst_clk_rate); 713 else 714 hs_clk = samsung_dsim_set_pll(dsi, DIV_ROUND_UP(pix_clk * bpp, dsi->lanes)); 715 716 if (!hs_clk) { 717 dev_err(dsi->dev, "failed to configure DSI PLL\n"); 718 return -EFAULT; 719 } 720 721 byte_clk = hs_clk / 8; 722 esc_div = DIV_ROUND_UP(byte_clk, dsi->esc_clk_rate); 723 esc_clk = byte_clk / esc_div; 724 725 if (esc_clk > 20 * HZ_PER_MHZ) { 726 ++esc_div; 727 esc_clk = byte_clk / esc_div; 728 } 729 730 dev_dbg(dsi->dev, "hs_clk = %lu, byte_clk = %lu, esc_clk = %lu\n", 731 hs_clk, byte_clk, esc_clk); 732 733 reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG); 734 reg &= ~(DSIM_ESC_PRESCALER_MASK | DSIM_LANE_ESC_CLK_EN_CLK 735 | DSIM_LANE_ESC_CLK_EN_DATA_MASK | DSIM_PLL_BYPASS 736 | DSIM_BYTE_CLK_SRC_MASK); 737 reg |= DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN 738 | DSIM_ESC_PRESCALER(esc_div) 739 | DSIM_LANE_ESC_CLK_EN_CLK 740 | DSIM_LANE_ESC_CLK_EN_DATA(BIT(dsi->lanes) - 1) 741 | DSIM_BYTE_CLK_SRC(0) 742 | DSIM_TX_REQUEST_HSCLK; 743 samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg); 744 745 return 0; 746 } 747 748 static void samsung_dsim_set_phy_ctrl(struct samsung_dsim *dsi) 749 { 750 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 751 const unsigned int *reg_values = driver_data->reg_values; 752 u32 reg; 753 struct phy_configure_opts_mipi_dphy cfg; 754 int clk_prepare, lpx, clk_zero, clk_post, clk_trail; 755 int hs_exit, hs_prepare, hs_zero, hs_trail; 756 unsigned long long byte_clock = dsi->hs_clock / 8; 757 758 if (driver_data->has_freqband) 759 return; 760 761 phy_mipi_dphy_get_default_config_for_hsclk(dsi->hs_clock, 762 dsi->lanes, &cfg); 763 764 /* 765 * TODO: 766 * The tech Applications Processor manuals for i.MX8M Mini, Nano, 767 * and Plus don't state what the definition of the PHYTIMING 768 * bits are beyond their address and bit position. 769 * After reviewing NXP's downstream code, it appears 770 * that the various PHYTIMING registers take the number 771 * of cycles and use various dividers on them. This 772 * calculation does not result in an exact match to the 773 * downstream code, but it is very close to the values 774 * generated by their lookup table, and it appears 775 * to sync at a variety of resolutions. If someone 776 * can get a more accurate mathematical equation needed 777 * for these registers, this should be updated. 778 */ 779 780 lpx = PS_TO_CYCLE(cfg.lpx, byte_clock); 781 hs_exit = PS_TO_CYCLE(cfg.hs_exit, byte_clock); 782 clk_prepare = PS_TO_CYCLE(cfg.clk_prepare, byte_clock); 783 clk_zero = PS_TO_CYCLE(cfg.clk_zero, byte_clock); 784 clk_post = PS_TO_CYCLE(cfg.clk_post, byte_clock); 785 clk_trail = PS_TO_CYCLE(cfg.clk_trail, byte_clock); 786 hs_prepare = PS_TO_CYCLE(cfg.hs_prepare, byte_clock); 787 hs_zero = PS_TO_CYCLE(cfg.hs_zero, byte_clock); 788 hs_trail = PS_TO_CYCLE(cfg.hs_trail, byte_clock); 789 790 /* B D-PHY: D-PHY Master & Slave Analog Block control */ 791 reg = reg_values[PHYCTRL_ULPS_EXIT] | reg_values[PHYCTRL_VREG_LP] | 792 reg_values[PHYCTRL_SLEW_UP]; 793 794 samsung_dsim_write(dsi, DSIM_PHYCTRL_REG, reg); 795 796 /* 797 * T LPX: Transmitted length of any Low-Power state period 798 * T HS-EXIT: Time that the transmitter drives LP-11 following a HS 799 * burst 800 */ 801 802 reg = DSIM_PHYTIMING_LPX(lpx) | DSIM_PHYTIMING_HS_EXIT(hs_exit); 803 804 samsung_dsim_write(dsi, DSIM_PHYTIMING_REG, reg); 805 806 /* 807 * T CLK-PREPARE: Time that the transmitter drives the Clock Lane LP-00 808 * Line state immediately before the HS-0 Line state starting the 809 * HS transmission 810 * T CLK-ZERO: Time that the transmitter drives the HS-0 state prior to 811 * transmitting the Clock. 812 * T CLK_POST: Time that the transmitter continues to send HS clock 813 * after the last associated Data Lane has transitioned to LP Mode 814 * Interval is defined as the period from the end of T HS-TRAIL to 815 * the beginning of T CLK-TRAIL 816 * T CLK-TRAIL: Time that the transmitter drives the HS-0 state after 817 * the last payload clock bit of a HS transmission burst 818 */ 819 820 reg = DSIM_PHYTIMING1_CLK_PREPARE(clk_prepare) | 821 DSIM_PHYTIMING1_CLK_ZERO(clk_zero) | 822 DSIM_PHYTIMING1_CLK_POST(clk_post) | 823 DSIM_PHYTIMING1_CLK_TRAIL(clk_trail); 824 825 samsung_dsim_write(dsi, DSIM_PHYTIMING1_REG, reg); 826 827 /* 828 * T HS-PREPARE: Time that the transmitter drives the Data Lane LP-00 829 * Line state immediately before the HS-0 Line state starting the 830 * HS transmission 831 * T HS-ZERO: Time that the transmitter drives the HS-0 state prior to 832 * transmitting the Sync sequence. 833 * T HS-TRAIL: Time that the transmitter drives the flipped differential 834 * state after last payload data bit of a HS transmission burst 835 */ 836 837 reg = DSIM_PHYTIMING2_HS_PREPARE(hs_prepare) | 838 DSIM_PHYTIMING2_HS_ZERO(hs_zero) | 839 DSIM_PHYTIMING2_HS_TRAIL(hs_trail); 840 841 samsung_dsim_write(dsi, DSIM_PHYTIMING2_REG, reg); 842 } 843 844 static void samsung_dsim_disable_clock(struct samsung_dsim *dsi) 845 { 846 u32 reg; 847 848 reg = samsung_dsim_read(dsi, DSIM_CLKCTRL_REG); 849 reg &= ~(DSIM_LANE_ESC_CLK_EN_CLK | DSIM_LANE_ESC_CLK_EN_DATA_MASK 850 | DSIM_ESC_CLKEN | DSIM_BYTE_CLKEN); 851 samsung_dsim_write(dsi, DSIM_CLKCTRL_REG, reg); 852 853 reg = samsung_dsim_read(dsi, DSIM_PLLCTRL_REG); 854 reg &= ~DSIM_PLL_EN; 855 samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg); 856 } 857 858 static void samsung_dsim_enable_lane(struct samsung_dsim *dsi, u32 lane) 859 { 860 u32 reg = samsung_dsim_read(dsi, DSIM_CONFIG_REG); 861 862 reg |= (DSIM_NUM_OF_DATA_LANE(dsi->lanes - 1) | DSIM_LANE_EN_CLK | 863 DSIM_LANE_EN(lane)); 864 samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg); 865 } 866 867 static int samsung_dsim_init_link(struct samsung_dsim *dsi) 868 { 869 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 870 int timeout; 871 u32 reg; 872 u32 lanes_mask; 873 874 /* Initialize FIFO pointers */ 875 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG); 876 reg &= ~0x1f; 877 samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg); 878 879 usleep_range(9000, 11000); 880 881 reg |= 0x1f; 882 samsung_dsim_write(dsi, DSIM_FIFOCTRL_REG, reg); 883 usleep_range(9000, 11000); 884 885 /* DSI configuration */ 886 reg = 0; 887 888 /* 889 * The first bit of mode_flags specifies display configuration. 890 * If this bit is set[= MIPI_DSI_MODE_VIDEO], dsi will support video 891 * mode, otherwise it will support command mode. 892 */ 893 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 894 reg |= DSIM_VIDEO_MODE; 895 896 /* 897 * The user manual describes that following bits are ignored in 898 * command mode. 899 */ 900 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) 901 reg |= DSIM_SYNC_INFORM; 902 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) 903 reg |= DSIM_BURST_MODE; 904 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_AUTO_VERT) 905 reg |= DSIM_AUTO_MODE; 906 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_HSE) 907 reg |= DSIM_HSE_DISABLE_MODE; 908 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HFP) 909 reg |= DSIM_HFP_DISABLE_MODE; 910 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HBP) 911 reg |= DSIM_HBP_DISABLE_MODE; 912 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_NO_HSA) 913 reg |= DSIM_HSA_DISABLE_MODE; 914 } 915 916 if (dsi->mode_flags & MIPI_DSI_MODE_NO_EOT_PACKET) 917 reg |= DSIM_EOT_DISABLE; 918 919 switch (dsi->format) { 920 case MIPI_DSI_FMT_RGB888: 921 reg |= DSIM_MAIN_PIX_FORMAT_RGB888; 922 break; 923 case MIPI_DSI_FMT_RGB666: 924 reg |= DSIM_MAIN_PIX_FORMAT_RGB666; 925 break; 926 case MIPI_DSI_FMT_RGB666_PACKED: 927 reg |= DSIM_MAIN_PIX_FORMAT_RGB666_P; 928 break; 929 case MIPI_DSI_FMT_RGB565: 930 reg |= DSIM_MAIN_PIX_FORMAT_RGB565; 931 break; 932 default: 933 dev_err(dsi->dev, "invalid pixel format\n"); 934 return -EINVAL; 935 } 936 937 /* 938 * Use non-continuous clock mode if the periparal wants and 939 * host controller supports 940 * 941 * In non-continous clock mode, host controller will turn off 942 * the HS clock between high-speed transmissions to reduce 943 * power consumption. 944 */ 945 if (driver_data->has_clklane_stop && 946 dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 947 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) 948 reg |= DSIM_NON_CONTINUOUS_CLKLANE; 949 950 reg |= DSIM_CLKLANE_STOP; 951 } 952 samsung_dsim_write(dsi, DSIM_CONFIG_REG, reg); 953 954 lanes_mask = BIT(dsi->lanes) - 1; 955 samsung_dsim_enable_lane(dsi, lanes_mask); 956 957 /* Check clock and data lane state are stop state */ 958 timeout = 100; 959 do { 960 if (timeout-- == 0) { 961 dev_err(dsi->dev, "waiting for bus lanes timed out\n"); 962 return -EFAULT; 963 } 964 965 reg = samsung_dsim_read(dsi, DSIM_STATUS_REG); 966 if ((reg & DSIM_STOP_STATE_DAT(lanes_mask)) 967 != DSIM_STOP_STATE_DAT(lanes_mask)) 968 continue; 969 } while (!(reg & (DSIM_STOP_STATE_CLK | DSIM_TX_READY_HS_CLK))); 970 971 reg = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); 972 reg &= ~DSIM_STOP_STATE_CNT_MASK; 973 reg |= DSIM_STOP_STATE_CNT(driver_data->reg_values[STOP_STATE_CNT]); 974 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, reg); 975 976 reg = DSIM_BTA_TIMEOUT(0xff) | DSIM_LPDR_TIMEOUT(0xffff); 977 samsung_dsim_write(dsi, DSIM_TIMEOUT_REG, reg); 978 979 return 0; 980 } 981 982 static void samsung_dsim_set_display_mode(struct samsung_dsim *dsi) 983 { 984 struct drm_display_mode *m = &dsi->mode; 985 unsigned int num_bits_resol = dsi->driver_data->num_bits_resol; 986 u32 reg; 987 988 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { 989 u64 byte_clk = dsi->hs_clock / 8; 990 u64 pix_clk = m->clock * 1000; 991 992 int hfp = DIV64_U64_ROUND_UP((m->hsync_start - m->hdisplay) * byte_clk, pix_clk); 993 int hbp = DIV64_U64_ROUND_UP((m->htotal - m->hsync_end) * byte_clk, pix_clk); 994 int hsa = DIV64_U64_ROUND_UP((m->hsync_end - m->hsync_start) * byte_clk, pix_clk); 995 996 /* remove packet overhead when possible */ 997 hfp = max(hfp - 6, 0); 998 hbp = max(hbp - 6, 0); 999 hsa = max(hsa - 6, 0); 1000 1001 dev_dbg(dsi->dev, "calculated hfp: %u, hbp: %u, hsa: %u", 1002 hfp, hbp, hsa); 1003 1004 reg = DSIM_CMD_ALLOW(0xf) 1005 | DSIM_STABLE_VFP(m->vsync_start - m->vdisplay) 1006 | DSIM_MAIN_VBP(m->vtotal - m->vsync_end); 1007 samsung_dsim_write(dsi, DSIM_MVPORCH_REG, reg); 1008 1009 reg = DSIM_MAIN_HFP(hfp) | DSIM_MAIN_HBP(hbp); 1010 samsung_dsim_write(dsi, DSIM_MHPORCH_REG, reg); 1011 1012 reg = DSIM_MAIN_VSA(m->vsync_end - m->vsync_start) 1013 | DSIM_MAIN_HSA(hsa); 1014 samsung_dsim_write(dsi, DSIM_MSYNC_REG, reg); 1015 } 1016 reg = DSIM_MAIN_HRESOL(m->hdisplay, num_bits_resol) | 1017 DSIM_MAIN_VRESOL(m->vdisplay, num_bits_resol); 1018 1019 samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg); 1020 1021 dev_dbg(dsi->dev, "LCD size = %dx%d\n", m->hdisplay, m->vdisplay); 1022 } 1023 1024 static void samsung_dsim_set_display_enable(struct samsung_dsim *dsi, bool enable) 1025 { 1026 u32 reg; 1027 1028 reg = samsung_dsim_read(dsi, DSIM_MDRESOL_REG); 1029 if (enable) 1030 reg |= DSIM_MAIN_STAND_BY; 1031 else 1032 reg &= ~DSIM_MAIN_STAND_BY; 1033 samsung_dsim_write(dsi, DSIM_MDRESOL_REG, reg); 1034 } 1035 1036 static int samsung_dsim_wait_for_hdr_fifo(struct samsung_dsim *dsi) 1037 { 1038 int timeout = 2000; 1039 1040 do { 1041 u32 reg = samsung_dsim_read(dsi, DSIM_FIFOCTRL_REG); 1042 1043 if (!dsi->driver_data->has_broken_fifoctrl_emptyhdr) { 1044 if (reg & DSIM_SFR_HEADER_EMPTY) 1045 return 0; 1046 } else { 1047 if (!(reg & DSIM_SFR_HEADER_FULL)) { 1048 /* 1049 * Wait a little bit, so the pending data can 1050 * actually leave the FIFO to avoid overflow. 1051 */ 1052 if (!cond_resched()) 1053 usleep_range(950, 1050); 1054 return 0; 1055 } 1056 } 1057 1058 if (!cond_resched()) 1059 usleep_range(950, 1050); 1060 } while (--timeout); 1061 1062 return -ETIMEDOUT; 1063 } 1064 1065 static void samsung_dsim_set_cmd_lpm(struct samsung_dsim *dsi, bool lpm) 1066 { 1067 u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); 1068 1069 if (lpm) 1070 v |= DSIM_CMD_LPDT_LP; 1071 else 1072 v &= ~DSIM_CMD_LPDT_LP; 1073 1074 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v); 1075 } 1076 1077 static void samsung_dsim_force_bta(struct samsung_dsim *dsi) 1078 { 1079 u32 v = samsung_dsim_read(dsi, DSIM_ESCMODE_REG); 1080 1081 v |= DSIM_FORCE_BTA; 1082 samsung_dsim_write(dsi, DSIM_ESCMODE_REG, v); 1083 } 1084 1085 static void samsung_dsim_send_to_fifo(struct samsung_dsim *dsi, 1086 struct samsung_dsim_transfer *xfer) 1087 { 1088 struct device *dev = dsi->dev; 1089 struct mipi_dsi_packet *pkt = &xfer->packet; 1090 const u8 *payload = pkt->payload + xfer->tx_done; 1091 u16 length = pkt->payload_length - xfer->tx_done; 1092 bool first = !xfer->tx_done; 1093 u32 reg; 1094 1095 dev_dbg(dev, "< xfer %p: tx len %u, done %u, rx len %u, done %u\n", 1096 xfer, length, xfer->tx_done, xfer->rx_len, xfer->rx_done); 1097 1098 if (length > DSI_TX_FIFO_SIZE) 1099 length = DSI_TX_FIFO_SIZE; 1100 1101 xfer->tx_done += length; 1102 1103 /* Send payload */ 1104 while (length >= 4) { 1105 reg = get_unaligned_le32(payload); 1106 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg); 1107 payload += 4; 1108 length -= 4; 1109 } 1110 1111 reg = 0; 1112 switch (length) { 1113 case 3: 1114 reg |= payload[2] << 16; 1115 fallthrough; 1116 case 2: 1117 reg |= payload[1] << 8; 1118 fallthrough; 1119 case 1: 1120 reg |= payload[0]; 1121 samsung_dsim_write(dsi, DSIM_PAYLOAD_REG, reg); 1122 break; 1123 } 1124 1125 /* Send packet header */ 1126 if (!first) 1127 return; 1128 1129 reg = get_unaligned_le32(pkt->header); 1130 if (samsung_dsim_wait_for_hdr_fifo(dsi)) { 1131 dev_err(dev, "waiting for header FIFO timed out\n"); 1132 return; 1133 } 1134 1135 if (NEQV(xfer->flags & MIPI_DSI_MSG_USE_LPM, 1136 dsi->state & DSIM_STATE_CMD_LPM)) { 1137 samsung_dsim_set_cmd_lpm(dsi, xfer->flags & MIPI_DSI_MSG_USE_LPM); 1138 dsi->state ^= DSIM_STATE_CMD_LPM; 1139 } 1140 1141 samsung_dsim_write(dsi, DSIM_PKTHDR_REG, reg); 1142 1143 if (xfer->flags & MIPI_DSI_MSG_REQ_ACK) 1144 samsung_dsim_force_bta(dsi); 1145 } 1146 1147 static void samsung_dsim_read_from_fifo(struct samsung_dsim *dsi, 1148 struct samsung_dsim_transfer *xfer) 1149 { 1150 u8 *payload = xfer->rx_payload + xfer->rx_done; 1151 bool first = !xfer->rx_done; 1152 struct device *dev = dsi->dev; 1153 u16 length; 1154 u32 reg; 1155 1156 if (first) { 1157 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1158 1159 switch (reg & 0x3f) { 1160 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 1161 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1162 if (xfer->rx_len >= 2) { 1163 payload[1] = reg >> 16; 1164 ++xfer->rx_done; 1165 } 1166 fallthrough; 1167 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 1168 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1169 payload[0] = reg >> 8; 1170 ++xfer->rx_done; 1171 xfer->rx_len = xfer->rx_done; 1172 xfer->result = 0; 1173 goto clear_fifo; 1174 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1175 dev_err(dev, "DSI Error Report: 0x%04x\n", (reg >> 8) & 0xffff); 1176 xfer->result = 0; 1177 goto clear_fifo; 1178 } 1179 1180 length = (reg >> 8) & 0xffff; 1181 if (length > xfer->rx_len) { 1182 dev_err(dev, 1183 "response too long (%u > %u bytes), stripping\n", 1184 xfer->rx_len, length); 1185 length = xfer->rx_len; 1186 } else if (length < xfer->rx_len) { 1187 xfer->rx_len = length; 1188 } 1189 } 1190 1191 length = xfer->rx_len - xfer->rx_done; 1192 xfer->rx_done += length; 1193 1194 /* Receive payload */ 1195 while (length >= 4) { 1196 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1197 payload[0] = (reg >> 0) & 0xff; 1198 payload[1] = (reg >> 8) & 0xff; 1199 payload[2] = (reg >> 16) & 0xff; 1200 payload[3] = (reg >> 24) & 0xff; 1201 payload += 4; 1202 length -= 4; 1203 } 1204 1205 if (length) { 1206 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1207 switch (length) { 1208 case 3: 1209 payload[2] = (reg >> 16) & 0xff; 1210 fallthrough; 1211 case 2: 1212 payload[1] = (reg >> 8) & 0xff; 1213 fallthrough; 1214 case 1: 1215 payload[0] = reg & 0xff; 1216 } 1217 } 1218 1219 if (xfer->rx_done == xfer->rx_len) 1220 xfer->result = 0; 1221 1222 clear_fifo: 1223 length = DSI_RX_FIFO_SIZE / 4; 1224 do { 1225 reg = samsung_dsim_read(dsi, DSIM_RXFIFO_REG); 1226 if (reg == DSI_RX_FIFO_EMPTY) 1227 break; 1228 } while (--length); 1229 } 1230 1231 static void samsung_dsim_transfer_start(struct samsung_dsim *dsi) 1232 { 1233 unsigned long flags; 1234 struct samsung_dsim_transfer *xfer; 1235 1236 spin_lock_irqsave(&dsi->transfer_lock, flags); 1237 1238 while (!list_empty(&dsi->transfer_list)) { 1239 xfer = list_first_entry(&dsi->transfer_list, 1240 struct samsung_dsim_transfer, list); 1241 1242 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1243 1244 if (xfer->packet.payload_length && 1245 xfer->tx_done == xfer->packet.payload_length) 1246 /* waiting for RX */ 1247 return; 1248 1249 samsung_dsim_send_to_fifo(dsi, xfer); 1250 1251 if (xfer->packet.payload_length || xfer->rx_len) 1252 return; 1253 1254 xfer->result = 0; 1255 complete(&xfer->completed); 1256 1257 spin_lock_irqsave(&dsi->transfer_lock, flags); 1258 1259 list_del_init(&xfer->list); 1260 } 1261 1262 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1263 } 1264 1265 static bool samsung_dsim_transfer_finish(struct samsung_dsim *dsi) 1266 { 1267 struct samsung_dsim_transfer *xfer; 1268 unsigned long flags; 1269 bool start = true; 1270 1271 spin_lock_irqsave(&dsi->transfer_lock, flags); 1272 1273 if (list_empty(&dsi->transfer_list)) { 1274 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1275 return false; 1276 } 1277 1278 xfer = list_first_entry(&dsi->transfer_list, 1279 struct samsung_dsim_transfer, list); 1280 1281 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1282 1283 dev_dbg(dsi->dev, 1284 "> xfer %p, tx_len %zu, tx_done %u, rx_len %u, rx_done %u\n", 1285 xfer, xfer->packet.payload_length, xfer->tx_done, xfer->rx_len, 1286 xfer->rx_done); 1287 1288 if (xfer->tx_done != xfer->packet.payload_length) 1289 return true; 1290 1291 if (xfer->rx_done != xfer->rx_len) 1292 samsung_dsim_read_from_fifo(dsi, xfer); 1293 1294 if (xfer->rx_done != xfer->rx_len) 1295 return true; 1296 1297 spin_lock_irqsave(&dsi->transfer_lock, flags); 1298 1299 list_del_init(&xfer->list); 1300 start = !list_empty(&dsi->transfer_list); 1301 1302 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1303 1304 if (!xfer->rx_len) 1305 xfer->result = 0; 1306 complete(&xfer->completed); 1307 1308 return start; 1309 } 1310 1311 static void samsung_dsim_remove_transfer(struct samsung_dsim *dsi, 1312 struct samsung_dsim_transfer *xfer) 1313 { 1314 unsigned long flags; 1315 bool start; 1316 1317 spin_lock_irqsave(&dsi->transfer_lock, flags); 1318 1319 if (!list_empty(&dsi->transfer_list) && 1320 xfer == list_first_entry(&dsi->transfer_list, 1321 struct samsung_dsim_transfer, list)) { 1322 list_del_init(&xfer->list); 1323 start = !list_empty(&dsi->transfer_list); 1324 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1325 if (start) 1326 samsung_dsim_transfer_start(dsi); 1327 return; 1328 } 1329 1330 list_del_init(&xfer->list); 1331 1332 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1333 } 1334 1335 static int samsung_dsim_transfer(struct samsung_dsim *dsi, 1336 struct samsung_dsim_transfer *xfer) 1337 { 1338 unsigned long flags; 1339 bool stopped; 1340 1341 xfer->tx_done = 0; 1342 xfer->rx_done = 0; 1343 xfer->result = -ETIMEDOUT; 1344 init_completion(&xfer->completed); 1345 1346 spin_lock_irqsave(&dsi->transfer_lock, flags); 1347 1348 stopped = list_empty(&dsi->transfer_list); 1349 list_add_tail(&xfer->list, &dsi->transfer_list); 1350 1351 spin_unlock_irqrestore(&dsi->transfer_lock, flags); 1352 1353 if (stopped) 1354 samsung_dsim_transfer_start(dsi); 1355 1356 wait_for_completion_timeout(&xfer->completed, 1357 msecs_to_jiffies(DSI_XFER_TIMEOUT_MS)); 1358 if (xfer->result == -ETIMEDOUT) { 1359 struct mipi_dsi_packet *pkt = &xfer->packet; 1360 1361 samsung_dsim_remove_transfer(dsi, xfer); 1362 dev_err(dsi->dev, "xfer timed out: %*ph %*ph\n", 4, pkt->header, 1363 (int)pkt->payload_length, pkt->payload); 1364 return -ETIMEDOUT; 1365 } 1366 1367 /* Also covers hardware timeout condition */ 1368 return xfer->result; 1369 } 1370 1371 static irqreturn_t samsung_dsim_irq(int irq, void *dev_id) 1372 { 1373 struct samsung_dsim *dsi = dev_id; 1374 u32 status; 1375 1376 status = samsung_dsim_read(dsi, DSIM_INTSRC_REG); 1377 if (!status) { 1378 static unsigned long j; 1379 1380 if (printk_timed_ratelimit(&j, 500)) 1381 dev_warn(dsi->dev, "spurious interrupt\n"); 1382 return IRQ_HANDLED; 1383 } 1384 samsung_dsim_write(dsi, DSIM_INTSRC_REG, status); 1385 1386 if (status & DSIM_INT_SW_RST_RELEASE) { 1387 unsigned long mask = ~(DSIM_INT_RX_DONE | 1388 DSIM_INT_SFR_FIFO_EMPTY | 1389 DSIM_INT_SFR_HDR_FIFO_EMPTY | 1390 DSIM_INT_RX_ECC_ERR | 1391 DSIM_INT_SW_RST_RELEASE); 1392 samsung_dsim_write(dsi, DSIM_INTMSK_REG, mask); 1393 complete(&dsi->completed); 1394 return IRQ_HANDLED; 1395 } 1396 1397 if (!(status & (DSIM_INT_RX_DONE | DSIM_INT_SFR_FIFO_EMPTY | 1398 DSIM_INT_PLL_STABLE))) 1399 return IRQ_HANDLED; 1400 1401 if (samsung_dsim_transfer_finish(dsi)) 1402 samsung_dsim_transfer_start(dsi); 1403 1404 return IRQ_HANDLED; 1405 } 1406 1407 static void samsung_dsim_enable_irq(struct samsung_dsim *dsi) 1408 { 1409 enable_irq(dsi->irq); 1410 1411 if (dsi->te_gpio) 1412 enable_irq(gpiod_to_irq(dsi->te_gpio)); 1413 } 1414 1415 static void samsung_dsim_disable_irq(struct samsung_dsim *dsi) 1416 { 1417 if (dsi->te_gpio) 1418 disable_irq(gpiod_to_irq(dsi->te_gpio)); 1419 1420 disable_irq(dsi->irq); 1421 } 1422 1423 static int samsung_dsim_init(struct samsung_dsim *dsi) 1424 { 1425 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 1426 1427 if (dsi->state & DSIM_STATE_INITIALIZED) 1428 return 0; 1429 1430 samsung_dsim_reset(dsi); 1431 samsung_dsim_enable_irq(dsi); 1432 1433 if (driver_data->reg_values[RESET_TYPE] == DSIM_FUNCRST) 1434 samsung_dsim_enable_lane(dsi, BIT(dsi->lanes) - 1); 1435 1436 samsung_dsim_enable_clock(dsi); 1437 if (driver_data->wait_for_reset) 1438 samsung_dsim_wait_for_reset(dsi); 1439 samsung_dsim_set_phy_ctrl(dsi); 1440 samsung_dsim_init_link(dsi); 1441 1442 dsi->state |= DSIM_STATE_INITIALIZED; 1443 1444 return 0; 1445 } 1446 1447 static void samsung_dsim_atomic_pre_enable(struct drm_bridge *bridge, 1448 struct drm_atomic_state *state) 1449 { 1450 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1451 int ret; 1452 1453 if (dsi->state & DSIM_STATE_ENABLED) 1454 return; 1455 1456 ret = pm_runtime_resume_and_get(dsi->dev); 1457 if (ret < 0) { 1458 dev_err(dsi->dev, "failed to enable DSI device.\n"); 1459 return; 1460 } 1461 1462 dsi->state |= DSIM_STATE_ENABLED; 1463 1464 /* 1465 * For Exynos-DSIM the downstream bridge, or panel are expecting 1466 * the host initialization during DSI transfer. 1467 */ 1468 if (!samsung_dsim_hw_is_exynos(dsi->plat_data->hw_type)) { 1469 ret = samsung_dsim_init(dsi); 1470 if (ret) 1471 return; 1472 } 1473 } 1474 1475 static void samsung_dsim_atomic_enable(struct drm_bridge *bridge, 1476 struct drm_atomic_state *state) 1477 { 1478 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1479 1480 samsung_dsim_set_display_mode(dsi); 1481 samsung_dsim_set_display_enable(dsi, true); 1482 1483 dsi->state |= DSIM_STATE_VIDOUT_AVAILABLE; 1484 } 1485 1486 static void samsung_dsim_atomic_disable(struct drm_bridge *bridge, 1487 struct drm_atomic_state *state) 1488 { 1489 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1490 1491 if (!(dsi->state & DSIM_STATE_ENABLED)) 1492 return; 1493 1494 samsung_dsim_set_display_enable(dsi, false); 1495 dsi->state &= ~DSIM_STATE_VIDOUT_AVAILABLE; 1496 } 1497 1498 static void samsung_dsim_atomic_post_disable(struct drm_bridge *bridge, 1499 struct drm_atomic_state *state) 1500 { 1501 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1502 1503 dsi->state &= ~DSIM_STATE_ENABLED; 1504 pm_runtime_put_sync(dsi->dev); 1505 } 1506 1507 /* 1508 * This pixel output formats list referenced from, 1509 * AN13573 i.MX 8/RT MIPI DSI/CSI-2, Rev. 0, 21 March 2022 1510 * 3.7.4 Pixel formats 1511 * Table 14. DSI pixel packing formats 1512 */ 1513 static const u32 samsung_dsim_pixel_output_fmts[] = { 1514 MEDIA_BUS_FMT_YUYV10_1X20, 1515 MEDIA_BUS_FMT_YUYV12_1X24, 1516 MEDIA_BUS_FMT_UYVY8_1X16, 1517 MEDIA_BUS_FMT_RGB101010_1X30, 1518 MEDIA_BUS_FMT_RGB121212_1X36, 1519 MEDIA_BUS_FMT_RGB565_1X16, 1520 MEDIA_BUS_FMT_RGB666_1X18, 1521 MEDIA_BUS_FMT_RGB888_1X24, 1522 }; 1523 1524 static bool samsung_dsim_pixel_output_fmt_supported(u32 fmt) 1525 { 1526 int i; 1527 1528 if (fmt == MEDIA_BUS_FMT_FIXED) 1529 return false; 1530 1531 for (i = 0; i < ARRAY_SIZE(samsung_dsim_pixel_output_fmts); i++) { 1532 if (samsung_dsim_pixel_output_fmts[i] == fmt) 1533 return true; 1534 } 1535 1536 return false; 1537 } 1538 1539 static u32 * 1540 samsung_dsim_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 1541 struct drm_bridge_state *bridge_state, 1542 struct drm_crtc_state *crtc_state, 1543 struct drm_connector_state *conn_state, 1544 u32 output_fmt, 1545 unsigned int *num_input_fmts) 1546 { 1547 u32 *input_fmts; 1548 1549 input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); 1550 if (!input_fmts) 1551 return NULL; 1552 1553 if (!samsung_dsim_pixel_output_fmt_supported(output_fmt)) 1554 /* 1555 * Some bridge/display drivers are still not able to pass the 1556 * correct format, so handle those pipelines by falling back 1557 * to the default format till the supported formats finalized. 1558 */ 1559 output_fmt = MEDIA_BUS_FMT_RGB888_1X24; 1560 1561 input_fmts[0] = output_fmt; 1562 *num_input_fmts = 1; 1563 1564 return input_fmts; 1565 } 1566 1567 static int samsung_dsim_atomic_check(struct drm_bridge *bridge, 1568 struct drm_bridge_state *bridge_state, 1569 struct drm_crtc_state *crtc_state, 1570 struct drm_connector_state *conn_state) 1571 { 1572 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1573 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 1574 1575 /* 1576 * The i.MX8M Mini/Nano glue logic between LCDIF and DSIM 1577 * inverts HS/VS/DE sync signals polarity, therefore, while 1578 * i.MX 8M Mini Applications Processor Reference Manual Rev. 3, 11/2020 1579 * 13.6.3.5.2 RGB interface 1580 * i.MX 8M Nano Applications Processor Reference Manual Rev. 2, 07/2022 1581 * 13.6.2.7.2 RGB interface 1582 * both claim "Vsync, Hsync, and VDEN are active high signals.", the 1583 * LCDIF must generate inverted HS/VS/DE signals, i.e. active LOW. 1584 * 1585 * The i.MX8M Plus glue logic between LCDIFv3 and DSIM does not 1586 * implement the same behavior, therefore LCDIFv3 must generate 1587 * HS/VS/DE signals active HIGH. 1588 */ 1589 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) { 1590 adjusted_mode->flags |= (DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1591 adjusted_mode->flags &= ~(DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1592 } else if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MP) { 1593 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 1594 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 1595 } 1596 1597 /* 1598 * When using video sync pulses, the HFP, HBP, and HSA are divided between 1599 * the available lanes if there is more than one lane. For certain 1600 * timings and lane configurations, the HFP may not be evenly divisible. 1601 * If the HFP is rounded down, it ends up being too small which can cause 1602 * some monitors to not sync properly. In these instances, adjust htotal 1603 * and hsync to round the HFP up, and recalculate the htotal. Through trial 1604 * and error, it appears that the HBP and HSA do not appearto need the same 1605 * correction that HFP does. 1606 */ 1607 if (dsi->lanes > 1) { 1608 int hfp = adjusted_mode->hsync_start - adjusted_mode->hdisplay; 1609 int remainder = hfp % dsi->lanes; 1610 1611 if (remainder) { 1612 adjusted_mode->hsync_start += remainder; 1613 adjusted_mode->hsync_end += remainder; 1614 adjusted_mode->htotal += remainder; 1615 } 1616 } 1617 1618 return 0; 1619 } 1620 1621 static void samsung_dsim_mode_set(struct drm_bridge *bridge, 1622 const struct drm_display_mode *mode, 1623 const struct drm_display_mode *adjusted_mode) 1624 { 1625 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1626 1627 drm_mode_copy(&dsi->mode, adjusted_mode); 1628 } 1629 1630 static int samsung_dsim_attach(struct drm_bridge *bridge, 1631 struct drm_encoder *encoder, 1632 enum drm_bridge_attach_flags flags) 1633 { 1634 struct samsung_dsim *dsi = bridge_to_dsi(bridge); 1635 1636 return drm_bridge_attach(encoder, dsi->out_bridge, bridge, 1637 flags); 1638 } 1639 1640 static const struct drm_bridge_funcs samsung_dsim_bridge_funcs = { 1641 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 1642 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 1643 .atomic_reset = drm_atomic_helper_bridge_reset, 1644 .atomic_get_input_bus_fmts = samsung_dsim_atomic_get_input_bus_fmts, 1645 .atomic_check = samsung_dsim_atomic_check, 1646 .atomic_pre_enable = samsung_dsim_atomic_pre_enable, 1647 .atomic_enable = samsung_dsim_atomic_enable, 1648 .atomic_disable = samsung_dsim_atomic_disable, 1649 .atomic_post_disable = samsung_dsim_atomic_post_disable, 1650 .mode_set = samsung_dsim_mode_set, 1651 .attach = samsung_dsim_attach, 1652 }; 1653 1654 static irqreturn_t samsung_dsim_te_irq_handler(int irq, void *dev_id) 1655 { 1656 struct samsung_dsim *dsi = (struct samsung_dsim *)dev_id; 1657 const struct samsung_dsim_plat_data *pdata = dsi->plat_data; 1658 1659 if (pdata->host_ops && pdata->host_ops->te_irq_handler) 1660 return pdata->host_ops->te_irq_handler(dsi); 1661 1662 return IRQ_HANDLED; 1663 } 1664 1665 static int samsung_dsim_register_te_irq(struct samsung_dsim *dsi, struct device *dev) 1666 { 1667 int te_gpio_irq; 1668 int ret; 1669 1670 dsi->te_gpio = devm_gpiod_get_optional(dev, "te", GPIOD_IN); 1671 if (!dsi->te_gpio) 1672 return 0; 1673 else if (IS_ERR(dsi->te_gpio)) 1674 return dev_err_probe(dev, PTR_ERR(dsi->te_gpio), "failed to get te GPIO\n"); 1675 1676 te_gpio_irq = gpiod_to_irq(dsi->te_gpio); 1677 1678 ret = request_threaded_irq(te_gpio_irq, samsung_dsim_te_irq_handler, NULL, 1679 IRQF_TRIGGER_RISING | IRQF_NO_AUTOEN, "TE", dsi); 1680 if (ret) { 1681 dev_err(dsi->dev, "request interrupt failed with %d\n", ret); 1682 gpiod_put(dsi->te_gpio); 1683 return ret; 1684 } 1685 1686 return 0; 1687 } 1688 1689 static int samsung_dsim_host_attach(struct mipi_dsi_host *host, 1690 struct mipi_dsi_device *device) 1691 { 1692 struct samsung_dsim *dsi = host_to_dsi(host); 1693 const struct samsung_dsim_plat_data *pdata = dsi->plat_data; 1694 struct device *dev = dsi->dev; 1695 struct device_node *np = dev->of_node; 1696 struct device_node *remote; 1697 struct drm_panel *panel; 1698 int ret; 1699 1700 /* 1701 * Devices can also be child nodes when we also control that device 1702 * through the upstream device (ie, MIPI-DCS for a MIPI-DSI device). 1703 * 1704 * Lookup for a child node of the given parent that isn't either port 1705 * or ports. 1706 */ 1707 for_each_available_child_of_node(np, remote) { 1708 if (of_node_name_eq(remote, "port") || 1709 of_node_name_eq(remote, "ports")) 1710 continue; 1711 1712 goto of_find_panel_or_bridge; 1713 } 1714 1715 /* 1716 * of_graph_get_remote_node() produces a noisy error message if port 1717 * node isn't found and the absence of the port is a legit case here, 1718 * so at first we silently check whether graph presents in the 1719 * device-tree node. 1720 */ 1721 if (!of_graph_is_present(np)) 1722 return -ENODEV; 1723 1724 remote = of_graph_get_remote_node(np, 1, 0); 1725 1726 of_find_panel_or_bridge: 1727 if (!remote) 1728 return -ENODEV; 1729 1730 panel = of_drm_find_panel(remote); 1731 if (!IS_ERR(panel)) { 1732 dsi->out_bridge = devm_drm_panel_bridge_add(dev, panel); 1733 } else { 1734 dsi->out_bridge = of_drm_find_bridge(remote); 1735 if (!dsi->out_bridge) 1736 dsi->out_bridge = ERR_PTR(-EINVAL); 1737 } 1738 1739 of_node_put(remote); 1740 1741 if (IS_ERR(dsi->out_bridge)) { 1742 ret = PTR_ERR(dsi->out_bridge); 1743 DRM_DEV_ERROR(dev, "failed to find the bridge: %d\n", ret); 1744 return ret; 1745 } 1746 1747 DRM_DEV_INFO(dev, "Attached %s device (lanes:%d bpp:%d mode-flags:0x%lx)\n", 1748 device->name, device->lanes, 1749 mipi_dsi_pixel_format_to_bpp(device->format), 1750 device->mode_flags); 1751 1752 drm_bridge_add(&dsi->bridge); 1753 1754 /* 1755 * This is a temporary solution and should be made by more generic way. 1756 * 1757 * If attached panel device is for command mode one, dsi should register 1758 * TE interrupt handler. 1759 */ 1760 if (!(device->mode_flags & MIPI_DSI_MODE_VIDEO)) { 1761 ret = samsung_dsim_register_te_irq(dsi, &device->dev); 1762 if (ret) 1763 return ret; 1764 } 1765 1766 if (pdata->host_ops && pdata->host_ops->attach) { 1767 ret = pdata->host_ops->attach(dsi, device); 1768 if (ret) 1769 return ret; 1770 } 1771 1772 dsi->lanes = device->lanes; 1773 dsi->format = device->format; 1774 dsi->mode_flags = device->mode_flags; 1775 1776 return 0; 1777 } 1778 1779 static void samsung_dsim_unregister_te_irq(struct samsung_dsim *dsi) 1780 { 1781 if (dsi->te_gpio) { 1782 free_irq(gpiod_to_irq(dsi->te_gpio), dsi); 1783 gpiod_put(dsi->te_gpio); 1784 } 1785 } 1786 1787 static int samsung_dsim_host_detach(struct mipi_dsi_host *host, 1788 struct mipi_dsi_device *device) 1789 { 1790 struct samsung_dsim *dsi = host_to_dsi(host); 1791 const struct samsung_dsim_plat_data *pdata = dsi->plat_data; 1792 1793 dsi->out_bridge = NULL; 1794 1795 if (pdata->host_ops && pdata->host_ops->detach) 1796 pdata->host_ops->detach(dsi, device); 1797 1798 samsung_dsim_unregister_te_irq(dsi); 1799 1800 drm_bridge_remove(&dsi->bridge); 1801 1802 return 0; 1803 } 1804 1805 static ssize_t samsung_dsim_host_transfer(struct mipi_dsi_host *host, 1806 const struct mipi_dsi_msg *msg) 1807 { 1808 struct samsung_dsim *dsi = host_to_dsi(host); 1809 struct samsung_dsim_transfer xfer; 1810 int ret; 1811 1812 if (!(dsi->state & DSIM_STATE_ENABLED)) 1813 return -EINVAL; 1814 1815 ret = samsung_dsim_init(dsi); 1816 if (ret) 1817 return ret; 1818 1819 ret = mipi_dsi_create_packet(&xfer.packet, msg); 1820 if (ret < 0) 1821 return ret; 1822 1823 xfer.rx_len = msg->rx_len; 1824 xfer.rx_payload = msg->rx_buf; 1825 xfer.flags = msg->flags; 1826 1827 ret = samsung_dsim_transfer(dsi, &xfer); 1828 return (ret < 0) ? ret : xfer.rx_done; 1829 } 1830 1831 static const struct mipi_dsi_host_ops samsung_dsim_ops = { 1832 .attach = samsung_dsim_host_attach, 1833 .detach = samsung_dsim_host_detach, 1834 .transfer = samsung_dsim_host_transfer, 1835 }; 1836 1837 static int samsung_dsim_of_read_u32(const struct device_node *np, 1838 const char *propname, u32 *out_value, bool optional) 1839 { 1840 int ret = of_property_read_u32(np, propname, out_value); 1841 1842 if (ret < 0 && !optional) 1843 pr_err("%pOF: failed to get '%s' property\n", np, propname); 1844 1845 return ret; 1846 } 1847 1848 static int samsung_dsim_parse_dt(struct samsung_dsim *dsi) 1849 { 1850 struct device *dev = dsi->dev; 1851 struct device_node *node = dev->of_node; 1852 u32 lane_polarities[5] = { 0 }; 1853 struct device_node *endpoint; 1854 int i, nr_lanes, ret; 1855 1856 ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency", 1857 &dsi->pll_clk_rate, 1); 1858 /* If it doesn't exist, read it from the clock instead of failing */ 1859 if (ret < 0) { 1860 dev_dbg(dev, "Using sclk_mipi for pll clock frequency\n"); 1861 dsi->pll_clk = devm_clk_get(dev, "sclk_mipi"); 1862 if (IS_ERR(dsi->pll_clk)) 1863 return PTR_ERR(dsi->pll_clk); 1864 } 1865 1866 /* If it doesn't exist, use pixel clock instead of failing */ 1867 ret = samsung_dsim_of_read_u32(node, "samsung,burst-clock-frequency", 1868 &dsi->burst_clk_rate, 1); 1869 if (ret < 0) { 1870 dev_dbg(dev, "Using pixel clock for HS clock frequency\n"); 1871 dsi->burst_clk_rate = 0; 1872 } 1873 1874 ret = samsung_dsim_of_read_u32(node, "samsung,esc-clock-frequency", 1875 &dsi->esc_clk_rate, 0); 1876 if (ret < 0) 1877 return ret; 1878 1879 endpoint = of_graph_get_endpoint_by_regs(node, 1, -1); 1880 nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes"); 1881 if (nr_lanes > 0 && nr_lanes <= 4) { 1882 /* Polarity 0 is clock lane, 1..4 are data lanes. */ 1883 of_property_read_u32_array(endpoint, "lane-polarities", 1884 lane_polarities, nr_lanes + 1); 1885 for (i = 1; i <= nr_lanes; i++) { 1886 if (lane_polarities[1] != lane_polarities[i]) 1887 DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match"); 1888 } 1889 if (lane_polarities[0]) 1890 dsi->swap_dn_dp_clk = true; 1891 if (lane_polarities[1]) 1892 dsi->swap_dn_dp_data = true; 1893 } 1894 1895 return 0; 1896 } 1897 1898 static int generic_dsim_register_host(struct samsung_dsim *dsi) 1899 { 1900 return mipi_dsi_host_register(&dsi->dsi_host); 1901 } 1902 1903 static void generic_dsim_unregister_host(struct samsung_dsim *dsi) 1904 { 1905 mipi_dsi_host_unregister(&dsi->dsi_host); 1906 } 1907 1908 static const struct samsung_dsim_host_ops generic_dsim_host_ops = { 1909 .register_host = generic_dsim_register_host, 1910 .unregister_host = generic_dsim_unregister_host, 1911 }; 1912 1913 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_high = { 1914 .input_bus_flags = DRM_BUS_FLAG_DE_HIGH, 1915 }; 1916 1917 static const struct drm_bridge_timings samsung_dsim_bridge_timings_de_low = { 1918 .input_bus_flags = DRM_BUS_FLAG_DE_LOW, 1919 }; 1920 1921 int samsung_dsim_probe(struct platform_device *pdev) 1922 { 1923 struct device *dev = &pdev->dev; 1924 struct samsung_dsim *dsi; 1925 int ret, i; 1926 1927 dsi = devm_drm_bridge_alloc(dev, struct samsung_dsim, bridge, &samsung_dsim_bridge_funcs); 1928 if (IS_ERR(dsi)) 1929 return PTR_ERR(dsi); 1930 1931 init_completion(&dsi->completed); 1932 spin_lock_init(&dsi->transfer_lock); 1933 INIT_LIST_HEAD(&dsi->transfer_list); 1934 1935 dsi->dsi_host.ops = &samsung_dsim_ops; 1936 dsi->dsi_host.dev = dev; 1937 1938 dsi->dev = dev; 1939 dsi->plat_data = of_device_get_match_data(dev); 1940 dsi->driver_data = samsung_dsim_types[dsi->plat_data->hw_type]; 1941 1942 dsi->supplies[0].supply = "vddcore"; 1943 dsi->supplies[1].supply = "vddio"; 1944 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(dsi->supplies), 1945 dsi->supplies); 1946 if (ret) 1947 return dev_err_probe(dev, ret, "failed to get regulators\n"); 1948 1949 dsi->clks = devm_kcalloc(dev, dsi->driver_data->num_clks, 1950 sizeof(*dsi->clks), GFP_KERNEL); 1951 if (!dsi->clks) 1952 return -ENOMEM; 1953 1954 for (i = 0; i < dsi->driver_data->num_clks; i++) { 1955 dsi->clks[i] = devm_clk_get(dev, clk_names[i]); 1956 if (IS_ERR(dsi->clks[i])) { 1957 if (strcmp(clk_names[i], "sclk_mipi") == 0) { 1958 dsi->clks[i] = devm_clk_get(dev, OLD_SCLK_MIPI_CLK_NAME); 1959 if (!IS_ERR(dsi->clks[i])) 1960 continue; 1961 } 1962 1963 dev_info(dev, "failed to get the clock: %s\n", clk_names[i]); 1964 return PTR_ERR(dsi->clks[i]); 1965 } 1966 } 1967 1968 dsi->reg_base = devm_platform_ioremap_resource(pdev, 0); 1969 if (IS_ERR(dsi->reg_base)) 1970 return PTR_ERR(dsi->reg_base); 1971 1972 dsi->phy = devm_phy_optional_get(dev, "dsim"); 1973 if (IS_ERR(dsi->phy)) { 1974 dev_info(dev, "failed to get dsim phy\n"); 1975 return PTR_ERR(dsi->phy); 1976 } 1977 1978 dsi->irq = platform_get_irq(pdev, 0); 1979 if (dsi->irq < 0) 1980 return dsi->irq; 1981 1982 ret = devm_request_threaded_irq(dev, dsi->irq, NULL, 1983 samsung_dsim_irq, 1984 IRQF_ONESHOT | IRQF_NO_AUTOEN, 1985 dev_name(dev), dsi); 1986 if (ret) { 1987 dev_err(dev, "failed to request dsi irq\n"); 1988 return ret; 1989 } 1990 1991 ret = samsung_dsim_parse_dt(dsi); 1992 if (ret) 1993 return ret; 1994 1995 platform_set_drvdata(pdev, dsi); 1996 1997 pm_runtime_enable(dev); 1998 1999 dsi->bridge.of_node = dev->of_node; 2000 dsi->bridge.type = DRM_MODE_CONNECTOR_DSI; 2001 2002 /* DE_LOW: i.MX8M Mini/Nano LCDIF-DSIM glue logic inverts HS/VS/DE */ 2003 if (dsi->plat_data->hw_type == DSIM_TYPE_IMX8MM) 2004 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_low; 2005 else 2006 dsi->bridge.timings = &samsung_dsim_bridge_timings_de_high; 2007 2008 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->register_host) { 2009 ret = dsi->plat_data->host_ops->register_host(dsi); 2010 if (ret) 2011 goto err_disable_runtime; 2012 } 2013 2014 return 0; 2015 2016 err_disable_runtime: 2017 pm_runtime_disable(dev); 2018 2019 return ret; 2020 } 2021 EXPORT_SYMBOL_GPL(samsung_dsim_probe); 2022 2023 void samsung_dsim_remove(struct platform_device *pdev) 2024 { 2025 struct samsung_dsim *dsi = platform_get_drvdata(pdev); 2026 2027 pm_runtime_disable(&pdev->dev); 2028 2029 if (dsi->plat_data->host_ops && dsi->plat_data->host_ops->unregister_host) 2030 dsi->plat_data->host_ops->unregister_host(dsi); 2031 } 2032 EXPORT_SYMBOL_GPL(samsung_dsim_remove); 2033 2034 static int samsung_dsim_suspend(struct device *dev) 2035 { 2036 struct samsung_dsim *dsi = dev_get_drvdata(dev); 2037 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 2038 int ret, i; 2039 2040 usleep_range(10000, 20000); 2041 2042 if (dsi->state & DSIM_STATE_INITIALIZED) { 2043 dsi->state &= ~DSIM_STATE_INITIALIZED; 2044 2045 samsung_dsim_disable_clock(dsi); 2046 2047 samsung_dsim_disable_irq(dsi); 2048 } 2049 2050 dsi->state &= ~DSIM_STATE_CMD_LPM; 2051 2052 phy_power_off(dsi->phy); 2053 2054 for (i = driver_data->num_clks - 1; i > -1; i--) 2055 clk_disable_unprepare(dsi->clks[i]); 2056 2057 ret = regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 2058 if (ret < 0) 2059 dev_err(dsi->dev, "cannot disable regulators %d\n", ret); 2060 2061 return 0; 2062 } 2063 2064 static int samsung_dsim_resume(struct device *dev) 2065 { 2066 struct samsung_dsim *dsi = dev_get_drvdata(dev); 2067 const struct samsung_dsim_driver_data *driver_data = dsi->driver_data; 2068 int ret, i; 2069 2070 ret = regulator_bulk_enable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 2071 if (ret < 0) { 2072 dev_err(dsi->dev, "cannot enable regulators %d\n", ret); 2073 return ret; 2074 } 2075 2076 for (i = 0; i < driver_data->num_clks; i++) { 2077 ret = clk_prepare_enable(dsi->clks[i]); 2078 if (ret < 0) 2079 goto err_clk; 2080 } 2081 2082 ret = phy_power_on(dsi->phy); 2083 if (ret < 0) { 2084 dev_err(dsi->dev, "cannot enable phy %d\n", ret); 2085 goto err_clk; 2086 } 2087 2088 return 0; 2089 2090 err_clk: 2091 while (--i > -1) 2092 clk_disable_unprepare(dsi->clks[i]); 2093 regulator_bulk_disable(ARRAY_SIZE(dsi->supplies), dsi->supplies); 2094 2095 return ret; 2096 } 2097 2098 const struct dev_pm_ops samsung_dsim_pm_ops = { 2099 RUNTIME_PM_OPS(samsung_dsim_suspend, samsung_dsim_resume, NULL) 2100 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2101 pm_runtime_force_resume) 2102 }; 2103 EXPORT_SYMBOL_GPL(samsung_dsim_pm_ops); 2104 2105 static const struct samsung_dsim_plat_data samsung_dsim_imx8mm_pdata = { 2106 .hw_type = DSIM_TYPE_IMX8MM, 2107 .host_ops = &generic_dsim_host_ops, 2108 }; 2109 2110 static const struct samsung_dsim_plat_data samsung_dsim_imx8mp_pdata = { 2111 .hw_type = DSIM_TYPE_IMX8MP, 2112 .host_ops = &generic_dsim_host_ops, 2113 }; 2114 2115 static const struct of_device_id samsung_dsim_of_match[] = { 2116 { 2117 .compatible = "fsl,imx8mm-mipi-dsim", 2118 .data = &samsung_dsim_imx8mm_pdata, 2119 }, 2120 { 2121 .compatible = "fsl,imx8mp-mipi-dsim", 2122 .data = &samsung_dsim_imx8mp_pdata, 2123 }, 2124 { /* sentinel. */ } 2125 }; 2126 MODULE_DEVICE_TABLE(of, samsung_dsim_of_match); 2127 2128 static struct platform_driver samsung_dsim_driver = { 2129 .probe = samsung_dsim_probe, 2130 .remove = samsung_dsim_remove, 2131 .driver = { 2132 .name = "samsung-dsim", 2133 .pm = pm_ptr(&samsung_dsim_pm_ops), 2134 .of_match_table = samsung_dsim_of_match, 2135 }, 2136 }; 2137 2138 module_platform_driver(samsung_dsim_driver); 2139 2140 MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>"); 2141 MODULE_DESCRIPTION("Samsung MIPI DSIM controller bridge"); 2142 MODULE_LICENSE("GPL"); 2143