1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * i.MX8 NWL MIPI DSI host driver 4 * 5 * Copyright (C) 2017 NXP 6 * Copyright (C) 2020 Purism SPC 7 */ 8 9 #include <linux/bitfield.h> 10 #include <linux/clk.h> 11 #include <linux/irq.h> 12 #include <linux/math64.h> 13 #include <linux/mfd/syscon.h> 14 #include <linux/module.h> 15 #include <linux/mux/consumer.h> 16 #include <linux/of.h> 17 #include <linux/of_platform.h> 18 #include <linux/phy/phy.h> 19 #include <linux/regmap.h> 20 #include <linux/reset.h> 21 #include <linux/sys_soc.h> 22 #include <linux/time64.h> 23 24 #include <drm/drm_atomic_state_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_mipi_dsi.h> 27 #include <drm/drm_of.h> 28 #include <drm/drm_panel.h> 29 #include <drm/drm_print.h> 30 31 #include <video/mipi_display.h> 32 33 #include "nwl-dsi.h" 34 35 #define DRV_NAME "nwl-dsi" 36 37 /* i.MX8 NWL quirks */ 38 /* i.MX8MQ errata E11418 */ 39 #define E11418_HS_MODE_QUIRK BIT(0) 40 41 #define NWL_DSI_MIPI_FIFO_TIMEOUT msecs_to_jiffies(500) 42 43 enum transfer_direction { 44 DSI_PACKET_SEND, 45 DSI_PACKET_RECEIVE, 46 }; 47 48 #define NWL_DSI_ENDPOINT_LCDIF 0 49 #define NWL_DSI_ENDPOINT_DCSS 1 50 51 struct nwl_dsi_transfer { 52 const struct mipi_dsi_msg *msg; 53 struct mipi_dsi_packet packet; 54 struct completion completed; 55 56 int status; /* status of transmission */ 57 enum transfer_direction direction; 58 bool need_bta; 59 u8 cmd; 60 u16 rx_word_count; 61 size_t tx_len; /* in bytes */ 62 size_t rx_len; /* in bytes */ 63 }; 64 65 struct nwl_dsi { 66 struct drm_bridge bridge; 67 struct mipi_dsi_host dsi_host; 68 struct device *dev; 69 struct phy *phy; 70 union phy_configure_opts phy_cfg; 71 unsigned int quirks; 72 73 struct regmap *regmap; 74 int irq; 75 /* 76 * The DSI host controller needs this reset sequence according to NWL: 77 * 1. Deassert pclk reset to get access to DSI regs 78 * 2. Configure DSI Host and DPHY and enable DPHY 79 * 3. Deassert ESC and BYTE resets to allow host TX operations) 80 * 4. Send DSI cmds to configure peripheral (handled by panel drv) 81 * 5. Deassert DPI reset so DPI receives pixels and starts sending 82 * DSI data 83 * 84 * TODO: Since panel_bridges do their DSI setup in enable we 85 * currently have 4. and 5. swapped. 86 */ 87 struct reset_control *rst_byte; 88 struct reset_control *rst_esc; 89 struct reset_control *rst_dpi; 90 struct reset_control *rst_pclk; 91 struct mux_control *mux; 92 93 /* DSI clocks */ 94 struct clk *phy_ref_clk; 95 struct clk *rx_esc_clk; 96 struct clk *tx_esc_clk; 97 struct clk *core_clk; 98 /* 99 * hardware bug: the i.MX8MQ needs this clock on during reset 100 * even when not using LCDIF. 101 */ 102 struct clk *lcdif_clk; 103 104 /* dsi lanes */ 105 u32 lanes; 106 enum mipi_dsi_pixel_format format; 107 struct drm_display_mode mode; 108 unsigned long dsi_mode_flags; 109 int error; 110 111 struct nwl_dsi_transfer *xfer; 112 }; 113 114 static const struct regmap_config nwl_dsi_regmap_config = { 115 .reg_bits = 16, 116 .val_bits = 32, 117 .reg_stride = 4, 118 .max_register = NWL_DSI_IRQ_MASK2, 119 .name = DRV_NAME, 120 }; 121 122 static inline struct nwl_dsi *bridge_to_dsi(struct drm_bridge *bridge) 123 { 124 return container_of(bridge, struct nwl_dsi, bridge); 125 } 126 127 static int nwl_dsi_clear_error(struct nwl_dsi *dsi) 128 { 129 int ret = dsi->error; 130 131 dsi->error = 0; 132 return ret; 133 } 134 135 static void nwl_dsi_write(struct nwl_dsi *dsi, unsigned int reg, u32 val) 136 { 137 int ret; 138 139 if (dsi->error) 140 return; 141 142 ret = regmap_write(dsi->regmap, reg, val); 143 if (ret < 0) { 144 DRM_DEV_ERROR(dsi->dev, 145 "Failed to write NWL DSI reg 0x%x: %d\n", reg, 146 ret); 147 dsi->error = ret; 148 } 149 } 150 151 static u32 nwl_dsi_read(struct nwl_dsi *dsi, u32 reg) 152 { 153 unsigned int val; 154 int ret; 155 156 if (dsi->error) 157 return 0; 158 159 ret = regmap_read(dsi->regmap, reg, &val); 160 if (ret < 0) { 161 DRM_DEV_ERROR(dsi->dev, "Failed to read NWL DSI reg 0x%x: %d\n", 162 reg, ret); 163 dsi->error = ret; 164 } 165 return val; 166 } 167 168 static int nwl_dsi_get_dpi_pixel_format(enum mipi_dsi_pixel_format format) 169 { 170 switch (format) { 171 case MIPI_DSI_FMT_RGB565: 172 return NWL_DSI_PIXEL_FORMAT_16; 173 case MIPI_DSI_FMT_RGB666: 174 return NWL_DSI_PIXEL_FORMAT_18L; 175 case MIPI_DSI_FMT_RGB666_PACKED: 176 return NWL_DSI_PIXEL_FORMAT_18; 177 case MIPI_DSI_FMT_RGB888: 178 return NWL_DSI_PIXEL_FORMAT_24; 179 default: 180 return -EINVAL; 181 } 182 } 183 184 /* 185 * ps2bc - Picoseconds to byte clock cycles 186 */ 187 static u32 ps2bc(struct nwl_dsi *dsi, unsigned long long ps) 188 { 189 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 190 191 return DIV64_U64_ROUND_UP(ps * dsi->mode.clock * bpp, 192 dsi->lanes * 8ULL * NSEC_PER_SEC); 193 } 194 195 /* 196 * ui2bc - UI time periods to byte clock cycles 197 */ 198 static u32 ui2bc(struct nwl_dsi *dsi, unsigned long long ui) 199 { 200 u32 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 201 202 return DIV64_U64_ROUND_UP(ui * dsi->lanes, 203 dsi->mode.clock * 1000 * bpp); 204 } 205 206 /* 207 * us2bc - micro seconds to lp clock cycles 208 */ 209 static u32 us2lp(u32 lp_clk_rate, unsigned long us) 210 { 211 return DIV_ROUND_UP(us * lp_clk_rate, USEC_PER_SEC); 212 } 213 214 static int nwl_dsi_config_host(struct nwl_dsi *dsi) 215 { 216 u32 cycles; 217 struct phy_configure_opts_mipi_dphy *cfg = &dsi->phy_cfg.mipi_dphy; 218 219 if (dsi->lanes < 1 || dsi->lanes > 4) 220 return -EINVAL; 221 222 DRM_DEV_DEBUG_DRIVER(dsi->dev, "DSI Lanes %d\n", dsi->lanes); 223 nwl_dsi_write(dsi, NWL_DSI_CFG_NUM_LANES, dsi->lanes - 1); 224 225 if (dsi->dsi_mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) { 226 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x01); 227 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x01); 228 } else { 229 nwl_dsi_write(dsi, NWL_DSI_CFG_NONCONTINUOUS_CLK, 0x00); 230 nwl_dsi_write(dsi, NWL_DSI_CFG_AUTOINSERT_EOTP, 0x00); 231 } 232 233 /* values in byte clock cycles */ 234 cycles = ui2bc(dsi, cfg->clk_pre); 235 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_pre: 0x%x\n", cycles); 236 nwl_dsi_write(dsi, NWL_DSI_CFG_T_PRE, cycles); 237 cycles = ps2bc(dsi, cfg->lpx + cfg->clk_prepare + cfg->clk_zero); 238 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap (pre): 0x%x\n", cycles); 239 cycles += ui2bc(dsi, cfg->clk_pre); 240 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_t_post: 0x%x\n", cycles); 241 nwl_dsi_write(dsi, NWL_DSI_CFG_T_POST, cycles); 242 cycles = ps2bc(dsi, cfg->hs_exit); 243 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_tx_gap: 0x%x\n", cycles); 244 nwl_dsi_write(dsi, NWL_DSI_CFG_TX_GAP, cycles); 245 246 nwl_dsi_write(dsi, NWL_DSI_CFG_EXTRA_CMDS_AFTER_EOTP, 0x01); 247 nwl_dsi_write(dsi, NWL_DSI_CFG_HTX_TO_COUNT, 0x00); 248 nwl_dsi_write(dsi, NWL_DSI_CFG_LRX_H_TO_COUNT, 0x00); 249 nwl_dsi_write(dsi, NWL_DSI_CFG_BTA_H_TO_COUNT, 0x00); 250 /* In LP clock cycles */ 251 cycles = us2lp(cfg->lp_clk_rate, cfg->wakeup); 252 DRM_DEV_DEBUG_DRIVER(dsi->dev, "cfg_twakeup: 0x%x\n", cycles); 253 nwl_dsi_write(dsi, NWL_DSI_CFG_TWAKEUP, cycles); 254 255 return nwl_dsi_clear_error(dsi); 256 } 257 258 static int nwl_dsi_config_dpi(struct nwl_dsi *dsi) 259 { 260 u32 mode; 261 int color_format; 262 bool burst_mode; 263 int hfront_porch, hback_porch, vfront_porch, vback_porch; 264 int hsync_len, vsync_len; 265 266 hfront_porch = dsi->mode.hsync_start - dsi->mode.hdisplay; 267 hsync_len = dsi->mode.hsync_end - dsi->mode.hsync_start; 268 hback_porch = dsi->mode.htotal - dsi->mode.hsync_end; 269 270 vfront_porch = dsi->mode.vsync_start - dsi->mode.vdisplay; 271 vsync_len = dsi->mode.vsync_end - dsi->mode.vsync_start; 272 vback_porch = dsi->mode.vtotal - dsi->mode.vsync_end; 273 274 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hfront_porch = %d\n", hfront_porch); 275 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hback_porch = %d\n", hback_porch); 276 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hsync_len = %d\n", hsync_len); 277 DRM_DEV_DEBUG_DRIVER(dsi->dev, "hdisplay = %d\n", dsi->mode.hdisplay); 278 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vfront_porch = %d\n", vfront_porch); 279 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vback_porch = %d\n", vback_porch); 280 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vsync_len = %d\n", vsync_len); 281 DRM_DEV_DEBUG_DRIVER(dsi->dev, "vactive = %d\n", dsi->mode.vdisplay); 282 DRM_DEV_DEBUG_DRIVER(dsi->dev, "clock = %d kHz\n", dsi->mode.clock); 283 284 color_format = nwl_dsi_get_dpi_pixel_format(dsi->format); 285 if (color_format < 0) { 286 DRM_DEV_ERROR(dsi->dev, "Invalid color format 0x%x\n", 287 dsi->format); 288 return color_format; 289 } 290 DRM_DEV_DEBUG_DRIVER(dsi->dev, "pixel fmt = %d\n", dsi->format); 291 292 nwl_dsi_write(dsi, NWL_DSI_INTERFACE_COLOR_CODING, NWL_DSI_DPI_24_BIT); 293 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FORMAT, color_format); 294 /* 295 * Adjusting input polarity based on the video mode results in 296 * a black screen so always pick active low: 297 */ 298 nwl_dsi_write(dsi, NWL_DSI_VSYNC_POLARITY, 299 NWL_DSI_VSYNC_POLARITY_ACTIVE_LOW); 300 nwl_dsi_write(dsi, NWL_DSI_HSYNC_POLARITY, 301 NWL_DSI_HSYNC_POLARITY_ACTIVE_LOW); 302 303 burst_mode = (dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_BURST) && 304 !(dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE); 305 306 if (burst_mode) { 307 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, NWL_DSI_VM_BURST_MODE); 308 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 256); 309 } else { 310 mode = ((dsi->dsi_mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) ? 311 NWL_DSI_VM_BURST_MODE_WITH_SYNC_PULSES : 312 NWL_DSI_VM_NON_BURST_MODE_WITH_SYNC_EVENTS); 313 nwl_dsi_write(dsi, NWL_DSI_VIDEO_MODE, mode); 314 nwl_dsi_write(dsi, NWL_DSI_PIXEL_FIFO_SEND_LEVEL, 315 dsi->mode.hdisplay); 316 } 317 318 nwl_dsi_write(dsi, NWL_DSI_HFP, hfront_porch); 319 nwl_dsi_write(dsi, NWL_DSI_HBP, hback_porch); 320 nwl_dsi_write(dsi, NWL_DSI_HSA, hsync_len); 321 322 nwl_dsi_write(dsi, NWL_DSI_ENABLE_MULT_PKTS, 0x0); 323 nwl_dsi_write(dsi, NWL_DSI_BLLP_MODE, 0x1); 324 nwl_dsi_write(dsi, NWL_DSI_USE_NULL_PKT_BLLP, 0x0); 325 nwl_dsi_write(dsi, NWL_DSI_VC, 0x0); 326 327 nwl_dsi_write(dsi, NWL_DSI_PIXEL_PAYLOAD_SIZE, dsi->mode.hdisplay); 328 nwl_dsi_write(dsi, NWL_DSI_VACTIVE, dsi->mode.vdisplay - 1); 329 nwl_dsi_write(dsi, NWL_DSI_VBP, vback_porch); 330 nwl_dsi_write(dsi, NWL_DSI_VFP, vfront_porch); 331 332 return nwl_dsi_clear_error(dsi); 333 } 334 335 static int nwl_dsi_init_interrupts(struct nwl_dsi *dsi) 336 { 337 u32 irq_enable; 338 339 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, 0xffffffff); 340 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK2, 0x7); 341 342 irq_enable = ~(u32)(NWL_DSI_TX_PKT_DONE_MASK | 343 NWL_DSI_RX_PKT_HDR_RCVD_MASK | 344 NWL_DSI_TX_FIFO_OVFLW_MASK | 345 NWL_DSI_HS_TX_TIMEOUT_MASK); 346 347 nwl_dsi_write(dsi, NWL_DSI_IRQ_MASK, irq_enable); 348 349 return nwl_dsi_clear_error(dsi); 350 } 351 352 static int nwl_dsi_host_attach(struct mipi_dsi_host *dsi_host, 353 struct mipi_dsi_device *device) 354 { 355 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host); 356 struct device *dev = dsi->dev; 357 358 DRM_DEV_INFO(dev, "lanes=%u, format=0x%x flags=0x%lx\n", device->lanes, 359 device->format, device->mode_flags); 360 361 if (device->lanes < 1 || device->lanes > 4) 362 return -EINVAL; 363 364 dsi->lanes = device->lanes; 365 dsi->format = device->format; 366 dsi->dsi_mode_flags = device->mode_flags; 367 368 return 0; 369 } 370 371 static bool nwl_dsi_read_packet(struct nwl_dsi *dsi, u32 status) 372 { 373 struct device *dev = dsi->dev; 374 struct nwl_dsi_transfer *xfer = dsi->xfer; 375 int err; 376 u8 *payload = xfer->msg->rx_buf; 377 u32 val; 378 u16 word_count; 379 u8 channel; 380 u8 data_type; 381 382 xfer->status = 0; 383 384 if (xfer->rx_word_count == 0) { 385 if (!(status & NWL_DSI_RX_PKT_HDR_RCVD)) 386 return false; 387 /* Get the RX header and parse it */ 388 val = nwl_dsi_read(dsi, NWL_DSI_RX_PKT_HEADER); 389 err = nwl_dsi_clear_error(dsi); 390 if (err) 391 xfer->status = err; 392 word_count = NWL_DSI_WC(val); 393 channel = NWL_DSI_RX_VC(val); 394 data_type = NWL_DSI_RX_DT(val); 395 396 if (channel != xfer->msg->channel) { 397 DRM_DEV_ERROR(dev, 398 "[%02X] Channel mismatch (%u != %u)\n", 399 xfer->cmd, channel, xfer->msg->channel); 400 xfer->status = -EINVAL; 401 return true; 402 } 403 404 switch (data_type) { 405 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE: 406 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 407 if (xfer->msg->rx_len > 1) { 408 /* read second byte */ 409 payload[1] = word_count >> 8; 410 ++xfer->rx_len; 411 } 412 fallthrough; 413 case MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE: 414 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 415 if (xfer->msg->rx_len > 0) { 416 /* read first byte */ 417 payload[0] = word_count & 0xff; 418 ++xfer->rx_len; 419 } 420 xfer->status = xfer->rx_len; 421 return true; 422 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 423 word_count &= 0xff; 424 DRM_DEV_ERROR(dev, "[%02X] DSI error report: 0x%02x\n", 425 xfer->cmd, word_count); 426 xfer->status = -EPROTO; 427 return true; 428 } 429 430 if (word_count > xfer->msg->rx_len) { 431 DRM_DEV_ERROR(dev, 432 "[%02X] Receive buffer too small: %zu (< %u)\n", 433 xfer->cmd, xfer->msg->rx_len, word_count); 434 xfer->status = -EINVAL; 435 return true; 436 } 437 438 xfer->rx_word_count = word_count; 439 } else { 440 /* Set word_count from previous header read */ 441 word_count = xfer->rx_word_count; 442 } 443 444 /* If RX payload is not yet received, wait for it */ 445 if (!(status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)) 446 return false; 447 448 /* Read the RX payload */ 449 while (word_count >= 4) { 450 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD); 451 payload[0] = (val >> 0) & 0xff; 452 payload[1] = (val >> 8) & 0xff; 453 payload[2] = (val >> 16) & 0xff; 454 payload[3] = (val >> 24) & 0xff; 455 payload += 4; 456 xfer->rx_len += 4; 457 word_count -= 4; 458 } 459 460 if (word_count > 0) { 461 val = nwl_dsi_read(dsi, NWL_DSI_RX_PAYLOAD); 462 switch (word_count) { 463 case 3: 464 payload[2] = (val >> 16) & 0xff; 465 ++xfer->rx_len; 466 fallthrough; 467 case 2: 468 payload[1] = (val >> 8) & 0xff; 469 ++xfer->rx_len; 470 fallthrough; 471 case 1: 472 payload[0] = (val >> 0) & 0xff; 473 ++xfer->rx_len; 474 break; 475 } 476 } 477 478 xfer->status = xfer->rx_len; 479 err = nwl_dsi_clear_error(dsi); 480 if (err) 481 xfer->status = err; 482 483 return true; 484 } 485 486 static void nwl_dsi_finish_transmission(struct nwl_dsi *dsi, u32 status) 487 { 488 struct nwl_dsi_transfer *xfer = dsi->xfer; 489 bool end_packet = false; 490 491 if (!xfer) 492 return; 493 494 if (xfer->direction == DSI_PACKET_SEND && 495 status & NWL_DSI_TX_PKT_DONE) { 496 xfer->status = xfer->tx_len; 497 end_packet = true; 498 } else if (status & NWL_DSI_DPHY_DIRECTION && 499 ((status & (NWL_DSI_RX_PKT_HDR_RCVD | 500 NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD)))) { 501 end_packet = nwl_dsi_read_packet(dsi, status); 502 } 503 504 if (end_packet) 505 complete(&xfer->completed); 506 } 507 508 static void nwl_dsi_begin_transmission(struct nwl_dsi *dsi) 509 { 510 struct nwl_dsi_transfer *xfer = dsi->xfer; 511 struct mipi_dsi_packet *pkt = &xfer->packet; 512 const u8 *payload; 513 size_t length; 514 u16 word_count; 515 u8 hs_mode; 516 u32 val; 517 u32 hs_workaround = 0; 518 519 /* Send the payload, if any */ 520 length = pkt->payload_length; 521 payload = pkt->payload; 522 523 while (length >= 4) { 524 val = *(u32 *)payload; 525 hs_workaround |= !(val & 0xFFFF00); 526 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val); 527 payload += 4; 528 length -= 4; 529 } 530 /* Send the rest of the payload */ 531 val = 0; 532 switch (length) { 533 case 3: 534 val |= payload[2] << 16; 535 fallthrough; 536 case 2: 537 val |= payload[1] << 8; 538 hs_workaround |= !(val & 0xFFFF00); 539 fallthrough; 540 case 1: 541 val |= payload[0]; 542 nwl_dsi_write(dsi, NWL_DSI_TX_PAYLOAD, val); 543 break; 544 } 545 xfer->tx_len = pkt->payload_length; 546 547 /* 548 * Send the header 549 * header[0] = Virtual Channel + Data Type 550 * header[1] = Word Count LSB (LP) or first param (SP) 551 * header[2] = Word Count MSB (LP) or second param (SP) 552 */ 553 word_count = pkt->header[1] | (pkt->header[2] << 8); 554 if (hs_workaround && (dsi->quirks & E11418_HS_MODE_QUIRK)) { 555 DRM_DEV_DEBUG_DRIVER(dsi->dev, 556 "Using hs mode workaround for cmd 0x%x\n", 557 xfer->cmd); 558 hs_mode = 1; 559 } else { 560 hs_mode = (xfer->msg->flags & MIPI_DSI_MSG_USE_LPM) ? 0 : 1; 561 } 562 val = NWL_DSI_WC(word_count) | NWL_DSI_TX_VC(xfer->msg->channel) | 563 NWL_DSI_TX_DT(xfer->msg->type) | NWL_DSI_HS_SEL(hs_mode) | 564 NWL_DSI_BTA_TX(xfer->need_bta); 565 nwl_dsi_write(dsi, NWL_DSI_PKT_CONTROL, val); 566 567 /* Send packet command */ 568 nwl_dsi_write(dsi, NWL_DSI_SEND_PACKET, 0x1); 569 } 570 571 static ssize_t nwl_dsi_host_transfer(struct mipi_dsi_host *dsi_host, 572 const struct mipi_dsi_msg *msg) 573 { 574 struct nwl_dsi *dsi = container_of(dsi_host, struct nwl_dsi, dsi_host); 575 struct nwl_dsi_transfer xfer; 576 ssize_t ret = 0; 577 578 /* Create packet to be sent */ 579 dsi->xfer = &xfer; 580 ret = mipi_dsi_create_packet(&xfer.packet, msg); 581 if (ret < 0) { 582 dsi->xfer = NULL; 583 return ret; 584 } 585 586 if ((msg->type & MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM || 587 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM || 588 msg->type & MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM || 589 msg->type & MIPI_DSI_DCS_READ) && 590 msg->rx_len > 0 && msg->rx_buf) 591 xfer.direction = DSI_PACKET_RECEIVE; 592 else 593 xfer.direction = DSI_PACKET_SEND; 594 595 xfer.need_bta = (xfer.direction == DSI_PACKET_RECEIVE); 596 xfer.need_bta |= (msg->flags & MIPI_DSI_MSG_REQ_ACK) ? 1 : 0; 597 xfer.msg = msg; 598 xfer.status = -ETIMEDOUT; 599 xfer.rx_word_count = 0; 600 xfer.rx_len = 0; 601 xfer.cmd = 0x00; 602 if (msg->tx_len > 0) 603 xfer.cmd = ((u8 *)(msg->tx_buf))[0]; 604 init_completion(&xfer.completed); 605 606 ret = clk_prepare_enable(dsi->rx_esc_clk); 607 if (ret < 0) { 608 DRM_DEV_ERROR(dsi->dev, "Failed to enable rx_esc clk: %zd\n", 609 ret); 610 return ret; 611 } 612 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled rx_esc clk @%lu Hz\n", 613 clk_get_rate(dsi->rx_esc_clk)); 614 615 /* Initiate the DSI packet transmision */ 616 nwl_dsi_begin_transmission(dsi); 617 618 if (!wait_for_completion_timeout(&xfer.completed, 619 NWL_DSI_MIPI_FIFO_TIMEOUT)) { 620 DRM_DEV_ERROR(dsi_host->dev, "[%02X] DSI transfer timed out\n", 621 xfer.cmd); 622 ret = -ETIMEDOUT; 623 } else { 624 ret = xfer.status; 625 } 626 627 clk_disable_unprepare(dsi->rx_esc_clk); 628 629 return ret; 630 } 631 632 static const struct mipi_dsi_host_ops nwl_dsi_host_ops = { 633 .attach = nwl_dsi_host_attach, 634 .transfer = nwl_dsi_host_transfer, 635 }; 636 637 static irqreturn_t nwl_dsi_irq_handler(int irq, void *data) 638 { 639 u32 irq_status; 640 struct nwl_dsi *dsi = data; 641 642 irq_status = nwl_dsi_read(dsi, NWL_DSI_IRQ_STATUS); 643 644 if (irq_status & NWL_DSI_TX_FIFO_OVFLW) 645 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "tx fifo overflow\n"); 646 647 if (irq_status & NWL_DSI_HS_TX_TIMEOUT) 648 DRM_DEV_ERROR_RATELIMITED(dsi->dev, "HS tx timeout\n"); 649 650 if (irq_status & NWL_DSI_TX_PKT_DONE || 651 irq_status & NWL_DSI_RX_PKT_HDR_RCVD || 652 irq_status & NWL_DSI_RX_PKT_PAYLOAD_DATA_RCVD) 653 nwl_dsi_finish_transmission(dsi, irq_status); 654 655 return IRQ_HANDLED; 656 } 657 658 static int nwl_dsi_mode_set(struct nwl_dsi *dsi) 659 { 660 struct device *dev = dsi->dev; 661 union phy_configure_opts *phy_cfg = &dsi->phy_cfg; 662 int ret; 663 664 if (!dsi->lanes) { 665 DRM_DEV_ERROR(dev, "Need DSI lanes: %d\n", dsi->lanes); 666 return -EINVAL; 667 } 668 669 ret = phy_init(dsi->phy); 670 if (ret < 0) { 671 DRM_DEV_ERROR(dev, "Failed to init DSI phy: %d\n", ret); 672 return ret; 673 } 674 675 ret = phy_configure(dsi->phy, phy_cfg); 676 if (ret < 0) { 677 DRM_DEV_ERROR(dev, "Failed to configure DSI phy: %d\n", ret); 678 goto uninit_phy; 679 } 680 681 ret = clk_prepare_enable(dsi->tx_esc_clk); 682 if (ret < 0) { 683 DRM_DEV_ERROR(dsi->dev, "Failed to enable tx_esc clk: %d\n", 684 ret); 685 goto uninit_phy; 686 } 687 DRM_DEV_DEBUG_DRIVER(dsi->dev, "Enabled tx_esc clk @%lu Hz\n", 688 clk_get_rate(dsi->tx_esc_clk)); 689 690 ret = nwl_dsi_config_host(dsi); 691 if (ret < 0) { 692 DRM_DEV_ERROR(dev, "Failed to set up DSI: %d", ret); 693 goto disable_clock; 694 } 695 696 ret = nwl_dsi_config_dpi(dsi); 697 if (ret < 0) { 698 DRM_DEV_ERROR(dev, "Failed to set up DPI: %d", ret); 699 goto disable_clock; 700 } 701 702 ret = phy_power_on(dsi->phy); 703 if (ret < 0) { 704 DRM_DEV_ERROR(dev, "Failed to power on DPHY (%d)\n", ret); 705 goto disable_clock; 706 } 707 708 ret = nwl_dsi_init_interrupts(dsi); 709 if (ret < 0) 710 goto power_off_phy; 711 712 return ret; 713 714 power_off_phy: 715 phy_power_off(dsi->phy); 716 disable_clock: 717 clk_disable_unprepare(dsi->tx_esc_clk); 718 uninit_phy: 719 phy_exit(dsi->phy); 720 721 return ret; 722 } 723 724 static int nwl_dsi_disable(struct nwl_dsi *dsi) 725 { 726 struct device *dev = dsi->dev; 727 728 DRM_DEV_DEBUG_DRIVER(dev, "Disabling clocks and phy\n"); 729 730 phy_power_off(dsi->phy); 731 phy_exit(dsi->phy); 732 733 /* Disabling the clock before the phy breaks enabling dsi again */ 734 clk_disable_unprepare(dsi->tx_esc_clk); 735 736 return 0; 737 } 738 739 static void 740 nwl_dsi_bridge_atomic_disable(struct drm_bridge *bridge, 741 struct drm_bridge_state *old_bridge_state) 742 { 743 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 744 int ret; 745 746 nwl_dsi_disable(dsi); 747 748 ret = reset_control_assert(dsi->rst_dpi); 749 if (ret < 0) { 750 DRM_DEV_ERROR(dsi->dev, "Failed to assert DPI: %d\n", ret); 751 return; 752 } 753 ret = reset_control_assert(dsi->rst_byte); 754 if (ret < 0) { 755 DRM_DEV_ERROR(dsi->dev, "Failed to assert ESC: %d\n", ret); 756 return; 757 } 758 ret = reset_control_assert(dsi->rst_esc); 759 if (ret < 0) { 760 DRM_DEV_ERROR(dsi->dev, "Failed to assert BYTE: %d\n", ret); 761 return; 762 } 763 ret = reset_control_assert(dsi->rst_pclk); 764 if (ret < 0) { 765 DRM_DEV_ERROR(dsi->dev, "Failed to assert PCLK: %d\n", ret); 766 return; 767 } 768 769 clk_disable_unprepare(dsi->core_clk); 770 clk_disable_unprepare(dsi->lcdif_clk); 771 772 pm_runtime_put(dsi->dev); 773 } 774 775 static int nwl_dsi_get_dphy_params(struct nwl_dsi *dsi, 776 const struct drm_display_mode *mode, 777 union phy_configure_opts *phy_opts) 778 { 779 unsigned long rate; 780 int ret; 781 782 if (dsi->lanes < 1 || dsi->lanes > 4) 783 return -EINVAL; 784 785 /* 786 * So far the DPHY spec minimal timings work for both mixel 787 * dphy and nwl dsi host 788 */ 789 ret = phy_mipi_dphy_get_default_config(mode->clock * 1000, 790 mipi_dsi_pixel_format_to_bpp(dsi->format), dsi->lanes, 791 &phy_opts->mipi_dphy); 792 if (ret < 0) 793 return ret; 794 795 rate = clk_get_rate(dsi->tx_esc_clk); 796 DRM_DEV_DEBUG_DRIVER(dsi->dev, "LP clk is @%lu Hz\n", rate); 797 phy_opts->mipi_dphy.lp_clk_rate = rate; 798 799 return 0; 800 } 801 802 static enum drm_mode_status 803 nwl_dsi_bridge_mode_valid(struct drm_bridge *bridge, 804 const struct drm_display_info *info, 805 const struct drm_display_mode *mode) 806 { 807 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 808 int bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); 809 810 if (mode->clock * bpp > 15000000 * dsi->lanes) 811 return MODE_CLOCK_HIGH; 812 813 if (mode->clock * bpp < 80000 * dsi->lanes) 814 return MODE_CLOCK_LOW; 815 816 return MODE_OK; 817 } 818 819 static int nwl_dsi_bridge_atomic_check(struct drm_bridge *bridge, 820 struct drm_bridge_state *bridge_state, 821 struct drm_crtc_state *crtc_state, 822 struct drm_connector_state *conn_state) 823 { 824 struct drm_display_mode *adjusted_mode = &crtc_state->adjusted_mode; 825 826 /* At least LCDIF + NWL needs active high sync */ 827 adjusted_mode->flags |= (DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC); 828 adjusted_mode->flags &= ~(DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC); 829 830 /* 831 * Do a full modeset if crtc_state->active is changed to be true. 832 * This ensures our ->mode_set() is called to get the DSI controller 833 * and the PHY ready to send DCS commands, when only the connector's 834 * DPMS is brought out of "Off" status. 835 */ 836 if (crtc_state->active_changed && crtc_state->active) 837 crtc_state->mode_changed = true; 838 839 return 0; 840 } 841 842 static void 843 nwl_dsi_bridge_mode_set(struct drm_bridge *bridge, 844 const struct drm_display_mode *mode, 845 const struct drm_display_mode *adjusted_mode) 846 { 847 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 848 struct device *dev = dsi->dev; 849 union phy_configure_opts new_cfg; 850 unsigned long phy_ref_rate; 851 int ret; 852 853 ret = nwl_dsi_get_dphy_params(dsi, adjusted_mode, &new_cfg); 854 if (ret < 0) 855 return; 856 857 phy_ref_rate = clk_get_rate(dsi->phy_ref_clk); 858 DRM_DEV_DEBUG_DRIVER(dev, "PHY at ref rate: %lu\n", phy_ref_rate); 859 /* Save the new desired phy config */ 860 memcpy(&dsi->phy_cfg, &new_cfg, sizeof(new_cfg)); 861 862 memcpy(&dsi->mode, adjusted_mode, sizeof(dsi->mode)); 863 drm_mode_debug_printmodeline(adjusted_mode); 864 865 if (pm_runtime_resume_and_get(dev) < 0) 866 return; 867 868 if (clk_prepare_enable(dsi->lcdif_clk) < 0) 869 goto runtime_put; 870 if (clk_prepare_enable(dsi->core_clk) < 0) 871 goto runtime_put; 872 873 /* Step 1 from DSI reset-out instructions */ 874 ret = reset_control_deassert(dsi->rst_pclk); 875 if (ret < 0) { 876 DRM_DEV_ERROR(dev, "Failed to deassert PCLK: %d\n", ret); 877 goto runtime_put; 878 } 879 880 /* Step 2 from DSI reset-out instructions */ 881 nwl_dsi_mode_set(dsi); 882 883 /* Step 3 from DSI reset-out instructions */ 884 ret = reset_control_deassert(dsi->rst_esc); 885 if (ret < 0) { 886 DRM_DEV_ERROR(dev, "Failed to deassert ESC: %d\n", ret); 887 goto runtime_put; 888 } 889 ret = reset_control_deassert(dsi->rst_byte); 890 if (ret < 0) { 891 DRM_DEV_ERROR(dev, "Failed to deassert BYTE: %d\n", ret); 892 goto runtime_put; 893 } 894 895 return; 896 897 runtime_put: 898 pm_runtime_put_sync(dev); 899 } 900 901 static void 902 nwl_dsi_bridge_atomic_enable(struct drm_bridge *bridge, 903 struct drm_bridge_state *old_bridge_state) 904 { 905 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 906 int ret; 907 908 /* Step 5 from DSI reset-out instructions */ 909 ret = reset_control_deassert(dsi->rst_dpi); 910 if (ret < 0) 911 DRM_DEV_ERROR(dsi->dev, "Failed to deassert DPI: %d\n", ret); 912 } 913 914 static int nwl_dsi_bridge_attach(struct drm_bridge *bridge, 915 enum drm_bridge_attach_flags flags) 916 { 917 struct nwl_dsi *dsi = bridge_to_dsi(bridge); 918 struct drm_bridge *panel_bridge; 919 struct drm_panel *panel; 920 int ret; 921 922 ret = drm_of_find_panel_or_bridge(dsi->dev->of_node, 1, 0, &panel, 923 &panel_bridge); 924 if (ret) 925 return ret; 926 927 if (panel) { 928 panel_bridge = drm_panel_bridge_add(panel); 929 if (IS_ERR(panel_bridge)) 930 return PTR_ERR(panel_bridge); 931 } 932 933 if (!panel_bridge) 934 return -EPROBE_DEFER; 935 936 return drm_bridge_attach(bridge->encoder, panel_bridge, bridge, flags); 937 } 938 939 static void nwl_dsi_bridge_detach(struct drm_bridge *bridge) 940 { struct nwl_dsi *dsi = bridge_to_dsi(bridge); 941 942 drm_of_panel_bridge_remove(dsi->dev->of_node, 1, 0); 943 } 944 945 static u32 *nwl_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 946 struct drm_bridge_state *bridge_state, 947 struct drm_crtc_state *crtc_state, 948 struct drm_connector_state *conn_state, 949 u32 output_fmt, 950 unsigned int *num_input_fmts) 951 { 952 u32 *input_fmts, input_fmt; 953 954 *num_input_fmts = 0; 955 956 switch (output_fmt) { 957 /* If MEDIA_BUS_FMT_FIXED is tested, return default bus format */ 958 case MEDIA_BUS_FMT_FIXED: 959 input_fmt = MEDIA_BUS_FMT_RGB888_1X24; 960 break; 961 case MEDIA_BUS_FMT_RGB888_1X24: 962 case MEDIA_BUS_FMT_RGB666_1X18: 963 case MEDIA_BUS_FMT_RGB565_1X16: 964 input_fmt = output_fmt; 965 break; 966 default: 967 return NULL; 968 } 969 970 input_fmts = kcalloc(1, sizeof(*input_fmts), GFP_KERNEL); 971 if (!input_fmts) 972 return NULL; 973 input_fmts[0] = input_fmt; 974 *num_input_fmts = 1; 975 976 return input_fmts; 977 } 978 979 static const struct drm_bridge_funcs nwl_dsi_bridge_funcs = { 980 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 981 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 982 .atomic_reset = drm_atomic_helper_bridge_reset, 983 .atomic_check = nwl_dsi_bridge_atomic_check, 984 .atomic_enable = nwl_dsi_bridge_atomic_enable, 985 .atomic_disable = nwl_dsi_bridge_atomic_disable, 986 .atomic_get_input_bus_fmts = nwl_bridge_atomic_get_input_bus_fmts, 987 .mode_set = nwl_dsi_bridge_mode_set, 988 .mode_valid = nwl_dsi_bridge_mode_valid, 989 .attach = nwl_dsi_bridge_attach, 990 .detach = nwl_dsi_bridge_detach, 991 }; 992 993 static int nwl_dsi_parse_dt(struct nwl_dsi *dsi) 994 { 995 struct platform_device *pdev = to_platform_device(dsi->dev); 996 struct clk *clk; 997 void __iomem *base; 998 int ret; 999 1000 dsi->phy = devm_phy_get(dsi->dev, "dphy"); 1001 if (IS_ERR(dsi->phy)) { 1002 ret = PTR_ERR(dsi->phy); 1003 if (ret != -EPROBE_DEFER) 1004 DRM_DEV_ERROR(dsi->dev, "Could not get PHY: %d\n", ret); 1005 return ret; 1006 } 1007 1008 clk = devm_clk_get(dsi->dev, "lcdif"); 1009 if (IS_ERR(clk)) { 1010 ret = PTR_ERR(clk); 1011 DRM_DEV_ERROR(dsi->dev, "Failed to get lcdif clock: %d\n", 1012 ret); 1013 return ret; 1014 } 1015 dsi->lcdif_clk = clk; 1016 1017 clk = devm_clk_get(dsi->dev, "core"); 1018 if (IS_ERR(clk)) { 1019 ret = PTR_ERR(clk); 1020 DRM_DEV_ERROR(dsi->dev, "Failed to get core clock: %d\n", 1021 ret); 1022 return ret; 1023 } 1024 dsi->core_clk = clk; 1025 1026 clk = devm_clk_get(dsi->dev, "phy_ref"); 1027 if (IS_ERR(clk)) { 1028 ret = PTR_ERR(clk); 1029 DRM_DEV_ERROR(dsi->dev, "Failed to get phy_ref clock: %d\n", 1030 ret); 1031 return ret; 1032 } 1033 dsi->phy_ref_clk = clk; 1034 1035 clk = devm_clk_get(dsi->dev, "rx_esc"); 1036 if (IS_ERR(clk)) { 1037 ret = PTR_ERR(clk); 1038 DRM_DEV_ERROR(dsi->dev, "Failed to get rx_esc clock: %d\n", 1039 ret); 1040 return ret; 1041 } 1042 dsi->rx_esc_clk = clk; 1043 1044 clk = devm_clk_get(dsi->dev, "tx_esc"); 1045 if (IS_ERR(clk)) { 1046 ret = PTR_ERR(clk); 1047 DRM_DEV_ERROR(dsi->dev, "Failed to get tx_esc clock: %d\n", 1048 ret); 1049 return ret; 1050 } 1051 dsi->tx_esc_clk = clk; 1052 1053 dsi->mux = devm_mux_control_get(dsi->dev, NULL); 1054 if (IS_ERR(dsi->mux)) { 1055 ret = PTR_ERR(dsi->mux); 1056 if (ret != -EPROBE_DEFER) 1057 DRM_DEV_ERROR(dsi->dev, "Failed to get mux: %d\n", ret); 1058 return ret; 1059 } 1060 1061 base = devm_platform_ioremap_resource(pdev, 0); 1062 if (IS_ERR(base)) 1063 return PTR_ERR(base); 1064 1065 dsi->regmap = 1066 devm_regmap_init_mmio(dsi->dev, base, &nwl_dsi_regmap_config); 1067 if (IS_ERR(dsi->regmap)) { 1068 ret = PTR_ERR(dsi->regmap); 1069 DRM_DEV_ERROR(dsi->dev, "Failed to create NWL DSI regmap: %d\n", 1070 ret); 1071 return ret; 1072 } 1073 1074 dsi->irq = platform_get_irq(pdev, 0); 1075 if (dsi->irq < 0) { 1076 DRM_DEV_ERROR(dsi->dev, "Failed to get device IRQ: %d\n", 1077 dsi->irq); 1078 return dsi->irq; 1079 } 1080 1081 dsi->rst_pclk = devm_reset_control_get_exclusive(dsi->dev, "pclk"); 1082 if (IS_ERR(dsi->rst_pclk)) { 1083 DRM_DEV_ERROR(dsi->dev, "Failed to get pclk reset: %ld\n", 1084 PTR_ERR(dsi->rst_pclk)); 1085 return PTR_ERR(dsi->rst_pclk); 1086 } 1087 dsi->rst_byte = devm_reset_control_get_exclusive(dsi->dev, "byte"); 1088 if (IS_ERR(dsi->rst_byte)) { 1089 DRM_DEV_ERROR(dsi->dev, "Failed to get byte reset: %ld\n", 1090 PTR_ERR(dsi->rst_byte)); 1091 return PTR_ERR(dsi->rst_byte); 1092 } 1093 dsi->rst_esc = devm_reset_control_get_exclusive(dsi->dev, "esc"); 1094 if (IS_ERR(dsi->rst_esc)) { 1095 DRM_DEV_ERROR(dsi->dev, "Failed to get esc reset: %ld\n", 1096 PTR_ERR(dsi->rst_esc)); 1097 return PTR_ERR(dsi->rst_esc); 1098 } 1099 dsi->rst_dpi = devm_reset_control_get_exclusive(dsi->dev, "dpi"); 1100 if (IS_ERR(dsi->rst_dpi)) { 1101 DRM_DEV_ERROR(dsi->dev, "Failed to get dpi reset: %ld\n", 1102 PTR_ERR(dsi->rst_dpi)); 1103 return PTR_ERR(dsi->rst_dpi); 1104 } 1105 return 0; 1106 } 1107 1108 static int nwl_dsi_select_input(struct nwl_dsi *dsi) 1109 { 1110 struct device_node *remote; 1111 u32 use_dcss = 1; 1112 int ret; 1113 1114 remote = of_graph_get_remote_node(dsi->dev->of_node, 0, 1115 NWL_DSI_ENDPOINT_LCDIF); 1116 if (remote) { 1117 use_dcss = 0; 1118 } else { 1119 remote = of_graph_get_remote_node(dsi->dev->of_node, 0, 1120 NWL_DSI_ENDPOINT_DCSS); 1121 if (!remote) { 1122 DRM_DEV_ERROR(dsi->dev, 1123 "No valid input endpoint found\n"); 1124 return -EINVAL; 1125 } 1126 } 1127 1128 DRM_DEV_INFO(dsi->dev, "Using %s as input source\n", 1129 (use_dcss) ? "DCSS" : "LCDIF"); 1130 ret = mux_control_try_select(dsi->mux, use_dcss); 1131 if (ret < 0) 1132 DRM_DEV_ERROR(dsi->dev, "Failed to select input: %d\n", ret); 1133 1134 of_node_put(remote); 1135 return ret; 1136 } 1137 1138 static int nwl_dsi_deselect_input(struct nwl_dsi *dsi) 1139 { 1140 int ret; 1141 1142 ret = mux_control_deselect(dsi->mux); 1143 if (ret < 0) 1144 DRM_DEV_ERROR(dsi->dev, "Failed to deselect input: %d\n", ret); 1145 1146 return ret; 1147 } 1148 1149 static const struct drm_bridge_timings nwl_dsi_timings = { 1150 .input_bus_flags = DRM_BUS_FLAG_DE_LOW, 1151 }; 1152 1153 static const struct of_device_id nwl_dsi_dt_ids[] = { 1154 { .compatible = "fsl,imx8mq-nwl-dsi", }, 1155 { /* sentinel */ } 1156 }; 1157 MODULE_DEVICE_TABLE(of, nwl_dsi_dt_ids); 1158 1159 static const struct soc_device_attribute nwl_dsi_quirks_match[] = { 1160 { .soc_id = "i.MX8MQ", .revision = "2.0", 1161 .data = (void *)E11418_HS_MODE_QUIRK }, 1162 { /* sentinel. */ }, 1163 }; 1164 1165 static int nwl_dsi_probe(struct platform_device *pdev) 1166 { 1167 struct device *dev = &pdev->dev; 1168 const struct soc_device_attribute *attr; 1169 struct nwl_dsi *dsi; 1170 int ret; 1171 1172 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1173 if (!dsi) 1174 return -ENOMEM; 1175 1176 dsi->dev = dev; 1177 1178 ret = nwl_dsi_parse_dt(dsi); 1179 if (ret) 1180 return ret; 1181 1182 ret = devm_request_irq(dev, dsi->irq, nwl_dsi_irq_handler, 0, 1183 dev_name(dev), dsi); 1184 if (ret < 0) { 1185 DRM_DEV_ERROR(dev, "Failed to request IRQ %d: %d\n", dsi->irq, 1186 ret); 1187 return ret; 1188 } 1189 1190 dsi->dsi_host.ops = &nwl_dsi_host_ops; 1191 dsi->dsi_host.dev = dev; 1192 ret = mipi_dsi_host_register(&dsi->dsi_host); 1193 if (ret) { 1194 DRM_DEV_ERROR(dev, "Failed to register MIPI host: %d\n", ret); 1195 return ret; 1196 } 1197 1198 attr = soc_device_match(nwl_dsi_quirks_match); 1199 if (attr) 1200 dsi->quirks = (uintptr_t)attr->data; 1201 1202 dsi->bridge.driver_private = dsi; 1203 dsi->bridge.funcs = &nwl_dsi_bridge_funcs; 1204 dsi->bridge.of_node = dev->of_node; 1205 dsi->bridge.timings = &nwl_dsi_timings; 1206 1207 dev_set_drvdata(dev, dsi); 1208 pm_runtime_enable(dev); 1209 1210 ret = nwl_dsi_select_input(dsi); 1211 if (ret < 0) { 1212 pm_runtime_disable(dev); 1213 mipi_dsi_host_unregister(&dsi->dsi_host); 1214 return ret; 1215 } 1216 1217 drm_bridge_add(&dsi->bridge); 1218 return 0; 1219 } 1220 1221 static int nwl_dsi_remove(struct platform_device *pdev) 1222 { 1223 struct nwl_dsi *dsi = platform_get_drvdata(pdev); 1224 1225 nwl_dsi_deselect_input(dsi); 1226 mipi_dsi_host_unregister(&dsi->dsi_host); 1227 drm_bridge_remove(&dsi->bridge); 1228 pm_runtime_disable(&pdev->dev); 1229 return 0; 1230 } 1231 1232 static struct platform_driver nwl_dsi_driver = { 1233 .probe = nwl_dsi_probe, 1234 .remove = nwl_dsi_remove, 1235 .driver = { 1236 .of_match_table = nwl_dsi_dt_ids, 1237 .name = DRV_NAME, 1238 }, 1239 }; 1240 1241 module_platform_driver(nwl_dsi_driver); 1242 1243 MODULE_AUTHOR("NXP Semiconductor"); 1244 MODULE_AUTHOR("Purism SPC"); 1245 MODULE_DESCRIPTION("Northwest Logic MIPI-DSI driver"); 1246 MODULE_LICENSE("GPL"); /* GPLv2 or later */ 1247