1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020 BayLibre, SAS 4 * Author: Phong LE <ple@baylibre.com> 5 * Copyright (C) 2018-2019, Artem Mygaiev 6 * Copyright (C) 2017, Fresco Logic, Incorporated. 7 * 8 */ 9 10 #include <linux/media-bus-format.h> 11 #include <linux/module.h> 12 #include <linux/device.h> 13 #include <linux/interrupt.h> 14 #include <linux/i2c.h> 15 #include <linux/bitfield.h> 16 #include <linux/property.h> 17 #include <linux/regmap.h> 18 #include <linux/of_graph.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/regulator/consumer.h> 22 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_edid.h> 26 #include <drm/drm_modes.h> 27 #include <drm/drm_print.h> 28 #include <drm/drm_probe_helper.h> 29 30 #include <sound/hdmi-codec.h> 31 32 #define IT66121_VENDOR_ID0_REG 0x00 33 #define IT66121_VENDOR_ID1_REG 0x01 34 #define IT66121_DEVICE_ID0_REG 0x02 35 #define IT66121_DEVICE_ID1_REG 0x03 36 37 #define IT66121_REVISION_MASK GENMASK(7, 4) 38 #define IT66121_DEVICE_ID1_MASK GENMASK(3, 0) 39 40 #define IT66121_MASTER_SEL_REG 0x10 41 #define IT66121_MASTER_SEL_HOST BIT(0) 42 43 #define IT66121_AFE_DRV_REG 0x61 44 #define IT66121_AFE_DRV_RST BIT(4) 45 #define IT66121_AFE_DRV_PWD BIT(5) 46 47 #define IT66121_INPUT_MODE_REG 0x70 48 #define IT66121_INPUT_MODE_RGB (0 << 6) 49 #define IT66121_INPUT_MODE_YUV422 BIT(6) 50 #define IT66121_INPUT_MODE_YUV444 (2 << 6) 51 #define IT66121_INPUT_MODE_CCIR656 BIT(4) 52 #define IT66121_INPUT_MODE_SYNCEMB BIT(3) 53 #define IT66121_INPUT_MODE_DDR BIT(2) 54 55 #define IT66121_INPUT_CSC_REG 0x72 56 #define IT66121_INPUT_CSC_ENDITHER BIT(7) 57 #define IT66121_INPUT_CSC_ENUDFILTER BIT(6) 58 #define IT66121_INPUT_CSC_DNFREE_GO BIT(5) 59 #define IT66121_INPUT_CSC_RGB_TO_YUV 0x02 60 #define IT66121_INPUT_CSC_YUV_TO_RGB 0x03 61 #define IT66121_INPUT_CSC_NO_CONV 0x00 62 63 #define IT66121_AFE_XP_REG 0x62 64 #define IT66121_AFE_XP_GAINBIT BIT(7) 65 #define IT66121_AFE_XP_PWDPLL BIT(6) 66 #define IT66121_AFE_XP_ENI BIT(5) 67 #define IT66121_AFE_XP_ENO BIT(4) 68 #define IT66121_AFE_XP_RESETB BIT(3) 69 #define IT66121_AFE_XP_PWDI BIT(2) 70 #define IT6610_AFE_XP_BYPASS BIT(0) 71 72 #define IT66121_AFE_IP_REG 0x64 73 #define IT66121_AFE_IP_GAINBIT BIT(7) 74 #define IT66121_AFE_IP_PWDPLL BIT(6) 75 #define IT66121_AFE_IP_CKSEL_05 (0 << 4) 76 #define IT66121_AFE_IP_CKSEL_1 BIT(4) 77 #define IT66121_AFE_IP_CKSEL_2 (2 << 4) 78 #define IT66121_AFE_IP_CKSEL_2OR4 (3 << 4) 79 #define IT66121_AFE_IP_ER0 BIT(3) 80 #define IT66121_AFE_IP_RESETB BIT(2) 81 #define IT66121_AFE_IP_ENC BIT(1) 82 #define IT66121_AFE_IP_EC1 BIT(0) 83 84 #define IT66121_AFE_XP_EC1_REG 0x68 85 #define IT66121_AFE_XP_EC1_LOWCLK BIT(4) 86 87 #define IT66121_SW_RST_REG 0x04 88 #define IT66121_SW_RST_REF BIT(5) 89 #define IT66121_SW_RST_AREF BIT(4) 90 #define IT66121_SW_RST_VID BIT(3) 91 #define IT66121_SW_RST_AUD BIT(2) 92 #define IT66121_SW_RST_HDCP BIT(0) 93 94 #define IT66121_DDC_COMMAND_REG 0x15 95 #define IT66121_DDC_COMMAND_BURST_READ 0x0 96 #define IT66121_DDC_COMMAND_EDID_READ 0x3 97 #define IT66121_DDC_COMMAND_FIFO_CLR 0x9 98 #define IT66121_DDC_COMMAND_SCL_PULSE 0xA 99 #define IT66121_DDC_COMMAND_ABORT 0xF 100 101 #define IT66121_HDCP_REG 0x20 102 #define IT66121_HDCP_CPDESIRED BIT(0) 103 #define IT66121_HDCP_EN1P1FEAT BIT(1) 104 105 #define IT66121_INT_STATUS1_REG 0x06 106 #define IT66121_INT_STATUS1_AUD_OVF BIT(7) 107 #define IT66121_INT_STATUS1_DDC_NOACK BIT(5) 108 #define IT66121_INT_STATUS1_DDC_FIFOERR BIT(4) 109 #define IT66121_INT_STATUS1_DDC_BUSHANG BIT(2) 110 #define IT66121_INT_STATUS1_RX_SENS_STATUS BIT(1) 111 #define IT66121_INT_STATUS1_HPD_STATUS BIT(0) 112 113 #define IT66121_DDC_HEADER_REG 0x11 114 #define IT66121_DDC_HEADER_HDCP 0x74 115 #define IT66121_DDC_HEADER_EDID 0xA0 116 117 #define IT66121_DDC_OFFSET_REG 0x12 118 #define IT66121_DDC_BYTE_REG 0x13 119 #define IT66121_DDC_SEGMENT_REG 0x14 120 #define IT66121_DDC_RD_FIFO_REG 0x17 121 122 #define IT66121_CLK_BANK_REG 0x0F 123 #define IT66121_CLK_BANK_PWROFF_RCLK BIT(6) 124 #define IT66121_CLK_BANK_PWROFF_ACLK BIT(5) 125 #define IT66121_CLK_BANK_PWROFF_TXCLK BIT(4) 126 #define IT66121_CLK_BANK_PWROFF_CRCLK BIT(3) 127 #define IT66121_CLK_BANK_0 0 128 #define IT66121_CLK_BANK_1 1 129 130 #define IT66121_INT_REG 0x05 131 #define IT66121_INT_ACTIVE_HIGH BIT(7) 132 #define IT66121_INT_OPEN_DRAIN BIT(6) 133 #define IT66121_INT_TX_CLK_OFF BIT(0) 134 135 #define IT66121_INT_MASK1_REG 0x09 136 #define IT66121_INT_MASK1_AUD_OVF BIT(7) 137 #define IT66121_INT_MASK1_DDC_NOACK BIT(5) 138 #define IT66121_INT_MASK1_DDC_FIFOERR BIT(4) 139 #define IT66121_INT_MASK1_DDC_BUSHANG BIT(2) 140 #define IT66121_INT_MASK1_RX_SENS BIT(1) 141 #define IT66121_INT_MASK1_HPD BIT(0) 142 143 #define IT66121_INT_CLR1_REG 0x0C 144 #define IT66121_INT_CLR1_PKTACP BIT(7) 145 #define IT66121_INT_CLR1_PKTNULL BIT(6) 146 #define IT66121_INT_CLR1_PKTGEN BIT(5) 147 #define IT66121_INT_CLR1_KSVLISTCHK BIT(4) 148 #define IT66121_INT_CLR1_AUTHDONE BIT(3) 149 #define IT66121_INT_CLR1_AUTHFAIL BIT(2) 150 #define IT66121_INT_CLR1_RX_SENS BIT(1) 151 #define IT66121_INT_CLR1_HPD BIT(0) 152 153 #define IT66121_AV_MUTE_REG 0xC1 154 #define IT66121_AV_MUTE_ON BIT(0) 155 #define IT66121_AV_MUTE_BLUESCR BIT(1) 156 157 #define IT66121_PKT_CTS_CTRL_REG 0xC5 158 #define IT66121_PKT_CTS_CTRL_SEL BIT(1) 159 160 #define IT66121_PKT_GEN_CTRL_REG 0xC6 161 #define IT66121_PKT_GEN_CTRL_ON BIT(0) 162 #define IT66121_PKT_GEN_CTRL_RPT BIT(1) 163 164 #define IT66121_AVIINFO_DB1_REG 0x158 165 #define IT66121_AVIINFO_DB2_REG 0x159 166 #define IT66121_AVIINFO_DB3_REG 0x15A 167 #define IT66121_AVIINFO_DB4_REG 0x15B 168 #define IT66121_AVIINFO_DB5_REG 0x15C 169 #define IT66121_AVIINFO_CSUM_REG 0x15D 170 #define IT66121_AVIINFO_DB6_REG 0x15E 171 #define IT66121_AVIINFO_DB7_REG 0x15F 172 #define IT66121_AVIINFO_DB8_REG 0x160 173 #define IT66121_AVIINFO_DB9_REG 0x161 174 #define IT66121_AVIINFO_DB10_REG 0x162 175 #define IT66121_AVIINFO_DB11_REG 0x163 176 #define IT66121_AVIINFO_DB12_REG 0x164 177 #define IT66121_AVIINFO_DB13_REG 0x165 178 179 #define IT66121_AVI_INFO_PKT_REG 0xCD 180 #define IT66121_AVI_INFO_PKT_ON BIT(0) 181 #define IT66121_AVI_INFO_PKT_RPT BIT(1) 182 183 #define IT66121_HDMI_MODE_REG 0xC0 184 #define IT66121_HDMI_MODE_HDMI BIT(0) 185 186 #define IT66121_SYS_STATUS_REG 0x0E 187 #define IT66121_SYS_STATUS_ACTIVE_IRQ BIT(7) 188 #define IT66121_SYS_STATUS_HPDETECT BIT(6) 189 #define IT66121_SYS_STATUS_SENDECTECT BIT(5) 190 #define IT66121_SYS_STATUS_VID_STABLE BIT(4) 191 #define IT66121_SYS_STATUS_AUD_CTS_CLR BIT(1) 192 #define IT66121_SYS_STATUS_CLEAR_IRQ BIT(0) 193 194 #define IT66121_DDC_STATUS_REG 0x16 195 #define IT66121_DDC_STATUS_TX_DONE BIT(7) 196 #define IT66121_DDC_STATUS_ACTIVE BIT(6) 197 #define IT66121_DDC_STATUS_NOACK BIT(5) 198 #define IT66121_DDC_STATUS_WAIT_BUS BIT(4) 199 #define IT66121_DDC_STATUS_ARBI_LOSE BIT(3) 200 #define IT66121_DDC_STATUS_FIFO_FULL BIT(2) 201 #define IT66121_DDC_STATUS_FIFO_EMPTY BIT(1) 202 #define IT66121_DDC_STATUS_FIFO_VALID BIT(0) 203 204 #define IT66121_EDID_SLEEP_US 20000 205 #define IT66121_EDID_TIMEOUT_US 200000 206 #define IT66121_EDID_FIFO_SIZE 32 207 208 #define IT66121_CLK_CTRL0_REG 0x58 209 #define IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING BIT(4) 210 #define IT66121_CLK_CTRL0_EXT_MCLK_MASK GENMASK(3, 2) 211 #define IT66121_CLK_CTRL0_EXT_MCLK_128FS (0 << 2) 212 #define IT66121_CLK_CTRL0_EXT_MCLK_256FS BIT(2) 213 #define IT66121_CLK_CTRL0_EXT_MCLK_512FS (2 << 2) 214 #define IT66121_CLK_CTRL0_EXT_MCLK_1024FS (3 << 2) 215 #define IT66121_CLK_CTRL0_AUTO_IPCLK BIT(0) 216 #define IT66121_CLK_STATUS1_REG 0x5E 217 #define IT66121_CLK_STATUS2_REG 0x5F 218 219 #define IT66121_AUD_CTRL0_REG 0xE0 220 #define IT66121_AUD_SWL (3 << 6) 221 #define IT66121_AUD_16BIT (0 << 6) 222 #define IT66121_AUD_18BIT BIT(6) 223 #define IT66121_AUD_20BIT (2 << 6) 224 #define IT66121_AUD_24BIT (3 << 6) 225 #define IT66121_AUD_SPDIFTC BIT(5) 226 #define IT66121_AUD_SPDIF BIT(4) 227 #define IT66121_AUD_I2S (0 << 4) 228 #define IT66121_AUD_EN_I2S3 BIT(3) 229 #define IT66121_AUD_EN_I2S2 BIT(2) 230 #define IT66121_AUD_EN_I2S1 BIT(1) 231 #define IT66121_AUD_EN_I2S0 BIT(0) 232 #define IT66121_AUD_CTRL0_AUD_SEL BIT(4) 233 234 #define IT66121_AUD_CTRL1_REG 0xE1 235 #define IT66121_AUD_FIFOMAP_REG 0xE2 236 #define IT66121_AUD_CTRL3_REG 0xE3 237 #define IT66121_AUD_SRCVALID_FLAT_REG 0xE4 238 #define IT66121_AUD_FLAT_SRC0 BIT(4) 239 #define IT66121_AUD_FLAT_SRC1 BIT(5) 240 #define IT66121_AUD_FLAT_SRC2 BIT(6) 241 #define IT66121_AUD_FLAT_SRC3 BIT(7) 242 #define IT66121_AUD_HDAUDIO_REG 0xE5 243 244 #define IT66121_AUD_PKT_CTS0_REG 0x130 245 #define IT66121_AUD_PKT_CTS1_REG 0x131 246 #define IT66121_AUD_PKT_CTS2_REG 0x132 247 #define IT66121_AUD_PKT_N0_REG 0x133 248 #define IT66121_AUD_PKT_N1_REG 0x134 249 #define IT66121_AUD_PKT_N2_REG 0x135 250 251 #define IT66121_AUD_CHST_MODE_REG 0x191 252 #define IT66121_AUD_CHST_CAT_REG 0x192 253 #define IT66121_AUD_CHST_SRCNUM_REG 0x193 254 #define IT66121_AUD_CHST_CHTNUM_REG 0x194 255 #define IT66121_AUD_CHST_CA_FS_REG 0x198 256 #define IT66121_AUD_CHST_OFS_WL_REG 0x199 257 258 #define IT66121_AUD_PKT_CTS_CNT0_REG 0x1A0 259 #define IT66121_AUD_PKT_CTS_CNT1_REG 0x1A1 260 #define IT66121_AUD_PKT_CTS_CNT2_REG 0x1A2 261 262 #define IT66121_AUD_FS_22P05K 0x4 263 #define IT66121_AUD_FS_44P1K 0x0 264 #define IT66121_AUD_FS_88P2K 0x8 265 #define IT66121_AUD_FS_176P4K 0xC 266 #define IT66121_AUD_FS_24K 0x6 267 #define IT66121_AUD_FS_48K 0x2 268 #define IT66121_AUD_FS_96K 0xA 269 #define IT66121_AUD_FS_192K 0xE 270 #define IT66121_AUD_FS_768K 0x9 271 #define IT66121_AUD_FS_32K 0x3 272 #define IT66121_AUD_FS_OTHER 0x1 273 274 #define IT66121_AUD_SWL_21BIT 0xD 275 #define IT66121_AUD_SWL_24BIT 0xB 276 #define IT66121_AUD_SWL_23BIT 0x9 277 #define IT66121_AUD_SWL_22BIT 0x5 278 #define IT66121_AUD_SWL_20BIT 0x3 279 #define IT66121_AUD_SWL_17BIT 0xC 280 #define IT66121_AUD_SWL_19BIT 0x8 281 #define IT66121_AUD_SWL_18BIT 0x4 282 #define IT66121_AUD_SWL_16BIT 0x2 283 #define IT66121_AUD_SWL_NOT_INDICATED 0x0 284 285 #define IT66121_AFE_CLK_HIGH 80000 /* Khz */ 286 287 enum chip_id { 288 ID_IT6610, 289 ID_IT66121, 290 }; 291 292 struct it66121_chip_info { 293 enum chip_id id; 294 u16 vid, pid; 295 }; 296 297 struct it66121_ctx { 298 struct regmap *regmap; 299 struct drm_bridge bridge; 300 struct drm_bridge *next_bridge; 301 struct drm_connector *connector; 302 struct device *dev; 303 struct gpio_desc *gpio_reset; 304 struct i2c_client *client; 305 u32 bus_width; 306 struct mutex lock; /* Protects fields below and device registers */ 307 struct hdmi_avi_infoframe hdmi_avi_infoframe; 308 struct { 309 struct platform_device *pdev; 310 u8 ch_enable; 311 u8 fs; 312 u8 swl; 313 bool auto_cts; 314 } audio; 315 const struct it66121_chip_info *info; 316 }; 317 318 static const struct regmap_range_cfg it66121_regmap_banks[] = { 319 { 320 .name = "it66121", 321 .range_min = 0x00, 322 .range_max = 0x1FF, 323 .selector_reg = IT66121_CLK_BANK_REG, 324 .selector_mask = 0x1, 325 .selector_shift = 0, 326 .window_start = 0x00, 327 .window_len = 0x100, 328 }, 329 }; 330 331 static const struct regmap_config it66121_regmap_config = { 332 .val_bits = 8, 333 .reg_bits = 8, 334 .max_register = 0x1FF, 335 .ranges = it66121_regmap_banks, 336 .num_ranges = ARRAY_SIZE(it66121_regmap_banks), 337 }; 338 339 static void it66121_hw_reset(struct it66121_ctx *ctx) 340 { 341 gpiod_set_value(ctx->gpio_reset, 1); 342 msleep(20); 343 gpiod_set_value(ctx->gpio_reset, 0); 344 } 345 346 static inline int it66121_preamble_ddc(struct it66121_ctx *ctx) 347 { 348 return regmap_write(ctx->regmap, IT66121_MASTER_SEL_REG, IT66121_MASTER_SEL_HOST); 349 } 350 351 static inline int it66121_fire_afe(struct it66121_ctx *ctx) 352 { 353 return regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 0); 354 } 355 356 /* TOFIX: Handle YCbCr Input & Output */ 357 static int it66121_configure_input(struct it66121_ctx *ctx) 358 { 359 int ret; 360 u8 mode = IT66121_INPUT_MODE_RGB; 361 362 if (ctx->bus_width == 12) 363 mode |= IT66121_INPUT_MODE_DDR; 364 365 ret = regmap_write(ctx->regmap, IT66121_INPUT_MODE_REG, mode); 366 if (ret) 367 return ret; 368 369 return regmap_write(ctx->regmap, IT66121_INPUT_CSC_REG, IT66121_INPUT_CSC_NO_CONV); 370 } 371 372 /** 373 * it66121_configure_afe() - Configure the analog front end 374 * @ctx: it66121_ctx object 375 * @mode: mode to configure 376 * 377 * RETURNS: 378 * zero if success, a negative error code otherwise. 379 */ 380 static int it66121_configure_afe(struct it66121_ctx *ctx, 381 const struct drm_display_mode *mode) 382 { 383 int ret; 384 385 ret = regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 386 IT66121_AFE_DRV_RST); 387 if (ret) 388 return ret; 389 390 if (mode->clock > IT66121_AFE_CLK_HIGH) { 391 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 392 IT66121_AFE_XP_GAINBIT | 393 IT66121_AFE_XP_ENO, 394 IT66121_AFE_XP_GAINBIT); 395 if (ret) 396 return ret; 397 398 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 399 IT66121_AFE_IP_GAINBIT | 400 IT66121_AFE_IP_ER0, 401 IT66121_AFE_IP_GAINBIT); 402 if (ret) 403 return ret; 404 405 if (ctx->info->id == ID_IT66121) { 406 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 407 IT66121_AFE_IP_EC1, 0); 408 if (ret) 409 return ret; 410 411 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG, 412 IT66121_AFE_XP_EC1_LOWCLK, 0x80); 413 if (ret) 414 return ret; 415 } 416 } else { 417 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 418 IT66121_AFE_XP_GAINBIT | 419 IT66121_AFE_XP_ENO, 420 IT66121_AFE_XP_ENO); 421 if (ret) 422 return ret; 423 424 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 425 IT66121_AFE_IP_GAINBIT | 426 IT66121_AFE_IP_ER0, 427 IT66121_AFE_IP_ER0); 428 if (ret) 429 return ret; 430 431 if (ctx->info->id == ID_IT66121) { 432 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 433 IT66121_AFE_IP_EC1, 434 IT66121_AFE_IP_EC1); 435 if (ret) 436 return ret; 437 438 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG, 439 IT66121_AFE_XP_EC1_LOWCLK, 440 IT66121_AFE_XP_EC1_LOWCLK); 441 if (ret) 442 return ret; 443 } 444 } 445 446 /* Clear reset flags */ 447 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 448 IT66121_SW_RST_REF | IT66121_SW_RST_VID, 0); 449 if (ret) 450 return ret; 451 452 if (ctx->info->id == ID_IT6610) { 453 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 454 IT6610_AFE_XP_BYPASS, 455 IT6610_AFE_XP_BYPASS); 456 if (ret) 457 return ret; 458 } 459 460 return it66121_fire_afe(ctx); 461 } 462 463 static inline int it66121_wait_ddc_ready(struct it66121_ctx *ctx) 464 { 465 int ret, val; 466 u32 error = IT66121_DDC_STATUS_NOACK | IT66121_DDC_STATUS_WAIT_BUS | 467 IT66121_DDC_STATUS_ARBI_LOSE; 468 u32 done = IT66121_DDC_STATUS_TX_DONE; 469 470 ret = regmap_read_poll_timeout(ctx->regmap, IT66121_DDC_STATUS_REG, val, 471 val & (error | done), IT66121_EDID_SLEEP_US, 472 IT66121_EDID_TIMEOUT_US); 473 if (ret) 474 return ret; 475 476 if (val & error) 477 return -EAGAIN; 478 479 return 0; 480 } 481 482 static int it66121_abort_ddc_ops(struct it66121_ctx *ctx) 483 { 484 int ret; 485 unsigned int swreset, cpdesire; 486 487 ret = regmap_read(ctx->regmap, IT66121_SW_RST_REG, &swreset); 488 if (ret) 489 return ret; 490 491 ret = regmap_read(ctx->regmap, IT66121_HDCP_REG, &cpdesire); 492 if (ret) 493 return ret; 494 495 ret = regmap_write(ctx->regmap, IT66121_HDCP_REG, 496 cpdesire & (~IT66121_HDCP_CPDESIRED & 0xFF)); 497 if (ret) 498 return ret; 499 500 ret = regmap_write(ctx->regmap, IT66121_SW_RST_REG, 501 (swreset | IT66121_SW_RST_HDCP)); 502 if (ret) 503 return ret; 504 505 ret = it66121_preamble_ddc(ctx); 506 if (ret) 507 return ret; 508 509 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 510 IT66121_DDC_COMMAND_ABORT); 511 if (ret) 512 return ret; 513 514 return it66121_wait_ddc_ready(ctx); 515 } 516 517 static int it66121_get_edid_block(void *context, u8 *buf, 518 unsigned int block, size_t len) 519 { 520 struct it66121_ctx *ctx = context; 521 int remain = len; 522 int offset = 0; 523 int ret, cnt; 524 525 offset = (block % 2) * len; 526 block = block / 2; 527 528 while (remain > 0) { 529 cnt = (remain > IT66121_EDID_FIFO_SIZE) ? 530 IT66121_EDID_FIFO_SIZE : remain; 531 532 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 533 IT66121_DDC_COMMAND_FIFO_CLR); 534 if (ret) 535 return ret; 536 537 ret = it66121_wait_ddc_ready(ctx); 538 if (ret) 539 return ret; 540 541 ret = regmap_write(ctx->regmap, IT66121_DDC_OFFSET_REG, offset); 542 if (ret) 543 return ret; 544 545 ret = regmap_write(ctx->regmap, IT66121_DDC_BYTE_REG, cnt); 546 if (ret) 547 return ret; 548 549 ret = regmap_write(ctx->regmap, IT66121_DDC_SEGMENT_REG, block); 550 if (ret) 551 return ret; 552 553 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 554 IT66121_DDC_COMMAND_EDID_READ); 555 if (ret) 556 return ret; 557 558 offset += cnt; 559 remain -= cnt; 560 561 ret = it66121_wait_ddc_ready(ctx); 562 if (ret) { 563 it66121_abort_ddc_ops(ctx); 564 return ret; 565 } 566 567 ret = regmap_noinc_read(ctx->regmap, IT66121_DDC_RD_FIFO_REG, 568 buf, cnt); 569 if (ret) 570 return ret; 571 572 buf += cnt; 573 } 574 575 return 0; 576 } 577 578 static bool it66121_is_hpd_detect(struct it66121_ctx *ctx) 579 { 580 int val; 581 582 if (regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val)) 583 return false; 584 585 return val & IT66121_SYS_STATUS_HPDETECT; 586 } 587 588 static int it66121_bridge_attach(struct drm_bridge *bridge, 589 enum drm_bridge_attach_flags flags) 590 { 591 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 592 int ret; 593 594 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 595 return -EINVAL; 596 597 ret = drm_bridge_attach(bridge->encoder, ctx->next_bridge, bridge, flags); 598 if (ret) 599 return ret; 600 601 if (ctx->info->id == ID_IT66121) { 602 ret = regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, 603 IT66121_CLK_BANK_PWROFF_RCLK, 0); 604 if (ret) 605 return ret; 606 } 607 608 ret = regmap_write_bits(ctx->regmap, IT66121_INT_REG, 609 IT66121_INT_TX_CLK_OFF, 0); 610 if (ret) 611 return ret; 612 613 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG, 614 IT66121_AFE_DRV_PWD, 0); 615 if (ret) 616 return ret; 617 618 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 619 IT66121_AFE_XP_PWDI | IT66121_AFE_XP_PWDPLL, 0); 620 if (ret) 621 return ret; 622 623 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 624 IT66121_AFE_IP_PWDPLL, 0); 625 if (ret) 626 return ret; 627 628 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG, 629 IT66121_AFE_DRV_RST, 0); 630 if (ret) 631 return ret; 632 633 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 634 IT66121_AFE_XP_RESETB, IT66121_AFE_XP_RESETB); 635 if (ret) 636 return ret; 637 638 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 639 IT66121_AFE_IP_RESETB, IT66121_AFE_IP_RESETB); 640 if (ret) 641 return ret; 642 643 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 644 IT66121_SW_RST_REF, 645 IT66121_SW_RST_REF); 646 if (ret) 647 return ret; 648 649 /* Per programming manual, sleep here for bridge to settle */ 650 msleep(50); 651 652 return 0; 653 } 654 655 static int it66121_set_mute(struct it66121_ctx *ctx, bool mute) 656 { 657 int ret; 658 unsigned int val = 0; 659 660 if (mute) 661 val = IT66121_AV_MUTE_ON; 662 663 ret = regmap_write_bits(ctx->regmap, IT66121_AV_MUTE_REG, IT66121_AV_MUTE_ON, val); 664 if (ret) 665 return ret; 666 667 return regmap_write(ctx->regmap, IT66121_PKT_GEN_CTRL_REG, 668 IT66121_PKT_GEN_CTRL_ON | IT66121_PKT_GEN_CTRL_RPT); 669 } 670 671 #define MAX_OUTPUT_SEL_FORMATS 1 672 673 static u32 *it66121_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 674 struct drm_bridge_state *bridge_state, 675 struct drm_crtc_state *crtc_state, 676 struct drm_connector_state *conn_state, 677 unsigned int *num_output_fmts) 678 { 679 u32 *output_fmts; 680 681 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), 682 GFP_KERNEL); 683 if (!output_fmts) 684 return NULL; 685 686 /* TOFIX handle more than MEDIA_BUS_FMT_RGB888_1X24 as output format */ 687 output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 688 *num_output_fmts = 1; 689 690 return output_fmts; 691 } 692 693 #define MAX_INPUT_SEL_FORMATS 1 694 695 static u32 *it66121_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 696 struct drm_bridge_state *bridge_state, 697 struct drm_crtc_state *crtc_state, 698 struct drm_connector_state *conn_state, 699 u32 output_fmt, 700 unsigned int *num_input_fmts) 701 { 702 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 703 u32 *input_fmts; 704 705 *num_input_fmts = 0; 706 707 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 708 GFP_KERNEL); 709 if (!input_fmts) 710 return NULL; 711 712 if (ctx->bus_width == 12) 713 /* IT66121FN Datasheet specifies Little-Endian ordering */ 714 input_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE; 715 else 716 /* TOFIX support more input bus formats in 24bit width */ 717 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 718 *num_input_fmts = 1; 719 720 return input_fmts; 721 } 722 723 static void it66121_bridge_enable(struct drm_bridge *bridge, 724 struct drm_bridge_state *bridge_state) 725 { 726 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 727 struct drm_atomic_state *state = bridge_state->base.state; 728 729 ctx->connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 730 731 it66121_set_mute(ctx, false); 732 } 733 734 static void it66121_bridge_disable(struct drm_bridge *bridge, 735 struct drm_bridge_state *bridge_state) 736 { 737 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 738 739 it66121_set_mute(ctx, true); 740 741 ctx->connector = NULL; 742 } 743 744 static int it66121_bridge_check(struct drm_bridge *bridge, 745 struct drm_bridge_state *bridge_state, 746 struct drm_crtc_state *crtc_state, 747 struct drm_connector_state *conn_state) 748 { 749 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 750 751 if (ctx->info->id == ID_IT6610) { 752 /* The IT6610 only supports these settings */ 753 bridge_state->input_bus_cfg.flags |= DRM_BUS_FLAG_DE_HIGH | 754 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE; 755 bridge_state->input_bus_cfg.flags &= 756 ~DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE; 757 } 758 759 return 0; 760 } 761 762 static 763 void it66121_bridge_mode_set(struct drm_bridge *bridge, 764 const struct drm_display_mode *mode, 765 const struct drm_display_mode *adjusted_mode) 766 { 767 u8 buf[HDMI_INFOFRAME_SIZE(AVI)]; 768 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 769 int ret; 770 771 mutex_lock(&ctx->lock); 772 773 ret = drm_hdmi_avi_infoframe_from_display_mode(&ctx->hdmi_avi_infoframe, ctx->connector, 774 adjusted_mode); 775 if (ret) { 776 DRM_ERROR("Failed to setup AVI infoframe: %d\n", ret); 777 goto unlock; 778 } 779 780 ret = hdmi_avi_infoframe_pack(&ctx->hdmi_avi_infoframe, buf, sizeof(buf)); 781 if (ret < 0) { 782 DRM_ERROR("Failed to pack infoframe: %d\n", ret); 783 goto unlock; 784 } 785 786 /* Write new AVI infoframe packet */ 787 ret = regmap_bulk_write(ctx->regmap, IT66121_AVIINFO_DB1_REG, 788 &buf[HDMI_INFOFRAME_HEADER_SIZE], 789 HDMI_AVI_INFOFRAME_SIZE); 790 if (ret) 791 goto unlock; 792 793 if (regmap_write(ctx->regmap, IT66121_AVIINFO_CSUM_REG, buf[3])) 794 goto unlock; 795 796 /* Enable AVI infoframe */ 797 if (regmap_write(ctx->regmap, IT66121_AVI_INFO_PKT_REG, 798 IT66121_AVI_INFO_PKT_ON | IT66121_AVI_INFO_PKT_RPT)) 799 goto unlock; 800 801 /* Set TX mode to HDMI */ 802 if (regmap_write(ctx->regmap, IT66121_HDMI_MODE_REG, IT66121_HDMI_MODE_HDMI)) 803 goto unlock; 804 805 if (ctx->info->id == ID_IT66121 && 806 regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, 807 IT66121_CLK_BANK_PWROFF_TXCLK, 808 IT66121_CLK_BANK_PWROFF_TXCLK)) { 809 goto unlock; 810 } 811 812 if (it66121_configure_input(ctx)) 813 goto unlock; 814 815 if (it66121_configure_afe(ctx, adjusted_mode)) 816 goto unlock; 817 818 if (ctx->info->id == ID_IT66121 && 819 regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, 820 IT66121_CLK_BANK_PWROFF_TXCLK, 0)) { 821 goto unlock; 822 } 823 824 unlock: 825 mutex_unlock(&ctx->lock); 826 } 827 828 static enum drm_mode_status it66121_bridge_mode_valid(struct drm_bridge *bridge, 829 const struct drm_display_info *info, 830 const struct drm_display_mode *mode) 831 { 832 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 833 unsigned long max_clock; 834 835 max_clock = (ctx->bus_width == 12) ? 74250 : 148500; 836 837 if (mode->clock > max_clock) 838 return MODE_CLOCK_HIGH; 839 840 if (mode->clock < 25000) 841 return MODE_CLOCK_LOW; 842 843 return MODE_OK; 844 } 845 846 static enum drm_connector_status it66121_bridge_detect(struct drm_bridge *bridge) 847 { 848 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 849 850 return it66121_is_hpd_detect(ctx) ? connector_status_connected 851 : connector_status_disconnected; 852 } 853 854 static void it66121_bridge_hpd_enable(struct drm_bridge *bridge) 855 { 856 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 857 int ret; 858 859 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, IT66121_INT_MASK1_HPD, 0); 860 if (ret) 861 dev_err(ctx->dev, "failed to enable HPD IRQ\n"); 862 } 863 864 static void it66121_bridge_hpd_disable(struct drm_bridge *bridge) 865 { 866 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 867 int ret; 868 869 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, 870 IT66121_INT_MASK1_HPD, IT66121_INT_MASK1_HPD); 871 if (ret) 872 dev_err(ctx->dev, "failed to disable HPD IRQ\n"); 873 } 874 875 static const struct drm_edid *it66121_bridge_edid_read(struct drm_bridge *bridge, 876 struct drm_connector *connector) 877 { 878 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 879 const struct drm_edid *drm_edid; 880 int ret; 881 882 mutex_lock(&ctx->lock); 883 ret = it66121_preamble_ddc(ctx); 884 if (ret) { 885 drm_edid = NULL; 886 goto out_unlock; 887 } 888 889 ret = regmap_write(ctx->regmap, IT66121_DDC_HEADER_REG, 890 IT66121_DDC_HEADER_EDID); 891 if (ret) { 892 drm_edid = NULL; 893 goto out_unlock; 894 } 895 896 drm_edid = drm_edid_read_custom(connector, it66121_get_edid_block, ctx); 897 898 out_unlock: 899 mutex_unlock(&ctx->lock); 900 901 return drm_edid; 902 } 903 904 static const struct drm_bridge_funcs it66121_bridge_funcs = { 905 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 906 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 907 .atomic_reset = drm_atomic_helper_bridge_reset, 908 .attach = it66121_bridge_attach, 909 .atomic_get_output_bus_fmts = it66121_bridge_atomic_get_output_bus_fmts, 910 .atomic_get_input_bus_fmts = it66121_bridge_atomic_get_input_bus_fmts, 911 .atomic_enable = it66121_bridge_enable, 912 .atomic_disable = it66121_bridge_disable, 913 .atomic_check = it66121_bridge_check, 914 .mode_set = it66121_bridge_mode_set, 915 .mode_valid = it66121_bridge_mode_valid, 916 .detect = it66121_bridge_detect, 917 .edid_read = it66121_bridge_edid_read, 918 .hpd_enable = it66121_bridge_hpd_enable, 919 .hpd_disable = it66121_bridge_hpd_disable, 920 }; 921 922 static irqreturn_t it66121_irq_threaded_handler(int irq, void *dev_id) 923 { 924 int ret; 925 unsigned int val; 926 struct it66121_ctx *ctx = dev_id; 927 struct device *dev = ctx->dev; 928 enum drm_connector_status status; 929 bool event = false; 930 931 mutex_lock(&ctx->lock); 932 933 ret = regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val); 934 if (ret) 935 goto unlock; 936 937 if (!(val & IT66121_SYS_STATUS_ACTIVE_IRQ)) 938 goto unlock; 939 940 ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val); 941 if (ret) { 942 dev_err(dev, "Cannot read STATUS1_REG %d\n", ret); 943 } else if (val & IT66121_INT_STATUS1_HPD_STATUS) { 944 regmap_write_bits(ctx->regmap, IT66121_INT_CLR1_REG, 945 IT66121_INT_CLR1_HPD, IT66121_INT_CLR1_HPD); 946 947 status = it66121_is_hpd_detect(ctx) ? connector_status_connected 948 : connector_status_disconnected; 949 950 event = true; 951 } 952 953 regmap_write_bits(ctx->regmap, IT66121_SYS_STATUS_REG, 954 IT66121_SYS_STATUS_CLEAR_IRQ, 955 IT66121_SYS_STATUS_CLEAR_IRQ); 956 957 unlock: 958 mutex_unlock(&ctx->lock); 959 960 if (event) 961 drm_bridge_hpd_notify(&ctx->bridge, status); 962 963 return IRQ_HANDLED; 964 } 965 966 static int it661221_set_chstat(struct it66121_ctx *ctx, u8 iec60958_chstat[]) 967 { 968 int ret; 969 970 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_MODE_REG, iec60958_chstat[0] & 0x7C); 971 if (ret) 972 return ret; 973 974 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CAT_REG, iec60958_chstat[1]); 975 if (ret) 976 return ret; 977 978 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_SRCNUM_REG, iec60958_chstat[2] & 0x0F); 979 if (ret) 980 return ret; 981 982 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CHTNUM_REG, 983 (iec60958_chstat[2] >> 4) & 0x0F); 984 if (ret) 985 return ret; 986 987 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CA_FS_REG, iec60958_chstat[3]); 988 if (ret) 989 return ret; 990 991 return regmap_write(ctx->regmap, IT66121_AUD_CHST_OFS_WL_REG, iec60958_chstat[4]); 992 } 993 994 static int it661221_set_lpcm_audio(struct it66121_ctx *ctx, u8 audio_src_num, u8 audio_swl) 995 { 996 int ret; 997 unsigned int audio_enable = 0; 998 unsigned int audio_format = 0; 999 1000 switch (audio_swl) { 1001 case 16: 1002 audio_enable |= IT66121_AUD_16BIT; 1003 break; 1004 case 18: 1005 audio_enable |= IT66121_AUD_18BIT; 1006 break; 1007 case 20: 1008 audio_enable |= IT66121_AUD_20BIT; 1009 break; 1010 case 24: 1011 default: 1012 audio_enable |= IT66121_AUD_24BIT; 1013 break; 1014 } 1015 1016 audio_format |= 0x40; 1017 switch (audio_src_num) { 1018 case 4: 1019 audio_enable |= IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 | 1020 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0; 1021 break; 1022 case 3: 1023 audio_enable |= IT66121_AUD_EN_I2S2 | IT66121_AUD_EN_I2S1 | 1024 IT66121_AUD_EN_I2S0; 1025 break; 1026 case 2: 1027 audio_enable |= IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0; 1028 break; 1029 case 1: 1030 default: 1031 audio_format &= ~0x40; 1032 audio_enable |= IT66121_AUD_EN_I2S0; 1033 break; 1034 } 1035 1036 audio_format |= 0x01; 1037 ctx->audio.ch_enable = audio_enable; 1038 1039 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, audio_enable & 0xF0); 1040 if (ret) 1041 return ret; 1042 1043 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL1_REG, audio_format); 1044 if (ret) 1045 return ret; 1046 1047 ret = regmap_write(ctx->regmap, IT66121_AUD_FIFOMAP_REG, 0xE4); 1048 if (ret) 1049 return ret; 1050 1051 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL3_REG, 0x00); 1052 if (ret) 1053 return ret; 1054 1055 ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0x00); 1056 if (ret) 1057 return ret; 1058 1059 return regmap_write(ctx->regmap, IT66121_AUD_HDAUDIO_REG, 0x00); 1060 } 1061 1062 static int it661221_set_ncts(struct it66121_ctx *ctx, u8 fs) 1063 { 1064 int ret; 1065 unsigned int n; 1066 1067 switch (fs) { 1068 case IT66121_AUD_FS_32K: 1069 n = 4096; 1070 break; 1071 case IT66121_AUD_FS_44P1K: 1072 n = 6272; 1073 break; 1074 case IT66121_AUD_FS_48K: 1075 n = 6144; 1076 break; 1077 case IT66121_AUD_FS_88P2K: 1078 n = 12544; 1079 break; 1080 case IT66121_AUD_FS_96K: 1081 n = 12288; 1082 break; 1083 case IT66121_AUD_FS_176P4K: 1084 n = 25088; 1085 break; 1086 case IT66121_AUD_FS_192K: 1087 n = 24576; 1088 break; 1089 case IT66121_AUD_FS_768K: 1090 n = 24576; 1091 break; 1092 default: 1093 n = 6144; 1094 break; 1095 } 1096 1097 ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N0_REG, (u8)((n) & 0xFF)); 1098 if (ret) 1099 return ret; 1100 1101 ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N1_REG, (u8)((n >> 8) & 0xFF)); 1102 if (ret) 1103 return ret; 1104 1105 ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N2_REG, (u8)((n >> 16) & 0xF)); 1106 if (ret) 1107 return ret; 1108 1109 if (ctx->audio.auto_cts) { 1110 u8 loop_cnt = 255; 1111 u8 cts_stable_cnt = 0; 1112 unsigned int sum_cts = 0; 1113 unsigned int cts = 0; 1114 unsigned int last_cts = 0; 1115 unsigned int diff; 1116 unsigned int val; 1117 1118 while (loop_cnt--) { 1119 msleep(30); 1120 regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT2_REG, &val); 1121 cts = val << 12; 1122 regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT1_REG, &val); 1123 cts |= val << 4; 1124 regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT0_REG, &val); 1125 cts |= val >> 4; 1126 if (cts == 0) { 1127 continue; 1128 } else { 1129 if (last_cts > cts) 1130 diff = last_cts - cts; 1131 else 1132 diff = cts - last_cts; 1133 last_cts = cts; 1134 if (diff < 5) { 1135 cts_stable_cnt++; 1136 sum_cts += cts; 1137 } else { 1138 cts_stable_cnt = 0; 1139 sum_cts = 0; 1140 continue; 1141 } 1142 1143 if (cts_stable_cnt >= 32) { 1144 last_cts = (sum_cts >> 5); 1145 break; 1146 } 1147 } 1148 } 1149 1150 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS0_REG, (u8)((last_cts) & 0xFF)); 1151 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS1_REG, (u8)((last_cts >> 8) & 0xFF)); 1152 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS2_REG, (u8)((last_cts >> 16) & 0x0F)); 1153 } 1154 1155 ret = regmap_write(ctx->regmap, 0xF8, 0xC3); 1156 if (ret) 1157 return ret; 1158 1159 ret = regmap_write(ctx->regmap, 0xF8, 0xA5); 1160 if (ret) 1161 return ret; 1162 1163 if (ctx->audio.auto_cts) { 1164 ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG, 1165 IT66121_PKT_CTS_CTRL_SEL, 1166 1); 1167 } else { 1168 ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG, 1169 IT66121_PKT_CTS_CTRL_SEL, 1170 0); 1171 } 1172 1173 if (ret) 1174 return ret; 1175 1176 return regmap_write(ctx->regmap, 0xF8, 0xFF); 1177 } 1178 1179 static int it661221_audio_output_enable(struct it66121_ctx *ctx, bool enable) 1180 { 1181 int ret; 1182 1183 if (enable) { 1184 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 1185 IT66121_SW_RST_AUD | IT66121_SW_RST_AREF, 1186 0); 1187 if (ret) 1188 return ret; 1189 1190 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG, 1191 IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 | 1192 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0, 1193 ctx->audio.ch_enable); 1194 } else { 1195 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG, 1196 IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 | 1197 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0, 1198 ctx->audio.ch_enable & 0xF0); 1199 if (ret) 1200 return ret; 1201 1202 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 1203 IT66121_SW_RST_AUD | IT66121_SW_RST_AREF, 1204 IT66121_SW_RST_AUD | IT66121_SW_RST_AREF); 1205 } 1206 1207 return ret; 1208 } 1209 1210 static int it661221_audio_ch_enable(struct it66121_ctx *ctx, bool enable) 1211 { 1212 int ret; 1213 1214 if (enable) { 1215 ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0); 1216 if (ret) 1217 return ret; 1218 1219 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable); 1220 } else { 1221 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable & 0xF0); 1222 } 1223 1224 return ret; 1225 } 1226 1227 static int it66121_audio_hw_params(struct device *dev, void *data, 1228 struct hdmi_codec_daifmt *daifmt, 1229 struct hdmi_codec_params *params) 1230 { 1231 u8 fs; 1232 u8 swl; 1233 int ret; 1234 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1235 static u8 iec60958_chstat[5]; 1236 unsigned int channels = params->channels; 1237 unsigned int sample_rate = params->sample_rate; 1238 unsigned int sample_width = params->sample_width; 1239 1240 mutex_lock(&ctx->lock); 1241 dev_dbg(dev, "%s: %u, %u, %u, %u\n", __func__, 1242 daifmt->fmt, sample_rate, sample_width, channels); 1243 1244 switch (daifmt->fmt) { 1245 case HDMI_I2S: 1246 dev_dbg(dev, "Using HDMI I2S\n"); 1247 break; 1248 default: 1249 dev_err(dev, "Invalid or unsupported DAI format %d\n", daifmt->fmt); 1250 ret = -EINVAL; 1251 goto out; 1252 } 1253 1254 // Set audio clock recovery (N/CTS) 1255 ret = regmap_write(ctx->regmap, IT66121_CLK_CTRL0_REG, 1256 IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING | 1257 IT66121_CLK_CTRL0_EXT_MCLK_256FS | 1258 IT66121_CLK_CTRL0_AUTO_IPCLK); 1259 if (ret) 1260 goto out; 1261 1262 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG, 1263 IT66121_AUD_CTRL0_AUD_SEL, 0); // remove spdif selection 1264 if (ret) 1265 goto out; 1266 1267 switch (sample_rate) { 1268 case 44100L: 1269 fs = IT66121_AUD_FS_44P1K; 1270 break; 1271 case 88200L: 1272 fs = IT66121_AUD_FS_88P2K; 1273 break; 1274 case 176400L: 1275 fs = IT66121_AUD_FS_176P4K; 1276 break; 1277 case 32000L: 1278 fs = IT66121_AUD_FS_32K; 1279 break; 1280 case 48000L: 1281 fs = IT66121_AUD_FS_48K; 1282 break; 1283 case 96000L: 1284 fs = IT66121_AUD_FS_96K; 1285 break; 1286 case 192000L: 1287 fs = IT66121_AUD_FS_192K; 1288 break; 1289 case 768000L: 1290 fs = IT66121_AUD_FS_768K; 1291 break; 1292 default: 1293 fs = IT66121_AUD_FS_48K; 1294 break; 1295 } 1296 1297 ctx->audio.fs = fs; 1298 ret = it661221_set_ncts(ctx, fs); 1299 if (ret) { 1300 dev_err(dev, "Failed to set N/CTS: %d\n", ret); 1301 goto out; 1302 } 1303 1304 // Set audio format register (except audio channel enable) 1305 ret = it661221_set_lpcm_audio(ctx, (channels + 1) / 2, sample_width); 1306 if (ret) { 1307 dev_err(dev, "Failed to set LPCM audio: %d\n", ret); 1308 goto out; 1309 } 1310 1311 // Set audio channel status 1312 iec60958_chstat[0] = 0; 1313 if ((channels + 1) / 2 == 1) 1314 iec60958_chstat[0] |= 0x1; 1315 iec60958_chstat[0] &= ~(1 << 1); 1316 iec60958_chstat[1] = 0; 1317 iec60958_chstat[2] = (channels + 1) / 2; 1318 iec60958_chstat[2] |= (channels << 4) & 0xF0; 1319 iec60958_chstat[3] = fs; 1320 1321 switch (sample_width) { 1322 case 21L: 1323 swl = IT66121_AUD_SWL_21BIT; 1324 break; 1325 case 24L: 1326 swl = IT66121_AUD_SWL_24BIT; 1327 break; 1328 case 23L: 1329 swl = IT66121_AUD_SWL_23BIT; 1330 break; 1331 case 22L: 1332 swl = IT66121_AUD_SWL_22BIT; 1333 break; 1334 case 20L: 1335 swl = IT66121_AUD_SWL_20BIT; 1336 break; 1337 case 17L: 1338 swl = IT66121_AUD_SWL_17BIT; 1339 break; 1340 case 19L: 1341 swl = IT66121_AUD_SWL_19BIT; 1342 break; 1343 case 18L: 1344 swl = IT66121_AUD_SWL_18BIT; 1345 break; 1346 case 16L: 1347 swl = IT66121_AUD_SWL_16BIT; 1348 break; 1349 default: 1350 swl = IT66121_AUD_SWL_NOT_INDICATED; 1351 break; 1352 } 1353 1354 iec60958_chstat[4] = (((~fs) << 4) & 0xF0) | swl; 1355 ret = it661221_set_chstat(ctx, iec60958_chstat); 1356 if (ret) { 1357 dev_err(dev, "Failed to set channel status: %d\n", ret); 1358 goto out; 1359 } 1360 1361 // Enable audio channel enable while input clock stable (if SPDIF). 1362 ret = it661221_audio_ch_enable(ctx, true); 1363 if (ret) { 1364 dev_err(dev, "Failed to enable audio channel: %d\n", ret); 1365 goto out; 1366 } 1367 1368 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, 1369 IT66121_INT_MASK1_AUD_OVF, 1370 0); 1371 if (ret) 1372 goto out; 1373 1374 dev_dbg(dev, "HDMI audio enabled.\n"); 1375 out: 1376 mutex_unlock(&ctx->lock); 1377 1378 return ret; 1379 } 1380 1381 static int it66121_audio_startup(struct device *dev, void *data) 1382 { 1383 int ret; 1384 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1385 1386 dev_dbg(dev, "%s\n", __func__); 1387 1388 mutex_lock(&ctx->lock); 1389 ret = it661221_audio_output_enable(ctx, true); 1390 if (ret) 1391 dev_err(dev, "Failed to enable audio output: %d\n", ret); 1392 1393 mutex_unlock(&ctx->lock); 1394 1395 return ret; 1396 } 1397 1398 static void it66121_audio_shutdown(struct device *dev, void *data) 1399 { 1400 int ret; 1401 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1402 1403 dev_dbg(dev, "%s\n", __func__); 1404 1405 mutex_lock(&ctx->lock); 1406 ret = it661221_audio_output_enable(ctx, false); 1407 if (ret) 1408 dev_err(dev, "Failed to disable audio output: %d\n", ret); 1409 1410 mutex_unlock(&ctx->lock); 1411 } 1412 1413 static int it66121_audio_mute(struct device *dev, void *data, 1414 bool enable, int direction) 1415 { 1416 int ret; 1417 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1418 1419 dev_dbg(dev, "%s: enable=%s, direction=%d\n", 1420 __func__, enable ? "true" : "false", direction); 1421 1422 mutex_lock(&ctx->lock); 1423 1424 if (enable) { 1425 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 1426 IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 | 1427 IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3, 1428 IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 | 1429 IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3); 1430 } else { 1431 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 1432 IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 | 1433 IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3, 1434 0); 1435 } 1436 1437 mutex_unlock(&ctx->lock); 1438 1439 return ret; 1440 } 1441 1442 static int it66121_audio_get_eld(struct device *dev, void *data, 1443 u8 *buf, size_t len) 1444 { 1445 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1446 1447 mutex_lock(&ctx->lock); 1448 if (!ctx->connector) { 1449 /* Pass en empty ELD if connector not available */ 1450 dev_dbg(dev, "No connector present, passing empty EDID data"); 1451 memset(buf, 0, len); 1452 } else { 1453 memcpy(buf, ctx->connector->eld, 1454 min(sizeof(ctx->connector->eld), len)); 1455 } 1456 mutex_unlock(&ctx->lock); 1457 1458 return 0; 1459 } 1460 1461 static const struct hdmi_codec_ops it66121_audio_codec_ops = { 1462 .hw_params = it66121_audio_hw_params, 1463 .audio_startup = it66121_audio_startup, 1464 .audio_shutdown = it66121_audio_shutdown, 1465 .mute_stream = it66121_audio_mute, 1466 .get_eld = it66121_audio_get_eld, 1467 .no_capture_mute = 1, 1468 }; 1469 1470 static int it66121_audio_codec_init(struct it66121_ctx *ctx, struct device *dev) 1471 { 1472 struct hdmi_codec_pdata codec_data = { 1473 .ops = &it66121_audio_codec_ops, 1474 .i2s = 1, /* Only i2s support for now */ 1475 .spdif = 0, 1476 .max_i2s_channels = 8, 1477 }; 1478 1479 dev_dbg(dev, "%s\n", __func__); 1480 1481 if (!of_property_read_bool(dev->of_node, "#sound-dai-cells")) { 1482 dev_info(dev, "No \"#sound-dai-cells\", no audio\n"); 1483 return 0; 1484 } 1485 1486 ctx->audio.pdev = platform_device_register_data(dev, 1487 HDMI_CODEC_DRV_NAME, 1488 PLATFORM_DEVID_AUTO, 1489 &codec_data, 1490 sizeof(codec_data)); 1491 1492 if (IS_ERR(ctx->audio.pdev)) { 1493 dev_err(dev, "Failed to initialize HDMI audio codec: %d\n", 1494 PTR_ERR_OR_ZERO(ctx->audio.pdev)); 1495 } 1496 1497 return PTR_ERR_OR_ZERO(ctx->audio.pdev); 1498 } 1499 1500 static const char * const it66121_supplies[] = { 1501 "vcn33", "vcn18", "vrf12" 1502 }; 1503 1504 static int it66121_probe(struct i2c_client *client) 1505 { 1506 u32 revision_id, vendor_ids[2] = { 0 }, device_ids[2] = { 0 }; 1507 struct device_node *ep; 1508 int ret; 1509 struct it66121_ctx *ctx; 1510 struct device *dev = &client->dev; 1511 1512 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1513 dev_err(dev, "I2C check functionality failed.\n"); 1514 return -ENXIO; 1515 } 1516 1517 ctx = devm_kzalloc(dev, sizeof(*ctx), GFP_KERNEL); 1518 if (!ctx) 1519 return -ENOMEM; 1520 1521 ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 1522 if (!ep) 1523 return -EINVAL; 1524 1525 ctx->dev = dev; 1526 ctx->client = client; 1527 ctx->info = i2c_get_match_data(client); 1528 1529 of_property_read_u32(ep, "bus-width", &ctx->bus_width); 1530 of_node_put(ep); 1531 1532 if (ctx->bus_width != 12 && ctx->bus_width != 24) 1533 return -EINVAL; 1534 1535 ep = of_graph_get_remote_node(dev->of_node, 1, -1); 1536 if (!ep) { 1537 dev_err(ctx->dev, "The endpoint is unconnected\n"); 1538 return -EINVAL; 1539 } 1540 1541 ctx->next_bridge = of_drm_find_bridge(ep); 1542 of_node_put(ep); 1543 if (!ctx->next_bridge) { 1544 dev_dbg(ctx->dev, "Next bridge not found, deferring probe\n"); 1545 return -EPROBE_DEFER; 1546 } 1547 1548 i2c_set_clientdata(client, ctx); 1549 mutex_init(&ctx->lock); 1550 1551 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it66121_supplies), 1552 it66121_supplies); 1553 if (ret) { 1554 dev_err(dev, "Failed to enable power supplies\n"); 1555 return ret; 1556 } 1557 1558 it66121_hw_reset(ctx); 1559 1560 ctx->regmap = devm_regmap_init_i2c(client, &it66121_regmap_config); 1561 if (IS_ERR(ctx->regmap)) 1562 return PTR_ERR(ctx->regmap); 1563 1564 regmap_read(ctx->regmap, IT66121_VENDOR_ID0_REG, &vendor_ids[0]); 1565 regmap_read(ctx->regmap, IT66121_VENDOR_ID1_REG, &vendor_ids[1]); 1566 regmap_read(ctx->regmap, IT66121_DEVICE_ID0_REG, &device_ids[0]); 1567 regmap_read(ctx->regmap, IT66121_DEVICE_ID1_REG, &device_ids[1]); 1568 1569 /* Revision is shared with DEVICE_ID1 */ 1570 revision_id = FIELD_GET(IT66121_REVISION_MASK, device_ids[1]); 1571 device_ids[1] &= IT66121_DEVICE_ID1_MASK; 1572 1573 if ((vendor_ids[1] << 8 | vendor_ids[0]) != ctx->info->vid || 1574 (device_ids[1] << 8 | device_ids[0]) != ctx->info->pid) { 1575 return -ENODEV; 1576 } 1577 1578 ctx->bridge.funcs = &it66121_bridge_funcs; 1579 ctx->bridge.of_node = dev->of_node; 1580 ctx->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 1581 ctx->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID; 1582 if (client->irq > 0) { 1583 ctx->bridge.ops |= DRM_BRIDGE_OP_HPD; 1584 1585 ret = devm_request_threaded_irq(dev, client->irq, NULL, 1586 it66121_irq_threaded_handler, 1587 IRQF_ONESHOT, dev_name(dev), 1588 ctx); 1589 if (ret < 0) { 1590 dev_err(dev, "Failed to request irq %d:%d\n", client->irq, ret); 1591 return ret; 1592 } 1593 } 1594 1595 it66121_audio_codec_init(ctx, dev); 1596 1597 drm_bridge_add(&ctx->bridge); 1598 1599 dev_info(ctx->dev, "IT66121 revision %d probed\n", revision_id); 1600 1601 return 0; 1602 } 1603 1604 static void it66121_remove(struct i2c_client *client) 1605 { 1606 struct it66121_ctx *ctx = i2c_get_clientdata(client); 1607 1608 drm_bridge_remove(&ctx->bridge); 1609 mutex_destroy(&ctx->lock); 1610 } 1611 1612 static const struct it66121_chip_info it66121_chip_info = { 1613 .id = ID_IT66121, 1614 .vid = 0x4954, 1615 .pid = 0x0612, 1616 }; 1617 1618 static const struct it66121_chip_info it6610_chip_info = { 1619 .id = ID_IT6610, 1620 .vid = 0xca00, 1621 .pid = 0x0611, 1622 }; 1623 1624 static const struct of_device_id it66121_dt_match[] = { 1625 { .compatible = "ite,it66121", &it66121_chip_info }, 1626 { .compatible = "ite,it6610", &it6610_chip_info }, 1627 { } 1628 }; 1629 MODULE_DEVICE_TABLE(of, it66121_dt_match); 1630 1631 static const struct i2c_device_id it66121_id[] = { 1632 { "it66121", (kernel_ulong_t) &it66121_chip_info }, 1633 { "it6610", (kernel_ulong_t) &it6610_chip_info }, 1634 { } 1635 }; 1636 MODULE_DEVICE_TABLE(i2c, it66121_id); 1637 1638 static struct i2c_driver it66121_driver = { 1639 .driver = { 1640 .name = "it66121", 1641 .of_match_table = it66121_dt_match, 1642 }, 1643 .probe = it66121_probe, 1644 .remove = it66121_remove, 1645 .id_table = it66121_id, 1646 }; 1647 1648 module_i2c_driver(it66121_driver); 1649 1650 MODULE_AUTHOR("Phong LE"); 1651 MODULE_DESCRIPTION("IT66121 HDMI transmitter driver"); 1652 MODULE_LICENSE("GPL v2"); 1653