1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2020 BayLibre, SAS 4 * Author: Phong LE <ple@baylibre.com> 5 * Copyright (C) 2018-2019, Artem Mygaiev 6 * Copyright (C) 2017, Fresco Logic, Incorporated. 7 * 8 */ 9 10 #include <linux/media-bus-format.h> 11 #include <linux/module.h> 12 #include <linux/device.h> 13 #include <linux/interrupt.h> 14 #include <linux/i2c.h> 15 #include <linux/bitfield.h> 16 #include <linux/property.h> 17 #include <linux/regmap.h> 18 #include <linux/of_graph.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/pinctrl/consumer.h> 21 #include <linux/regulator/consumer.h> 22 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_edid.h> 26 #include <drm/drm_modes.h> 27 #include <drm/drm_print.h> 28 #include <drm/drm_probe_helper.h> 29 30 #include <sound/hdmi-codec.h> 31 32 #define IT66121_VENDOR_ID0_REG 0x00 33 #define IT66121_VENDOR_ID1_REG 0x01 34 #define IT66121_DEVICE_ID0_REG 0x02 35 #define IT66121_DEVICE_ID1_REG 0x03 36 37 #define IT66121_REVISION_MASK GENMASK(7, 4) 38 #define IT66121_DEVICE_ID1_MASK GENMASK(3, 0) 39 40 #define IT66121_MASTER_SEL_REG 0x10 41 #define IT66121_MASTER_SEL_HOST BIT(0) 42 43 #define IT66121_AFE_DRV_REG 0x61 44 #define IT66121_AFE_DRV_RST BIT(4) 45 #define IT66121_AFE_DRV_PWD BIT(5) 46 47 #define IT66121_INPUT_MODE_REG 0x70 48 #define IT66121_INPUT_MODE_RGB (0 << 6) 49 #define IT66121_INPUT_MODE_YUV422 BIT(6) 50 #define IT66121_INPUT_MODE_YUV444 (2 << 6) 51 #define IT66121_INPUT_MODE_CCIR656 BIT(4) 52 #define IT66121_INPUT_MODE_SYNCEMB BIT(3) 53 #define IT66121_INPUT_MODE_DDR BIT(2) 54 55 #define IT66121_INPUT_CSC_REG 0x72 56 #define IT66121_INPUT_CSC_ENDITHER BIT(7) 57 #define IT66121_INPUT_CSC_ENUDFILTER BIT(6) 58 #define IT66121_INPUT_CSC_DNFREE_GO BIT(5) 59 #define IT66121_INPUT_CSC_RGB_TO_YUV 0x02 60 #define IT66121_INPUT_CSC_YUV_TO_RGB 0x03 61 #define IT66121_INPUT_CSC_NO_CONV 0x00 62 63 #define IT66121_AFE_XP_REG 0x62 64 #define IT66121_AFE_XP_GAINBIT BIT(7) 65 #define IT66121_AFE_XP_PWDPLL BIT(6) 66 #define IT66121_AFE_XP_ENI BIT(5) 67 #define IT66121_AFE_XP_ENO BIT(4) 68 #define IT66121_AFE_XP_RESETB BIT(3) 69 #define IT66121_AFE_XP_PWDI BIT(2) 70 #define IT6610_AFE_XP_BYPASS BIT(0) 71 72 #define IT66121_AFE_IP_REG 0x64 73 #define IT66121_AFE_IP_GAINBIT BIT(7) 74 #define IT66121_AFE_IP_PWDPLL BIT(6) 75 #define IT66121_AFE_IP_CKSEL_05 (0 << 4) 76 #define IT66121_AFE_IP_CKSEL_1 BIT(4) 77 #define IT66121_AFE_IP_CKSEL_2 (2 << 4) 78 #define IT66121_AFE_IP_CKSEL_2OR4 (3 << 4) 79 #define IT66121_AFE_IP_ER0 BIT(3) 80 #define IT66121_AFE_IP_RESETB BIT(2) 81 #define IT66121_AFE_IP_ENC BIT(1) 82 #define IT66121_AFE_IP_EC1 BIT(0) 83 84 #define IT66121_AFE_XP_EC1_REG 0x68 85 #define IT66121_AFE_XP_EC1_LOWCLK BIT(4) 86 87 #define IT66121_SW_RST_REG 0x04 88 #define IT66121_SW_RST_REF BIT(5) 89 #define IT66121_SW_RST_AREF BIT(4) 90 #define IT66121_SW_RST_VID BIT(3) 91 #define IT66121_SW_RST_AUD BIT(2) 92 #define IT66121_SW_RST_HDCP BIT(0) 93 94 #define IT66121_DDC_COMMAND_REG 0x15 95 #define IT66121_DDC_COMMAND_BURST_READ 0x0 96 #define IT66121_DDC_COMMAND_EDID_READ 0x3 97 #define IT66121_DDC_COMMAND_FIFO_CLR 0x9 98 #define IT66121_DDC_COMMAND_SCL_PULSE 0xA 99 #define IT66121_DDC_COMMAND_ABORT 0xF 100 101 #define IT66121_HDCP_REG 0x20 102 #define IT66121_HDCP_CPDESIRED BIT(0) 103 #define IT66121_HDCP_EN1P1FEAT BIT(1) 104 105 #define IT66121_INT_STATUS1_REG 0x06 106 #define IT66121_INT_STATUS1_AUD_OVF BIT(7) 107 #define IT66121_INT_STATUS1_DDC_NOACK BIT(5) 108 #define IT66121_INT_STATUS1_DDC_FIFOERR BIT(4) 109 #define IT66121_INT_STATUS1_DDC_BUSHANG BIT(2) 110 #define IT66121_INT_STATUS1_RX_SENS_STATUS BIT(1) 111 #define IT66121_INT_STATUS1_HPD_STATUS BIT(0) 112 113 #define IT66121_DDC_HEADER_REG 0x11 114 #define IT66121_DDC_HEADER_HDCP 0x74 115 #define IT66121_DDC_HEADER_EDID 0xA0 116 117 #define IT66121_DDC_OFFSET_REG 0x12 118 #define IT66121_DDC_BYTE_REG 0x13 119 #define IT66121_DDC_SEGMENT_REG 0x14 120 #define IT66121_DDC_RD_FIFO_REG 0x17 121 122 #define IT66121_CLK_BANK_REG 0x0F 123 #define IT66121_CLK_BANK_PWROFF_RCLK BIT(6) 124 #define IT66121_CLK_BANK_PWROFF_ACLK BIT(5) 125 #define IT66121_CLK_BANK_PWROFF_TXCLK BIT(4) 126 #define IT66121_CLK_BANK_PWROFF_CRCLK BIT(3) 127 #define IT66121_CLK_BANK_0 0 128 #define IT66121_CLK_BANK_1 1 129 130 #define IT66121_INT_REG 0x05 131 #define IT66121_INT_ACTIVE_HIGH BIT(7) 132 #define IT66121_INT_OPEN_DRAIN BIT(6) 133 #define IT66121_INT_TX_CLK_OFF BIT(0) 134 135 #define IT66121_INT_MASK1_REG 0x09 136 #define IT66121_INT_MASK1_AUD_OVF BIT(7) 137 #define IT66121_INT_MASK1_DDC_NOACK BIT(5) 138 #define IT66121_INT_MASK1_DDC_FIFOERR BIT(4) 139 #define IT66121_INT_MASK1_DDC_BUSHANG BIT(2) 140 #define IT66121_INT_MASK1_RX_SENS BIT(1) 141 #define IT66121_INT_MASK1_HPD BIT(0) 142 143 #define IT66121_INT_CLR1_REG 0x0C 144 #define IT66121_INT_CLR1_PKTACP BIT(7) 145 #define IT66121_INT_CLR1_PKTNULL BIT(6) 146 #define IT66121_INT_CLR1_PKTGEN BIT(5) 147 #define IT66121_INT_CLR1_KSVLISTCHK BIT(4) 148 #define IT66121_INT_CLR1_AUTHDONE BIT(3) 149 #define IT66121_INT_CLR1_AUTHFAIL BIT(2) 150 #define IT66121_INT_CLR1_RX_SENS BIT(1) 151 #define IT66121_INT_CLR1_HPD BIT(0) 152 153 #define IT66121_AV_MUTE_REG 0xC1 154 #define IT66121_AV_MUTE_ON BIT(0) 155 #define IT66121_AV_MUTE_BLUESCR BIT(1) 156 157 #define IT66121_PKT_CTS_CTRL_REG 0xC5 158 #define IT66121_PKT_CTS_CTRL_SEL BIT(1) 159 160 #define IT66121_PKT_GEN_CTRL_REG 0xC6 161 #define IT66121_PKT_GEN_CTRL_ON BIT(0) 162 #define IT66121_PKT_GEN_CTRL_RPT BIT(1) 163 164 #define IT66121_AVIINFO_DB1_REG 0x158 165 #define IT66121_AVIINFO_DB2_REG 0x159 166 #define IT66121_AVIINFO_DB3_REG 0x15A 167 #define IT66121_AVIINFO_DB4_REG 0x15B 168 #define IT66121_AVIINFO_DB5_REG 0x15C 169 #define IT66121_AVIINFO_CSUM_REG 0x15D 170 #define IT66121_AVIINFO_DB6_REG 0x15E 171 #define IT66121_AVIINFO_DB7_REG 0x15F 172 #define IT66121_AVIINFO_DB8_REG 0x160 173 #define IT66121_AVIINFO_DB9_REG 0x161 174 #define IT66121_AVIINFO_DB10_REG 0x162 175 #define IT66121_AVIINFO_DB11_REG 0x163 176 #define IT66121_AVIINFO_DB12_REG 0x164 177 #define IT66121_AVIINFO_DB13_REG 0x165 178 179 #define IT66121_AVI_INFO_PKT_REG 0xCD 180 #define IT66121_AVI_INFO_PKT_ON BIT(0) 181 #define IT66121_AVI_INFO_PKT_RPT BIT(1) 182 183 #define IT66121_HDMI_MODE_REG 0xC0 184 #define IT66121_HDMI_MODE_HDMI BIT(0) 185 186 #define IT66121_SYS_STATUS_REG 0x0E 187 #define IT66121_SYS_STATUS_ACTIVE_IRQ BIT(7) 188 #define IT66121_SYS_STATUS_HPDETECT BIT(6) 189 #define IT66121_SYS_STATUS_SENDECTECT BIT(5) 190 #define IT66121_SYS_STATUS_VID_STABLE BIT(4) 191 #define IT66121_SYS_STATUS_AUD_CTS_CLR BIT(1) 192 #define IT66121_SYS_STATUS_CLEAR_IRQ BIT(0) 193 194 #define IT66121_DDC_STATUS_REG 0x16 195 #define IT66121_DDC_STATUS_TX_DONE BIT(7) 196 #define IT66121_DDC_STATUS_ACTIVE BIT(6) 197 #define IT66121_DDC_STATUS_NOACK BIT(5) 198 #define IT66121_DDC_STATUS_WAIT_BUS BIT(4) 199 #define IT66121_DDC_STATUS_ARBI_LOSE BIT(3) 200 #define IT66121_DDC_STATUS_FIFO_FULL BIT(2) 201 #define IT66121_DDC_STATUS_FIFO_EMPTY BIT(1) 202 #define IT66121_DDC_STATUS_FIFO_VALID BIT(0) 203 204 #define IT66121_EDID_SLEEP_US 20000 205 #define IT66121_EDID_TIMEOUT_US 200000 206 #define IT66121_EDID_FIFO_SIZE 32 207 208 #define IT66121_CLK_CTRL0_REG 0x58 209 #define IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING BIT(4) 210 #define IT66121_CLK_CTRL0_EXT_MCLK_MASK GENMASK(3, 2) 211 #define IT66121_CLK_CTRL0_EXT_MCLK_128FS (0 << 2) 212 #define IT66121_CLK_CTRL0_EXT_MCLK_256FS BIT(2) 213 #define IT66121_CLK_CTRL0_EXT_MCLK_512FS (2 << 2) 214 #define IT66121_CLK_CTRL0_EXT_MCLK_1024FS (3 << 2) 215 #define IT66121_CLK_CTRL0_AUTO_IPCLK BIT(0) 216 #define IT66121_CLK_STATUS1_REG 0x5E 217 #define IT66121_CLK_STATUS2_REG 0x5F 218 219 #define IT66121_AUD_CTRL0_REG 0xE0 220 #define IT66121_AUD_SWL (3 << 6) 221 #define IT66121_AUD_16BIT (0 << 6) 222 #define IT66121_AUD_18BIT BIT(6) 223 #define IT66121_AUD_20BIT (2 << 6) 224 #define IT66121_AUD_24BIT (3 << 6) 225 #define IT66121_AUD_SPDIFTC BIT(5) 226 #define IT66121_AUD_SPDIF BIT(4) 227 #define IT66121_AUD_I2S (0 << 4) 228 #define IT66121_AUD_EN_I2S3 BIT(3) 229 #define IT66121_AUD_EN_I2S2 BIT(2) 230 #define IT66121_AUD_EN_I2S1 BIT(1) 231 #define IT66121_AUD_EN_I2S0 BIT(0) 232 #define IT66121_AUD_CTRL0_AUD_SEL BIT(4) 233 234 #define IT66121_AUD_CTRL1_REG 0xE1 235 #define IT66121_AUD_FIFOMAP_REG 0xE2 236 #define IT66121_AUD_CTRL3_REG 0xE3 237 #define IT66121_AUD_SRCVALID_FLAT_REG 0xE4 238 #define IT66121_AUD_FLAT_SRC0 BIT(4) 239 #define IT66121_AUD_FLAT_SRC1 BIT(5) 240 #define IT66121_AUD_FLAT_SRC2 BIT(6) 241 #define IT66121_AUD_FLAT_SRC3 BIT(7) 242 #define IT66121_AUD_HDAUDIO_REG 0xE5 243 244 #define IT66121_AUD_PKT_CTS0_REG 0x130 245 #define IT66121_AUD_PKT_CTS1_REG 0x131 246 #define IT66121_AUD_PKT_CTS2_REG 0x132 247 #define IT66121_AUD_PKT_N0_REG 0x133 248 #define IT66121_AUD_PKT_N1_REG 0x134 249 #define IT66121_AUD_PKT_N2_REG 0x135 250 251 #define IT66121_AUD_CHST_MODE_REG 0x191 252 #define IT66121_AUD_CHST_CAT_REG 0x192 253 #define IT66121_AUD_CHST_SRCNUM_REG 0x193 254 #define IT66121_AUD_CHST_CHTNUM_REG 0x194 255 #define IT66121_AUD_CHST_CA_FS_REG 0x198 256 #define IT66121_AUD_CHST_OFS_WL_REG 0x199 257 258 #define IT66121_AUD_PKT_CTS_CNT0_REG 0x1A0 259 #define IT66121_AUD_PKT_CTS_CNT1_REG 0x1A1 260 #define IT66121_AUD_PKT_CTS_CNT2_REG 0x1A2 261 262 #define IT66121_AUD_FS_22P05K 0x4 263 #define IT66121_AUD_FS_44P1K 0x0 264 #define IT66121_AUD_FS_88P2K 0x8 265 #define IT66121_AUD_FS_176P4K 0xC 266 #define IT66121_AUD_FS_24K 0x6 267 #define IT66121_AUD_FS_48K 0x2 268 #define IT66121_AUD_FS_96K 0xA 269 #define IT66121_AUD_FS_192K 0xE 270 #define IT66121_AUD_FS_768K 0x9 271 #define IT66121_AUD_FS_32K 0x3 272 #define IT66121_AUD_FS_OTHER 0x1 273 274 #define IT66121_AUD_SWL_21BIT 0xD 275 #define IT66121_AUD_SWL_24BIT 0xB 276 #define IT66121_AUD_SWL_23BIT 0x9 277 #define IT66121_AUD_SWL_22BIT 0x5 278 #define IT66121_AUD_SWL_20BIT 0x3 279 #define IT66121_AUD_SWL_17BIT 0xC 280 #define IT66121_AUD_SWL_19BIT 0x8 281 #define IT66121_AUD_SWL_18BIT 0x4 282 #define IT66121_AUD_SWL_16BIT 0x2 283 #define IT66121_AUD_SWL_NOT_INDICATED 0x0 284 285 #define IT66121_AFE_CLK_HIGH 80000 /* Khz */ 286 287 enum chip_id { 288 ID_IT6610, 289 ID_IT66121, 290 }; 291 292 struct it66121_chip_info { 293 enum chip_id id; 294 u16 vid, pid; 295 }; 296 297 struct it66121_ctx { 298 struct regmap *regmap; 299 struct drm_bridge bridge; 300 struct drm_bridge *next_bridge; 301 struct drm_connector *connector; 302 struct device *dev; 303 struct gpio_desc *gpio_reset; 304 struct i2c_client *client; 305 u32 bus_width; 306 struct mutex lock; /* Protects fields below and device registers */ 307 struct hdmi_avi_infoframe hdmi_avi_infoframe; 308 struct { 309 struct platform_device *pdev; 310 u8 ch_enable; 311 u8 fs; 312 u8 swl; 313 bool auto_cts; 314 } audio; 315 const struct it66121_chip_info *info; 316 }; 317 318 static const struct regmap_range_cfg it66121_regmap_banks[] = { 319 { 320 .name = "it66121", 321 .range_min = 0x00, 322 .range_max = 0x1FF, 323 .selector_reg = IT66121_CLK_BANK_REG, 324 .selector_mask = 0x1, 325 .selector_shift = 0, 326 .window_start = 0x00, 327 .window_len = 0x100, 328 }, 329 }; 330 331 static const struct regmap_config it66121_regmap_config = { 332 .val_bits = 8, 333 .reg_bits = 8, 334 .max_register = 0x1FF, 335 .ranges = it66121_regmap_banks, 336 .num_ranges = ARRAY_SIZE(it66121_regmap_banks), 337 }; 338 339 static void it66121_hw_reset(struct it66121_ctx *ctx) 340 { 341 gpiod_set_value(ctx->gpio_reset, 1); 342 msleep(20); 343 gpiod_set_value(ctx->gpio_reset, 0); 344 } 345 346 static inline int it66121_preamble_ddc(struct it66121_ctx *ctx) 347 { 348 return regmap_write(ctx->regmap, IT66121_MASTER_SEL_REG, IT66121_MASTER_SEL_HOST); 349 } 350 351 static inline int it66121_fire_afe(struct it66121_ctx *ctx) 352 { 353 return regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 0); 354 } 355 356 /* TOFIX: Handle YCbCr Input & Output */ 357 static int it66121_configure_input(struct it66121_ctx *ctx) 358 { 359 int ret; 360 u8 mode = IT66121_INPUT_MODE_RGB; 361 362 if (ctx->bus_width == 12) 363 mode |= IT66121_INPUT_MODE_DDR; 364 365 ret = regmap_write(ctx->regmap, IT66121_INPUT_MODE_REG, mode); 366 if (ret) 367 return ret; 368 369 return regmap_write(ctx->regmap, IT66121_INPUT_CSC_REG, IT66121_INPUT_CSC_NO_CONV); 370 } 371 372 /** 373 * it66121_configure_afe() - Configure the analog front end 374 * @ctx: it66121_ctx object 375 * @mode: mode to configure 376 * 377 * RETURNS: 378 * zero if success, a negative error code otherwise. 379 */ 380 static int it66121_configure_afe(struct it66121_ctx *ctx, 381 const struct drm_display_mode *mode) 382 { 383 int ret; 384 385 ret = regmap_write(ctx->regmap, IT66121_AFE_DRV_REG, 386 IT66121_AFE_DRV_RST); 387 if (ret) 388 return ret; 389 390 if (mode->clock > IT66121_AFE_CLK_HIGH) { 391 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 392 IT66121_AFE_XP_GAINBIT | 393 IT66121_AFE_XP_ENO, 394 IT66121_AFE_XP_GAINBIT); 395 if (ret) 396 return ret; 397 398 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 399 IT66121_AFE_IP_GAINBIT | 400 IT66121_AFE_IP_ER0, 401 IT66121_AFE_IP_GAINBIT); 402 if (ret) 403 return ret; 404 405 if (ctx->info->id == ID_IT66121) { 406 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 407 IT66121_AFE_IP_EC1, 0); 408 if (ret) 409 return ret; 410 411 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG, 412 IT66121_AFE_XP_EC1_LOWCLK, 0x80); 413 if (ret) 414 return ret; 415 } 416 } else { 417 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 418 IT66121_AFE_XP_GAINBIT | 419 IT66121_AFE_XP_ENO, 420 IT66121_AFE_XP_ENO); 421 if (ret) 422 return ret; 423 424 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 425 IT66121_AFE_IP_GAINBIT | 426 IT66121_AFE_IP_ER0, 427 IT66121_AFE_IP_ER0); 428 if (ret) 429 return ret; 430 431 if (ctx->info->id == ID_IT66121) { 432 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 433 IT66121_AFE_IP_EC1, 434 IT66121_AFE_IP_EC1); 435 if (ret) 436 return ret; 437 438 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_EC1_REG, 439 IT66121_AFE_XP_EC1_LOWCLK, 440 IT66121_AFE_XP_EC1_LOWCLK); 441 if (ret) 442 return ret; 443 } 444 } 445 446 /* Clear reset flags */ 447 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 448 IT66121_SW_RST_REF | IT66121_SW_RST_VID, 0); 449 if (ret) 450 return ret; 451 452 if (ctx->info->id == ID_IT6610) { 453 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 454 IT6610_AFE_XP_BYPASS, 455 IT6610_AFE_XP_BYPASS); 456 if (ret) 457 return ret; 458 } 459 460 return it66121_fire_afe(ctx); 461 } 462 463 static inline int it66121_wait_ddc_ready(struct it66121_ctx *ctx) 464 { 465 int ret, val; 466 u32 error = IT66121_DDC_STATUS_NOACK | IT66121_DDC_STATUS_WAIT_BUS | 467 IT66121_DDC_STATUS_ARBI_LOSE; 468 u32 done = IT66121_DDC_STATUS_TX_DONE; 469 470 ret = regmap_read_poll_timeout(ctx->regmap, IT66121_DDC_STATUS_REG, val, 471 val & (error | done), IT66121_EDID_SLEEP_US, 472 IT66121_EDID_TIMEOUT_US); 473 if (ret) 474 return ret; 475 476 if (val & error) 477 return -EAGAIN; 478 479 return 0; 480 } 481 482 static int it66121_abort_ddc_ops(struct it66121_ctx *ctx) 483 { 484 int ret; 485 unsigned int swreset, cpdesire; 486 487 ret = regmap_read(ctx->regmap, IT66121_SW_RST_REG, &swreset); 488 if (ret) 489 return ret; 490 491 ret = regmap_read(ctx->regmap, IT66121_HDCP_REG, &cpdesire); 492 if (ret) 493 return ret; 494 495 ret = regmap_write(ctx->regmap, IT66121_HDCP_REG, 496 cpdesire & (~IT66121_HDCP_CPDESIRED & 0xFF)); 497 if (ret) 498 return ret; 499 500 ret = regmap_write(ctx->regmap, IT66121_SW_RST_REG, 501 (swreset | IT66121_SW_RST_HDCP)); 502 if (ret) 503 return ret; 504 505 ret = it66121_preamble_ddc(ctx); 506 if (ret) 507 return ret; 508 509 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 510 IT66121_DDC_COMMAND_ABORT); 511 if (ret) 512 return ret; 513 514 return it66121_wait_ddc_ready(ctx); 515 } 516 517 static int it66121_get_edid_block(void *context, u8 *buf, 518 unsigned int block, size_t len) 519 { 520 struct it66121_ctx *ctx = context; 521 int remain = len; 522 int offset = 0; 523 int ret, cnt; 524 525 offset = (block % 2) * len; 526 block = block / 2; 527 528 while (remain > 0) { 529 cnt = (remain > IT66121_EDID_FIFO_SIZE) ? 530 IT66121_EDID_FIFO_SIZE : remain; 531 532 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 533 IT66121_DDC_COMMAND_FIFO_CLR); 534 if (ret) 535 return ret; 536 537 ret = it66121_wait_ddc_ready(ctx); 538 if (ret) 539 return ret; 540 541 ret = regmap_write(ctx->regmap, IT66121_DDC_OFFSET_REG, offset); 542 if (ret) 543 return ret; 544 545 ret = regmap_write(ctx->regmap, IT66121_DDC_BYTE_REG, cnt); 546 if (ret) 547 return ret; 548 549 ret = regmap_write(ctx->regmap, IT66121_DDC_SEGMENT_REG, block); 550 if (ret) 551 return ret; 552 553 ret = regmap_write(ctx->regmap, IT66121_DDC_COMMAND_REG, 554 IT66121_DDC_COMMAND_EDID_READ); 555 if (ret) 556 return ret; 557 558 offset += cnt; 559 remain -= cnt; 560 561 ret = it66121_wait_ddc_ready(ctx); 562 if (ret) { 563 it66121_abort_ddc_ops(ctx); 564 return ret; 565 } 566 567 ret = regmap_noinc_read(ctx->regmap, IT66121_DDC_RD_FIFO_REG, 568 buf, cnt); 569 if (ret) 570 return ret; 571 572 buf += cnt; 573 } 574 575 return 0; 576 } 577 578 static bool it66121_is_hpd_detect(struct it66121_ctx *ctx) 579 { 580 int val; 581 582 if (regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val)) 583 return false; 584 585 return val & IT66121_SYS_STATUS_HPDETECT; 586 } 587 588 static int it66121_bridge_attach(struct drm_bridge *bridge, 589 struct drm_encoder *encoder, 590 enum drm_bridge_attach_flags flags) 591 { 592 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 593 int ret; 594 595 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 596 return -EINVAL; 597 598 ret = drm_bridge_attach(encoder, ctx->next_bridge, bridge, flags); 599 if (ret) 600 return ret; 601 602 if (ctx->info->id == ID_IT66121) { 603 ret = regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, 604 IT66121_CLK_BANK_PWROFF_RCLK, 0); 605 if (ret) 606 return ret; 607 } 608 609 ret = regmap_write_bits(ctx->regmap, IT66121_INT_REG, 610 IT66121_INT_TX_CLK_OFF, 0); 611 if (ret) 612 return ret; 613 614 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG, 615 IT66121_AFE_DRV_PWD, 0); 616 if (ret) 617 return ret; 618 619 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 620 IT66121_AFE_XP_PWDI | IT66121_AFE_XP_PWDPLL, 0); 621 if (ret) 622 return ret; 623 624 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 625 IT66121_AFE_IP_PWDPLL, 0); 626 if (ret) 627 return ret; 628 629 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_DRV_REG, 630 IT66121_AFE_DRV_RST, 0); 631 if (ret) 632 return ret; 633 634 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_XP_REG, 635 IT66121_AFE_XP_RESETB, IT66121_AFE_XP_RESETB); 636 if (ret) 637 return ret; 638 639 ret = regmap_write_bits(ctx->regmap, IT66121_AFE_IP_REG, 640 IT66121_AFE_IP_RESETB, IT66121_AFE_IP_RESETB); 641 if (ret) 642 return ret; 643 644 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 645 IT66121_SW_RST_REF, 646 IT66121_SW_RST_REF); 647 if (ret) 648 return ret; 649 650 /* Per programming manual, sleep here for bridge to settle */ 651 msleep(50); 652 653 return 0; 654 } 655 656 static int it66121_set_mute(struct it66121_ctx *ctx, bool mute) 657 { 658 int ret; 659 unsigned int val = 0; 660 661 if (mute) 662 val = IT66121_AV_MUTE_ON; 663 664 ret = regmap_write_bits(ctx->regmap, IT66121_AV_MUTE_REG, IT66121_AV_MUTE_ON, val); 665 if (ret) 666 return ret; 667 668 return regmap_write(ctx->regmap, IT66121_PKT_GEN_CTRL_REG, 669 IT66121_PKT_GEN_CTRL_ON | IT66121_PKT_GEN_CTRL_RPT); 670 } 671 672 #define MAX_OUTPUT_SEL_FORMATS 1 673 674 static u32 *it66121_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 675 struct drm_bridge_state *bridge_state, 676 struct drm_crtc_state *crtc_state, 677 struct drm_connector_state *conn_state, 678 unsigned int *num_output_fmts) 679 { 680 u32 *output_fmts; 681 682 output_fmts = kcalloc(MAX_OUTPUT_SEL_FORMATS, sizeof(*output_fmts), 683 GFP_KERNEL); 684 if (!output_fmts) 685 return NULL; 686 687 /* TOFIX handle more than MEDIA_BUS_FMT_RGB888_1X24 as output format */ 688 output_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 689 *num_output_fmts = 1; 690 691 return output_fmts; 692 } 693 694 #define MAX_INPUT_SEL_FORMATS 1 695 696 static u32 *it66121_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 697 struct drm_bridge_state *bridge_state, 698 struct drm_crtc_state *crtc_state, 699 struct drm_connector_state *conn_state, 700 u32 output_fmt, 701 unsigned int *num_input_fmts) 702 { 703 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 704 u32 *input_fmts; 705 706 *num_input_fmts = 0; 707 708 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 709 GFP_KERNEL); 710 if (!input_fmts) 711 return NULL; 712 713 if (ctx->bus_width == 12) 714 /* IT66121FN Datasheet specifies Little-Endian ordering */ 715 input_fmts[0] = MEDIA_BUS_FMT_RGB888_2X12_LE; 716 else 717 /* TOFIX support more input bus formats in 24bit width */ 718 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 719 *num_input_fmts = 1; 720 721 return input_fmts; 722 } 723 724 static void it66121_bridge_enable(struct drm_bridge *bridge, 725 struct drm_atomic_state *state) 726 { 727 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 728 729 ctx->connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 730 731 it66121_set_mute(ctx, false); 732 } 733 734 static void it66121_bridge_disable(struct drm_bridge *bridge, 735 struct drm_atomic_state *state) 736 { 737 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 738 739 it66121_set_mute(ctx, true); 740 741 ctx->connector = NULL; 742 } 743 744 static int it66121_bridge_check(struct drm_bridge *bridge, 745 struct drm_bridge_state *bridge_state, 746 struct drm_crtc_state *crtc_state, 747 struct drm_connector_state *conn_state) 748 { 749 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 750 751 if (ctx->info->id == ID_IT6610) { 752 /* The IT6610 only supports these settings */ 753 bridge_state->input_bus_cfg.flags |= DRM_BUS_FLAG_DE_HIGH | 754 DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE; 755 bridge_state->input_bus_cfg.flags &= 756 ~DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE; 757 } 758 759 return 0; 760 } 761 762 static 763 void it66121_bridge_mode_set(struct drm_bridge *bridge, 764 const struct drm_display_mode *mode, 765 const struct drm_display_mode *adjusted_mode) 766 { 767 u8 buf[HDMI_INFOFRAME_SIZE(AVI)]; 768 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 769 int ret; 770 771 mutex_lock(&ctx->lock); 772 773 ret = drm_hdmi_avi_infoframe_from_display_mode(&ctx->hdmi_avi_infoframe, ctx->connector, 774 adjusted_mode); 775 if (ret) { 776 DRM_ERROR("Failed to setup AVI infoframe: %d\n", ret); 777 goto unlock; 778 } 779 780 ret = hdmi_avi_infoframe_pack(&ctx->hdmi_avi_infoframe, buf, sizeof(buf)); 781 if (ret < 0) { 782 DRM_ERROR("Failed to pack infoframe: %d\n", ret); 783 goto unlock; 784 } 785 786 /* Write new AVI infoframe packet */ 787 ret = regmap_bulk_write(ctx->regmap, IT66121_AVIINFO_DB1_REG, 788 &buf[HDMI_INFOFRAME_HEADER_SIZE], 789 HDMI_AVI_INFOFRAME_SIZE); 790 if (ret) 791 goto unlock; 792 793 if (regmap_write(ctx->regmap, IT66121_AVIINFO_CSUM_REG, buf[3])) 794 goto unlock; 795 796 /* Enable AVI infoframe */ 797 if (regmap_write(ctx->regmap, IT66121_AVI_INFO_PKT_REG, 798 IT66121_AVI_INFO_PKT_ON | IT66121_AVI_INFO_PKT_RPT)) 799 goto unlock; 800 801 /* Set TX mode to HDMI */ 802 if (regmap_write(ctx->regmap, IT66121_HDMI_MODE_REG, IT66121_HDMI_MODE_HDMI)) 803 goto unlock; 804 805 if (ctx->info->id == ID_IT66121 && 806 regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, 807 IT66121_CLK_BANK_PWROFF_TXCLK, 808 IT66121_CLK_BANK_PWROFF_TXCLK)) { 809 goto unlock; 810 } 811 812 if (it66121_configure_input(ctx)) 813 goto unlock; 814 815 if (it66121_configure_afe(ctx, adjusted_mode)) 816 goto unlock; 817 818 if (ctx->info->id == ID_IT66121 && 819 regmap_write_bits(ctx->regmap, IT66121_CLK_BANK_REG, 820 IT66121_CLK_BANK_PWROFF_TXCLK, 0)) { 821 goto unlock; 822 } 823 824 unlock: 825 mutex_unlock(&ctx->lock); 826 } 827 828 static enum drm_mode_status it66121_bridge_mode_valid(struct drm_bridge *bridge, 829 const struct drm_display_info *info, 830 const struct drm_display_mode *mode) 831 { 832 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 833 unsigned long max_clock; 834 835 max_clock = (ctx->bus_width == 12) ? 74250 : 148500; 836 837 if (mode->clock > max_clock) 838 return MODE_CLOCK_HIGH; 839 840 if (mode->clock < 25000) 841 return MODE_CLOCK_LOW; 842 843 return MODE_OK; 844 } 845 846 static enum drm_connector_status 847 it66121_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 848 { 849 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 850 851 return it66121_is_hpd_detect(ctx) ? connector_status_connected 852 : connector_status_disconnected; 853 } 854 855 static void it66121_bridge_hpd_enable(struct drm_bridge *bridge) 856 { 857 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 858 int ret; 859 860 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, IT66121_INT_MASK1_HPD, 0); 861 if (ret) 862 dev_err(ctx->dev, "failed to enable HPD IRQ\n"); 863 } 864 865 static void it66121_bridge_hpd_disable(struct drm_bridge *bridge) 866 { 867 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 868 int ret; 869 870 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, 871 IT66121_INT_MASK1_HPD, IT66121_INT_MASK1_HPD); 872 if (ret) 873 dev_err(ctx->dev, "failed to disable HPD IRQ\n"); 874 } 875 876 static const struct drm_edid *it66121_bridge_edid_read(struct drm_bridge *bridge, 877 struct drm_connector *connector) 878 { 879 struct it66121_ctx *ctx = container_of(bridge, struct it66121_ctx, bridge); 880 const struct drm_edid *drm_edid; 881 int ret; 882 883 mutex_lock(&ctx->lock); 884 ret = it66121_preamble_ddc(ctx); 885 if (ret) { 886 drm_edid = NULL; 887 goto out_unlock; 888 } 889 890 ret = regmap_write(ctx->regmap, IT66121_DDC_HEADER_REG, 891 IT66121_DDC_HEADER_EDID); 892 if (ret) { 893 drm_edid = NULL; 894 goto out_unlock; 895 } 896 897 drm_edid = drm_edid_read_custom(connector, it66121_get_edid_block, ctx); 898 899 out_unlock: 900 mutex_unlock(&ctx->lock); 901 902 return drm_edid; 903 } 904 905 static const struct drm_bridge_funcs it66121_bridge_funcs = { 906 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 907 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 908 .atomic_reset = drm_atomic_helper_bridge_reset, 909 .attach = it66121_bridge_attach, 910 .atomic_get_output_bus_fmts = it66121_bridge_atomic_get_output_bus_fmts, 911 .atomic_get_input_bus_fmts = it66121_bridge_atomic_get_input_bus_fmts, 912 .atomic_enable = it66121_bridge_enable, 913 .atomic_disable = it66121_bridge_disable, 914 .atomic_check = it66121_bridge_check, 915 .mode_set = it66121_bridge_mode_set, 916 .mode_valid = it66121_bridge_mode_valid, 917 .detect = it66121_bridge_detect, 918 .edid_read = it66121_bridge_edid_read, 919 .hpd_enable = it66121_bridge_hpd_enable, 920 .hpd_disable = it66121_bridge_hpd_disable, 921 }; 922 923 static irqreturn_t it66121_irq_threaded_handler(int irq, void *dev_id) 924 { 925 int ret; 926 unsigned int val; 927 struct it66121_ctx *ctx = dev_id; 928 struct device *dev = ctx->dev; 929 enum drm_connector_status status; 930 bool event = false; 931 932 mutex_lock(&ctx->lock); 933 934 ret = regmap_read(ctx->regmap, IT66121_SYS_STATUS_REG, &val); 935 if (ret) 936 goto unlock; 937 938 if (!(val & IT66121_SYS_STATUS_ACTIVE_IRQ)) 939 goto unlock; 940 941 ret = regmap_read(ctx->regmap, IT66121_INT_STATUS1_REG, &val); 942 if (ret) { 943 dev_err(dev, "Cannot read STATUS1_REG %d\n", ret); 944 } else if (val & IT66121_INT_STATUS1_HPD_STATUS) { 945 regmap_write_bits(ctx->regmap, IT66121_INT_CLR1_REG, 946 IT66121_INT_CLR1_HPD, IT66121_INT_CLR1_HPD); 947 948 status = it66121_is_hpd_detect(ctx) ? connector_status_connected 949 : connector_status_disconnected; 950 951 event = true; 952 } 953 954 regmap_write_bits(ctx->regmap, IT66121_SYS_STATUS_REG, 955 IT66121_SYS_STATUS_CLEAR_IRQ, 956 IT66121_SYS_STATUS_CLEAR_IRQ); 957 958 unlock: 959 mutex_unlock(&ctx->lock); 960 961 if (event) 962 drm_bridge_hpd_notify(&ctx->bridge, status); 963 964 return IRQ_HANDLED; 965 } 966 967 static int it661221_set_chstat(struct it66121_ctx *ctx, u8 iec60958_chstat[]) 968 { 969 int ret; 970 971 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_MODE_REG, iec60958_chstat[0] & 0x7C); 972 if (ret) 973 return ret; 974 975 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CAT_REG, iec60958_chstat[1]); 976 if (ret) 977 return ret; 978 979 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_SRCNUM_REG, iec60958_chstat[2] & 0x0F); 980 if (ret) 981 return ret; 982 983 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CHTNUM_REG, 984 (iec60958_chstat[2] >> 4) & 0x0F); 985 if (ret) 986 return ret; 987 988 ret = regmap_write(ctx->regmap, IT66121_AUD_CHST_CA_FS_REG, iec60958_chstat[3]); 989 if (ret) 990 return ret; 991 992 return regmap_write(ctx->regmap, IT66121_AUD_CHST_OFS_WL_REG, iec60958_chstat[4]); 993 } 994 995 static int it661221_set_lpcm_audio(struct it66121_ctx *ctx, u8 audio_src_num, u8 audio_swl) 996 { 997 int ret; 998 unsigned int audio_enable = 0; 999 unsigned int audio_format = 0; 1000 1001 switch (audio_swl) { 1002 case 16: 1003 audio_enable |= IT66121_AUD_16BIT; 1004 break; 1005 case 18: 1006 audio_enable |= IT66121_AUD_18BIT; 1007 break; 1008 case 20: 1009 audio_enable |= IT66121_AUD_20BIT; 1010 break; 1011 case 24: 1012 default: 1013 audio_enable |= IT66121_AUD_24BIT; 1014 break; 1015 } 1016 1017 audio_format |= 0x40; 1018 switch (audio_src_num) { 1019 case 4: 1020 audio_enable |= IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 | 1021 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0; 1022 break; 1023 case 3: 1024 audio_enable |= IT66121_AUD_EN_I2S2 | IT66121_AUD_EN_I2S1 | 1025 IT66121_AUD_EN_I2S0; 1026 break; 1027 case 2: 1028 audio_enable |= IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0; 1029 break; 1030 case 1: 1031 default: 1032 audio_format &= ~0x40; 1033 audio_enable |= IT66121_AUD_EN_I2S0; 1034 break; 1035 } 1036 1037 audio_format |= 0x01; 1038 ctx->audio.ch_enable = audio_enable; 1039 1040 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, audio_enable & 0xF0); 1041 if (ret) 1042 return ret; 1043 1044 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL1_REG, audio_format); 1045 if (ret) 1046 return ret; 1047 1048 ret = regmap_write(ctx->regmap, IT66121_AUD_FIFOMAP_REG, 0xE4); 1049 if (ret) 1050 return ret; 1051 1052 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL3_REG, 0x00); 1053 if (ret) 1054 return ret; 1055 1056 ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0x00); 1057 if (ret) 1058 return ret; 1059 1060 return regmap_write(ctx->regmap, IT66121_AUD_HDAUDIO_REG, 0x00); 1061 } 1062 1063 static int it661221_set_ncts(struct it66121_ctx *ctx, u8 fs) 1064 { 1065 int ret; 1066 unsigned int n; 1067 1068 switch (fs) { 1069 case IT66121_AUD_FS_32K: 1070 n = 4096; 1071 break; 1072 case IT66121_AUD_FS_44P1K: 1073 n = 6272; 1074 break; 1075 case IT66121_AUD_FS_48K: 1076 n = 6144; 1077 break; 1078 case IT66121_AUD_FS_88P2K: 1079 n = 12544; 1080 break; 1081 case IT66121_AUD_FS_96K: 1082 n = 12288; 1083 break; 1084 case IT66121_AUD_FS_176P4K: 1085 n = 25088; 1086 break; 1087 case IT66121_AUD_FS_192K: 1088 n = 24576; 1089 break; 1090 case IT66121_AUD_FS_768K: 1091 n = 24576; 1092 break; 1093 default: 1094 n = 6144; 1095 break; 1096 } 1097 1098 ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N0_REG, (u8)((n) & 0xFF)); 1099 if (ret) 1100 return ret; 1101 1102 ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N1_REG, (u8)((n >> 8) & 0xFF)); 1103 if (ret) 1104 return ret; 1105 1106 ret = regmap_write(ctx->regmap, IT66121_AUD_PKT_N2_REG, (u8)((n >> 16) & 0xF)); 1107 if (ret) 1108 return ret; 1109 1110 if (ctx->audio.auto_cts) { 1111 u8 loop_cnt = 255; 1112 u8 cts_stable_cnt = 0; 1113 unsigned int sum_cts = 0; 1114 unsigned int cts = 0; 1115 unsigned int last_cts = 0; 1116 unsigned int diff; 1117 unsigned int val; 1118 1119 while (loop_cnt--) { 1120 msleep(30); 1121 regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT2_REG, &val); 1122 cts = val << 12; 1123 regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT1_REG, &val); 1124 cts |= val << 4; 1125 regmap_read(ctx->regmap, IT66121_AUD_PKT_CTS_CNT0_REG, &val); 1126 cts |= val >> 4; 1127 if (cts == 0) { 1128 continue; 1129 } else { 1130 if (last_cts > cts) 1131 diff = last_cts - cts; 1132 else 1133 diff = cts - last_cts; 1134 last_cts = cts; 1135 if (diff < 5) { 1136 cts_stable_cnt++; 1137 sum_cts += cts; 1138 } else { 1139 cts_stable_cnt = 0; 1140 sum_cts = 0; 1141 continue; 1142 } 1143 1144 if (cts_stable_cnt >= 32) { 1145 last_cts = (sum_cts >> 5); 1146 break; 1147 } 1148 } 1149 } 1150 1151 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS0_REG, (u8)((last_cts) & 0xFF)); 1152 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS1_REG, (u8)((last_cts >> 8) & 0xFF)); 1153 regmap_write(ctx->regmap, IT66121_AUD_PKT_CTS2_REG, (u8)((last_cts >> 16) & 0x0F)); 1154 } 1155 1156 ret = regmap_write(ctx->regmap, 0xF8, 0xC3); 1157 if (ret) 1158 return ret; 1159 1160 ret = regmap_write(ctx->regmap, 0xF8, 0xA5); 1161 if (ret) 1162 return ret; 1163 1164 if (ctx->audio.auto_cts) { 1165 ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG, 1166 IT66121_PKT_CTS_CTRL_SEL, 1167 1); 1168 } else { 1169 ret = regmap_write_bits(ctx->regmap, IT66121_PKT_CTS_CTRL_REG, 1170 IT66121_PKT_CTS_CTRL_SEL, 1171 0); 1172 } 1173 1174 if (ret) 1175 return ret; 1176 1177 return regmap_write(ctx->regmap, 0xF8, 0xFF); 1178 } 1179 1180 static int it661221_audio_output_enable(struct it66121_ctx *ctx, bool enable) 1181 { 1182 int ret; 1183 1184 if (enable) { 1185 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 1186 IT66121_SW_RST_AUD | IT66121_SW_RST_AREF, 1187 0); 1188 if (ret) 1189 return ret; 1190 1191 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG, 1192 IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 | 1193 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0, 1194 ctx->audio.ch_enable); 1195 } else { 1196 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG, 1197 IT66121_AUD_EN_I2S3 | IT66121_AUD_EN_I2S2 | 1198 IT66121_AUD_EN_I2S1 | IT66121_AUD_EN_I2S0, 1199 ctx->audio.ch_enable & 0xF0); 1200 if (ret) 1201 return ret; 1202 1203 ret = regmap_write_bits(ctx->regmap, IT66121_SW_RST_REG, 1204 IT66121_SW_RST_AUD | IT66121_SW_RST_AREF, 1205 IT66121_SW_RST_AUD | IT66121_SW_RST_AREF); 1206 } 1207 1208 return ret; 1209 } 1210 1211 static int it661221_audio_ch_enable(struct it66121_ctx *ctx, bool enable) 1212 { 1213 int ret; 1214 1215 if (enable) { 1216 ret = regmap_write(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 0); 1217 if (ret) 1218 return ret; 1219 1220 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable); 1221 } else { 1222 ret = regmap_write(ctx->regmap, IT66121_AUD_CTRL0_REG, ctx->audio.ch_enable & 0xF0); 1223 } 1224 1225 return ret; 1226 } 1227 1228 static int it66121_audio_hw_params(struct device *dev, void *data, 1229 struct hdmi_codec_daifmt *daifmt, 1230 struct hdmi_codec_params *params) 1231 { 1232 u8 fs; 1233 u8 swl; 1234 int ret; 1235 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1236 static u8 iec60958_chstat[5]; 1237 unsigned int channels = params->channels; 1238 unsigned int sample_rate = params->sample_rate; 1239 unsigned int sample_width = params->sample_width; 1240 1241 mutex_lock(&ctx->lock); 1242 dev_dbg(dev, "%s: %u, %u, %u, %u\n", __func__, 1243 daifmt->fmt, sample_rate, sample_width, channels); 1244 1245 switch (daifmt->fmt) { 1246 case HDMI_I2S: 1247 dev_dbg(dev, "Using HDMI I2S\n"); 1248 break; 1249 default: 1250 dev_err(dev, "Invalid or unsupported DAI format %d\n", daifmt->fmt); 1251 ret = -EINVAL; 1252 goto out; 1253 } 1254 1255 // Set audio clock recovery (N/CTS) 1256 ret = regmap_write(ctx->regmap, IT66121_CLK_CTRL0_REG, 1257 IT66121_CLK_CTRL0_AUTO_OVER_SAMPLING | 1258 IT66121_CLK_CTRL0_EXT_MCLK_256FS | 1259 IT66121_CLK_CTRL0_AUTO_IPCLK); 1260 if (ret) 1261 goto out; 1262 1263 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_CTRL0_REG, 1264 IT66121_AUD_CTRL0_AUD_SEL, 0); // remove spdif selection 1265 if (ret) 1266 goto out; 1267 1268 switch (sample_rate) { 1269 case 44100L: 1270 fs = IT66121_AUD_FS_44P1K; 1271 break; 1272 case 88200L: 1273 fs = IT66121_AUD_FS_88P2K; 1274 break; 1275 case 176400L: 1276 fs = IT66121_AUD_FS_176P4K; 1277 break; 1278 case 32000L: 1279 fs = IT66121_AUD_FS_32K; 1280 break; 1281 case 48000L: 1282 fs = IT66121_AUD_FS_48K; 1283 break; 1284 case 96000L: 1285 fs = IT66121_AUD_FS_96K; 1286 break; 1287 case 192000L: 1288 fs = IT66121_AUD_FS_192K; 1289 break; 1290 case 768000L: 1291 fs = IT66121_AUD_FS_768K; 1292 break; 1293 default: 1294 fs = IT66121_AUD_FS_48K; 1295 break; 1296 } 1297 1298 ctx->audio.fs = fs; 1299 ret = it661221_set_ncts(ctx, fs); 1300 if (ret) { 1301 dev_err(dev, "Failed to set N/CTS: %d\n", ret); 1302 goto out; 1303 } 1304 1305 // Set audio format register (except audio channel enable) 1306 ret = it661221_set_lpcm_audio(ctx, (channels + 1) / 2, sample_width); 1307 if (ret) { 1308 dev_err(dev, "Failed to set LPCM audio: %d\n", ret); 1309 goto out; 1310 } 1311 1312 // Set audio channel status 1313 iec60958_chstat[0] = 0; 1314 if ((channels + 1) / 2 == 1) 1315 iec60958_chstat[0] |= 0x1; 1316 iec60958_chstat[0] &= ~(1 << 1); 1317 iec60958_chstat[1] = 0; 1318 iec60958_chstat[2] = (channels + 1) / 2; 1319 iec60958_chstat[2] |= (channels << 4) & 0xF0; 1320 iec60958_chstat[3] = fs; 1321 1322 switch (sample_width) { 1323 case 21L: 1324 swl = IT66121_AUD_SWL_21BIT; 1325 break; 1326 case 24L: 1327 swl = IT66121_AUD_SWL_24BIT; 1328 break; 1329 case 23L: 1330 swl = IT66121_AUD_SWL_23BIT; 1331 break; 1332 case 22L: 1333 swl = IT66121_AUD_SWL_22BIT; 1334 break; 1335 case 20L: 1336 swl = IT66121_AUD_SWL_20BIT; 1337 break; 1338 case 17L: 1339 swl = IT66121_AUD_SWL_17BIT; 1340 break; 1341 case 19L: 1342 swl = IT66121_AUD_SWL_19BIT; 1343 break; 1344 case 18L: 1345 swl = IT66121_AUD_SWL_18BIT; 1346 break; 1347 case 16L: 1348 swl = IT66121_AUD_SWL_16BIT; 1349 break; 1350 default: 1351 swl = IT66121_AUD_SWL_NOT_INDICATED; 1352 break; 1353 } 1354 1355 iec60958_chstat[4] = (((~fs) << 4) & 0xF0) | swl; 1356 ret = it661221_set_chstat(ctx, iec60958_chstat); 1357 if (ret) { 1358 dev_err(dev, "Failed to set channel status: %d\n", ret); 1359 goto out; 1360 } 1361 1362 // Enable audio channel enable while input clock stable (if SPDIF). 1363 ret = it661221_audio_ch_enable(ctx, true); 1364 if (ret) { 1365 dev_err(dev, "Failed to enable audio channel: %d\n", ret); 1366 goto out; 1367 } 1368 1369 ret = regmap_write_bits(ctx->regmap, IT66121_INT_MASK1_REG, 1370 IT66121_INT_MASK1_AUD_OVF, 1371 0); 1372 if (ret) 1373 goto out; 1374 1375 dev_dbg(dev, "HDMI audio enabled.\n"); 1376 out: 1377 mutex_unlock(&ctx->lock); 1378 1379 return ret; 1380 } 1381 1382 static int it66121_audio_startup(struct device *dev, void *data) 1383 { 1384 int ret; 1385 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1386 1387 dev_dbg(dev, "%s\n", __func__); 1388 1389 mutex_lock(&ctx->lock); 1390 ret = it661221_audio_output_enable(ctx, true); 1391 if (ret) 1392 dev_err(dev, "Failed to enable audio output: %d\n", ret); 1393 1394 mutex_unlock(&ctx->lock); 1395 1396 return ret; 1397 } 1398 1399 static void it66121_audio_shutdown(struct device *dev, void *data) 1400 { 1401 int ret; 1402 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1403 1404 dev_dbg(dev, "%s\n", __func__); 1405 1406 mutex_lock(&ctx->lock); 1407 ret = it661221_audio_output_enable(ctx, false); 1408 if (ret) 1409 dev_err(dev, "Failed to disable audio output: %d\n", ret); 1410 1411 mutex_unlock(&ctx->lock); 1412 } 1413 1414 static int it66121_audio_mute(struct device *dev, void *data, 1415 bool enable, int direction) 1416 { 1417 int ret; 1418 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1419 1420 dev_dbg(dev, "%s: enable=%s, direction=%d\n", 1421 __func__, enable ? "true" : "false", direction); 1422 1423 mutex_lock(&ctx->lock); 1424 1425 if (enable) { 1426 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 1427 IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 | 1428 IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3, 1429 IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 | 1430 IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3); 1431 } else { 1432 ret = regmap_write_bits(ctx->regmap, IT66121_AUD_SRCVALID_FLAT_REG, 1433 IT66121_AUD_FLAT_SRC0 | IT66121_AUD_FLAT_SRC1 | 1434 IT66121_AUD_FLAT_SRC2 | IT66121_AUD_FLAT_SRC3, 1435 0); 1436 } 1437 1438 mutex_unlock(&ctx->lock); 1439 1440 return ret; 1441 } 1442 1443 static int it66121_audio_get_eld(struct device *dev, void *data, 1444 u8 *buf, size_t len) 1445 { 1446 struct it66121_ctx *ctx = dev_get_drvdata(dev); 1447 1448 mutex_lock(&ctx->lock); 1449 if (!ctx->connector) { 1450 /* Pass en empty ELD if connector not available */ 1451 dev_dbg(dev, "No connector present, passing empty EDID data"); 1452 memset(buf, 0, len); 1453 } else { 1454 mutex_lock(&ctx->connector->eld_mutex); 1455 memcpy(buf, ctx->connector->eld, 1456 min(sizeof(ctx->connector->eld), len)); 1457 mutex_unlock(&ctx->connector->eld_mutex); 1458 } 1459 mutex_unlock(&ctx->lock); 1460 1461 return 0; 1462 } 1463 1464 static const struct hdmi_codec_ops it66121_audio_codec_ops = { 1465 .hw_params = it66121_audio_hw_params, 1466 .audio_startup = it66121_audio_startup, 1467 .audio_shutdown = it66121_audio_shutdown, 1468 .mute_stream = it66121_audio_mute, 1469 .get_eld = it66121_audio_get_eld, 1470 }; 1471 1472 static int it66121_audio_codec_init(struct it66121_ctx *ctx, struct device *dev) 1473 { 1474 struct hdmi_codec_pdata codec_data = { 1475 .ops = &it66121_audio_codec_ops, 1476 .i2s = 1, /* Only i2s support for now */ 1477 .spdif = 0, 1478 .max_i2s_channels = 8, 1479 .no_capture_mute = 1, 1480 }; 1481 1482 dev_dbg(dev, "%s\n", __func__); 1483 1484 if (!of_property_present(dev->of_node, "#sound-dai-cells")) { 1485 dev_info(dev, "No \"#sound-dai-cells\", no audio\n"); 1486 return 0; 1487 } 1488 1489 ctx->audio.pdev = platform_device_register_data(dev, 1490 HDMI_CODEC_DRV_NAME, 1491 PLATFORM_DEVID_AUTO, 1492 &codec_data, 1493 sizeof(codec_data)); 1494 1495 if (IS_ERR(ctx->audio.pdev)) { 1496 dev_err(dev, "Failed to initialize HDMI audio codec: %d\n", 1497 PTR_ERR_OR_ZERO(ctx->audio.pdev)); 1498 } 1499 1500 return PTR_ERR_OR_ZERO(ctx->audio.pdev); 1501 } 1502 1503 static const char * const it66121_supplies[] = { 1504 "vcn33", "vcn18", "vrf12" 1505 }; 1506 1507 static int it66121_probe(struct i2c_client *client) 1508 { 1509 u32 revision_id, vendor_ids[2] = { 0 }, device_ids[2] = { 0 }; 1510 struct device_node *ep; 1511 int ret; 1512 struct it66121_ctx *ctx; 1513 struct device *dev = &client->dev; 1514 1515 if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) { 1516 dev_err(dev, "I2C check functionality failed.\n"); 1517 return -ENXIO; 1518 } 1519 1520 ctx = devm_drm_bridge_alloc(dev, struct it66121_ctx, bridge, 1521 &it66121_bridge_funcs); 1522 if (IS_ERR(ctx)) 1523 return PTR_ERR(ctx); 1524 1525 ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 1526 if (!ep) 1527 return -EINVAL; 1528 1529 ctx->dev = dev; 1530 ctx->client = client; 1531 ctx->info = i2c_get_match_data(client); 1532 1533 of_property_read_u32(ep, "bus-width", &ctx->bus_width); 1534 of_node_put(ep); 1535 1536 if (ctx->bus_width != 12 && ctx->bus_width != 24) 1537 return -EINVAL; 1538 1539 ep = of_graph_get_remote_node(dev->of_node, 1, -1); 1540 if (!ep) { 1541 dev_err(ctx->dev, "The endpoint is unconnected\n"); 1542 return -EINVAL; 1543 } 1544 1545 ctx->next_bridge = of_drm_find_bridge(ep); 1546 of_node_put(ep); 1547 if (!ctx->next_bridge) { 1548 dev_dbg(ctx->dev, "Next bridge not found, deferring probe\n"); 1549 return -EPROBE_DEFER; 1550 } 1551 1552 i2c_set_clientdata(client, ctx); 1553 mutex_init(&ctx->lock); 1554 1555 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it66121_supplies), 1556 it66121_supplies); 1557 if (ret) { 1558 dev_err(dev, "Failed to enable power supplies\n"); 1559 return ret; 1560 } 1561 1562 it66121_hw_reset(ctx); 1563 1564 ctx->regmap = devm_regmap_init_i2c(client, &it66121_regmap_config); 1565 if (IS_ERR(ctx->regmap)) 1566 return PTR_ERR(ctx->regmap); 1567 1568 regmap_read(ctx->regmap, IT66121_VENDOR_ID0_REG, &vendor_ids[0]); 1569 regmap_read(ctx->regmap, IT66121_VENDOR_ID1_REG, &vendor_ids[1]); 1570 regmap_read(ctx->regmap, IT66121_DEVICE_ID0_REG, &device_ids[0]); 1571 regmap_read(ctx->regmap, IT66121_DEVICE_ID1_REG, &device_ids[1]); 1572 1573 /* Revision is shared with DEVICE_ID1 */ 1574 revision_id = FIELD_GET(IT66121_REVISION_MASK, device_ids[1]); 1575 device_ids[1] &= IT66121_DEVICE_ID1_MASK; 1576 1577 if ((vendor_ids[1] << 8 | vendor_ids[0]) != ctx->info->vid || 1578 (device_ids[1] << 8 | device_ids[0]) != ctx->info->pid) { 1579 return -ENODEV; 1580 } 1581 1582 ctx->bridge.of_node = dev->of_node; 1583 ctx->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 1584 ctx->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID; 1585 if (client->irq > 0) { 1586 ctx->bridge.ops |= DRM_BRIDGE_OP_HPD; 1587 1588 ret = devm_request_threaded_irq(dev, client->irq, NULL, 1589 it66121_irq_threaded_handler, 1590 IRQF_ONESHOT, dev_name(dev), 1591 ctx); 1592 if (ret < 0) { 1593 dev_err(dev, "Failed to request irq %d:%d\n", client->irq, ret); 1594 return ret; 1595 } 1596 } 1597 1598 it66121_audio_codec_init(ctx, dev); 1599 1600 drm_bridge_add(&ctx->bridge); 1601 1602 dev_info(ctx->dev, "IT66121 revision %d probed\n", revision_id); 1603 1604 return 0; 1605 } 1606 1607 static void it66121_remove(struct i2c_client *client) 1608 { 1609 struct it66121_ctx *ctx = i2c_get_clientdata(client); 1610 1611 drm_bridge_remove(&ctx->bridge); 1612 mutex_destroy(&ctx->lock); 1613 } 1614 1615 static const struct it66121_chip_info it66121_chip_info = { 1616 .id = ID_IT66121, 1617 .vid = 0x4954, 1618 .pid = 0x0612, 1619 }; 1620 1621 static const struct it66121_chip_info it6610_chip_info = { 1622 .id = ID_IT6610, 1623 .vid = 0xca00, 1624 .pid = 0x0611, 1625 }; 1626 1627 static const struct of_device_id it66121_dt_match[] = { 1628 { .compatible = "ite,it66121", &it66121_chip_info }, 1629 { .compatible = "ite,it6610", &it6610_chip_info }, 1630 { } 1631 }; 1632 MODULE_DEVICE_TABLE(of, it66121_dt_match); 1633 1634 static const struct i2c_device_id it66121_id[] = { 1635 { "it66121", (kernel_ulong_t) &it66121_chip_info }, 1636 { "it6610", (kernel_ulong_t) &it6610_chip_info }, 1637 { } 1638 }; 1639 MODULE_DEVICE_TABLE(i2c, it66121_id); 1640 1641 static struct i2c_driver it66121_driver = { 1642 .driver = { 1643 .name = "it66121", 1644 .of_match_table = it66121_dt_match, 1645 }, 1646 .probe = it66121_probe, 1647 .remove = it66121_remove, 1648 .id_table = it66121_id, 1649 }; 1650 1651 module_i2c_driver(it66121_driver); 1652 1653 MODULE_AUTHOR("Phong LE"); 1654 MODULE_DESCRIPTION("IT66121 HDMI transmitter driver"); 1655 MODULE_LICENSE("GPL v2"); 1656