1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2024 NXP 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/bits.h> 8 #include <linux/delay.h> 9 #include <linux/gpio/consumer.h> 10 #include <linux/hdmi.h> 11 #include <linux/i2c.h> 12 #include <linux/media-bus-format.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/regmap.h> 16 #include <linux/regulator/consumer.h> 17 18 #include <drm/display/drm_hdmi_helper.h> 19 #include <drm/display/drm_hdmi_state_helper.h> 20 #include <drm/drm_atomic.h> 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_atomic_state_helper.h> 23 #include <drm/drm_bridge.h> 24 #include <drm/drm_bridge_connector.h> 25 #include <drm/drm_connector.h> 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_edid.h> 28 #include <drm/drm_of.h> 29 #include <drm/drm_probe_helper.h> 30 31 /* ----------------------------------------------------------------------------- 32 * LVDS registers 33 */ 34 35 /* LVDS software reset registers */ 36 #define LVDS_REG_05 0x05 37 #define REG_SOFT_P_RST BIT(1) 38 39 /* LVDS system configuration registers */ 40 /* 0x0b */ 41 #define LVDS_REG_0B 0x0b 42 #define REG_SSC_PCLK_RF BIT(0) 43 #define REG_LVDS_IN_SWAP BIT(1) 44 45 /* LVDS test pattern gen control registers */ 46 /* 0x2c */ 47 #define LVDS_REG_2C 0x2c 48 #define REG_COL_DEP GENMASK(1, 0) 49 #define BIT8 FIELD_PREP(REG_COL_DEP, 1) 50 #define OUT_MAP BIT(4) 51 #define VESA BIT(4) 52 #define JEIDA 0 53 #define REG_DESSC_ENB BIT(6) 54 #define DMODE BIT(7) 55 #define DISO BIT(7) 56 #define SISO 0 57 58 #define LVDS_REG_3C 0x3c 59 #define LVDS_REG_3F 0x3f 60 #define LVDS_REG_47 0x47 61 #define LVDS_REG_48 0x48 62 #define LVDS_REG_4F 0x4f 63 #define LVDS_REG_52 0x52 64 65 /* ----------------------------------------------------------------------------- 66 * HDMI registers are separated into three banks: 67 * 1) HDMI register common bank: 0x00 ~ 0x2f 68 */ 69 70 /* HDMI genernal registers */ 71 #define HDMI_REG_SW_RST 0x04 72 #define SOFTREF_RST BIT(5) 73 #define SOFTA_RST BIT(4) 74 #define SOFTV_RST BIT(3) 75 #define AUD_RST BIT(2) 76 #define HDCP_RST BIT(0) 77 #define HDMI_RST_ALL (SOFTREF_RST | SOFTA_RST | SOFTV_RST | \ 78 AUD_RST | HDCP_RST) 79 80 #define HDMI_REG_SYS_STATUS 0x0e 81 #define HPDETECT BIT(6) 82 #define TXVIDSTABLE BIT(4) 83 84 #define HDMI_REG_BANK_CTRL 0x0f 85 #define REG_BANK_SEL BIT(0) 86 87 /* HDMI System DDC control registers */ 88 #define HDMI_REG_DDC_MASTER_CTRL 0x10 89 #define MASTER_SEL_HOST BIT(0) 90 91 #define HDMI_REG_DDC_HEADER 0x11 92 93 #define HDMI_REG_DDC_REQOFF 0x12 94 #define HDMI_REG_DDC_REQCOUNT 0x13 95 #define HDMI_REG_DDC_EDIDSEG 0x14 96 97 #define HDMI_REG_DDC_CMD 0x15 98 #define DDC_CMD_EDID_READ 0x3 99 #define DDC_CMD_FIFO_CLR 0x9 100 101 #define HDMI_REG_DDC_STATUS 0x16 102 #define DDC_DONE BIT(7) 103 #define DDC_NOACK BIT(5) 104 #define DDC_WAITBUS BIT(4) 105 #define DDC_ARBILOSE BIT(3) 106 #define DDC_ERROR (DDC_NOACK | DDC_WAITBUS | DDC_ARBILOSE) 107 108 #define HDMI_DDC_FIFO_BYTES 32 109 #define HDMI_REG_DDC_READFIFO 0x17 110 #define HDMI_REG_LVDS_PORT 0x1d /* LVDS input control I2C addr */ 111 #define HDMI_REG_LVDS_PORT_EN 0x1e 112 #define LVDS_INPUT_CTRL_I2C_ADDR 0x33 113 114 /* ----------------------------------------------------------------------------- 115 * 2) HDMI register bank0: 0x30 ~ 0xff 116 */ 117 118 /* HDMI AFE registers */ 119 #define HDMI_REG_AFE_DRV_CTRL 0x61 120 #define AFE_DRV_PWD BIT(5) 121 #define AFE_DRV_RST BIT(4) 122 123 #define HDMI_REG_AFE_XP_CTRL 0x62 124 #define AFE_XP_GAINBIT BIT(7) 125 #define AFE_XP_ER0 BIT(4) 126 #define AFE_XP_RESETB BIT(3) 127 128 #define HDMI_REG_AFE_ISW_CTRL 0x63 129 130 #define HDMI_REG_AFE_IP_CTRL 0x64 131 #define AFE_IP_GAINBIT BIT(7) 132 #define AFE_IP_ER0 BIT(3) 133 #define AFE_IP_RESETB BIT(2) 134 135 /* HDMI input data format registers */ 136 #define HDMI_REG_INPUT_MODE 0x70 137 #define IN_RGB 0x00 138 139 /* HDMI general control registers */ 140 #define HDMI_REG_HDMI_MODE 0xc0 141 #define TX_HDMI_MODE BIT(0) 142 143 #define HDMI_REG_GCP 0xc1 144 #define AVMUTE BIT(0) 145 #define HDMI_COLOR_DEPTH GENMASK(6, 4) 146 #define HDMI_COLOR_DEPTH_24 FIELD_PREP(HDMI_COLOR_DEPTH, 4) 147 148 #define HDMI_REG_PKT_GENERAL_CTRL 0xc6 149 #define HDMI_REG_PKT_NULL_CTRL 0xc9 150 #define HDMI_REG_AVI_INFOFRM_CTRL 0xcd 151 #define ENABLE_PKT BIT(0) 152 #define REPEAT_PKT BIT(1) 153 154 /* ----------------------------------------------------------------------------- 155 * 3) HDMI register bank1: 0x130 ~ 0x1ff (HDMI packet registers) 156 */ 157 158 /* NULL packet registers */ 159 /* Header Byte(HB): n = 0 ~ 2 */ 160 #define HDMI_REG_PKT_HB(n) (0x138 + (n)) 161 /* Packet Byte(PB): n = 0 ~ 27(HDMI_MAX_INFOFRAME_SIZE), n = 0 for checksum */ 162 #define HDMI_REG_PKT_PB(n) (0x13b + (n)) 163 164 /* AVI packet registers */ 165 #define HDMI_REG_AVI_DB1 0x158 166 #define HDMI_REG_AVI_DB2 0x159 167 #define HDMI_REG_AVI_DB3 0x15a 168 #define HDMI_REG_AVI_DB4 0x15b 169 #define HDMI_REG_AVI_DB5 0x15c 170 #define HDMI_REG_AVI_CSUM 0x15d 171 #define HDMI_REG_AVI_DB6 0x15e 172 #define HDMI_REG_AVI_DB7 0x15f 173 #define HDMI_REG_AVI_DB8 0x160 174 #define HDMI_REG_AVI_DB9 0x161 175 #define HDMI_REG_AVI_DB10 0x162 176 #define HDMI_REG_AVI_DB11 0x163 177 #define HDMI_REG_AVI_DB12 0x164 178 #define HDMI_REG_AVI_DB13 0x165 179 180 #define HDMI_AVI_DB_CHUNK1_SIZE (HDMI_REG_AVI_DB5 - HDMI_REG_AVI_DB1 + 1) 181 #define HDMI_AVI_DB_CHUNK2_SIZE (HDMI_REG_AVI_DB13 - HDMI_REG_AVI_DB6 + 1) 182 183 /* IT6263 data sheet Rev0.8: LVDS RX supports input clock rate up to 150MHz. */ 184 #define MAX_PIXEL_CLOCK_KHZ 150000 185 186 /* IT6263 programming guide Ver0.90: PCLK_HIGH for TMDS clock over 80MHz. */ 187 #define HIGH_PIXEL_CLOCK_KHZ 80000 188 189 /* 190 * IT6263 data sheet Rev0.8: HDMI TX supports link speeds of up to 2.25Gbps 191 * (link clock rate of 225MHz). 192 */ 193 #define MAX_HDMI_TMDS_CHAR_RATE_HZ 225000000 194 195 struct it6263 { 196 struct device *dev; 197 struct i2c_client *hdmi_i2c; 198 struct i2c_client *lvds_i2c; 199 struct regmap *hdmi_regmap; 200 struct regmap *lvds_regmap; 201 struct drm_bridge bridge; 202 struct drm_bridge *next_bridge; 203 struct gpio_desc *reset_gpio; 204 int lvds_data_mapping; 205 bool lvds_dual_link; 206 bool lvds_link12_swap; 207 }; 208 209 static inline struct it6263 *bridge_to_it6263(struct drm_bridge *bridge) 210 { 211 return container_of(bridge, struct it6263, bridge); 212 } 213 214 static bool it6263_hdmi_writeable_reg(struct device *dev, unsigned int reg) 215 { 216 switch (reg) { 217 case HDMI_REG_SW_RST: 218 case HDMI_REG_BANK_CTRL: 219 case HDMI_REG_DDC_MASTER_CTRL: 220 case HDMI_REG_DDC_HEADER: 221 case HDMI_REG_DDC_REQOFF: 222 case HDMI_REG_DDC_REQCOUNT: 223 case HDMI_REG_DDC_EDIDSEG: 224 case HDMI_REG_DDC_CMD: 225 case HDMI_REG_LVDS_PORT: 226 case HDMI_REG_LVDS_PORT_EN: 227 case HDMI_REG_AFE_DRV_CTRL: 228 case HDMI_REG_AFE_XP_CTRL: 229 case HDMI_REG_AFE_ISW_CTRL: 230 case HDMI_REG_AFE_IP_CTRL: 231 case HDMI_REG_INPUT_MODE: 232 case HDMI_REG_HDMI_MODE: 233 case HDMI_REG_GCP: 234 case HDMI_REG_PKT_GENERAL_CTRL: 235 case HDMI_REG_PKT_NULL_CTRL: 236 case HDMI_REG_AVI_INFOFRM_CTRL: 237 case HDMI_REG_PKT_HB(0) ... HDMI_REG_PKT_PB(HDMI_MAX_INFOFRAME_SIZE): 238 case HDMI_REG_AVI_DB1: 239 case HDMI_REG_AVI_DB2: 240 case HDMI_REG_AVI_DB3: 241 case HDMI_REG_AVI_DB4: 242 case HDMI_REG_AVI_DB5: 243 case HDMI_REG_AVI_CSUM: 244 case HDMI_REG_AVI_DB6: 245 case HDMI_REG_AVI_DB7: 246 case HDMI_REG_AVI_DB8: 247 case HDMI_REG_AVI_DB9: 248 case HDMI_REG_AVI_DB10: 249 case HDMI_REG_AVI_DB11: 250 case HDMI_REG_AVI_DB12: 251 case HDMI_REG_AVI_DB13: 252 return true; 253 default: 254 return false; 255 } 256 } 257 258 static bool it6263_hdmi_readable_reg(struct device *dev, unsigned int reg) 259 { 260 if (it6263_hdmi_writeable_reg(dev, reg)) 261 return true; 262 263 switch (reg) { 264 case HDMI_REG_SYS_STATUS: 265 case HDMI_REG_DDC_STATUS: 266 case HDMI_REG_DDC_READFIFO: 267 return true; 268 default: 269 return false; 270 } 271 } 272 273 static bool it6263_hdmi_volatile_reg(struct device *dev, unsigned int reg) 274 { 275 switch (reg) { 276 case HDMI_REG_SW_RST: 277 case HDMI_REG_SYS_STATUS: 278 case HDMI_REG_DDC_STATUS: 279 case HDMI_REG_DDC_READFIFO: 280 return true; 281 default: 282 return false; 283 } 284 } 285 286 static const struct regmap_range_cfg it6263_hdmi_range_cfg = { 287 .range_min = 0x00, 288 .range_max = HDMI_REG_AVI_DB13, 289 .selector_reg = HDMI_REG_BANK_CTRL, 290 .selector_mask = REG_BANK_SEL, 291 .selector_shift = 0, 292 .window_start = 0x00, 293 .window_len = 0x100, 294 }; 295 296 static const struct regmap_config it6263_hdmi_regmap_config = { 297 .name = "it6263-hdmi", 298 .reg_bits = 8, 299 .val_bits = 8, 300 .writeable_reg = it6263_hdmi_writeable_reg, 301 .readable_reg = it6263_hdmi_readable_reg, 302 .volatile_reg = it6263_hdmi_volatile_reg, 303 .max_register = HDMI_REG_AVI_DB13, 304 .ranges = &it6263_hdmi_range_cfg, 305 .num_ranges = 1, 306 .cache_type = REGCACHE_MAPLE, 307 }; 308 309 static bool it6263_lvds_writeable_reg(struct device *dev, unsigned int reg) 310 { 311 switch (reg) { 312 case LVDS_REG_05: 313 case LVDS_REG_0B: 314 case LVDS_REG_2C: 315 case LVDS_REG_3C: 316 case LVDS_REG_3F: 317 case LVDS_REG_47: 318 case LVDS_REG_48: 319 case LVDS_REG_4F: 320 case LVDS_REG_52: 321 return true; 322 default: 323 return false; 324 } 325 } 326 327 static bool it6263_lvds_readable_reg(struct device *dev, unsigned int reg) 328 { 329 return it6263_lvds_writeable_reg(dev, reg); 330 } 331 332 static bool it6263_lvds_volatile_reg(struct device *dev, unsigned int reg) 333 { 334 return reg == LVDS_REG_05; 335 } 336 337 static const struct regmap_config it6263_lvds_regmap_config = { 338 .name = "it6263-lvds", 339 .reg_bits = 8, 340 .val_bits = 8, 341 .writeable_reg = it6263_lvds_writeable_reg, 342 .readable_reg = it6263_lvds_readable_reg, 343 .volatile_reg = it6263_lvds_volatile_reg, 344 .max_register = LVDS_REG_52, 345 .cache_type = REGCACHE_MAPLE, 346 }; 347 348 static const char * const it6263_supplies[] = { 349 "ivdd", "ovdd", "txavcc18", "txavcc33", "pvcc1", "pvcc2", 350 "avcc", "anvdd", "apvdd" 351 }; 352 353 static int it6263_parse_dt(struct it6263 *it) 354 { 355 struct device *dev = it->dev; 356 struct device_node *port0, *port1; 357 int ret = 0; 358 359 it->lvds_data_mapping = drm_of_lvds_get_data_mapping(dev->of_node); 360 if (it->lvds_data_mapping < 0) { 361 dev_err(dev, "%pOF: invalid or missing %s DT property: %d\n", 362 dev->of_node, "data-mapping", it->lvds_data_mapping); 363 return it->lvds_data_mapping; 364 } 365 366 it->next_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 2, 0); 367 if (IS_ERR(it->next_bridge)) 368 return dev_err_probe(dev, PTR_ERR(it->next_bridge), 369 "failed to get next bridge\n"); 370 371 port0 = of_graph_get_port_by_id(dev->of_node, 0); 372 port1 = of_graph_get_port_by_id(dev->of_node, 1); 373 if (port0 && port1) { 374 int order; 375 376 it->lvds_dual_link = true; 377 order = drm_of_lvds_get_dual_link_pixel_order_sink(port0, port1); 378 if (order < 0) { 379 dev_err(dev, 380 "failed to get dual link pixel order: %d\n", 381 order); 382 ret = order; 383 } else if (order == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { 384 it->lvds_link12_swap = true; 385 } 386 } else if (port1) { 387 ret = -EINVAL; 388 dev_err(dev, "single input LVDS port1 is not supported\n"); 389 } else if (!port0) { 390 ret = -EINVAL; 391 dev_err(dev, "no input LVDS port\n"); 392 } 393 394 of_node_put(port0); 395 of_node_put(port1); 396 397 return ret; 398 } 399 400 static inline void it6263_hw_reset(struct gpio_desc *reset_gpio) 401 { 402 if (!reset_gpio) 403 return; 404 405 gpiod_set_value_cansleep(reset_gpio, 0); 406 fsleep(1000); 407 gpiod_set_value_cansleep(reset_gpio, 1); 408 /* The chip maker says the low pulse should be at least 40ms. */ 409 fsleep(40000); 410 gpiod_set_value_cansleep(reset_gpio, 0); 411 /* addtional time to wait the high voltage to be stable */ 412 fsleep(5000); 413 } 414 415 static inline int it6263_lvds_set_i2c_addr(struct it6263 *it) 416 { 417 int ret; 418 419 ret = regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT, 420 LVDS_INPUT_CTRL_I2C_ADDR << 1); 421 if (ret) 422 return ret; 423 424 return regmap_write(it->hdmi_regmap, HDMI_REG_LVDS_PORT_EN, BIT(0)); 425 } 426 427 static inline void it6263_lvds_reset(struct it6263 *it) 428 { 429 /* AFE PLL reset */ 430 regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), 0x0); 431 fsleep(1000); 432 regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, BIT(0), BIT(0)); 433 434 /* software pixel clock domain reset */ 435 regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST, 436 REG_SOFT_P_RST); 437 fsleep(1000); 438 regmap_write_bits(it->lvds_regmap, LVDS_REG_05, REG_SOFT_P_RST, 0x0); 439 fsleep(10000); 440 } 441 442 static inline bool it6263_is_input_bus_fmt_valid(int input_fmt) 443 { 444 switch (input_fmt) { 445 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 446 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 447 return true; 448 } 449 return false; 450 } 451 452 static inline void it6263_lvds_set_interface(struct it6263 *it) 453 { 454 u8 fmt; 455 456 /* color depth */ 457 regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_COL_DEP, BIT8); 458 459 if (it->lvds_data_mapping == MEDIA_BUS_FMT_RGB888_1X7X4_SPWG) 460 fmt = VESA; 461 else 462 fmt = JEIDA; 463 464 /* output mapping */ 465 regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, OUT_MAP, fmt); 466 467 if (it->lvds_dual_link) { 468 regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, DISO); 469 regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), BIT(1)); 470 } else { 471 regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, DMODE, SISO); 472 regmap_write_bits(it->lvds_regmap, LVDS_REG_52, BIT(1), 0); 473 } 474 } 475 476 static inline void it6263_lvds_set_afe(struct it6263 *it) 477 { 478 regmap_write(it->lvds_regmap, LVDS_REG_3C, 0xaa); 479 regmap_write(it->lvds_regmap, LVDS_REG_3F, 0x02); 480 regmap_write(it->lvds_regmap, LVDS_REG_47, 0xaa); 481 regmap_write(it->lvds_regmap, LVDS_REG_48, 0x02); 482 regmap_write(it->lvds_regmap, LVDS_REG_4F, 0x11); 483 484 regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_SSC_PCLK_RF, 485 REG_SSC_PCLK_RF); 486 regmap_write_bits(it->lvds_regmap, LVDS_REG_3C, 0x07, 0); 487 regmap_write_bits(it->lvds_regmap, LVDS_REG_2C, REG_DESSC_ENB, 488 REG_DESSC_ENB); 489 } 490 491 static inline void it6263_lvds_sys_cfg(struct it6263 *it) 492 { 493 regmap_write_bits(it->lvds_regmap, LVDS_REG_0B, REG_LVDS_IN_SWAP, 494 it->lvds_link12_swap ? REG_LVDS_IN_SWAP : 0); 495 } 496 497 static inline void it6263_lvds_config(struct it6263 *it) 498 { 499 it6263_lvds_reset(it); 500 it6263_lvds_set_interface(it); 501 it6263_lvds_set_afe(it); 502 it6263_lvds_sys_cfg(it); 503 } 504 505 static inline void it6263_hdmi_config(struct it6263 *it) 506 { 507 regmap_write(it->hdmi_regmap, HDMI_REG_SW_RST, HDMI_RST_ALL); 508 regmap_write(it->hdmi_regmap, HDMI_REG_INPUT_MODE, IN_RGB); 509 regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, HDMI_COLOR_DEPTH, 510 HDMI_COLOR_DEPTH_24); 511 } 512 513 static enum drm_connector_status it6263_detect(struct it6263 *it) 514 { 515 unsigned int val; 516 517 regmap_read(it->hdmi_regmap, HDMI_REG_SYS_STATUS, &val); 518 if (val & HPDETECT) 519 return connector_status_connected; 520 else 521 return connector_status_disconnected; 522 } 523 524 static int it6263_read_edid(void *data, u8 *buf, unsigned int block, size_t len) 525 { 526 struct it6263 *it = data; 527 struct regmap *regmap = it->hdmi_regmap; 528 unsigned int start = (block % 2) * EDID_LENGTH; 529 unsigned int segment = block >> 1; 530 unsigned int count, val; 531 int ret; 532 533 regmap_write(regmap, HDMI_REG_DDC_MASTER_CTRL, MASTER_SEL_HOST); 534 regmap_write(regmap, HDMI_REG_DDC_HEADER, DDC_ADDR << 1); 535 regmap_write(regmap, HDMI_REG_DDC_EDIDSEG, segment); 536 537 while (len) { 538 /* clear DDC FIFO */ 539 regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_FIFO_CLR); 540 541 ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS, 542 val, val & DDC_DONE, 543 2000, 10000); 544 if (ret) { 545 dev_err(it->dev, "failed to clear DDC FIFO:%d\n", ret); 546 return ret; 547 } 548 549 count = len > HDMI_DDC_FIFO_BYTES ? HDMI_DDC_FIFO_BYTES : len; 550 551 /* fire the read command */ 552 regmap_write(regmap, HDMI_REG_DDC_REQOFF, start); 553 regmap_write(regmap, HDMI_REG_DDC_REQCOUNT, count); 554 regmap_write(regmap, HDMI_REG_DDC_CMD, DDC_CMD_EDID_READ); 555 556 start += count; 557 len -= count; 558 559 ret = regmap_read_poll_timeout(regmap, HDMI_REG_DDC_STATUS, val, 560 val & (DDC_DONE | DDC_ERROR), 561 20000, 250000); 562 if (ret && !(val & DDC_ERROR)) { 563 dev_err(it->dev, "failed to read EDID:%d\n", ret); 564 return ret; 565 } 566 567 if (val & DDC_ERROR) { 568 dev_err(it->dev, "DDC error\n"); 569 return -EIO; 570 } 571 572 /* cache to buffer */ 573 for (; count > 0; count--) { 574 regmap_read(regmap, HDMI_REG_DDC_READFIFO, &val); 575 *(buf++) = val; 576 } 577 } 578 579 return 0; 580 } 581 582 static void it6263_bridge_atomic_disable(struct drm_bridge *bridge, 583 struct drm_atomic_commit *state) 584 { 585 struct it6263 *it = bridge_to_it6263(bridge); 586 587 regmap_write_bits(it->hdmi_regmap, HDMI_REG_GCP, AVMUTE, AVMUTE); 588 regmap_write(it->hdmi_regmap, HDMI_REG_PKT_GENERAL_CTRL, 0); 589 regmap_write(it->hdmi_regmap, HDMI_REG_AFE_DRV_CTRL, 590 AFE_DRV_RST | AFE_DRV_PWD); 591 } 592 593 static void it6263_bridge_atomic_enable(struct drm_bridge *bridge, 594 struct drm_atomic_commit *state) 595 { 596 struct it6263 *it = bridge_to_it6263(bridge); 597 const struct drm_crtc_state *crtc_state; 598 struct regmap *regmap = it->hdmi_regmap; 599 const struct drm_display_mode *mode; 600 struct drm_connector *connector; 601 bool is_stable = false; 602 struct drm_crtc *crtc; 603 unsigned int val; 604 bool pclk_high; 605 int i, ret; 606 607 it6263_hw_reset(it->reset_gpio); 608 609 ret = it6263_lvds_set_i2c_addr(it); 610 if (ret) 611 dev_err(it->dev, "failed to set I2C addr\n"); 612 613 it6263_lvds_config(it); 614 it6263_hdmi_config(it); 615 616 connector = drm_atomic_get_new_connector_for_encoder(state, 617 bridge->encoder); 618 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 619 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 620 mode = &crtc_state->adjusted_mode; 621 622 regmap_write(regmap, HDMI_REG_HDMI_MODE, TX_HDMI_MODE); 623 624 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 625 626 /* HDMI AFE setup */ 627 pclk_high = mode->clock > HIGH_PIXEL_CLOCK_KHZ; 628 regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, AFE_DRV_RST); 629 if (pclk_high) 630 regmap_write(regmap, HDMI_REG_AFE_XP_CTRL, 631 AFE_XP_GAINBIT | AFE_XP_RESETB); 632 else 633 regmap_write(regmap, HDMI_REG_AFE_XP_CTRL, 634 AFE_XP_ER0 | AFE_XP_RESETB); 635 regmap_write(regmap, HDMI_REG_AFE_ISW_CTRL, 0x10); 636 if (pclk_high) 637 regmap_write(regmap, HDMI_REG_AFE_IP_CTRL, 638 AFE_IP_GAINBIT | AFE_IP_RESETB); 639 else 640 regmap_write(regmap, HDMI_REG_AFE_IP_CTRL, 641 AFE_IP_ER0 | AFE_IP_RESETB); 642 643 /* HDMI software video reset */ 644 regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, SOFTV_RST); 645 fsleep(1000); 646 regmap_write_bits(regmap, HDMI_REG_SW_RST, SOFTV_RST, 0); 647 648 /* reconfigure LVDS and retry several times in case video is instable */ 649 for (i = 0; i < 3; i++) { 650 ret = regmap_read_poll_timeout(regmap, HDMI_REG_SYS_STATUS, val, 651 val & TXVIDSTABLE, 652 20000, 500000); 653 if (!ret) { 654 is_stable = true; 655 break; 656 } 657 658 it6263_lvds_config(it); 659 } 660 661 if (!is_stable) 662 dev_warn(it->dev, "failed to wait for video stable\n"); 663 664 /* HDMI AFE reset release and power up */ 665 regmap_write(regmap, HDMI_REG_AFE_DRV_CTRL, 0); 666 667 regmap_write_bits(regmap, HDMI_REG_GCP, AVMUTE, 0); 668 669 regmap_write(regmap, HDMI_REG_PKT_GENERAL_CTRL, ENABLE_PKT | REPEAT_PKT); 670 } 671 672 static enum drm_mode_status 673 it6263_bridge_mode_valid(struct drm_bridge *bridge, 674 const struct drm_display_info *info, 675 const struct drm_display_mode *mode) 676 { 677 unsigned long long rate; 678 679 rate = drm_hdmi_compute_mode_clock(mode, 8, DRM_OUTPUT_COLOR_FORMAT_RGB444); 680 if (rate == 0) 681 return MODE_NOCLOCK; 682 683 return bridge->funcs->hdmi_tmds_char_rate_valid(bridge, mode, rate); 684 } 685 686 static int it6263_bridge_attach(struct drm_bridge *bridge, 687 struct drm_encoder *encoder, 688 enum drm_bridge_attach_flags flags) 689 { 690 struct it6263 *it = bridge_to_it6263(bridge); 691 struct drm_connector *connector; 692 int ret; 693 694 ret = drm_bridge_attach(encoder, it->next_bridge, bridge, 695 flags | DRM_BRIDGE_ATTACH_NO_CONNECTOR); 696 if (ret < 0) 697 return ret; 698 699 if (flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR) 700 return 0; 701 702 connector = drm_bridge_connector_init(bridge->dev, encoder); 703 if (IS_ERR(connector)) { 704 ret = PTR_ERR(connector); 705 dev_err(it->dev, "failed to initialize bridge connector: %d\n", 706 ret); 707 return ret; 708 } 709 710 return 0; 711 } 712 713 static enum drm_connector_status 714 it6263_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 715 { 716 struct it6263 *it = bridge_to_it6263(bridge); 717 718 return it6263_detect(it); 719 } 720 721 static const struct drm_edid * 722 it6263_bridge_edid_read(struct drm_bridge *bridge, 723 struct drm_connector *connector) 724 { 725 struct it6263 *it = bridge_to_it6263(bridge); 726 727 return drm_edid_read_custom(connector, it6263_read_edid, it); 728 } 729 730 static u32 * 731 it6263_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 732 struct drm_bridge_state *bridge_state, 733 struct drm_crtc_state *crtc_state, 734 struct drm_connector_state *conn_state, 735 u32 output_fmt, 736 unsigned int *num_input_fmts) 737 { 738 struct it6263 *it = bridge_to_it6263(bridge); 739 u32 *input_fmts; 740 741 *num_input_fmts = 0; 742 743 if (!it6263_is_input_bus_fmt_valid(it->lvds_data_mapping)) 744 return NULL; 745 746 input_fmts = kmalloc_obj(*input_fmts); 747 if (!input_fmts) 748 return NULL; 749 750 input_fmts[0] = it->lvds_data_mapping; 751 *num_input_fmts = 1; 752 753 return input_fmts; 754 } 755 756 static enum drm_mode_status 757 it6263_hdmi_tmds_char_rate_valid(const struct drm_bridge *bridge, 758 const struct drm_display_mode *mode, 759 unsigned long long tmds_rate) 760 { 761 if (mode->clock > MAX_PIXEL_CLOCK_KHZ) 762 return MODE_CLOCK_HIGH; 763 764 if (tmds_rate > MAX_HDMI_TMDS_CHAR_RATE_HZ) 765 return MODE_CLOCK_HIGH; 766 767 return MODE_OK; 768 } 769 770 static int it6263_hdmi_clear_avi_infoframe(struct drm_bridge *bridge) 771 { 772 struct it6263 *it = bridge_to_it6263(bridge); 773 774 regmap_write(it->hdmi_regmap, HDMI_REG_AVI_INFOFRM_CTRL, 0); 775 776 return 0; 777 } 778 779 static int it6263_hdmi_clear_hdmi_infoframe(struct drm_bridge *bridge) 780 { 781 struct it6263 *it = bridge_to_it6263(bridge); 782 783 regmap_write(it->hdmi_regmap, HDMI_REG_PKT_NULL_CTRL, 0); 784 785 return 0; 786 } 787 788 static int it6263_hdmi_write_avi_infoframe(struct drm_bridge *bridge, 789 const u8 *buffer, size_t len) 790 { 791 struct it6263 *it = bridge_to_it6263(bridge); 792 struct regmap *regmap = it->hdmi_regmap; 793 794 /* write the first AVI infoframe data byte chunk(DB1-DB5) */ 795 regmap_bulk_write(regmap, HDMI_REG_AVI_DB1, 796 &buffer[HDMI_INFOFRAME_HEADER_SIZE], 797 HDMI_AVI_DB_CHUNK1_SIZE); 798 799 /* write the second AVI infoframe data byte chunk(DB6-DB13) */ 800 regmap_bulk_write(regmap, HDMI_REG_AVI_DB6, 801 &buffer[HDMI_INFOFRAME_HEADER_SIZE + 802 HDMI_AVI_DB_CHUNK1_SIZE], 803 HDMI_AVI_DB_CHUNK2_SIZE); 804 805 /* write checksum */ 806 regmap_write(regmap, HDMI_REG_AVI_CSUM, buffer[3]); 807 808 regmap_write(regmap, HDMI_REG_AVI_INFOFRM_CTRL, 809 ENABLE_PKT | REPEAT_PKT); 810 811 return 0; 812 } 813 814 static int it6263_hdmi_write_hdmi_infoframe(struct drm_bridge *bridge, 815 const u8 *buffer, size_t len) 816 { 817 struct it6263 *it = bridge_to_it6263(bridge); 818 struct regmap *regmap = it->hdmi_regmap; 819 820 /* write header and payload */ 821 regmap_bulk_write(regmap, HDMI_REG_PKT_HB(0), buffer, len); 822 823 regmap_write(regmap, HDMI_REG_PKT_NULL_CTRL, 824 ENABLE_PKT | REPEAT_PKT); 825 826 return 0; 827 } 828 829 static const struct drm_bridge_funcs it6263_bridge_funcs = { 830 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 831 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 832 .atomic_reset = drm_atomic_helper_bridge_reset, 833 .attach = it6263_bridge_attach, 834 .mode_valid = it6263_bridge_mode_valid, 835 .atomic_disable = it6263_bridge_atomic_disable, 836 .atomic_enable = it6263_bridge_atomic_enable, 837 .detect = it6263_bridge_detect, 838 .edid_read = it6263_bridge_edid_read, 839 .atomic_get_input_bus_fmts = it6263_bridge_atomic_get_input_bus_fmts, 840 .hdmi_tmds_char_rate_valid = it6263_hdmi_tmds_char_rate_valid, 841 .hdmi_clear_avi_infoframe = it6263_hdmi_clear_avi_infoframe, 842 .hdmi_write_avi_infoframe = it6263_hdmi_write_avi_infoframe, 843 .hdmi_clear_hdmi_infoframe = it6263_hdmi_clear_hdmi_infoframe, 844 .hdmi_write_hdmi_infoframe = it6263_hdmi_write_hdmi_infoframe, 845 }; 846 847 static int it6263_probe(struct i2c_client *client) 848 { 849 struct device *dev = &client->dev; 850 struct it6263 *it; 851 int ret; 852 853 it = devm_drm_bridge_alloc(dev, struct it6263, bridge, 854 &it6263_bridge_funcs); 855 if (IS_ERR(it)) 856 return PTR_ERR(it); 857 858 it->dev = dev; 859 it->hdmi_i2c = client; 860 861 it->hdmi_regmap = devm_regmap_init_i2c(client, 862 &it6263_hdmi_regmap_config); 863 if (IS_ERR(it->hdmi_regmap)) 864 return dev_err_probe(dev, PTR_ERR(it->hdmi_regmap), 865 "failed to init I2C regmap for HDMI\n"); 866 867 it->reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 868 if (IS_ERR(it->reset_gpio)) 869 return dev_err_probe(dev, PTR_ERR(it->reset_gpio), 870 "failed to get reset gpio\n"); 871 872 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(it6263_supplies), 873 it6263_supplies); 874 if (ret) 875 return dev_err_probe(dev, ret, "failed to get power supplies\n"); 876 877 ret = it6263_parse_dt(it); 878 if (ret) 879 return ret; 880 881 it->lvds_i2c = devm_i2c_new_dummy_device(dev, client->adapter, 882 LVDS_INPUT_CTRL_I2C_ADDR); 883 if (IS_ERR(it->lvds_i2c)) 884 return dev_err_probe(it->dev, PTR_ERR(it->lvds_i2c), 885 "failed to allocate I2C device for LVDS\n"); 886 887 it->lvds_regmap = devm_regmap_init_i2c(it->lvds_i2c, 888 &it6263_lvds_regmap_config); 889 if (IS_ERR(it->lvds_regmap)) 890 return dev_err_probe(dev, PTR_ERR(it->lvds_regmap), 891 "failed to init I2C regmap for LVDS\n"); 892 893 i2c_set_clientdata(client, it); 894 895 it->bridge.of_node = dev->of_node; 896 /* IT6263 chip doesn't support HPD interrupt. */ 897 it->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID | 898 DRM_BRIDGE_OP_HDMI; 899 it->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 900 it->bridge.vendor = "ITE"; 901 it->bridge.product = "IT6263"; 902 903 return devm_drm_bridge_add(dev, &it->bridge); 904 } 905 906 static const struct of_device_id it6263_of_match[] = { 907 { .compatible = "ite,it6263", }, 908 { } 909 }; 910 MODULE_DEVICE_TABLE(of, it6263_of_match); 911 912 static const struct i2c_device_id it6263_i2c_ids[] = { 913 { "it6263" }, 914 { } 915 }; 916 MODULE_DEVICE_TABLE(i2c, it6263_i2c_ids); 917 918 static struct i2c_driver it6263_driver = { 919 .probe = it6263_probe, 920 .driver = { 921 .name = "it6263", 922 .of_match_table = it6263_of_match, 923 }, 924 .id_table = it6263_i2c_ids, 925 }; 926 module_i2c_driver(it6263_driver); 927 928 MODULE_DESCRIPTION("ITE Tech. Inc. IT6263 LVDS/HDMI bridge"); 929 MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>"); 930 MODULE_LICENSE("GPL"); 931