1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) Rockchip Electronics Co., Ltd. 4 * Zheng Yang <zhengyang@rock-chips.com> 5 * Yakir Yang <ykk@rock-chips.com> 6 * Andy Yan <andyshrk@163.com> 7 */ 8 9 #include <linux/irq.h> 10 #include <linux/clk.h> 11 #include <linux/delay.h> 12 #include <linux/err.h> 13 #include <linux/i2c.h> 14 #include <linux/hdmi.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/mod_devicetable.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/platform_device.h> 20 #include <linux/regmap.h> 21 22 #include <drm/bridge/inno_hdmi.h> 23 #include <drm/drm_atomic.h> 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_edid.h> 26 #include <drm/drm_of.h> 27 #include <drm/drm_print.h> 28 #include <drm/drm_probe_helper.h> 29 #include <drm/drm_simple_kms_helper.h> 30 31 #include <drm/display/drm_hdmi_helper.h> 32 #include <drm/display/drm_hdmi_state_helper.h> 33 34 #define INNO_HDMI_MIN_TMDS_CLOCK 25000000U 35 36 #define DDC_SEGMENT_ADDR 0x30 37 38 #define HDMI_SCL_RATE (100 * 1000) 39 40 #define DDC_BUS_FREQ_L 0x4b 41 #define DDC_BUS_FREQ_H 0x4c 42 43 #define HDMI_SYS_CTRL 0x00 44 #define m_RST_ANALOG BIT(6) 45 #define v_RST_ANALOG (0 << 6) 46 #define v_NOT_RST_ANALOG BIT(6) 47 #define m_RST_DIGITAL BIT(5) 48 #define v_RST_DIGITAL (0 << 5) 49 #define v_NOT_RST_DIGITAL BIT(5) 50 #define m_REG_CLK_INV BIT(4) 51 #define v_REG_CLK_NOT_INV (0 << 4) 52 #define v_REG_CLK_INV BIT(4) 53 #define m_VCLK_INV BIT(3) 54 #define v_VCLK_NOT_INV (0 << 3) 55 #define v_VCLK_INV BIT(3) 56 #define m_REG_CLK_SOURCE BIT(2) 57 #define v_REG_CLK_SOURCE_TMDS (0 << 2) 58 #define v_REG_CLK_SOURCE_SYS BIT(2) 59 #define m_POWER BIT(1) 60 #define v_PWR_ON (0 << 1) 61 #define v_PWR_OFF BIT(1) 62 #define m_INT_POL BIT(0) 63 #define v_INT_POL_HIGH 1 64 #define v_INT_POL_LOW 0 65 66 #define HDMI_VIDEO_CONTRL1 0x01 67 #define m_VIDEO_INPUT_FORMAT (7 << 1) 68 #define m_DE_SOURCE BIT(0) 69 #define v_VIDEO_INPUT_FORMAT(n) ((n) << 1) 70 #define v_DE_EXTERNAL 1 71 #define v_DE_INTERNAL 0 72 enum { 73 VIDEO_INPUT_SDR_RGB444 = 0, 74 VIDEO_INPUT_DDR_RGB444 = 5, 75 VIDEO_INPUT_DDR_YCBCR422 = 6 76 }; 77 78 #define HDMI_VIDEO_CONTRL2 0x02 79 #define m_VIDEO_OUTPUT_COLOR (3 << 6) 80 #define m_VIDEO_INPUT_BITS (3 << 4) 81 #define m_VIDEO_INPUT_CSP BIT(0) 82 #define v_VIDEO_OUTPUT_COLOR(n) (((n) & 0x3) << 6) 83 #define v_VIDEO_INPUT_BITS(n) ((n) << 4) 84 #define v_VIDEO_INPUT_CSP(n) ((n) << 0) 85 enum { 86 VIDEO_INPUT_12BITS = 0, 87 VIDEO_INPUT_10BITS = 1, 88 VIDEO_INPUT_REVERT = 2, 89 VIDEO_INPUT_8BITS = 3, 90 }; 91 92 #define HDMI_VIDEO_CONTRL 0x03 93 #define m_VIDEO_AUTO_CSC BIT(7) 94 #define v_VIDEO_AUTO_CSC(n) ((n) << 7) 95 #define m_VIDEO_C0_C2_SWAP BIT(0) 96 #define v_VIDEO_C0_C2_SWAP(n) ((n) << 0) 97 enum { 98 C0_C2_CHANGE_ENABLE = 0, 99 C0_C2_CHANGE_DISABLE = 1, 100 AUTO_CSC_DISABLE = 0, 101 AUTO_CSC_ENABLE = 1, 102 }; 103 104 #define HDMI_VIDEO_CONTRL3 0x04 105 #define m_COLOR_DEPTH_NOT_INDICATED BIT(4) 106 #define m_SOF BIT(3) 107 #define m_COLOR_RANGE BIT(2) 108 #define m_CSC BIT(0) 109 #define v_COLOR_DEPTH_NOT_INDICATED(n) ((n) << 4) 110 #define v_SOF_ENABLE (0 << 3) 111 #define v_SOF_DISABLE BIT(3) 112 #define v_COLOR_RANGE_FULL BIT(2) 113 #define v_COLOR_RANGE_LIMITED (0 << 2) 114 #define v_CSC_ENABLE 1 115 #define v_CSC_DISABLE 0 116 117 #define HDMI_AV_MUTE 0x05 118 #define m_AVMUTE_CLEAR BIT(7) 119 #define m_AVMUTE_ENABLE BIT(6) 120 #define m_AUDIO_MUTE BIT(1) 121 #define m_VIDEO_BLACK BIT(0) 122 #define v_AVMUTE_CLEAR(n) ((n) << 7) 123 #define v_AVMUTE_ENABLE(n) ((n) << 6) 124 #define v_AUDIO_MUTE(n) ((n) << 1) 125 #define v_VIDEO_MUTE(n) ((n) << 0) 126 127 #define HDMI_VIDEO_TIMING_CTL 0x08 128 #define v_HSYNC_POLARITY(n) ((n) << 3) 129 #define v_VSYNC_POLARITY(n) ((n) << 2) 130 #define v_INETLACE(n) ((n) << 1) 131 #define v_EXTERANL_VIDEO(n) ((n) << 0) 132 133 #define HDMI_VIDEO_EXT_HTOTAL_L 0x09 134 #define HDMI_VIDEO_EXT_HTOTAL_H 0x0a 135 #define HDMI_VIDEO_EXT_HBLANK_L 0x0b 136 #define HDMI_VIDEO_EXT_HBLANK_H 0x0c 137 #define HDMI_VIDEO_EXT_HDELAY_L 0x0d 138 #define HDMI_VIDEO_EXT_HDELAY_H 0x0e 139 #define HDMI_VIDEO_EXT_HDURATION_L 0x0f 140 #define HDMI_VIDEO_EXT_HDURATION_H 0x10 141 #define HDMI_VIDEO_EXT_VTOTAL_L 0x11 142 #define HDMI_VIDEO_EXT_VTOTAL_H 0x12 143 #define HDMI_VIDEO_EXT_VBLANK 0x13 144 #define HDMI_VIDEO_EXT_VDELAY 0x14 145 #define HDMI_VIDEO_EXT_VDURATION 0x15 146 147 #define HDMI_VIDEO_CSC_COEF 0x18 148 149 #define HDMI_AUDIO_CTRL1 0x35 150 enum { 151 CTS_SOURCE_INTERNAL = 0, 152 CTS_SOURCE_EXTERNAL = 1, 153 }; 154 155 #define v_CTS_SOURCE(n) ((n) << 7) 156 157 enum { 158 DOWNSAMPLE_DISABLE = 0, 159 DOWNSAMPLE_1_2 = 1, 160 DOWNSAMPLE_1_4 = 2, 161 }; 162 163 #define v_DOWN_SAMPLE(n) ((n) << 5) 164 165 enum { 166 AUDIO_SOURCE_IIS = 0, 167 AUDIO_SOURCE_SPDIF = 1, 168 }; 169 170 #define v_AUDIO_SOURCE(n) ((n) << 3) 171 172 #define v_MCLK_ENABLE(n) ((n) << 2) 173 174 enum { 175 MCLK_128FS = 0, 176 MCLK_256FS = 1, 177 MCLK_384FS = 2, 178 MCLK_512FS = 3, 179 }; 180 181 #define v_MCLK_RATIO(n) (n) 182 183 #define AUDIO_SAMPLE_RATE 0x37 184 185 enum { 186 AUDIO_32K = 0x3, 187 AUDIO_441K = 0x0, 188 AUDIO_48K = 0x2, 189 AUDIO_882K = 0x8, 190 AUDIO_96K = 0xa, 191 AUDIO_1764K = 0xc, 192 AUDIO_192K = 0xe, 193 }; 194 195 #define AUDIO_I2S_MODE 0x38 196 197 enum { 198 I2S_CHANNEL_1_2 = 1, 199 I2S_CHANNEL_3_4 = 3, 200 I2S_CHANNEL_5_6 = 7, 201 I2S_CHANNEL_7_8 = 0xf 202 }; 203 204 #define v_I2S_CHANNEL(n) ((n) << 2) 205 206 enum { 207 I2S_STANDARD = 0, 208 I2S_LEFT_JUSTIFIED = 1, 209 I2S_RIGHT_JUSTIFIED = 2, 210 }; 211 212 #define v_I2S_MODE(n) (n) 213 214 #define AUDIO_I2S_MAP 0x39 215 #define AUDIO_I2S_SWAPS_SPDIF 0x3a 216 #define v_SPIDF_FREQ(n) (n) 217 218 #define N_32K 0x1000 219 #define N_441K 0x1880 220 #define N_882K 0x3100 221 #define N_1764K 0x6200 222 #define N_48K 0x1800 223 #define N_96K 0x3000 224 #define N_192K 0x6000 225 226 #define HDMI_AUDIO_CHANNEL_STATUS 0x3e 227 #define m_AUDIO_STATUS_NLPCM BIT(7) 228 #define m_AUDIO_STATUS_USE BIT(6) 229 #define m_AUDIO_STATUS_COPYRIGHT BIT(5) 230 #define m_AUDIO_STATUS_ADDITION (3 << 2) 231 #define m_AUDIO_STATUS_CLK_ACCURACY (2 << 0) 232 #define v_AUDIO_STATUS_NLPCM(n) (((n) & 1) << 7) 233 #define AUDIO_N_H 0x3f 234 #define AUDIO_N_M 0x40 235 #define AUDIO_N_L 0x41 236 237 #define HDMI_AUDIO_CTS_H 0x45 238 #define HDMI_AUDIO_CTS_M 0x46 239 #define HDMI_AUDIO_CTS_L 0x47 240 241 #define HDMI_DDC_CLK_L 0x4b 242 #define HDMI_DDC_CLK_H 0x4c 243 244 #define HDMI_EDID_SEGMENT_POINTER 0x4d 245 #define HDMI_EDID_WORD_ADDR 0x4e 246 #define HDMI_EDID_FIFO_OFFSET 0x4f 247 #define HDMI_EDID_FIFO_ADDR 0x50 248 249 #define HDMI_PACKET_SEND_MANUAL 0x9c 250 #define HDMI_PACKET_SEND_AUTO 0x9d 251 #define m_PACKET_GCP_EN BIT(7) 252 #define m_PACKET_MSI_EN BIT(6) 253 #define m_PACKET_SDI_EN BIT(5) 254 #define m_PACKET_VSI_EN BIT(4) 255 #define v_PACKET_GCP_EN(n) (((n) & 1) << 7) 256 #define v_PACKET_MSI_EN(n) (((n) & 1) << 6) 257 #define v_PACKET_SDI_EN(n) (((n) & 1) << 5) 258 #define v_PACKET_VSI_EN(n) (((n) & 1) << 4) 259 260 #define HDMI_CONTROL_PACKET_BUF_INDEX 0x9f 261 262 enum { 263 INFOFRAME_VSI = 0x05, 264 INFOFRAME_AVI = 0x06, 265 INFOFRAME_AAI = 0x08, 266 }; 267 268 #define HDMI_CONTROL_PACKET_ADDR 0xa0 269 #define HDMI_MAXIMUM_INFO_FRAME_SIZE 0x11 270 271 enum { 272 AVI_COLOR_MODE_RGB = 0, 273 AVI_COLOR_MODE_YCBCR422 = 1, 274 AVI_COLOR_MODE_YCBCR444 = 2, 275 AVI_COLORIMETRY_NO_DATA = 0, 276 277 AVI_COLORIMETRY_SMPTE_170M = 1, 278 AVI_COLORIMETRY_ITU709 = 2, 279 AVI_COLORIMETRY_EXTENDED = 3, 280 281 AVI_CODED_FRAME_ASPECT_NO_DATA = 0, 282 AVI_CODED_FRAME_ASPECT_4_3 = 1, 283 AVI_CODED_FRAME_ASPECT_16_9 = 2, 284 285 ACTIVE_ASPECT_RATE_SAME_AS_CODED_FRAME = 0x08, 286 ACTIVE_ASPECT_RATE_4_3 = 0x09, 287 ACTIVE_ASPECT_RATE_16_9 = 0x0A, 288 ACTIVE_ASPECT_RATE_14_9 = 0x0B, 289 }; 290 291 #define HDMI_HDCP_CTRL 0x52 292 #define m_HDMI_DVI BIT(1) 293 #define v_HDMI_DVI(n) ((n) << 1) 294 295 #define HDMI_INTERRUPT_MASK1 0xc0 296 #define HDMI_INTERRUPT_STATUS1 0xc1 297 #define m_INT_ACTIVE_VSYNC BIT(5) 298 #define m_INT_EDID_READY BIT(2) 299 300 #define HDMI_INTERRUPT_MASK2 0xc2 301 #define HDMI_INTERRUPT_STATUS2 0xc3 302 #define m_INT_HDCP_ERR BIT(7) 303 #define m_INT_BKSV_FLAG BIT(6) 304 #define m_INT_HDCP_OK BIT(4) 305 306 #define HDMI_STATUS 0xc8 307 #define m_HOTPLUG BIT(7) 308 #define m_MASK_INT_HOTPLUG BIT(5) 309 #define m_INT_HOTPLUG BIT(1) 310 #define v_MASK_INT_HOTPLUG(n) (((n) & 0x1) << 5) 311 312 #define HDMI_COLORBAR 0xc9 313 314 #define HDMI_PHY_SYNC 0xce 315 #define HDMI_PHY_SYS_CTL 0xe0 316 #define m_TMDS_CLK_SOURCE BIT(5) 317 #define v_TMDS_FROM_PLL (0 << 5) 318 #define v_TMDS_FROM_GEN BIT(5) 319 #define m_PHASE_CLK BIT(4) 320 #define v_DEFAULT_PHASE (0 << 4) 321 #define v_SYNC_PHASE BIT(4) 322 #define m_TMDS_CURRENT_PWR BIT(3) 323 #define v_TURN_ON_CURRENT (0 << 3) 324 #define v_CAT_OFF_CURRENT BIT(3) 325 #define m_BANDGAP_PWR BIT(2) 326 #define v_BANDGAP_PWR_UP (0 << 2) 327 #define v_BANDGAP_PWR_DOWN BIT(2) 328 #define m_PLL_PWR BIT(1) 329 #define v_PLL_PWR_UP (0 << 1) 330 #define v_PLL_PWR_DOWN BIT(1) 331 #define m_TMDS_CHG_PWR BIT(0) 332 #define v_TMDS_CHG_PWR_UP (0 << 0) 333 #define v_TMDS_CHG_PWR_DOWN BIT(0) 334 335 #define HDMI_PHY_CHG_PWR 0xe1 336 #define v_CLK_CHG_PWR(n) (((n) & 1) << 3) 337 #define v_DATA_CHG_PWR(n) (((n) & 7) << 0) 338 339 #define HDMI_PHY_DRIVER 0xe2 340 #define v_CLK_MAIN_DRIVER(n) ((n) << 4) 341 #define v_DATA_MAIN_DRIVER(n) ((n) << 0) 342 343 #define HDMI_PHY_PRE_EMPHASIS 0xe3 344 #define v_PRE_EMPHASIS(n) (((n) & 7) << 4) 345 #define v_CLK_PRE_DRIVER(n) (((n) & 3) << 2) 346 #define v_DATA_PRE_DRIVER(n) (((n) & 3) << 0) 347 348 #define HDMI_PHY_FEEDBACK_DIV_RATIO_LOW 0xe7 349 #define v_FEEDBACK_DIV_LOW(n) ((n) & 0xff) 350 #define HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH 0xe8 351 #define v_FEEDBACK_DIV_HIGH(n) ((n) & 1) 352 353 #define HDMI_PHY_PRE_DIV_RATIO 0xed 354 #define v_PRE_DIV_RATIO(n) ((n) & 0x1f) 355 356 #define HDMI_CEC_CTRL 0xd0 357 #define m_ADJUST_FOR_HISENSE BIT(6) 358 #define m_REJECT_RX_BROADCAST BIT(5) 359 #define m_BUSFREETIME_ENABLE BIT(2) 360 #define m_REJECT_RX BIT(1) 361 #define m_START_TX BIT(0) 362 363 #define HDMI_CEC_DATA 0xd1 364 #define HDMI_CEC_TX_OFFSET 0xd2 365 #define HDMI_CEC_RX_OFFSET 0xd3 366 #define HDMI_CEC_CLK_H 0xd4 367 #define HDMI_CEC_CLK_L 0xd5 368 #define HDMI_CEC_TX_LENGTH 0xd6 369 #define HDMI_CEC_RX_LENGTH 0xd7 370 #define HDMI_CEC_TX_INT_MASK 0xd8 371 #define m_TX_DONE BIT(3) 372 #define m_TX_NOACK BIT(2) 373 #define m_TX_BROADCAST_REJ BIT(1) 374 #define m_TX_BUSNOTFREE BIT(0) 375 376 #define HDMI_CEC_RX_INT_MASK 0xd9 377 #define m_RX_LA_ERR BIT(4) 378 #define m_RX_GLITCH BIT(3) 379 #define m_RX_DONE BIT(0) 380 381 #define HDMI_CEC_TX_INT 0xda 382 #define HDMI_CEC_RX_INT 0xdb 383 #define HDMI_CEC_BUSFREETIME_L 0xdc 384 #define HDMI_CEC_BUSFREETIME_H 0xdd 385 #define HDMI_CEC_LOGICADDR 0xde 386 387 struct inno_hdmi_i2c { 388 struct i2c_adapter adap; 389 390 u8 ddc_addr; 391 u8 segment_addr; 392 393 struct mutex lock; 394 struct completion cmp; 395 }; 396 397 struct inno_hdmi { 398 struct device *dev; 399 struct drm_bridge bridge; 400 struct clk *pclk; 401 struct clk *refclk; 402 void __iomem *regs; 403 struct regmap *grf; 404 405 struct inno_hdmi_i2c *i2c; 406 struct i2c_adapter *ddc; 407 const struct inno_hdmi_plat_data *plat_data; 408 }; 409 410 enum { 411 CSC_RGB_0_255_TO_ITU601_16_235_8BIT, 412 CSC_RGB_0_255_TO_ITU709_16_235_8BIT, 413 CSC_RGB_0_255_TO_RGB_16_235_8BIT, 414 }; 415 416 static const char coeff_csc[][24] = { 417 /* 418 * RGB2YUV:601 SD mode: 419 * Cb = -0.291G - 0.148R + 0.439B + 128 420 * Y = 0.504G + 0.257R + 0.098B + 16 421 * Cr = -0.368G + 0.439R - 0.071B + 128 422 */ 423 { 424 0x11, 0x5f, 0x01, 0x82, 0x10, 0x23, 0x00, 0x80, 425 0x02, 0x1c, 0x00, 0xa1, 0x00, 0x36, 0x00, 0x1e, 426 0x11, 0x29, 0x10, 0x59, 0x01, 0x82, 0x00, 0x80 427 }, 428 /* 429 * RGB2YUV:709 HD mode: 430 * Cb = - 0.338G - 0.101R + 0.439B + 128 431 * Y = 0.614G + 0.183R + 0.062B + 16 432 * Cr = - 0.399G + 0.439R - 0.040B + 128 433 */ 434 { 435 0x11, 0x98, 0x01, 0xc1, 0x10, 0x28, 0x00, 0x80, 436 0x02, 0x74, 0x00, 0xbb, 0x00, 0x3f, 0x00, 0x10, 437 0x11, 0x5a, 0x10, 0x67, 0x01, 0xc1, 0x00, 0x80 438 }, 439 /* 440 * RGB[0:255]2RGB[16:235]: 441 * R' = R x (235-16)/255 + 16; 442 * G' = G x (235-16)/255 + 16; 443 * B' = B x (235-16)/255 + 16; 444 */ 445 { 446 0x00, 0x00, 0x03, 0x6F, 0x00, 0x00, 0x00, 0x10, 447 0x03, 0x6F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 448 0x00, 0x00, 0x00, 0x00, 0x03, 0x6F, 0x00, 0x10 449 }, 450 }; 451 452 static struct inno_hdmi *bridge_to_inno_hdmi(struct drm_bridge *bridge) 453 { 454 return container_of(bridge, struct inno_hdmi, bridge); 455 } 456 457 static int inno_hdmi_find_phy_config(struct inno_hdmi *hdmi, 458 unsigned long pixelclk) 459 { 460 const struct inno_hdmi_phy_config *phy_configs = hdmi->plat_data->phy_configs; 461 int i; 462 463 for (i = 0; phy_configs[i].pixelclock != ~0UL; i++) { 464 if (pixelclk <= phy_configs[i].pixelclock) 465 return i; 466 } 467 468 DRM_DEV_DEBUG(hdmi->dev, "No phy configuration for pixelclock %lu\n", 469 pixelclk); 470 471 return -EINVAL; 472 } 473 474 static inline u8 hdmi_readb(struct inno_hdmi *hdmi, u16 offset) 475 { 476 return readl_relaxed(hdmi->regs + (offset) * 0x04); 477 } 478 479 static inline void hdmi_writeb(struct inno_hdmi *hdmi, u16 offset, u32 val) 480 { 481 writel_relaxed(val, hdmi->regs + (offset) * 0x04); 482 } 483 484 static inline void hdmi_modb(struct inno_hdmi *hdmi, u16 offset, 485 u32 msk, u32 val) 486 { 487 u8 temp = hdmi_readb(hdmi, offset) & ~msk; 488 489 temp |= val & msk; 490 hdmi_writeb(hdmi, offset, temp); 491 } 492 493 static void inno_hdmi_i2c_init(struct inno_hdmi *hdmi, unsigned long long rate) 494 { 495 unsigned long long ddc_bus_freq = rate >> 2; 496 497 do_div(ddc_bus_freq, HDMI_SCL_RATE); 498 499 hdmi_writeb(hdmi, DDC_BUS_FREQ_L, ddc_bus_freq & 0xFF); 500 hdmi_writeb(hdmi, DDC_BUS_FREQ_H, (ddc_bus_freq >> 8) & 0xFF); 501 502 /* Clear the EDID interrupt flag and mute the interrupt */ 503 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0); 504 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); 505 } 506 507 static void inno_hdmi_sys_power(struct inno_hdmi *hdmi, bool enable) 508 { 509 if (enable) 510 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_ON); 511 else 512 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_POWER, v_PWR_OFF); 513 } 514 515 static void inno_hdmi_standby(struct inno_hdmi *hdmi) 516 { 517 inno_hdmi_sys_power(hdmi, false); 518 519 hdmi_writeb(hdmi, HDMI_PHY_DRIVER, 0x00); 520 hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, 0x00); 521 hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x00); 522 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15); 523 }; 524 525 static void inno_hdmi_power_up(struct inno_hdmi *hdmi, 526 unsigned long mpixelclock) 527 { 528 struct inno_hdmi_phy_config *phy_config; 529 int ret = inno_hdmi_find_phy_config(hdmi, mpixelclock); 530 531 if (ret < 0) { 532 phy_config = hdmi->plat_data->default_phy_config; 533 DRM_DEV_ERROR(hdmi->dev, 534 "Using default phy configuration for TMDS rate %lu", 535 mpixelclock); 536 } else { 537 phy_config = &hdmi->plat_data->phy_configs[ret]; 538 } 539 540 inno_hdmi_sys_power(hdmi, false); 541 542 hdmi_writeb(hdmi, HDMI_PHY_PRE_EMPHASIS, phy_config->pre_emphasis); 543 hdmi_writeb(hdmi, HDMI_PHY_DRIVER, phy_config->voltage_level_control); 544 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x15); 545 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x14); 546 hdmi_writeb(hdmi, HDMI_PHY_SYS_CTL, 0x10); 547 hdmi_writeb(hdmi, HDMI_PHY_CHG_PWR, 0x0f); 548 hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x00); 549 hdmi_writeb(hdmi, HDMI_PHY_SYNC, 0x01); 550 551 inno_hdmi_sys_power(hdmi, true); 552 }; 553 554 static void inno_hdmi_init_hw(struct inno_hdmi *hdmi) 555 { 556 u32 val; 557 u32 msk; 558 559 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_DIGITAL, v_NOT_RST_DIGITAL); 560 usleep_range(100, 150); 561 562 hdmi_modb(hdmi, HDMI_SYS_CTRL, m_RST_ANALOG, v_NOT_RST_ANALOG); 563 usleep_range(100, 150); 564 565 msk = m_REG_CLK_INV | m_REG_CLK_SOURCE | m_POWER | m_INT_POL; 566 val = v_REG_CLK_INV | v_REG_CLK_SOURCE_SYS | v_PWR_ON | v_INT_POL_HIGH; 567 hdmi_modb(hdmi, HDMI_SYS_CTRL, msk, val); 568 569 inno_hdmi_standby(hdmi); 570 571 /* 572 * When the controller isn't configured to an accurate 573 * video timing and there is no reference clock available, 574 * then the TMDS clock source would be switched to PCLK_HDMI, 575 * so we need to init the TMDS rate to PCLK rate, and 576 * reconfigure the DDC clock. 577 */ 578 if (hdmi->refclk) 579 inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->refclk)); 580 else 581 inno_hdmi_i2c_init(hdmi, clk_get_rate(hdmi->pclk)); 582 583 /* Unmute hotplug interrupt */ 584 hdmi_modb(hdmi, HDMI_STATUS, m_MASK_INT_HOTPLUG, v_MASK_INT_HOTPLUG(1)); 585 } 586 587 static int inno_hdmi_bridge_clear_infoframe(struct drm_bridge *bridge, 588 enum hdmi_infoframe_type type) 589 { 590 struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); 591 592 if (type != HDMI_INFOFRAME_TYPE_AVI) { 593 drm_err(bridge->dev, "Unsupported infoframe type: %u\n", type); 594 return 0; 595 } 596 597 hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_BUF_INDEX, INFOFRAME_AVI); 598 599 return 0; 600 } 601 602 static int inno_hdmi_bridge_write_infoframe(struct drm_bridge *bridge, 603 enum hdmi_infoframe_type type, 604 const u8 *buffer, size_t len) 605 { 606 struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); 607 ssize_t i; 608 609 if (type != HDMI_INFOFRAME_TYPE_AVI) { 610 drm_err(bridge->dev, "Unsupported infoframe type: %u\n", type); 611 return 0; 612 } 613 614 inno_hdmi_bridge_clear_infoframe(bridge, type); 615 616 for (i = 0; i < len; i++) 617 hdmi_writeb(hdmi, HDMI_CONTROL_PACKET_ADDR + i, buffer[i]); 618 619 return 0; 620 } 621 622 static int inno_hdmi_config_video_csc(struct inno_hdmi *hdmi, 623 struct drm_connector *connector, 624 struct drm_display_mode *mode) 625 { 626 struct drm_connector_state *conn_state = connector->state; 627 int c0_c2_change = 0; 628 int csc_enable = 0; 629 int csc_mode = 0; 630 int auto_csc = 0; 631 int value; 632 int i; 633 int colorimetry; 634 u8 vic = drm_match_cea_mode(mode); 635 636 if (vic == 6 || vic == 7 || vic == 21 || vic == 22 || 637 vic == 2 || vic == 3 || vic == 17 || vic == 18) 638 colorimetry = HDMI_COLORIMETRY_ITU_601; 639 else 640 colorimetry = HDMI_COLORIMETRY_ITU_709; 641 642 643 /* Input video mode is SDR RGB24bit, data enable signal from external */ 644 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL1, v_DE_EXTERNAL | 645 v_VIDEO_INPUT_FORMAT(VIDEO_INPUT_SDR_RGB444)); 646 647 /* Input color hardcode to RGB, and output color hardcode to RGB888 */ 648 value = v_VIDEO_INPUT_BITS(VIDEO_INPUT_8BITS) | 649 v_VIDEO_OUTPUT_COLOR(0) | 650 v_VIDEO_INPUT_CSP(0); 651 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL2, value); 652 653 if (conn_state->hdmi.output_format == HDMI_COLORSPACE_RGB) { 654 if (conn_state->hdmi.is_limited_range) { 655 csc_mode = CSC_RGB_0_255_TO_RGB_16_235_8BIT; 656 auto_csc = AUTO_CSC_DISABLE; 657 c0_c2_change = C0_C2_CHANGE_DISABLE; 658 csc_enable = v_CSC_ENABLE; 659 660 } else { 661 value = v_SOF_DISABLE | v_COLOR_DEPTH_NOT_INDICATED(1); 662 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value); 663 664 hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, 665 m_VIDEO_AUTO_CSC | m_VIDEO_C0_C2_SWAP, 666 v_VIDEO_AUTO_CSC(AUTO_CSC_DISABLE) | 667 v_VIDEO_C0_C2_SWAP(C0_C2_CHANGE_DISABLE)); 668 return 0; 669 } 670 } else { 671 if (colorimetry == HDMI_COLORIMETRY_ITU_601) { 672 if (conn_state->hdmi.output_format == HDMI_COLORSPACE_YUV444) { 673 csc_mode = CSC_RGB_0_255_TO_ITU601_16_235_8BIT; 674 auto_csc = AUTO_CSC_DISABLE; 675 c0_c2_change = C0_C2_CHANGE_DISABLE; 676 csc_enable = v_CSC_ENABLE; 677 } 678 } else { 679 if (conn_state->hdmi.output_format == HDMI_COLORSPACE_YUV444) { 680 csc_mode = CSC_RGB_0_255_TO_ITU709_16_235_8BIT; 681 auto_csc = AUTO_CSC_DISABLE; 682 c0_c2_change = C0_C2_CHANGE_DISABLE; 683 csc_enable = v_CSC_ENABLE; 684 } 685 } 686 } 687 688 for (i = 0; i < 24; i++) 689 hdmi_writeb(hdmi, HDMI_VIDEO_CSC_COEF + i, coeff_csc[csc_mode][i]); 690 691 value = v_SOF_DISABLE | csc_enable | v_COLOR_DEPTH_NOT_INDICATED(1); 692 hdmi_writeb(hdmi, HDMI_VIDEO_CONTRL3, value); 693 hdmi_modb(hdmi, HDMI_VIDEO_CONTRL, m_VIDEO_AUTO_CSC | 694 m_VIDEO_C0_C2_SWAP, v_VIDEO_AUTO_CSC(auto_csc) | 695 v_VIDEO_C0_C2_SWAP(c0_c2_change)); 696 697 return 0; 698 } 699 700 static int inno_hdmi_config_video_timing(struct inno_hdmi *hdmi, 701 struct drm_display_mode *mode) 702 { 703 const struct inno_hdmi_plat_ops *plat_ops = hdmi->plat_data->ops; 704 u32 value; 705 706 if (plat_ops && plat_ops->enable) 707 plat_ops->enable(hdmi->dev, mode); 708 709 /* Set detail external video timing polarity and interlace mode */ 710 value = v_EXTERANL_VIDEO(1); 711 value |= mode->flags & DRM_MODE_FLAG_PHSYNC ? 712 v_HSYNC_POLARITY(1) : v_HSYNC_POLARITY(0); 713 value |= mode->flags & DRM_MODE_FLAG_PVSYNC ? 714 v_VSYNC_POLARITY(1) : v_VSYNC_POLARITY(0); 715 value |= mode->flags & DRM_MODE_FLAG_INTERLACE ? 716 v_INETLACE(1) : v_INETLACE(0); 717 hdmi_writeb(hdmi, HDMI_VIDEO_TIMING_CTL, value); 718 719 /* Set detail external video timing */ 720 value = mode->htotal; 721 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_L, value & 0xFF); 722 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HTOTAL_H, (value >> 8) & 0xFF); 723 724 value = mode->htotal - mode->hdisplay; 725 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_L, value & 0xFF); 726 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HBLANK_H, (value >> 8) & 0xFF); 727 728 value = mode->htotal - mode->hsync_start; 729 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_L, value & 0xFF); 730 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDELAY_H, (value >> 8) & 0xFF); 731 732 value = mode->hsync_end - mode->hsync_start; 733 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_L, value & 0xFF); 734 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_HDURATION_H, (value >> 8) & 0xFF); 735 736 value = mode->vtotal; 737 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_L, value & 0xFF); 738 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VTOTAL_H, (value >> 8) & 0xFF); 739 740 value = mode->vtotal - mode->vdisplay; 741 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VBLANK, value & 0xFF); 742 743 value = mode->vtotal - mode->vsync_start; 744 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDELAY, value & 0xFF); 745 746 value = mode->vsync_end - mode->vsync_start; 747 hdmi_writeb(hdmi, HDMI_VIDEO_EXT_VDURATION, value & 0xFF); 748 749 hdmi_writeb(hdmi, HDMI_PHY_PRE_DIV_RATIO, 0x1e); 750 hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_LOW, 0x2c); 751 hdmi_writeb(hdmi, HDMI_PHY_FEEDBACK_DIV_RATIO_HIGH, 0x01); 752 753 return 0; 754 } 755 756 static int inno_hdmi_setup(struct inno_hdmi *hdmi, struct drm_atomic_state *state) 757 { 758 struct drm_bridge *bridge = &hdmi->bridge; 759 struct drm_connector *connector; 760 struct drm_display_info *info; 761 struct drm_connector_state *new_conn_state; 762 struct drm_crtc_state *new_crtc_state; 763 764 connector = drm_atomic_get_new_connector_for_encoder(state, bridge->encoder); 765 766 new_conn_state = drm_atomic_get_new_connector_state(state, connector); 767 if (WARN_ON(!new_conn_state)) 768 return -EINVAL; 769 770 new_crtc_state = drm_atomic_get_new_crtc_state(state, new_conn_state->crtc); 771 if (WARN_ON(!new_crtc_state)) 772 return -EINVAL; 773 774 info = &connector->display_info; 775 776 /* Mute video and audio output */ 777 hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK, 778 v_AUDIO_MUTE(1) | v_VIDEO_MUTE(1)); 779 780 /* Set HDMI Mode */ 781 hdmi_writeb(hdmi, HDMI_HDCP_CTRL, v_HDMI_DVI(info->is_hdmi)); 782 783 inno_hdmi_config_video_timing(hdmi, &new_crtc_state->adjusted_mode); 784 785 inno_hdmi_config_video_csc(hdmi, connector, &new_crtc_state->adjusted_mode); 786 787 drm_atomic_helper_connector_hdmi_update_infoframes(connector, state); 788 789 /* 790 * When IP controller have configured to an accurate video 791 * timing, then the TMDS clock source would be switched to 792 * DCLK_LCDC, so we need to init the TMDS rate to mode pixel 793 * clock rate, and reconfigure the DDC clock. 794 */ 795 inno_hdmi_i2c_init(hdmi, new_conn_state->hdmi.tmds_char_rate); 796 797 /* Unmute video and audio output */ 798 hdmi_modb(hdmi, HDMI_AV_MUTE, m_AUDIO_MUTE | m_VIDEO_BLACK, 799 v_AUDIO_MUTE(0) | v_VIDEO_MUTE(0)); 800 801 inno_hdmi_power_up(hdmi, new_conn_state->hdmi.tmds_char_rate); 802 803 return 0; 804 } 805 806 static enum drm_mode_status inno_hdmi_bridge_mode_valid(struct drm_bridge *bridge, 807 const struct drm_display_info *info, 808 const struct drm_display_mode *mode) 809 { 810 struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); 811 unsigned long mpixelclk, max_tolerance; 812 long rounded_refclk; 813 814 /* No support for double-clock modes */ 815 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 816 return MODE_BAD; 817 818 mpixelclk = mode->clock * 1000; 819 820 if (mpixelclk < INNO_HDMI_MIN_TMDS_CLOCK) 821 return MODE_CLOCK_LOW; 822 823 if (inno_hdmi_find_phy_config(hdmi, mpixelclk) < 0) 824 return MODE_CLOCK_HIGH; 825 826 if (hdmi->refclk) { 827 rounded_refclk = clk_round_rate(hdmi->refclk, mpixelclk); 828 if (rounded_refclk < 0) 829 return MODE_BAD; 830 831 /* Vesa DMT standard mentions +/- 0.5% max tolerance */ 832 max_tolerance = mpixelclk / 200; 833 if (abs_diff((unsigned long)rounded_refclk, mpixelclk) > max_tolerance) 834 return MODE_NOCLOCK; 835 } 836 837 return MODE_OK; 838 } 839 840 static enum drm_connector_status 841 inno_hdmi_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 842 { 843 struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); 844 845 return (hdmi_readb(hdmi, HDMI_STATUS) & m_HOTPLUG) ? 846 connector_status_connected : connector_status_disconnected; 847 } 848 849 static const struct drm_edid * 850 inno_hdmi_bridge_edid_read(struct drm_bridge *bridge, struct drm_connector *connector) 851 { 852 struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); 853 const struct drm_edid *drm_edid; 854 855 drm_edid = drm_edid_read_ddc(connector, bridge->ddc); 856 if (!drm_edid) 857 dev_dbg(hdmi->dev, "failed to get edid\n"); 858 859 return drm_edid; 860 } 861 862 static void inno_hdmi_bridge_atomic_enable(struct drm_bridge *bridge, 863 struct drm_atomic_state *state) 864 { 865 struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); 866 867 inno_hdmi_setup(hdmi, state); 868 } 869 870 static void inno_hdmi_bridge_atomic_disable(struct drm_bridge *bridge, 871 struct drm_atomic_state *state) 872 { 873 struct inno_hdmi *hdmi = bridge_to_inno_hdmi(bridge); 874 875 inno_hdmi_standby(hdmi); 876 } 877 878 static const struct drm_bridge_funcs inno_hdmi_bridge_funcs = { 879 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 880 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 881 .atomic_reset = drm_atomic_helper_bridge_reset, 882 .atomic_enable = inno_hdmi_bridge_atomic_enable, 883 .atomic_disable = inno_hdmi_bridge_atomic_disable, 884 .detect = inno_hdmi_bridge_detect, 885 .edid_read = inno_hdmi_bridge_edid_read, 886 .hdmi_clear_infoframe = inno_hdmi_bridge_clear_infoframe, 887 .hdmi_write_infoframe = inno_hdmi_bridge_write_infoframe, 888 .mode_valid = inno_hdmi_bridge_mode_valid, 889 }; 890 891 static irqreturn_t inno_hdmi_i2c_irq(struct inno_hdmi *hdmi) 892 { 893 struct inno_hdmi_i2c *i2c = hdmi->i2c; 894 u8 stat; 895 896 stat = hdmi_readb(hdmi, HDMI_INTERRUPT_STATUS1); 897 if (!(stat & m_INT_EDID_READY)) 898 return IRQ_NONE; 899 900 /* Clear HDMI EDID interrupt flag */ 901 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); 902 903 complete(&i2c->cmp); 904 905 return IRQ_HANDLED; 906 } 907 908 static irqreturn_t inno_hdmi_hardirq(int irq, void *dev_id) 909 { 910 struct inno_hdmi *hdmi = dev_id; 911 irqreturn_t ret = IRQ_NONE; 912 u8 interrupt; 913 914 if (hdmi->i2c) 915 ret = inno_hdmi_i2c_irq(hdmi); 916 917 interrupt = hdmi_readb(hdmi, HDMI_STATUS); 918 if (interrupt & m_INT_HOTPLUG) { 919 hdmi_modb(hdmi, HDMI_STATUS, m_INT_HOTPLUG, m_INT_HOTPLUG); 920 ret = IRQ_WAKE_THREAD; 921 } 922 923 return ret; 924 } 925 926 static irqreturn_t inno_hdmi_irq(int irq, void *dev_id) 927 { 928 struct inno_hdmi *hdmi = dev_id; 929 930 drm_helper_hpd_irq_event(hdmi->bridge.dev); 931 932 return IRQ_HANDLED; 933 } 934 935 static int inno_hdmi_i2c_read(struct inno_hdmi *hdmi, struct i2c_msg *msgs) 936 { 937 int length = msgs->len; 938 u8 *buf = msgs->buf; 939 int ret; 940 941 ret = wait_for_completion_timeout(&hdmi->i2c->cmp, HZ / 10); 942 if (!ret) 943 return -EAGAIN; 944 945 while (length--) 946 *buf++ = hdmi_readb(hdmi, HDMI_EDID_FIFO_ADDR); 947 948 return 0; 949 } 950 951 static int inno_hdmi_i2c_write(struct inno_hdmi *hdmi, struct i2c_msg *msgs) 952 { 953 /* 954 * The DDC module only support read EDID message, so 955 * we assume that each word write to this i2c adapter 956 * should be the offset of EDID word address. 957 */ 958 if (msgs->len != 1 || (msgs->addr != DDC_ADDR && msgs->addr != DDC_SEGMENT_ADDR)) 959 return -EINVAL; 960 961 reinit_completion(&hdmi->i2c->cmp); 962 963 if (msgs->addr == DDC_SEGMENT_ADDR) 964 hdmi->i2c->segment_addr = msgs->buf[0]; 965 if (msgs->addr == DDC_ADDR) 966 hdmi->i2c->ddc_addr = msgs->buf[0]; 967 968 /* Set edid fifo first addr */ 969 hdmi_writeb(hdmi, HDMI_EDID_FIFO_OFFSET, 0x00); 970 971 /* Set edid word address 0x00/0x80 */ 972 hdmi_writeb(hdmi, HDMI_EDID_WORD_ADDR, hdmi->i2c->ddc_addr); 973 974 /* Set edid segment pointer */ 975 hdmi_writeb(hdmi, HDMI_EDID_SEGMENT_POINTER, hdmi->i2c->segment_addr); 976 977 return 0; 978 } 979 980 static int inno_hdmi_i2c_xfer(struct i2c_adapter *adap, 981 struct i2c_msg *msgs, int num) 982 { 983 struct inno_hdmi *hdmi = i2c_get_adapdata(adap); 984 struct inno_hdmi_i2c *i2c = hdmi->i2c; 985 int i, ret = 0; 986 987 mutex_lock(&i2c->lock); 988 989 /* Clear the EDID interrupt flag and unmute the interrupt */ 990 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, m_INT_EDID_READY); 991 hdmi_writeb(hdmi, HDMI_INTERRUPT_STATUS1, m_INT_EDID_READY); 992 993 for (i = 0; i < num; i++) { 994 DRM_DEV_DEBUG(hdmi->dev, 995 "xfer: num: %d/%d, len: %d, flags: %#x\n", 996 i + 1, num, msgs[i].len, msgs[i].flags); 997 998 if (msgs[i].flags & I2C_M_RD) 999 ret = inno_hdmi_i2c_read(hdmi, &msgs[i]); 1000 else 1001 ret = inno_hdmi_i2c_write(hdmi, &msgs[i]); 1002 1003 if (ret < 0) 1004 break; 1005 } 1006 1007 if (!ret) 1008 ret = num; 1009 1010 /* Mute HDMI EDID interrupt */ 1011 hdmi_writeb(hdmi, HDMI_INTERRUPT_MASK1, 0); 1012 1013 mutex_unlock(&i2c->lock); 1014 1015 return ret; 1016 } 1017 1018 static u32 inno_hdmi_i2c_func(struct i2c_adapter *adapter) 1019 { 1020 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 1021 } 1022 1023 static const struct i2c_algorithm inno_hdmi_algorithm = { 1024 .master_xfer = inno_hdmi_i2c_xfer, 1025 .functionality = inno_hdmi_i2c_func, 1026 }; 1027 1028 static struct i2c_adapter *inno_hdmi_i2c_adapter(struct inno_hdmi *hdmi) 1029 { 1030 struct i2c_adapter *adap; 1031 struct inno_hdmi_i2c *i2c; 1032 int ret; 1033 1034 i2c = devm_kzalloc(hdmi->dev, sizeof(*i2c), GFP_KERNEL); 1035 if (!i2c) 1036 return ERR_PTR(-ENOMEM); 1037 1038 mutex_init(&i2c->lock); 1039 init_completion(&i2c->cmp); 1040 1041 adap = &i2c->adap; 1042 adap->owner = THIS_MODULE; 1043 adap->dev.parent = hdmi->dev; 1044 adap->dev.of_node = hdmi->dev->of_node; 1045 adap->algo = &inno_hdmi_algorithm; 1046 strscpy(adap->name, "Inno HDMI", sizeof(adap->name)); 1047 i2c_set_adapdata(adap, hdmi); 1048 1049 ret = devm_i2c_add_adapter(hdmi->dev, adap); 1050 if (ret) { 1051 dev_warn(hdmi->dev, "cannot add %s I2C adapter\n", adap->name); 1052 return ERR_PTR(ret); 1053 } 1054 1055 hdmi->i2c = i2c; 1056 1057 DRM_DEV_INFO(hdmi->dev, "registered %s I2C bus driver\n", adap->name); 1058 1059 return adap; 1060 } 1061 1062 struct inno_hdmi *inno_hdmi_bind(struct device *dev, 1063 struct drm_encoder *encoder, 1064 const struct inno_hdmi_plat_data *plat_data) 1065 { 1066 struct platform_device *pdev = to_platform_device(dev); 1067 struct inno_hdmi *hdmi; 1068 int irq; 1069 int ret; 1070 1071 if (!plat_data->phy_configs || !plat_data->default_phy_config) { 1072 dev_err(dev, "Missing platform PHY ops\n"); 1073 return ERR_PTR(-ENODEV); 1074 } 1075 1076 hdmi = devm_drm_bridge_alloc(dev, struct inno_hdmi, bridge, &inno_hdmi_bridge_funcs); 1077 if (IS_ERR(hdmi)) 1078 return ERR_CAST(hdmi); 1079 1080 hdmi->dev = dev; 1081 hdmi->plat_data = plat_data; 1082 1083 hdmi->regs = devm_platform_ioremap_resource(pdev, 0); 1084 if (IS_ERR(hdmi->regs)) 1085 return ERR_CAST(hdmi->regs); 1086 1087 hdmi->pclk = devm_clk_get_enabled(hdmi->dev, "pclk"); 1088 if (IS_ERR(hdmi->pclk)) { 1089 dev_err_probe(dev, PTR_ERR(hdmi->pclk), "Unable to get HDMI pclk\n"); 1090 return ERR_CAST(hdmi->pclk); 1091 } 1092 1093 hdmi->refclk = devm_clk_get_optional_enabled(hdmi->dev, "ref"); 1094 if (IS_ERR(hdmi->refclk)) { 1095 dev_err_probe(dev, PTR_ERR(hdmi->refclk), "Unable to get HDMI refclk\n"); 1096 return ERR_CAST(hdmi->refclk); 1097 } 1098 1099 inno_hdmi_init_hw(hdmi); 1100 1101 irq = platform_get_irq(pdev, 0); 1102 if (irq < 0) 1103 return ERR_PTR(irq); 1104 1105 ret = devm_request_threaded_irq(dev, irq, inno_hdmi_hardirq, 1106 inno_hdmi_irq, IRQF_SHARED, 1107 dev_name(dev), hdmi); 1108 if (ret) 1109 return ERR_PTR(ret); 1110 1111 hdmi->bridge.driver_private = hdmi; 1112 hdmi->bridge.ops = DRM_BRIDGE_OP_DETECT | 1113 DRM_BRIDGE_OP_EDID | 1114 DRM_BRIDGE_OP_HDMI | 1115 DRM_BRIDGE_OP_HPD; 1116 hdmi->bridge.of_node = pdev->dev.of_node; 1117 hdmi->bridge.type = DRM_MODE_CONNECTOR_HDMIA; 1118 hdmi->bridge.vendor = "Inno"; 1119 hdmi->bridge.product = "Inno HDMI"; 1120 1121 hdmi->bridge.ddc = inno_hdmi_i2c_adapter(hdmi); 1122 if (IS_ERR(hdmi->bridge.ddc)) 1123 return ERR_CAST(hdmi->bridge.ddc); 1124 1125 ret = devm_drm_bridge_add(dev, &hdmi->bridge); 1126 if (ret) 1127 return ERR_PTR(ret); 1128 1129 ret = drm_bridge_attach(encoder, &hdmi->bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); 1130 if (ret) 1131 return ERR_PTR(ret); 1132 1133 return hdmi; 1134 } 1135 EXPORT_SYMBOL_GPL(inno_hdmi_bind); 1136 MODULE_AUTHOR("Andy Yan <andyshrk@163.com>"); 1137 MODULE_DESCRIPTION("INNOSILICON HDMI transmitter library"); 1138 MODULE_LICENSE("GPL"); 1139