1 // SPDX-License-Identifier: GPL-2.0+ 2 3 /* 4 * Copyright 2020 NXP 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/io.h> 11 #include <linux/media-bus-format.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_graph.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 18 #include <drm/drm_atomic_state_helper.h> 19 #include <drm/drm_bridge.h> 20 #include <drm/drm_print.h> 21 22 #define PC_CTRL_REG 0x0 23 #define PC_COMBINE_ENABLE BIT(0) 24 #define PC_DISP_BYPASS(n) BIT(1 + 21 * (n)) 25 #define PC_DISP_HSYNC_POLARITY(n) BIT(2 + 11 * (n)) 26 #define PC_DISP_HSYNC_POLARITY_POS(n) DISP_HSYNC_POLARITY(n) 27 #define PC_DISP_VSYNC_POLARITY(n) BIT(3 + 11 * (n)) 28 #define PC_DISP_VSYNC_POLARITY_POS(n) DISP_VSYNC_POLARITY(n) 29 #define PC_DISP_DVALID_POLARITY(n) BIT(4 + 11 * (n)) 30 #define PC_DISP_DVALID_POLARITY_POS(n) DISP_DVALID_POLARITY(n) 31 #define PC_VSYNC_MASK_ENABLE BIT(5) 32 #define PC_SKIP_MODE BIT(6) 33 #define PC_SKIP_NUMBER_MASK GENMASK(12, 7) 34 #define PC_SKIP_NUMBER(n) FIELD_PREP(PC_SKIP_NUMBER_MASK, (n)) 35 #define PC_DISP0_PIX_DATA_FORMAT_MASK GENMASK(18, 16) 36 #define PC_DISP0_PIX_DATA_FORMAT(fmt) \ 37 FIELD_PREP(PC_DISP0_PIX_DATA_FORMAT_MASK, (fmt)) 38 #define PC_DISP1_PIX_DATA_FORMAT_MASK GENMASK(21, 19) 39 #define PC_DISP1_PIX_DATA_FORMAT(fmt) \ 40 FIELD_PREP(PC_DISP1_PIX_DATA_FORMAT_MASK, (fmt)) 41 42 #define PC_SW_RESET_REG 0x20 43 #define PC_SW_RESET_N BIT(0) 44 #define PC_DISP_SW_RESET_N(n) BIT(1 + (n)) 45 #define PC_FULL_RESET_N (PC_SW_RESET_N | \ 46 PC_DISP_SW_RESET_N(0) | \ 47 PC_DISP_SW_RESET_N(1)) 48 49 #define PC_REG_SET 0x4 50 #define PC_REG_CLR 0x8 51 52 #define DRIVER_NAME "imx8qxp-pixel-combiner" 53 54 enum imx8qxp_pc_pix_data_format { 55 RGB, 56 YUV444, 57 YUV422, 58 SPLIT_RGB, 59 }; 60 61 struct imx8qxp_pc_channel { 62 struct drm_bridge bridge; 63 struct drm_bridge *next_bridge; 64 struct imx8qxp_pc *pc; 65 unsigned int stream_id; 66 }; 67 68 struct imx8qxp_pc { 69 struct device *dev; 70 struct imx8qxp_pc_channel *ch[2]; 71 struct clk *clk_apb; 72 void __iomem *base; 73 }; 74 75 static inline u32 imx8qxp_pc_read(struct imx8qxp_pc *pc, unsigned int offset) 76 { 77 return readl(pc->base + offset); 78 } 79 80 static inline void 81 imx8qxp_pc_write(struct imx8qxp_pc *pc, unsigned int offset, u32 value) 82 { 83 writel(value, pc->base + offset); 84 } 85 86 static inline void 87 imx8qxp_pc_write_set(struct imx8qxp_pc *pc, unsigned int offset, u32 value) 88 { 89 imx8qxp_pc_write(pc, offset + PC_REG_SET, value); 90 } 91 92 static inline void 93 imx8qxp_pc_write_clr(struct imx8qxp_pc *pc, unsigned int offset, u32 value) 94 { 95 imx8qxp_pc_write(pc, offset + PC_REG_CLR, value); 96 } 97 98 static enum drm_mode_status 99 imx8qxp_pc_bridge_mode_valid(struct drm_bridge *bridge, 100 const struct drm_display_info *info, 101 const struct drm_display_mode *mode) 102 { 103 if (mode->hdisplay > 2560) 104 return MODE_BAD_HVALUE; 105 106 return MODE_OK; 107 } 108 109 static int imx8qxp_pc_bridge_attach(struct drm_bridge *bridge, 110 struct drm_encoder *encoder, 111 enum drm_bridge_attach_flags flags) 112 { 113 struct imx8qxp_pc_channel *ch = bridge->driver_private; 114 struct imx8qxp_pc *pc = ch->pc; 115 116 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) { 117 DRM_DEV_ERROR(pc->dev, 118 "do not support creating a drm_connector\n"); 119 return -EINVAL; 120 } 121 122 return drm_bridge_attach(encoder, 123 ch->next_bridge, bridge, 124 DRM_BRIDGE_ATTACH_NO_CONNECTOR); 125 } 126 127 static void 128 imx8qxp_pc_bridge_mode_set(struct drm_bridge *bridge, 129 const struct drm_display_mode *mode, 130 const struct drm_display_mode *adjusted_mode) 131 { 132 struct imx8qxp_pc_channel *ch = bridge->driver_private; 133 struct imx8qxp_pc *pc = ch->pc; 134 u32 val; 135 int ret; 136 137 ret = pm_runtime_get_sync(pc->dev); 138 if (ret < 0) 139 DRM_DEV_ERROR(pc->dev, 140 "failed to get runtime PM sync: %d\n", ret); 141 142 ret = clk_prepare_enable(pc->clk_apb); 143 if (ret) 144 DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n", 145 __func__, ret); 146 147 /* HSYNC to pixel link is active low. */ 148 imx8qxp_pc_write_clr(pc, PC_CTRL_REG, 149 PC_DISP_HSYNC_POLARITY(ch->stream_id)); 150 151 /* VSYNC to pixel link is active low. */ 152 imx8qxp_pc_write_clr(pc, PC_CTRL_REG, 153 PC_DISP_VSYNC_POLARITY(ch->stream_id)); 154 155 /* Data enable to pixel link is active high. */ 156 imx8qxp_pc_write_set(pc, PC_CTRL_REG, 157 PC_DISP_DVALID_POLARITY(ch->stream_id)); 158 159 /* Mask the first frame output which may be incomplete. */ 160 imx8qxp_pc_write_set(pc, PC_CTRL_REG, PC_VSYNC_MASK_ENABLE); 161 162 /* Only support RGB currently. */ 163 val = imx8qxp_pc_read(pc, PC_CTRL_REG); 164 if (ch->stream_id == 0) { 165 val &= ~PC_DISP0_PIX_DATA_FORMAT_MASK; 166 val |= PC_DISP0_PIX_DATA_FORMAT(RGB); 167 } else { 168 val &= ~PC_DISP1_PIX_DATA_FORMAT_MASK; 169 val |= PC_DISP1_PIX_DATA_FORMAT(RGB); 170 } 171 imx8qxp_pc_write(pc, PC_CTRL_REG, val); 172 173 /* Only support bypass mode currently. */ 174 imx8qxp_pc_write_set(pc, PC_CTRL_REG, PC_DISP_BYPASS(ch->stream_id)); 175 176 clk_disable_unprepare(pc->clk_apb); 177 } 178 179 static void imx8qxp_pc_bridge_atomic_disable(struct drm_bridge *bridge, 180 struct drm_atomic_state *state) 181 { 182 struct imx8qxp_pc_channel *ch = bridge->driver_private; 183 struct imx8qxp_pc *pc = ch->pc; 184 185 pm_runtime_put(pc->dev); 186 } 187 188 static const u32 imx8qxp_pc_bus_output_fmts[] = { 189 MEDIA_BUS_FMT_RGB888_1X36_CPADLO, 190 MEDIA_BUS_FMT_RGB666_1X36_CPADLO, 191 }; 192 193 static bool imx8qxp_pc_bus_output_fmt_supported(u32 fmt) 194 { 195 int i; 196 197 for (i = 0; i < ARRAY_SIZE(imx8qxp_pc_bus_output_fmts); i++) { 198 if (imx8qxp_pc_bus_output_fmts[i] == fmt) 199 return true; 200 } 201 202 return false; 203 } 204 205 static u32 * 206 imx8qxp_pc_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 207 struct drm_bridge_state *bridge_state, 208 struct drm_crtc_state *crtc_state, 209 struct drm_connector_state *conn_state, 210 u32 output_fmt, 211 unsigned int *num_input_fmts) 212 { 213 u32 *input_fmts; 214 215 if (!imx8qxp_pc_bus_output_fmt_supported(output_fmt)) 216 return NULL; 217 218 *num_input_fmts = 1; 219 220 input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); 221 if (!input_fmts) 222 return NULL; 223 224 switch (output_fmt) { 225 case MEDIA_BUS_FMT_RGB888_1X36_CPADLO: 226 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X30_CPADLO; 227 break; 228 case MEDIA_BUS_FMT_RGB666_1X36_CPADLO: 229 input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X30_CPADLO; 230 break; 231 default: 232 kfree(input_fmts); 233 input_fmts = NULL; 234 break; 235 } 236 237 return input_fmts; 238 } 239 240 static u32 * 241 imx8qxp_pc_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 242 struct drm_bridge_state *bridge_state, 243 struct drm_crtc_state *crtc_state, 244 struct drm_connector_state *conn_state, 245 unsigned int *num_output_fmts) 246 { 247 *num_output_fmts = ARRAY_SIZE(imx8qxp_pc_bus_output_fmts); 248 return kmemdup(imx8qxp_pc_bus_output_fmts, 249 sizeof(imx8qxp_pc_bus_output_fmts), GFP_KERNEL); 250 } 251 252 static const struct drm_bridge_funcs imx8qxp_pc_bridge_funcs = { 253 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 254 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 255 .atomic_reset = drm_atomic_helper_bridge_reset, 256 .mode_valid = imx8qxp_pc_bridge_mode_valid, 257 .attach = imx8qxp_pc_bridge_attach, 258 .mode_set = imx8qxp_pc_bridge_mode_set, 259 .atomic_disable = imx8qxp_pc_bridge_atomic_disable, 260 .atomic_get_input_bus_fmts = 261 imx8qxp_pc_bridge_atomic_get_input_bus_fmts, 262 .atomic_get_output_bus_fmts = 263 imx8qxp_pc_bridge_atomic_get_output_bus_fmts, 264 }; 265 266 static int imx8qxp_pc_bridge_probe(struct platform_device *pdev) 267 { 268 struct imx8qxp_pc *pc; 269 struct imx8qxp_pc_channel *ch; 270 struct device *dev = &pdev->dev; 271 struct device_node *np = dev->of_node; 272 struct device_node *child, *remote; 273 u32 i; 274 int ret; 275 276 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL); 277 if (!pc) 278 return -ENOMEM; 279 280 pc->base = devm_platform_ioremap_resource(pdev, 0); 281 if (IS_ERR(pc->base)) 282 return PTR_ERR(pc->base); 283 284 pc->dev = dev; 285 286 pc->clk_apb = devm_clk_get(dev, "apb"); 287 if (IS_ERR(pc->clk_apb)) { 288 ret = PTR_ERR(pc->clk_apb); 289 if (ret != -EPROBE_DEFER) 290 DRM_DEV_ERROR(dev, "failed to get apb clock: %d\n", ret); 291 return ret; 292 } 293 294 platform_set_drvdata(pdev, pc); 295 pm_runtime_enable(dev); 296 297 for_each_available_child_of_node(np, child) { 298 ret = of_property_read_u32(child, "reg", &i); 299 if (ret || i > 1) { 300 ret = -EINVAL; 301 DRM_DEV_ERROR(dev, 302 "invalid channel(%u) node address\n", i); 303 goto free_child; 304 } 305 306 ch = devm_drm_bridge_alloc(dev, struct imx8qxp_pc_channel, bridge, 307 &imx8qxp_pc_bridge_funcs); 308 if (IS_ERR(ch)) { 309 ret = PTR_ERR(ch); 310 goto free_child; 311 } 312 313 pc->ch[i] = ch; 314 ch->pc = pc; 315 ch->stream_id = i; 316 317 remote = of_graph_get_remote_node(child, 1, 0); 318 if (!remote) { 319 ret = -ENODEV; 320 DRM_DEV_ERROR(dev, 321 "channel%u failed to get port1's remote node: %d\n", 322 i, ret); 323 goto free_child; 324 } 325 326 ch->next_bridge = of_drm_find_bridge(remote); 327 if (!ch->next_bridge) { 328 of_node_put(remote); 329 ret = -EPROBE_DEFER; 330 DRM_DEV_DEBUG_DRIVER(dev, 331 "channel%u failed to find next bridge: %d\n", 332 i, ret); 333 goto free_child; 334 } 335 336 of_node_put(remote); 337 338 ch->bridge.driver_private = ch; 339 ch->bridge.of_node = child; 340 341 drm_bridge_add(&ch->bridge); 342 } 343 344 return 0; 345 346 free_child: 347 of_node_put(child); 348 349 if (i == 1 && pc->ch[0]->next_bridge) 350 drm_bridge_remove(&pc->ch[0]->bridge); 351 352 pm_runtime_disable(dev); 353 return ret; 354 } 355 356 static void imx8qxp_pc_bridge_remove(struct platform_device *pdev) 357 { 358 struct imx8qxp_pc *pc = platform_get_drvdata(pdev); 359 struct imx8qxp_pc_channel *ch; 360 int i; 361 362 for (i = 0; i < 2; i++) { 363 ch = pc->ch[i]; 364 365 if (ch) 366 drm_bridge_remove(&ch->bridge); 367 } 368 369 pm_runtime_disable(&pdev->dev); 370 } 371 372 static int imx8qxp_pc_runtime_suspend(struct device *dev) 373 { 374 struct platform_device *pdev = to_platform_device(dev); 375 struct imx8qxp_pc *pc = platform_get_drvdata(pdev); 376 int ret; 377 378 ret = clk_prepare_enable(pc->clk_apb); 379 if (ret) 380 DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n", 381 __func__, ret); 382 383 /* Disable pixel combiner by full reset. */ 384 imx8qxp_pc_write_clr(pc, PC_SW_RESET_REG, PC_FULL_RESET_N); 385 386 clk_disable_unprepare(pc->clk_apb); 387 388 /* Ensure the reset takes effect. */ 389 usleep_range(10, 20); 390 391 return ret; 392 } 393 394 static int imx8qxp_pc_runtime_resume(struct device *dev) 395 { 396 struct platform_device *pdev = to_platform_device(dev); 397 struct imx8qxp_pc *pc = platform_get_drvdata(pdev); 398 int ret; 399 400 ret = clk_prepare_enable(pc->clk_apb); 401 if (ret) { 402 DRM_DEV_ERROR(pc->dev, "%s: failed to enable apb clock: %d\n", 403 __func__, ret); 404 return ret; 405 } 406 407 /* out of reset */ 408 imx8qxp_pc_write_set(pc, PC_SW_RESET_REG, PC_FULL_RESET_N); 409 410 clk_disable_unprepare(pc->clk_apb); 411 412 return ret; 413 } 414 415 static const struct dev_pm_ops imx8qxp_pc_pm_ops = { 416 RUNTIME_PM_OPS(imx8qxp_pc_runtime_suspend, imx8qxp_pc_runtime_resume, NULL) 417 }; 418 419 static const struct of_device_id imx8qxp_pc_dt_ids[] = { 420 { .compatible = "fsl,imx8qm-pixel-combiner", }, 421 { .compatible = "fsl,imx8qxp-pixel-combiner", }, 422 { /* sentinel */ } 423 }; 424 MODULE_DEVICE_TABLE(of, imx8qxp_pc_dt_ids); 425 426 static struct platform_driver imx8qxp_pc_bridge_driver = { 427 .probe = imx8qxp_pc_bridge_probe, 428 .remove = imx8qxp_pc_bridge_remove, 429 .driver = { 430 .pm = pm_ptr(&imx8qxp_pc_pm_ops), 431 .name = DRIVER_NAME, 432 .of_match_table = imx8qxp_pc_dt_ids, 433 }, 434 }; 435 module_platform_driver(imx8qxp_pc_bridge_driver); 436 437 MODULE_DESCRIPTION("i.MX8QM/QXP pixel combiner bridge driver"); 438 MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>"); 439 MODULE_LICENSE("GPL v2"); 440 MODULE_ALIAS("platform:" DRIVER_NAME); 441