1 // SPDX-License-Identifier: GPL-2.0+ 2 3 /* 4 * Copyright 2020 NXP 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/media-bus-format.h> 9 #include <linux/mfd/syscon.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_device.h> 13 #include <linux/of_graph.h> 14 #include <linux/phy/phy.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regmap.h> 18 19 #include <drm/drm_atomic_state_helper.h> 20 #include <drm/drm_bridge.h> 21 #include <drm/drm_connector.h> 22 #include <drm/drm_fourcc.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_print.h> 25 26 #include "imx-ldb-helper.h" 27 28 #define LDB_CH_SEL BIT(28) 29 30 #define SS_CTRL 0x20 31 #define CH_HSYNC_M(id) BIT(0 + ((id) * 2)) 32 #define CH_VSYNC_M(id) BIT(1 + ((id) * 2)) 33 #define CH_PHSYNC(id) BIT(0 + ((id) * 2)) 34 #define CH_PVSYNC(id) BIT(1 + ((id) * 2)) 35 36 #define DRIVER_NAME "imx8qxp-ldb" 37 38 struct imx8qxp_ldb_channel { 39 struct ldb_channel base; 40 struct phy *phy; 41 unsigned int di_id; 42 }; 43 44 struct imx8qxp_ldb { 45 struct ldb base; 46 struct device *dev; 47 struct imx8qxp_ldb_channel *channel[MAX_LDB_CHAN_NUM]; 48 struct clk *clk_pixel; 49 struct clk *clk_bypass; 50 struct drm_bridge *companion; 51 int active_chno; 52 }; 53 54 static inline struct imx8qxp_ldb_channel * 55 base_to_imx8qxp_ldb_channel(struct ldb_channel *base) 56 { 57 return container_of(base, struct imx8qxp_ldb_channel, base); 58 } 59 60 static inline struct imx8qxp_ldb *base_to_imx8qxp_ldb(struct ldb *base) 61 { 62 return container_of(base, struct imx8qxp_ldb, base); 63 } 64 65 static void imx8qxp_ldb_set_phy_cfg(struct imx8qxp_ldb *imx8qxp_ldb, 66 unsigned long di_clk, bool is_split, 67 struct phy_configure_opts_lvds *phy_cfg) 68 { 69 phy_cfg->bits_per_lane_and_dclk_cycle = 7; 70 phy_cfg->lanes = 4; 71 72 if (is_split) { 73 phy_cfg->differential_clk_rate = di_clk / 2; 74 phy_cfg->is_slave = !imx8qxp_ldb->companion; 75 } else { 76 phy_cfg->differential_clk_rate = di_clk; 77 phy_cfg->is_slave = false; 78 } 79 } 80 81 static int 82 imx8qxp_ldb_bridge_atomic_check(struct drm_bridge *bridge, 83 struct drm_bridge_state *bridge_state, 84 struct drm_crtc_state *crtc_state, 85 struct drm_connector_state *conn_state) 86 { 87 struct ldb_channel *ldb_ch = bridge->driver_private; 88 struct ldb *ldb = ldb_ch->ldb; 89 struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = 90 base_to_imx8qxp_ldb_channel(ldb_ch); 91 struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); 92 struct drm_bridge *companion = imx8qxp_ldb->companion; 93 struct drm_display_mode *adj = &crtc_state->adjusted_mode; 94 unsigned long di_clk = adj->clock * 1000; 95 bool is_split = ldb_channel_is_split_link(ldb_ch); 96 union phy_configure_opts opts = { }; 97 struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; 98 int ret; 99 100 ret = ldb_bridge_atomic_check_helper(bridge, bridge_state, 101 crtc_state, conn_state); 102 if (ret) 103 return ret; 104 105 imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg); 106 ret = phy_validate(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS, 0, &opts); 107 if (ret < 0) { 108 DRM_DEV_DEBUG_DRIVER(imx8qxp_ldb->dev, 109 "failed to validate PHY: %d\n", ret); 110 return ret; 111 } 112 113 if (is_split && companion) { 114 ret = companion->funcs->atomic_check(companion, 115 bridge_state, crtc_state, conn_state); 116 if (ret) 117 return ret; 118 } 119 120 return ret; 121 } 122 123 static void 124 imx8qxp_ldb_bridge_mode_set(struct drm_bridge *bridge, 125 const struct drm_display_mode *mode, 126 const struct drm_display_mode *adjusted_mode) 127 { 128 struct ldb_channel *ldb_ch = bridge->driver_private; 129 struct ldb_channel *companion_ldb_ch; 130 struct ldb *ldb = ldb_ch->ldb; 131 struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = 132 base_to_imx8qxp_ldb_channel(ldb_ch); 133 struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); 134 struct drm_bridge *companion = imx8qxp_ldb->companion; 135 struct device *dev = imx8qxp_ldb->dev; 136 unsigned long di_clk = adjusted_mode->clock * 1000; 137 bool is_split = ldb_channel_is_split_link(ldb_ch); 138 union phy_configure_opts opts = { }; 139 struct phy_configure_opts_lvds *phy_cfg = &opts.lvds; 140 u32 chno = ldb_ch->chno; 141 int ret; 142 143 ret = pm_runtime_get_sync(dev); 144 if (ret < 0) 145 DRM_DEV_ERROR(dev, "failed to get runtime PM sync: %d\n", ret); 146 147 ret = phy_init(imx8qxp_ldb_ch->phy); 148 if (ret < 0) 149 DRM_DEV_ERROR(dev, "failed to initialize PHY: %d\n", ret); 150 151 ret = phy_set_mode(imx8qxp_ldb_ch->phy, PHY_MODE_LVDS); 152 if (ret < 0) 153 DRM_DEV_ERROR(dev, "failed to set PHY mode: %d\n", ret); 154 155 if (is_split && companion) { 156 companion_ldb_ch = bridge_to_ldb_ch(companion); 157 158 companion_ldb_ch->in_bus_format = ldb_ch->in_bus_format; 159 companion_ldb_ch->out_bus_format = ldb_ch->out_bus_format; 160 } 161 162 clk_set_rate(imx8qxp_ldb->clk_bypass, di_clk); 163 clk_set_rate(imx8qxp_ldb->clk_pixel, di_clk); 164 165 imx8qxp_ldb_set_phy_cfg(imx8qxp_ldb, di_clk, is_split, phy_cfg); 166 ret = phy_configure(imx8qxp_ldb_ch->phy, &opts); 167 if (ret < 0) 168 DRM_DEV_ERROR(dev, "failed to configure PHY: %d\n", ret); 169 170 if (chno == 0) 171 ldb->ldb_ctrl &= ~LDB_CH_SEL; 172 else 173 ldb->ldb_ctrl |= LDB_CH_SEL; 174 175 /* input VSYNC signal from pixel link is active low */ 176 if (imx8qxp_ldb_ch->di_id == 0) 177 ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW; 178 else 179 ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW; 180 181 /* 182 * For split mode, settle input VSYNC signal polarity and 183 * channel selection down early. 184 */ 185 if (is_split) 186 regmap_write(ldb->regmap, ldb->ctrl_reg, ldb->ldb_ctrl); 187 188 ldb_bridge_mode_set_helper(bridge, mode, adjusted_mode); 189 190 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) 191 regmap_update_bits(ldb->regmap, SS_CTRL, CH_VSYNC_M(chno), 0); 192 else if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 193 regmap_update_bits(ldb->regmap, SS_CTRL, 194 CH_VSYNC_M(chno), CH_PVSYNC(chno)); 195 196 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) 197 regmap_update_bits(ldb->regmap, SS_CTRL, CH_HSYNC_M(chno), 0); 198 else if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 199 regmap_update_bits(ldb->regmap, SS_CTRL, 200 CH_HSYNC_M(chno), CH_PHSYNC(chno)); 201 202 if (is_split && companion) 203 companion->funcs->mode_set(companion, mode, adjusted_mode); 204 } 205 206 static void imx8qxp_ldb_bridge_atomic_pre_enable(struct drm_bridge *bridge, 207 struct drm_atomic_state *state) 208 { 209 struct ldb_channel *ldb_ch = bridge->driver_private; 210 struct ldb *ldb = ldb_ch->ldb; 211 struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); 212 struct drm_bridge *companion = imx8qxp_ldb->companion; 213 bool is_split = ldb_channel_is_split_link(ldb_ch); 214 215 clk_prepare_enable(imx8qxp_ldb->clk_pixel); 216 clk_prepare_enable(imx8qxp_ldb->clk_bypass); 217 218 if (is_split && companion) 219 companion->funcs->atomic_pre_enable(companion, state); 220 } 221 222 static void imx8qxp_ldb_bridge_atomic_enable(struct drm_bridge *bridge, 223 struct drm_atomic_state *state) 224 { 225 struct ldb_channel *ldb_ch = bridge->driver_private; 226 struct ldb *ldb = ldb_ch->ldb; 227 struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = 228 base_to_imx8qxp_ldb_channel(ldb_ch); 229 struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); 230 struct drm_bridge *companion = imx8qxp_ldb->companion; 231 struct device *dev = imx8qxp_ldb->dev; 232 bool is_split = ldb_channel_is_split_link(ldb_ch); 233 int ret; 234 235 if (ldb_ch->chno == 0 || is_split) { 236 ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK; 237 ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ? 238 LDB_CH0_MODE_EN_TO_DI0 : LDB_CH0_MODE_EN_TO_DI1; 239 } 240 if (ldb_ch->chno == 1 || is_split) { 241 ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK; 242 ldb->ldb_ctrl |= imx8qxp_ldb_ch->di_id == 0 ? 243 LDB_CH1_MODE_EN_TO_DI0 : LDB_CH1_MODE_EN_TO_DI1; 244 } 245 246 ldb_bridge_enable_helper(bridge); 247 248 ret = phy_power_on(imx8qxp_ldb_ch->phy); 249 if (ret) 250 DRM_DEV_ERROR(dev, "failed to power on PHY: %d\n", ret); 251 252 if (is_split && companion) 253 companion->funcs->atomic_enable(companion, state); 254 } 255 256 static void imx8qxp_ldb_bridge_atomic_disable(struct drm_bridge *bridge, 257 struct drm_atomic_state *state) 258 { 259 struct ldb_channel *ldb_ch = bridge->driver_private; 260 struct ldb *ldb = ldb_ch->ldb; 261 struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = 262 base_to_imx8qxp_ldb_channel(ldb_ch); 263 struct imx8qxp_ldb *imx8qxp_ldb = base_to_imx8qxp_ldb(ldb); 264 struct drm_bridge *companion = imx8qxp_ldb->companion; 265 struct device *dev = imx8qxp_ldb->dev; 266 bool is_split = ldb_channel_is_split_link(ldb_ch); 267 int ret; 268 269 ret = phy_power_off(imx8qxp_ldb_ch->phy); 270 if (ret) 271 DRM_DEV_ERROR(dev, "failed to power off PHY: %d\n", ret); 272 273 ret = phy_exit(imx8qxp_ldb_ch->phy); 274 if (ret < 0) 275 DRM_DEV_ERROR(dev, "failed to teardown PHY: %d\n", ret); 276 277 ldb_bridge_disable_helper(bridge); 278 279 clk_disable_unprepare(imx8qxp_ldb->clk_bypass); 280 clk_disable_unprepare(imx8qxp_ldb->clk_pixel); 281 282 if (is_split && companion) 283 companion->funcs->atomic_disable(companion, state); 284 285 pm_runtime_put(dev); 286 } 287 288 static const u32 imx8qxp_ldb_bus_output_fmts[] = { 289 MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 290 MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 291 MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 292 MEDIA_BUS_FMT_FIXED, 293 }; 294 295 static bool imx8qxp_ldb_bus_output_fmt_supported(u32 fmt) 296 { 297 int i; 298 299 for (i = 0; i < ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts); i++) { 300 if (imx8qxp_ldb_bus_output_fmts[i] == fmt) 301 return true; 302 } 303 304 return false; 305 } 306 307 static u32 * 308 imx8qxp_ldb_bridge_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 309 struct drm_bridge_state *bridge_state, 310 struct drm_crtc_state *crtc_state, 311 struct drm_connector_state *conn_state, 312 u32 output_fmt, 313 unsigned int *num_input_fmts) 314 { 315 struct drm_display_info *di; 316 const struct drm_format_info *finfo; 317 u32 *input_fmts; 318 319 if (!imx8qxp_ldb_bus_output_fmt_supported(output_fmt)) 320 return NULL; 321 322 *num_input_fmts = 1; 323 324 input_fmts = kmalloc(sizeof(*input_fmts), GFP_KERNEL); 325 if (!input_fmts) 326 return NULL; 327 328 switch (output_fmt) { 329 case MEDIA_BUS_FMT_FIXED: 330 di = &conn_state->connector->display_info; 331 332 /* 333 * Look at the first bus format to determine input format. 334 * Default to MEDIA_BUS_FMT_RGB888_1X24, if no match. 335 */ 336 if (di->num_bus_formats) { 337 finfo = drm_format_info(di->bus_formats[0]); 338 339 input_fmts[0] = finfo->depth == 18 ? 340 MEDIA_BUS_FMT_RGB666_1X24_CPADHI : 341 MEDIA_BUS_FMT_RGB888_1X24; 342 } else { 343 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 344 } 345 break; 346 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 347 input_fmts[0] = MEDIA_BUS_FMT_RGB666_1X24_CPADHI; 348 break; 349 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 350 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 351 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 352 break; 353 default: 354 kfree(input_fmts); 355 input_fmts = NULL; 356 break; 357 } 358 359 return input_fmts; 360 } 361 362 static u32 * 363 imx8qxp_ldb_bridge_atomic_get_output_bus_fmts(struct drm_bridge *bridge, 364 struct drm_bridge_state *bridge_state, 365 struct drm_crtc_state *crtc_state, 366 struct drm_connector_state *conn_state, 367 unsigned int *num_output_fmts) 368 { 369 *num_output_fmts = ARRAY_SIZE(imx8qxp_ldb_bus_output_fmts); 370 return kmemdup(imx8qxp_ldb_bus_output_fmts, 371 sizeof(imx8qxp_ldb_bus_output_fmts), GFP_KERNEL); 372 } 373 374 static enum drm_mode_status 375 imx8qxp_ldb_bridge_mode_valid(struct drm_bridge *bridge, 376 const struct drm_display_info *info, 377 const struct drm_display_mode *mode) 378 { 379 struct ldb_channel *ldb_ch = bridge->driver_private; 380 bool is_single = ldb_channel_is_single_link(ldb_ch); 381 382 if (mode->clock > 170000) 383 return MODE_CLOCK_HIGH; 384 385 if (mode->clock > 150000 && is_single) 386 return MODE_CLOCK_HIGH; 387 388 return MODE_OK; 389 } 390 391 static const struct drm_bridge_funcs imx8qxp_ldb_bridge_funcs = { 392 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 393 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 394 .atomic_reset = drm_atomic_helper_bridge_reset, 395 .mode_valid = imx8qxp_ldb_bridge_mode_valid, 396 .attach = ldb_bridge_attach_helper, 397 .atomic_check = imx8qxp_ldb_bridge_atomic_check, 398 .mode_set = imx8qxp_ldb_bridge_mode_set, 399 .atomic_pre_enable = imx8qxp_ldb_bridge_atomic_pre_enable, 400 .atomic_enable = imx8qxp_ldb_bridge_atomic_enable, 401 .atomic_disable = imx8qxp_ldb_bridge_atomic_disable, 402 .atomic_get_input_bus_fmts = 403 imx8qxp_ldb_bridge_atomic_get_input_bus_fmts, 404 .atomic_get_output_bus_fmts = 405 imx8qxp_ldb_bridge_atomic_get_output_bus_fmts, 406 }; 407 408 static int imx8qxp_ldb_set_di_id(struct imx8qxp_ldb *imx8qxp_ldb) 409 { 410 struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = 411 imx8qxp_ldb->channel[imx8qxp_ldb->active_chno]; 412 struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base; 413 struct device_node *ep, *remote; 414 struct device *dev = imx8qxp_ldb->dev; 415 struct of_endpoint endpoint; 416 int ret; 417 418 ep = of_graph_get_endpoint_by_regs(ldb_ch->np, 0, -1); 419 if (!ep) { 420 DRM_DEV_ERROR(dev, "failed to get port0 endpoint\n"); 421 return -EINVAL; 422 } 423 424 remote = of_graph_get_remote_endpoint(ep); 425 of_node_put(ep); 426 if (!remote) { 427 DRM_DEV_ERROR(dev, "failed to get port0 remote endpoint\n"); 428 return -EINVAL; 429 } 430 431 ret = of_graph_parse_endpoint(remote, &endpoint); 432 of_node_put(remote); 433 if (ret) { 434 DRM_DEV_ERROR(dev, "failed to parse port0 remote endpoint: %d\n", 435 ret); 436 return ret; 437 } 438 439 imx8qxp_ldb_ch->di_id = endpoint.id; 440 441 return 0; 442 } 443 444 static int 445 imx8qxp_ldb_check_chno_and_dual_link(struct ldb_channel *ldb_ch, int link) 446 { 447 if ((link == DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS && ldb_ch->chno != 0) || 448 (link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS && ldb_ch->chno != 1)) 449 return -EINVAL; 450 451 return 0; 452 } 453 454 static int imx8qxp_ldb_parse_dt_companion(struct imx8qxp_ldb *imx8qxp_ldb) 455 { 456 struct imx8qxp_ldb_channel *imx8qxp_ldb_ch = 457 imx8qxp_ldb->channel[imx8qxp_ldb->active_chno]; 458 struct ldb_channel *ldb_ch = &imx8qxp_ldb_ch->base; 459 struct ldb_channel *companion_ldb_ch; 460 struct device_node *companion; 461 struct device_node *child; 462 struct device_node *companion_port = NULL; 463 struct device_node *port1, *port2; 464 struct device *dev = imx8qxp_ldb->dev; 465 const struct of_device_id *match; 466 u32 i; 467 int dual_link; 468 int ret; 469 470 /* Locate the companion LDB for dual-link operation, if any. */ 471 companion = of_parse_phandle(dev->of_node, "fsl,companion-ldb", 0); 472 if (!companion) 473 return 0; 474 475 if (!of_device_is_available(companion)) { 476 DRM_DEV_ERROR(dev, "companion LDB is not available\n"); 477 ret = -ENODEV; 478 goto out; 479 } 480 481 /* 482 * Sanity check: the companion bridge must have the same compatible 483 * string. 484 */ 485 match = of_match_device(dev->driver->of_match_table, dev); 486 if (!of_device_is_compatible(companion, match->compatible)) { 487 DRM_DEV_ERROR(dev, "companion LDB is incompatible\n"); 488 ret = -ENXIO; 489 goto out; 490 } 491 492 for_each_available_child_of_node(companion, child) { 493 ret = of_property_read_u32(child, "reg", &i); 494 if (ret || i > MAX_LDB_CHAN_NUM - 1) { 495 DRM_DEV_ERROR(dev, 496 "invalid channel node address: %u\n", i); 497 ret = -EINVAL; 498 of_node_put(child); 499 goto out; 500 } 501 502 /* 503 * Channel numbers have to be different, because channel0 504 * transmits odd pixels and channel1 transmits even pixels. 505 */ 506 if (i == (ldb_ch->chno ^ 0x1)) { 507 companion_port = child; 508 break; 509 } 510 } 511 512 if (!companion_port) { 513 DRM_DEV_ERROR(dev, 514 "failed to find companion LDB channel port\n"); 515 ret = -EINVAL; 516 goto out; 517 } 518 519 /* 520 * We need to work out if the sink is expecting us to function in 521 * dual-link mode. We do this by looking at the DT port nodes we are 522 * connected to. If they are marked as expecting odd pixels and 523 * even pixels than we need to enable LDB split mode. 524 */ 525 port1 = of_graph_get_port_by_id(ldb_ch->np, 1); 526 port2 = of_graph_get_port_by_id(companion_port, 1); 527 dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2); 528 of_node_put(port1); 529 of_node_put(port2); 530 531 switch (dual_link) { 532 case DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS: 533 ldb_ch->link_type = LDB_CH_DUAL_LINK_ODD_EVEN_PIXELS; 534 break; 535 case DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS: 536 ldb_ch->link_type = LDB_CH_DUAL_LINK_EVEN_ODD_PIXELS; 537 break; 538 default: 539 ret = dual_link; 540 DRM_DEV_ERROR(dev, 541 "failed to get dual link pixel order: %d\n", ret); 542 goto out; 543 } 544 545 ret = imx8qxp_ldb_check_chno_and_dual_link(ldb_ch, dual_link); 546 if (ret < 0) { 547 DRM_DEV_ERROR(dev, 548 "unmatched channel number(%u) vs dual link(%d)\n", 549 ldb_ch->chno, dual_link); 550 goto out; 551 } 552 553 imx8qxp_ldb->companion = of_drm_find_bridge(companion_port); 554 if (!imx8qxp_ldb->companion) { 555 ret = -EPROBE_DEFER; 556 DRM_DEV_DEBUG_DRIVER(dev, 557 "failed to find bridge for companion bridge: %d\n", 558 ret); 559 goto out; 560 } 561 562 DRM_DEV_DEBUG_DRIVER(dev, 563 "dual-link configuration detected (companion bridge %pOF)\n", 564 companion); 565 566 companion_ldb_ch = bridge_to_ldb_ch(imx8qxp_ldb->companion); 567 companion_ldb_ch->link_type = ldb_ch->link_type; 568 out: 569 of_node_put(companion_port); 570 of_node_put(companion); 571 return ret; 572 } 573 574 static int imx8qxp_ldb_probe(struct platform_device *pdev) 575 { 576 struct device *dev = &pdev->dev; 577 struct imx8qxp_ldb *imx8qxp_ldb; 578 struct imx8qxp_ldb_channel *imx8qxp_ldb_ch; 579 struct ldb *ldb; 580 struct ldb_channel *ldb_ch; 581 int ret, i; 582 583 imx8qxp_ldb = devm_kzalloc(dev, sizeof(*imx8qxp_ldb), GFP_KERNEL); 584 if (!imx8qxp_ldb) 585 return -ENOMEM; 586 587 for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { 588 imx8qxp_ldb->channel[i] = 589 devm_drm_bridge_alloc(dev, struct imx8qxp_ldb_channel, base.bridge, 590 &imx8qxp_ldb_bridge_funcs); 591 if (IS_ERR(imx8qxp_ldb->channel[i])) 592 return PTR_ERR(imx8qxp_ldb->channel[i]); 593 } 594 595 imx8qxp_ldb->clk_pixel = devm_clk_get(dev, "pixel"); 596 if (IS_ERR(imx8qxp_ldb->clk_pixel)) { 597 ret = PTR_ERR(imx8qxp_ldb->clk_pixel); 598 if (ret != -EPROBE_DEFER) 599 DRM_DEV_ERROR(dev, 600 "failed to get pixel clock: %d\n", ret); 601 return ret; 602 } 603 604 imx8qxp_ldb->clk_bypass = devm_clk_get(dev, "bypass"); 605 if (IS_ERR(imx8qxp_ldb->clk_bypass)) { 606 ret = PTR_ERR(imx8qxp_ldb->clk_bypass); 607 if (ret != -EPROBE_DEFER) 608 DRM_DEV_ERROR(dev, 609 "failed to get bypass clock: %d\n", ret); 610 return ret; 611 } 612 613 imx8qxp_ldb->dev = dev; 614 615 ldb = &imx8qxp_ldb->base; 616 ldb->dev = dev; 617 ldb->ctrl_reg = 0xe0; 618 619 for (i = 0; i < MAX_LDB_CHAN_NUM; i++) 620 ldb->channel[i] = &imx8qxp_ldb->channel[i]->base; 621 622 ret = ldb_init_helper(ldb); 623 if (ret) 624 return ret; 625 626 if (ldb->available_ch_cnt == 0) { 627 DRM_DEV_DEBUG_DRIVER(dev, "no available channel\n"); 628 return 0; 629 } else if (ldb->available_ch_cnt > 1) { 630 DRM_DEV_ERROR(dev, "invalid available channel number(%u)\n", 631 ldb->available_ch_cnt); 632 return -EINVAL; 633 } 634 635 for (i = 0; i < MAX_LDB_CHAN_NUM; i++) { 636 imx8qxp_ldb_ch = imx8qxp_ldb->channel[i]; 637 ldb_ch = &imx8qxp_ldb_ch->base; 638 639 if (ldb_ch->is_available) { 640 imx8qxp_ldb->active_chno = ldb_ch->chno; 641 break; 642 } 643 } 644 645 imx8qxp_ldb_ch->phy = devm_of_phy_get(dev, ldb_ch->np, "lvds_phy"); 646 if (IS_ERR(imx8qxp_ldb_ch->phy)) { 647 ret = PTR_ERR(imx8qxp_ldb_ch->phy); 648 if (ret != -EPROBE_DEFER) 649 DRM_DEV_ERROR(dev, "failed to get channel%d PHY: %d\n", 650 imx8qxp_ldb->active_chno, ret); 651 return ret; 652 } 653 654 ret = ldb_find_next_bridge_helper(ldb); 655 if (ret) 656 return ret; 657 658 ret = imx8qxp_ldb_set_di_id(imx8qxp_ldb); 659 if (ret) 660 return ret; 661 662 ret = imx8qxp_ldb_parse_dt_companion(imx8qxp_ldb); 663 if (ret) 664 return ret; 665 666 platform_set_drvdata(pdev, imx8qxp_ldb); 667 pm_runtime_enable(dev); 668 669 ldb_add_bridge_helper(ldb); 670 671 return 0; 672 } 673 674 static void imx8qxp_ldb_remove(struct platform_device *pdev) 675 { 676 struct imx8qxp_ldb *imx8qxp_ldb = platform_get_drvdata(pdev); 677 struct ldb *ldb = &imx8qxp_ldb->base; 678 679 ldb_remove_bridge_helper(ldb); 680 681 pm_runtime_disable(&pdev->dev); 682 } 683 684 static int imx8qxp_ldb_runtime_resume(struct device *dev) 685 { 686 struct imx8qxp_ldb *imx8qxp_ldb = dev_get_drvdata(dev); 687 struct ldb *ldb = &imx8qxp_ldb->base; 688 689 /* disable LDB by resetting the control register to POR default */ 690 regmap_write(ldb->regmap, ldb->ctrl_reg, 0); 691 692 return 0; 693 } 694 695 static const struct dev_pm_ops imx8qxp_ldb_pm_ops = { 696 RUNTIME_PM_OPS(NULL, imx8qxp_ldb_runtime_resume, NULL) 697 }; 698 699 static const struct of_device_id imx8qxp_ldb_dt_ids[] = { 700 { .compatible = "fsl,imx8qxp-ldb" }, 701 { /* sentinel */ } 702 }; 703 MODULE_DEVICE_TABLE(of, imx8qxp_ldb_dt_ids); 704 705 static struct platform_driver imx8qxp_ldb_driver = { 706 .probe = imx8qxp_ldb_probe, 707 .remove = imx8qxp_ldb_remove, 708 .driver = { 709 .pm = pm_ptr(&imx8qxp_ldb_pm_ops), 710 .name = DRIVER_NAME, 711 .of_match_table = imx8qxp_ldb_dt_ids, 712 }, 713 }; 714 module_platform_driver(imx8qxp_ldb_driver); 715 716 MODULE_DESCRIPTION("i.MX8QXP LVDS Display Bridge(LDB)/Pixel Mapper bridge driver"); 717 MODULE_AUTHOR("Liu Ying <victor.liu@nxp.com>"); 718 MODULE_LICENSE("GPL v2"); 719 MODULE_ALIAS("platform:" DRIVER_NAME); 720