1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2022 Marek Vasut <marex@denx.de> 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/media-bus-format.h> 8 #include <linux/mfd/syscon.h> 9 #include <linux/module.h> 10 #include <linux/of.h> 11 #include <linux/of_graph.h> 12 #include <linux/platform_device.h> 13 #include <linux/regmap.h> 14 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_bridge.h> 17 #include <drm/drm_of.h> 18 #include <drm/drm_panel.h> 19 20 #define LDB_CTRL_CH0_ENABLE BIT(0) 21 #define LDB_CTRL_CH0_DI_SELECT BIT(1) 22 #define LDB_CTRL_CH1_ENABLE BIT(2) 23 #define LDB_CTRL_CH1_DI_SELECT BIT(3) 24 #define LDB_CTRL_SPLIT_MODE BIT(4) 25 #define LDB_CTRL_CH0_DATA_WIDTH BIT(5) 26 #define LDB_CTRL_CH0_BIT_MAPPING BIT(6) 27 #define LDB_CTRL_CH1_DATA_WIDTH BIT(7) 28 #define LDB_CTRL_CH1_BIT_MAPPING BIT(8) 29 #define LDB_CTRL_DI0_VSYNC_POLARITY BIT(9) 30 #define LDB_CTRL_DI1_VSYNC_POLARITY BIT(10) 31 #define LDB_CTRL_REG_CH0_FIFO_RESET BIT(11) 32 #define LDB_CTRL_REG_CH1_FIFO_RESET BIT(12) 33 #define LDB_CTRL_ASYNC_FIFO_ENABLE BIT(24) 34 #define LDB_CTRL_ASYNC_FIFO_THRESHOLD_MASK GENMASK(27, 25) 35 36 #define LVDS_CTRL_CH0_EN BIT(0) 37 #define LVDS_CTRL_CH1_EN BIT(1) 38 /* 39 * LVDS_CTRL_LVDS_EN bit is poorly named in i.MX93 reference manual. 40 * Clear it to enable LVDS and set it to disable LVDS. 41 */ 42 #define LVDS_CTRL_LVDS_EN BIT(1) 43 #define LVDS_CTRL_VBG_EN BIT(2) 44 #define LVDS_CTRL_HS_EN BIT(3) 45 #define LVDS_CTRL_PRE_EMPH_EN BIT(4) 46 #define LVDS_CTRL_PRE_EMPH_ADJ(n) (((n) & 0x7) << 5) 47 #define LVDS_CTRL_PRE_EMPH_ADJ_MASK GENMASK(7, 5) 48 #define LVDS_CTRL_CM_ADJ(n) (((n) & 0x7) << 8) 49 #define LVDS_CTRL_CM_ADJ_MASK GENMASK(10, 8) 50 #define LVDS_CTRL_CC_ADJ(n) (((n) & 0x7) << 11) 51 #define LVDS_CTRL_CC_ADJ_MASK GENMASK(13, 11) 52 #define LVDS_CTRL_SLEW_ADJ(n) (((n) & 0x7) << 14) 53 #define LVDS_CTRL_SLEW_ADJ_MASK GENMASK(16, 14) 54 #define LVDS_CTRL_VBG_ADJ(n) (((n) & 0x7) << 17) 55 #define LVDS_CTRL_VBG_ADJ_MASK GENMASK(19, 17) 56 57 enum fsl_ldb_devtype { 58 IMX6SX_LDB, 59 IMX8MP_LDB, 60 IMX93_LDB, 61 }; 62 63 struct fsl_ldb_devdata { 64 u32 ldb_ctrl; 65 u32 lvds_ctrl; 66 bool lvds_en_bit; 67 bool single_ctrl_reg; 68 }; 69 70 static const struct fsl_ldb_devdata fsl_ldb_devdata[] = { 71 [IMX6SX_LDB] = { 72 .ldb_ctrl = 0x18, 73 .single_ctrl_reg = true, 74 }, 75 [IMX8MP_LDB] = { 76 .ldb_ctrl = 0x5c, 77 .lvds_ctrl = 0x128, 78 }, 79 [IMX93_LDB] = { 80 .ldb_ctrl = 0x20, 81 .lvds_ctrl = 0x24, 82 .lvds_en_bit = true, 83 }, 84 }; 85 86 struct fsl_ldb { 87 struct device *dev; 88 struct drm_bridge bridge; 89 struct drm_bridge *panel_bridge; 90 struct clk *clk; 91 struct regmap *regmap; 92 const struct fsl_ldb_devdata *devdata; 93 bool ch0_enabled; 94 bool ch1_enabled; 95 bool use_termination_resistor; 96 }; 97 98 static bool fsl_ldb_is_dual(const struct fsl_ldb *fsl_ldb) 99 { 100 return (fsl_ldb->ch0_enabled && fsl_ldb->ch1_enabled); 101 } 102 103 static inline struct fsl_ldb *to_fsl_ldb(struct drm_bridge *bridge) 104 { 105 return container_of(bridge, struct fsl_ldb, bridge); 106 } 107 108 static unsigned long fsl_ldb_link_frequency(struct fsl_ldb *fsl_ldb, int clock) 109 { 110 if (fsl_ldb_is_dual(fsl_ldb)) 111 return clock * 3500; 112 else 113 return clock * 7000; 114 } 115 116 static int fsl_ldb_attach(struct drm_bridge *bridge, 117 struct drm_encoder *encoder, 118 enum drm_bridge_attach_flags flags) 119 { 120 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 121 122 return drm_bridge_attach(encoder, fsl_ldb->panel_bridge, 123 bridge, flags); 124 } 125 126 static void fsl_ldb_atomic_enable(struct drm_bridge *bridge, 127 struct drm_atomic_state *state) 128 { 129 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 130 const struct drm_bridge_state *bridge_state; 131 const struct drm_crtc_state *crtc_state; 132 const struct drm_display_mode *mode; 133 struct drm_connector *connector; 134 struct drm_crtc *crtc; 135 unsigned long configured_link_freq; 136 unsigned long requested_link_freq; 137 bool lvds_format_24bpp; 138 bool lvds_format_jeida; 139 u32 reg; 140 141 /* Get the LVDS format from the bridge state. */ 142 bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 143 144 switch (bridge_state->output_bus_cfg.format) { 145 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 146 lvds_format_24bpp = false; 147 lvds_format_jeida = true; 148 break; 149 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 150 lvds_format_24bpp = true; 151 lvds_format_jeida = true; 152 break; 153 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 154 lvds_format_24bpp = true; 155 lvds_format_jeida = false; 156 break; 157 default: 158 /* 159 * Some bridges still don't set the correct LVDS bus pixel 160 * format, use SPWG24 default format until those are fixed. 161 */ 162 lvds_format_24bpp = true; 163 lvds_format_jeida = false; 164 dev_warn(fsl_ldb->dev, 165 "Unsupported LVDS bus format 0x%04x, please check output bridge driver. Falling back to SPWG24.\n", 166 bridge_state->output_bus_cfg.format); 167 break; 168 } 169 170 /* 171 * Retrieve the CRTC adjusted mode. This requires a little dance to go 172 * from the bridge to the encoder, to the connector and to the CRTC. 173 */ 174 connector = drm_atomic_get_new_connector_for_encoder(state, 175 bridge->encoder); 176 crtc = drm_atomic_get_new_connector_state(state, connector)->crtc; 177 crtc_state = drm_atomic_get_new_crtc_state(state, crtc); 178 mode = &crtc_state->adjusted_mode; 179 180 requested_link_freq = fsl_ldb_link_frequency(fsl_ldb, mode->clock); 181 clk_set_rate(fsl_ldb->clk, requested_link_freq); 182 183 configured_link_freq = clk_get_rate(fsl_ldb->clk); 184 if (configured_link_freq != requested_link_freq) 185 dev_warn(fsl_ldb->dev, 186 "Configured %pC clock (%lu Hz) does not match requested LVDS clock: %lu Hz\n", 187 fsl_ldb->clk, configured_link_freq, requested_link_freq); 188 189 clk_prepare_enable(fsl_ldb->clk); 190 191 /* Program LDB_CTRL */ 192 reg = (fsl_ldb->ch0_enabled ? LDB_CTRL_CH0_ENABLE : 0) | 193 (fsl_ldb->ch1_enabled ? LDB_CTRL_CH1_ENABLE : 0) | 194 (fsl_ldb_is_dual(fsl_ldb) ? LDB_CTRL_SPLIT_MODE : 0); 195 196 if (lvds_format_24bpp) 197 reg |= (fsl_ldb->ch0_enabled ? LDB_CTRL_CH0_DATA_WIDTH : 0) | 198 (fsl_ldb->ch1_enabled ? LDB_CTRL_CH1_DATA_WIDTH : 0); 199 200 if (lvds_format_jeida) 201 reg |= (fsl_ldb->ch0_enabled ? LDB_CTRL_CH0_BIT_MAPPING : 0) | 202 (fsl_ldb->ch1_enabled ? LDB_CTRL_CH1_BIT_MAPPING : 0); 203 204 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 205 reg |= (fsl_ldb->ch0_enabled ? LDB_CTRL_DI0_VSYNC_POLARITY : 0) | 206 (fsl_ldb->ch1_enabled ? LDB_CTRL_DI1_VSYNC_POLARITY : 0); 207 208 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, reg); 209 210 if (fsl_ldb->devdata->single_ctrl_reg) 211 return; 212 213 /* Program LVDS_CTRL */ 214 reg = LVDS_CTRL_CC_ADJ(2) | LVDS_CTRL_PRE_EMPH_EN | 215 LVDS_CTRL_PRE_EMPH_ADJ(3) | LVDS_CTRL_VBG_EN; 216 217 if (fsl_ldb->use_termination_resistor) 218 reg |= LVDS_CTRL_HS_EN; 219 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, reg); 220 221 /* Wait for VBG to stabilize. */ 222 usleep_range(15, 20); 223 224 reg |= (fsl_ldb->ch0_enabled ? LVDS_CTRL_CH0_EN : 0) | 225 (fsl_ldb->ch1_enabled ? LVDS_CTRL_CH1_EN : 0); 226 227 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, reg); 228 } 229 230 static void fsl_ldb_atomic_disable(struct drm_bridge *bridge, 231 struct drm_atomic_state *state) 232 { 233 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 234 235 /* Stop channel(s). */ 236 if (fsl_ldb->devdata->lvds_en_bit) 237 /* Set LVDS_CTRL_LVDS_EN bit to disable. */ 238 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 239 LVDS_CTRL_LVDS_EN); 240 else 241 if (!fsl_ldb->devdata->single_ctrl_reg) 242 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->lvds_ctrl, 0); 243 regmap_write(fsl_ldb->regmap, fsl_ldb->devdata->ldb_ctrl, 0); 244 245 clk_disable_unprepare(fsl_ldb->clk); 246 } 247 248 #define MAX_INPUT_SEL_FORMATS 1 249 static u32 * 250 fsl_ldb_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 251 struct drm_bridge_state *bridge_state, 252 struct drm_crtc_state *crtc_state, 253 struct drm_connector_state *conn_state, 254 u32 output_fmt, 255 unsigned int *num_input_fmts) 256 { 257 u32 *input_fmts; 258 259 *num_input_fmts = 0; 260 261 input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 262 GFP_KERNEL); 263 if (!input_fmts) 264 return NULL; 265 266 input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 267 *num_input_fmts = MAX_INPUT_SEL_FORMATS; 268 269 return input_fmts; 270 } 271 272 static enum drm_mode_status 273 fsl_ldb_mode_valid(struct drm_bridge *bridge, 274 const struct drm_display_info *info, 275 const struct drm_display_mode *mode) 276 { 277 struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); 278 279 if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 160000 : 80000)) 280 return MODE_CLOCK_HIGH; 281 282 return MODE_OK; 283 } 284 285 static const struct drm_bridge_funcs funcs = { 286 .attach = fsl_ldb_attach, 287 .atomic_enable = fsl_ldb_atomic_enable, 288 .atomic_disable = fsl_ldb_atomic_disable, 289 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 290 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 291 .atomic_get_input_bus_fmts = fsl_ldb_atomic_get_input_bus_fmts, 292 .atomic_reset = drm_atomic_helper_bridge_reset, 293 .mode_valid = fsl_ldb_mode_valid, 294 }; 295 296 static int fsl_ldb_probe(struct platform_device *pdev) 297 { 298 struct device *dev = &pdev->dev; 299 struct device_node *panel_node; 300 struct device_node *remote1, *remote2; 301 struct drm_panel *panel; 302 struct fsl_ldb *fsl_ldb; 303 int dual_link; 304 305 fsl_ldb = devm_drm_bridge_alloc(dev, struct fsl_ldb, bridge, &funcs); 306 if (IS_ERR(fsl_ldb)) 307 return PTR_ERR(fsl_ldb); 308 309 fsl_ldb->devdata = of_device_get_match_data(dev); 310 if (!fsl_ldb->devdata) 311 return -EINVAL; 312 313 fsl_ldb->dev = &pdev->dev; 314 fsl_ldb->bridge.of_node = dev->of_node; 315 316 fsl_ldb->clk = devm_clk_get(dev, "ldb"); 317 if (IS_ERR(fsl_ldb->clk)) 318 return PTR_ERR(fsl_ldb->clk); 319 320 fsl_ldb->regmap = syscon_node_to_regmap(dev->of_node->parent); 321 if (IS_ERR(fsl_ldb->regmap)) 322 return PTR_ERR(fsl_ldb->regmap); 323 324 /* Locate the remote ports and the panel node */ 325 remote1 = of_graph_get_remote_node(dev->of_node, 1, 0); 326 remote2 = of_graph_get_remote_node(dev->of_node, 2, 0); 327 fsl_ldb->ch0_enabled = (remote1 != NULL); 328 fsl_ldb->ch1_enabled = (remote2 != NULL); 329 panel_node = of_node_get(remote1 ? remote1 : remote2); 330 of_node_put(remote1); 331 of_node_put(remote2); 332 333 if (!fsl_ldb->ch0_enabled && !fsl_ldb->ch1_enabled) { 334 of_node_put(panel_node); 335 return dev_err_probe(dev, -ENXIO, "No panel node found"); 336 } 337 338 dev_dbg(dev, "Using %s\n", 339 fsl_ldb_is_dual(fsl_ldb) ? "dual-link mode" : 340 fsl_ldb->ch0_enabled ? "channel 0" : "channel 1"); 341 342 panel = of_drm_find_panel(panel_node); 343 of_node_put(panel_node); 344 if (IS_ERR(panel)) 345 return PTR_ERR(panel); 346 347 if (of_property_present(dev->of_node, "nxp,enable-termination-resistor")) 348 fsl_ldb->use_termination_resistor = true; 349 350 fsl_ldb->panel_bridge = devm_drm_panel_bridge_add(dev, panel); 351 if (IS_ERR(fsl_ldb->panel_bridge)) 352 return PTR_ERR(fsl_ldb->panel_bridge); 353 354 355 if (fsl_ldb_is_dual(fsl_ldb)) { 356 struct device_node *port1, *port2; 357 358 port1 = of_graph_get_port_by_id(dev->of_node, 1); 359 port2 = of_graph_get_port_by_id(dev->of_node, 2); 360 dual_link = drm_of_lvds_get_dual_link_pixel_order(port1, port2); 361 of_node_put(port1); 362 of_node_put(port2); 363 364 if (dual_link < 0) 365 return dev_err_probe(dev, dual_link, 366 "Error getting dual link configuration\n"); 367 368 /* Only DRM_LVDS_DUAL_LINK_ODD_EVEN_PIXELS is supported */ 369 if (dual_link == DRM_LVDS_DUAL_LINK_EVEN_ODD_PIXELS) { 370 dev_err(dev, "LVDS channel pixel swap not supported.\n"); 371 return -EINVAL; 372 } 373 } 374 375 platform_set_drvdata(pdev, fsl_ldb); 376 377 drm_bridge_add(&fsl_ldb->bridge); 378 379 return 0; 380 } 381 382 static void fsl_ldb_remove(struct platform_device *pdev) 383 { 384 struct fsl_ldb *fsl_ldb = platform_get_drvdata(pdev); 385 386 drm_bridge_remove(&fsl_ldb->bridge); 387 } 388 389 static const struct of_device_id fsl_ldb_match[] = { 390 { .compatible = "fsl,imx6sx-ldb", 391 .data = &fsl_ldb_devdata[IMX6SX_LDB], }, 392 { .compatible = "fsl,imx8mp-ldb", 393 .data = &fsl_ldb_devdata[IMX8MP_LDB], }, 394 { .compatible = "fsl,imx93-ldb", 395 .data = &fsl_ldb_devdata[IMX93_LDB], }, 396 { /* sentinel */ }, 397 }; 398 MODULE_DEVICE_TABLE(of, fsl_ldb_match); 399 400 static struct platform_driver fsl_ldb_driver = { 401 .probe = fsl_ldb_probe, 402 .remove = fsl_ldb_remove, 403 .driver = { 404 .name = "fsl-ldb", 405 .of_match_table = fsl_ldb_match, 406 }, 407 }; 408 module_platform_driver(fsl_ldb_driver); 409 410 MODULE_AUTHOR("Marek Vasut <marex@denx.de>"); 411 MODULE_DESCRIPTION("Freescale i.MX8MP LDB"); 412 MODULE_LICENSE("GPL"); 413