1ce517f18SJagan Teki // SPDX-License-Identifier: GPL-2.0+ 2ce517f18SJagan Teki /* 3ce517f18SJagan Teki * Copyright (C) 2020 Amarula Solutions(India) 4ce517f18SJagan Teki * Author: Jagan Teki <jagan@amarulasolutions.com> 5ce517f18SJagan Teki */ 6ce517f18SJagan Teki 73b26a291SJagan Teki #include <drm/drm_atomic_helper.h> 8ce517f18SJagan Teki #include <drm/drm_of.h> 9ce517f18SJagan Teki #include <drm/drm_print.h> 10ce517f18SJagan Teki #include <drm/drm_mipi_dsi.h> 11ce517f18SJagan Teki 12ce517f18SJagan Teki #include <linux/delay.h> 13ce517f18SJagan Teki #include <linux/gpio/consumer.h> 148dde6f74SMarek Vasut #include <linux/i2c.h> 15ce517f18SJagan Teki #include <linux/module.h> 16ce517f18SJagan Teki #include <linux/of_device.h> 17ce517f18SJagan Teki #include <linux/regulator/consumer.h> 18ce517f18SJagan Teki 192dcec57bSMarek Vasut #define VENDOR_ID 0x00 202dcec57bSMarek Vasut #define DEVICE_ID_H 0x01 212dcec57bSMarek Vasut #define DEVICE_ID_L 0x02 222dcec57bSMarek Vasut #define VERSION_ID 0x03 232dcec57bSMarek Vasut #define FIRMWARE_VERSION 0x08 242dcec57bSMarek Vasut #define CONFIG_FINISH 0x09 252dcec57bSMarek Vasut #define PD_CTRL(n) (0x0a + ((n) & 0x3)) /* 0..3 */ 262dcec57bSMarek Vasut #define RST_CTRL(n) (0x0e + ((n) & 0x1)) /* 0..1 */ 272dcec57bSMarek Vasut #define SYS_CTRL(n) (0x10 + ((n) & 0x7)) /* 0..4 */ 282dcec57bSMarek Vasut #define RGB_DRV(n) (0x18 + ((n) & 0x3)) /* 0..3 */ 292dcec57bSMarek Vasut #define RGB_DLY(n) (0x1c + ((n) & 0x1)) /* 0..1 */ 302dcec57bSMarek Vasut #define RGB_TEST_CTRL 0x1e 312dcec57bSMarek Vasut #define ATE_PLL_EN 0x1f 32ce517f18SJagan Teki #define HACTIVE_LI 0x20 33ce517f18SJagan Teki #define VACTIVE_LI 0x21 34ce517f18SJagan Teki #define VACTIVE_HACTIVE_HI 0x22 35ce517f18SJagan Teki #define HFP_LI 0x23 36ce517f18SJagan Teki #define HSYNC_LI 0x24 37ce517f18SJagan Teki #define HBP_LI 0x25 38ce517f18SJagan Teki #define HFP_HSW_HBP_HI 0x26 39c0ff7a64SMarek Vasut #define HFP_HSW_HBP_HI_HFP(n) (((n) & 0x300) >> 4) 40c0ff7a64SMarek Vasut #define HFP_HSW_HBP_HI_HS(n) (((n) & 0x300) >> 6) 41c0ff7a64SMarek Vasut #define HFP_HSW_HBP_HI_HBP(n) (((n) & 0x300) >> 8) 42ce517f18SJagan Teki #define VFP 0x27 43ce517f18SJagan Teki #define VSYNC 0x28 44ce517f18SJagan Teki #define VBP 0x29 452dcec57bSMarek Vasut #define BIST_POL 0x2a 462dcec57bSMarek Vasut #define BIST_POL_BIST_MODE(n) (((n) & 0xf) << 4) 472dcec57bSMarek Vasut #define BIST_POL_BIST_GEN BIT(3) 482dcec57bSMarek Vasut #define BIST_POL_HSYNC_POL BIT(2) 492dcec57bSMarek Vasut #define BIST_POL_VSYNC_POL BIT(1) 502dcec57bSMarek Vasut #define BIST_POL_DE_POL BIT(0) 512dcec57bSMarek Vasut #define BIST_RED 0x2b 522dcec57bSMarek Vasut #define BIST_GREEN 0x2c 532dcec57bSMarek Vasut #define BIST_BLUE 0x2d 542dcec57bSMarek Vasut #define BIST_CHESS_X 0x2e 552dcec57bSMarek Vasut #define BIST_CHESS_Y 0x2f 562dcec57bSMarek Vasut #define BIST_CHESS_XY_H 0x30 572dcec57bSMarek Vasut #define BIST_FRAME_TIME_L 0x31 582dcec57bSMarek Vasut #define BIST_FRAME_TIME_H 0x32 592dcec57bSMarek Vasut #define FIFO_MAX_ADDR_LOW 0x33 602dcec57bSMarek Vasut #define SYNC_EVENT_DLY 0x34 612dcec57bSMarek Vasut #define HSW_MIN 0x35 622dcec57bSMarek Vasut #define HFP_MIN 0x36 632dcec57bSMarek Vasut #define LOGIC_RST_NUM 0x37 642dcec57bSMarek Vasut #define OSC_CTRL(n) (0x48 + ((n) & 0x7)) /* 0..5 */ 652dcec57bSMarek Vasut #define BG_CTRL 0x4e 662dcec57bSMarek Vasut #define LDO_PLL 0x4f 672dcec57bSMarek Vasut #define PLL_CTRL(n) (0x50 + ((n) & 0xf)) /* 0..15 */ 682dcec57bSMarek Vasut #define PLL_CTRL_6_EXTERNAL 0x90 692dcec57bSMarek Vasut #define PLL_CTRL_6_MIPI_CLK 0x92 702dcec57bSMarek Vasut #define PLL_CTRL_6_INTERNAL 0x93 712dcec57bSMarek Vasut #define PLL_REM(n) (0x60 + ((n) & 0x3)) /* 0..2 */ 722dcec57bSMarek Vasut #define PLL_DIV(n) (0x63 + ((n) & 0x3)) /* 0..2 */ 732dcec57bSMarek Vasut #define PLL_FRAC(n) (0x66 + ((n) & 0x3)) /* 0..2 */ 742dcec57bSMarek Vasut #define PLL_INT(n) (0x69 + ((n) & 0x1)) /* 0..1 */ 752dcec57bSMarek Vasut #define PLL_REF_DIV 0x6b 762dcec57bSMarek Vasut #define PLL_REF_DIV_P(n) ((n) & 0xf) 772dcec57bSMarek Vasut #define PLL_REF_DIV_Pe BIT(4) 782dcec57bSMarek Vasut #define PLL_REF_DIV_S(n) (((n) & 0x7) << 5) 792dcec57bSMarek Vasut #define PLL_SSC_P(n) (0x6c + ((n) & 0x3)) /* 0..2 */ 802dcec57bSMarek Vasut #define PLL_SSC_STEP(n) (0x6f + ((n) & 0x3)) /* 0..2 */ 812dcec57bSMarek Vasut #define PLL_SSC_OFFSET(n) (0x72 + ((n) & 0x3)) /* 0..3 */ 822dcec57bSMarek Vasut #define GPIO_OEN 0x79 832dcec57bSMarek Vasut #define MIPI_CFG_PW 0x7a 842dcec57bSMarek Vasut #define MIPI_CFG_PW_CONFIG_DSI 0xc1 852dcec57bSMarek Vasut #define MIPI_CFG_PW_CONFIG_I2C 0x3e 862dcec57bSMarek Vasut #define GPIO_SEL(n) (0x7b + ((n) & 0x1)) /* 0..1 */ 872dcec57bSMarek Vasut #define IRQ_SEL 0x7d 882dcec57bSMarek Vasut #define DBG_SEL 0x7e 892dcec57bSMarek Vasut #define DBG_SIGNAL 0x7f 902dcec57bSMarek Vasut #define MIPI_ERR_VECTOR_L 0x80 912dcec57bSMarek Vasut #define MIPI_ERR_VECTOR_H 0x81 922dcec57bSMarek Vasut #define MIPI_ERR_VECTOR_EN_L 0x82 932dcec57bSMarek Vasut #define MIPI_ERR_VECTOR_EN_H 0x83 942dcec57bSMarek Vasut #define MIPI_MAX_SIZE_L 0x84 952dcec57bSMarek Vasut #define MIPI_MAX_SIZE_H 0x85 962dcec57bSMarek Vasut #define DSI_CTRL 0x86 972dcec57bSMarek Vasut #define DSI_CTRL_UNKNOWN 0x28 982dcec57bSMarek Vasut #define DSI_CTRL_DSI_LANES(n) ((n) & 0x3) 992dcec57bSMarek Vasut #define MIPI_PN_SWAP 0x87 1002dcec57bSMarek Vasut #define MIPI_PN_SWAP_CLK BIT(4) 1012dcec57bSMarek Vasut #define MIPI_PN_SWAP_D(n) BIT((n) & 0x3) 1022dcec57bSMarek Vasut #define MIPI_SOT_SYNC_BIT_(n) (0x88 + ((n) & 0x1)) /* 0..1 */ 1032dcec57bSMarek Vasut #define MIPI_ULPS_CTRL 0x8a 1042dcec57bSMarek Vasut #define MIPI_CLK_CHK_VAR 0x8e 1052dcec57bSMarek Vasut #define MIPI_CLK_CHK_INI 0x8f 1062dcec57bSMarek Vasut #define MIPI_T_TERM_EN 0x90 1072dcec57bSMarek Vasut #define MIPI_T_HS_SETTLE 0x91 1082dcec57bSMarek Vasut #define MIPI_T_TA_SURE_PRE 0x92 1092dcec57bSMarek Vasut #define MIPI_T_LPX_SET 0x94 1102dcec57bSMarek Vasut #define MIPI_T_CLK_MISS 0x95 1112dcec57bSMarek Vasut #define MIPI_INIT_TIME_L 0x96 1122dcec57bSMarek Vasut #define MIPI_INIT_TIME_H 0x97 1132dcec57bSMarek Vasut #define MIPI_T_CLK_TERM_EN 0x99 1142dcec57bSMarek Vasut #define MIPI_T_CLK_SETTLE 0x9a 1152dcec57bSMarek Vasut #define MIPI_TO_HS_RX_L 0x9e 1162dcec57bSMarek Vasut #define MIPI_TO_HS_RX_H 0x9f 1172dcec57bSMarek Vasut #define MIPI_PHY_(n) (0xa0 + ((n) & 0x7)) /* 0..5 */ 1182dcec57bSMarek Vasut #define MIPI_PD_RX 0xb0 1192dcec57bSMarek Vasut #define MIPI_PD_TERM 0xb1 1202dcec57bSMarek Vasut #define MIPI_PD_HSRX 0xb2 1212dcec57bSMarek Vasut #define MIPI_PD_LPTX 0xb3 1222dcec57bSMarek Vasut #define MIPI_PD_LPRX 0xb4 1232dcec57bSMarek Vasut #define MIPI_PD_CK_LANE 0xb5 1242dcec57bSMarek Vasut #define MIPI_FORCE_0 0xb6 1252dcec57bSMarek Vasut #define MIPI_RST_CTRL 0xb7 1262dcec57bSMarek Vasut #define MIPI_RST_NUM 0xb8 1272dcec57bSMarek Vasut #define MIPI_DBG_SET_(n) (0xc0 + ((n) & 0xf)) /* 0..9 */ 1282dcec57bSMarek Vasut #define MIPI_DBG_SEL 0xe0 1292dcec57bSMarek Vasut #define MIPI_DBG_DATA 0xe1 1302dcec57bSMarek Vasut #define MIPI_ATE_TEST_SEL 0xe2 1312dcec57bSMarek Vasut #define MIPI_ATE_STATUS_(n) (0xe3 + ((n) & 0x1)) /* 0..1 */ 1322dcec57bSMarek Vasut #define MIPI_ATE_STATUS_1 0xe4 1332dcec57bSMarek Vasut #define ICN6211_MAX_REGISTER MIPI_ATE_STATUS(1) 134ce517f18SJagan Teki 135ce517f18SJagan Teki struct chipone { 136ce517f18SJagan Teki struct device *dev; 1378dde6f74SMarek Vasut struct i2c_client *client; 138ce517f18SJagan Teki struct drm_bridge bridge; 13950d76e3dSJagan Teki struct drm_display_mode mode; 140ce517f18SJagan Teki struct drm_bridge *panel_bridge; 141f30cf0ecSMarek Vasut struct mipi_dsi_device *dsi; 142ce517f18SJagan Teki struct gpio_desc *enable_gpio; 143ce517f18SJagan Teki struct regulator *vdd1; 144ce517f18SJagan Teki struct regulator *vdd2; 145ce517f18SJagan Teki struct regulator *vdd3; 1468dde6f74SMarek Vasut bool interface_i2c; 147ce517f18SJagan Teki }; 148ce517f18SJagan Teki 149ce517f18SJagan Teki static inline struct chipone *bridge_to_chipone(struct drm_bridge *bridge) 150ce517f18SJagan Teki { 151ce517f18SJagan Teki return container_of(bridge, struct chipone, bridge); 152ce517f18SJagan Teki } 153ce517f18SJagan Teki 15417a9c1aaSMarek Vasut static void chipone_readb(struct chipone *icn, u8 reg, u8 *val) 15517a9c1aaSMarek Vasut { 15617a9c1aaSMarek Vasut if (icn->interface_i2c) 15717a9c1aaSMarek Vasut *val = i2c_smbus_read_byte_data(icn->client, reg); 15817a9c1aaSMarek Vasut else 15917a9c1aaSMarek Vasut mipi_dsi_generic_read(icn->dsi, (u8[]){reg, 1}, 2, val, 1); 16017a9c1aaSMarek Vasut } 16117a9c1aaSMarek Vasut 16233f1036bSMarek Vasut static int chipone_writeb(struct chipone *icn, u8 reg, u8 val) 163ce517f18SJagan Teki { 16433f1036bSMarek Vasut if (icn->interface_i2c) 16533f1036bSMarek Vasut return i2c_smbus_write_byte_data(icn->client, reg, val); 16633f1036bSMarek Vasut else 16733f1036bSMarek Vasut return mipi_dsi_generic_write(icn->dsi, (u8[]){reg, val}, 2); 168ce517f18SJagan Teki } 169ce517f18SJagan Teki 170f30cf0ecSMarek Vasut static void chipone_configure_pll(struct chipone *icn, 171f30cf0ecSMarek Vasut const struct drm_display_mode *mode) 172f30cf0ecSMarek Vasut { 173f30cf0ecSMarek Vasut unsigned int best_p = 0, best_m = 0, best_s = 0; 17421d139a9SMarek Vasut unsigned int mode_clock = mode->clock * 1000; 175f30cf0ecSMarek Vasut unsigned int delta, min_delta = 0xffffffff; 176f30cf0ecSMarek Vasut unsigned int freq_p, freq_s, freq_out; 177f30cf0ecSMarek Vasut unsigned int p_min, p_max; 178f30cf0ecSMarek Vasut unsigned int p, m, s; 179f30cf0ecSMarek Vasut unsigned int fin; 18021d139a9SMarek Vasut bool best_p_pot; 18121d139a9SMarek Vasut u8 ref_div; 182f30cf0ecSMarek Vasut 183f30cf0ecSMarek Vasut /* 18421d139a9SMarek Vasut * DSI byte clock frequency (input into PLL) is calculated as: 18521d139a9SMarek Vasut * DSI_CLK = mode clock * bpp / dsi_data_lanes / 8 186f30cf0ecSMarek Vasut * 187f30cf0ecSMarek Vasut * DPI pixel clock frequency (output from PLL) is mode clock. 188f30cf0ecSMarek Vasut * 189f30cf0ecSMarek Vasut * The chip contains fractional PLL which works as follows: 190f30cf0ecSMarek Vasut * DPI_CLK = ((DSI_CLK / P) * M) / S 19121d139a9SMarek Vasut * P is pre-divider, register PLL_REF_DIV[3:0] is 1:n divider 192f30cf0ecSMarek Vasut * register PLL_REF_DIV[4] is extra 1:2 divider 193f30cf0ecSMarek Vasut * M is integer multiplier, register PLL_INT(0) is multiplier 194f30cf0ecSMarek Vasut * S is post-divider, register PLL_REF_DIV[7:5] is 2^(n+1) divider 195f30cf0ecSMarek Vasut * 196f30cf0ecSMarek Vasut * It seems the PLL input clock after applying P pre-divider have 197f30cf0ecSMarek Vasut * to be lower than 20 MHz. 198f30cf0ecSMarek Vasut */ 19921d139a9SMarek Vasut fin = mode_clock * mipi_dsi_pixel_format_to_bpp(icn->dsi->format) / 20021d139a9SMarek Vasut icn->dsi->lanes / 8; /* in Hz */ 201f30cf0ecSMarek Vasut 202f30cf0ecSMarek Vasut /* Minimum value of P predivider for PLL input in 5..20 MHz */ 20321d139a9SMarek Vasut p_min = clamp(DIV_ROUND_UP(fin, 20000000), 1U, 31U); 20421d139a9SMarek Vasut p_max = clamp(fin / 5000000, 1U, 31U); 205f30cf0ecSMarek Vasut 206f30cf0ecSMarek Vasut for (p = p_min; p < p_max; p++) { /* PLL_REF_DIV[4,3:0] */ 20721d139a9SMarek Vasut if (p > 16 && p & 1) /* P > 16 uses extra /2 */ 20821d139a9SMarek Vasut continue; 20921d139a9SMarek Vasut freq_p = fin / p; 210f30cf0ecSMarek Vasut if (freq_p == 0) /* Divider too high */ 211f30cf0ecSMarek Vasut break; 212f30cf0ecSMarek Vasut 213f30cf0ecSMarek Vasut for (s = 0; s < 0x7; s++) { /* PLL_REF_DIV[7:5] */ 214f30cf0ecSMarek Vasut freq_s = freq_p / BIT(s + 1); 215f30cf0ecSMarek Vasut if (freq_s == 0) /* Divider too high */ 216f30cf0ecSMarek Vasut break; 217f30cf0ecSMarek Vasut 21821d139a9SMarek Vasut m = mode_clock / freq_s; 219f30cf0ecSMarek Vasut 220f30cf0ecSMarek Vasut /* Multiplier is 8 bit */ 221f30cf0ecSMarek Vasut if (m > 0xff) 222f30cf0ecSMarek Vasut continue; 223f30cf0ecSMarek Vasut 224f30cf0ecSMarek Vasut /* Limit PLL VCO frequency to 1 GHz */ 22521d139a9SMarek Vasut freq_out = (fin * m) / p; 22621d139a9SMarek Vasut if (freq_out > 1000000000) 227f30cf0ecSMarek Vasut continue; 228f30cf0ecSMarek Vasut 229f30cf0ecSMarek Vasut /* Apply post-divider */ 230f30cf0ecSMarek Vasut freq_out /= BIT(s + 1); 231f30cf0ecSMarek Vasut 23221d139a9SMarek Vasut delta = abs(mode_clock - freq_out); 233f30cf0ecSMarek Vasut if (delta < min_delta) { 234f30cf0ecSMarek Vasut best_p = p; 235f30cf0ecSMarek Vasut best_m = m; 236f30cf0ecSMarek Vasut best_s = s; 237f30cf0ecSMarek Vasut min_delta = delta; 238f30cf0ecSMarek Vasut } 239f30cf0ecSMarek Vasut } 240f30cf0ecSMarek Vasut } 241f30cf0ecSMarek Vasut 24221d139a9SMarek Vasut best_p_pot = !(best_p & 1); 24321d139a9SMarek Vasut 244f30cf0ecSMarek Vasut dev_dbg(icn->dev, 24521d139a9SMarek Vasut "PLL: P[3:0]=%d P[4]=2*%d M=%d S[7:5]=2^%d delta=%d => DSI f_in=%d Hz ; DPI f_out=%d Hz\n", 24621d139a9SMarek Vasut best_p >> best_p_pot, best_p_pot, best_m, best_s + 1, 24721d139a9SMarek Vasut min_delta, fin, (fin * best_m) / (best_p << (best_s + 1))); 24821d139a9SMarek Vasut 24921d139a9SMarek Vasut ref_div = PLL_REF_DIV_P(best_p >> best_p_pot) | PLL_REF_DIV_S(best_s); 25021d139a9SMarek Vasut if (best_p_pot) /* Prefer /2 pre-divider */ 25121d139a9SMarek Vasut ref_div |= PLL_REF_DIV_Pe; 252f30cf0ecSMarek Vasut 253f30cf0ecSMarek Vasut /* Clock source selection fixed to MIPI DSI clock lane */ 25433f1036bSMarek Vasut chipone_writeb(icn, PLL_CTRL(6), PLL_CTRL_6_MIPI_CLK); 25521d139a9SMarek Vasut chipone_writeb(icn, PLL_REF_DIV, ref_div); 25633f1036bSMarek Vasut chipone_writeb(icn, PLL_INT(0), best_m); 257f30cf0ecSMarek Vasut } 258f30cf0ecSMarek Vasut 2593b26a291SJagan Teki static void chipone_atomic_enable(struct drm_bridge *bridge, 2603b26a291SJagan Teki struct drm_bridge_state *old_bridge_state) 261ce517f18SJagan Teki { 262ce517f18SJagan Teki struct chipone *icn = bridge_to_chipone(bridge); 2632dff97f2SMarek Vasut struct drm_atomic_state *state = old_bridge_state->base.state; 26450d76e3dSJagan Teki struct drm_display_mode *mode = &icn->mode; 2652dff97f2SMarek Vasut const struct drm_bridge_state *bridge_state; 266c0ff7a64SMarek Vasut u16 hfp, hbp, hsync; 2672dff97f2SMarek Vasut u32 bus_flags; 26817a9c1aaSMarek Vasut u8 pol, id[4]; 26917a9c1aaSMarek Vasut 27017a9c1aaSMarek Vasut chipone_readb(icn, VENDOR_ID, id); 27117a9c1aaSMarek Vasut chipone_readb(icn, DEVICE_ID_H, id + 1); 27217a9c1aaSMarek Vasut chipone_readb(icn, DEVICE_ID_L, id + 2); 27317a9c1aaSMarek Vasut chipone_readb(icn, VERSION_ID, id + 3); 27417a9c1aaSMarek Vasut 27517a9c1aaSMarek Vasut dev_dbg(icn->dev, 27617a9c1aaSMarek Vasut "Chip IDs: Vendor=0x%02x Device=0x%02x:0x%02x Version=0x%02x\n", 27717a9c1aaSMarek Vasut id[0], id[1], id[2], id[3]); 27817a9c1aaSMarek Vasut 27917a9c1aaSMarek Vasut if (id[0] != 0xc1 || id[1] != 0x62 || id[2] != 0x11) { 28017a9c1aaSMarek Vasut dev_dbg(icn->dev, "Invalid Chip IDs, aborting configuration\n"); 28117a9c1aaSMarek Vasut return; 28217a9c1aaSMarek Vasut } 2832dff97f2SMarek Vasut 2842dff97f2SMarek Vasut /* Get the DPI flags from the bridge state. */ 2852dff97f2SMarek Vasut bridge_state = drm_atomic_get_new_bridge_state(state, bridge); 2862dff97f2SMarek Vasut bus_flags = bridge_state->output_bus_cfg.flags; 287ce517f18SJagan Teki 2888dde6f74SMarek Vasut if (icn->interface_i2c) 28933f1036bSMarek Vasut chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_I2C); 2908dde6f74SMarek Vasut else 29133f1036bSMarek Vasut chipone_writeb(icn, MIPI_CFG_PW, MIPI_CFG_PW_CONFIG_DSI); 292ce517f18SJagan Teki 29333f1036bSMarek Vasut chipone_writeb(icn, HACTIVE_LI, mode->hdisplay & 0xff); 294ce517f18SJagan Teki 29533f1036bSMarek Vasut chipone_writeb(icn, VACTIVE_LI, mode->vdisplay & 0xff); 296ce517f18SJagan Teki 2972dcec57bSMarek Vasut /* 298ce517f18SJagan Teki * lsb nibble: 2nd nibble of hdisplay 299ce517f18SJagan Teki * msb nibble: 2nd nibble of vdisplay 300ce517f18SJagan Teki */ 30133f1036bSMarek Vasut chipone_writeb(icn, VACTIVE_HACTIVE_HI, 302ce517f18SJagan Teki ((mode->hdisplay >> 8) & 0xf) | 303ce517f18SJagan Teki (((mode->vdisplay >> 8) & 0xf) << 4)); 304ce517f18SJagan Teki 305c0ff7a64SMarek Vasut hfp = mode->hsync_start - mode->hdisplay; 306c0ff7a64SMarek Vasut hsync = mode->hsync_end - mode->hsync_start; 307c0ff7a64SMarek Vasut hbp = mode->htotal - mode->hsync_end; 308ce517f18SJagan Teki 30933f1036bSMarek Vasut chipone_writeb(icn, HFP_LI, hfp & 0xff); 31033f1036bSMarek Vasut chipone_writeb(icn, HSYNC_LI, hsync & 0xff); 31133f1036bSMarek Vasut chipone_writeb(icn, HBP_LI, hbp & 0xff); 312c0ff7a64SMarek Vasut /* Top two bits of Horizontal Front porch/Sync/Back porch */ 31333f1036bSMarek Vasut chipone_writeb(icn, HFP_HSW_HBP_HI, 314c0ff7a64SMarek Vasut HFP_HSW_HBP_HI_HFP(hfp) | 315c0ff7a64SMarek Vasut HFP_HSW_HBP_HI_HS(hsync) | 316c0ff7a64SMarek Vasut HFP_HSW_HBP_HI_HBP(hbp)); 317ce517f18SJagan Teki 31833f1036bSMarek Vasut chipone_writeb(icn, VFP, mode->vsync_start - mode->vdisplay); 319ce517f18SJagan Teki 32033f1036bSMarek Vasut chipone_writeb(icn, VSYNC, mode->vsync_end - mode->vsync_start); 321ce517f18SJagan Teki 32233f1036bSMarek Vasut chipone_writeb(icn, VBP, mode->vtotal - mode->vsync_end); 323ce517f18SJagan Teki 324ce517f18SJagan Teki /* dsi specific sequence */ 32533f1036bSMarek Vasut chipone_writeb(icn, SYNC_EVENT_DLY, 0x80); 32633f1036bSMarek Vasut chipone_writeb(icn, HFP_MIN, hfp & 0xff); 32733f1036bSMarek Vasut chipone_writeb(icn, MIPI_PD_CK_LANE, 0xa0); 32833f1036bSMarek Vasut chipone_writeb(icn, PLL_CTRL(12), 0xff); 32933f1036bSMarek Vasut chipone_writeb(icn, MIPI_PN_SWAP, 0x00); 3302dff97f2SMarek Vasut 3312dff97f2SMarek Vasut /* DPI HS/VS/DE polarity */ 3322dff97f2SMarek Vasut pol = ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? BIST_POL_HSYNC_POL : 0) | 3332dff97f2SMarek Vasut ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? BIST_POL_VSYNC_POL : 0) | 3342dff97f2SMarek Vasut ((bus_flags & DRM_BUS_FLAG_DE_HIGH) ? BIST_POL_DE_POL : 0); 33533f1036bSMarek Vasut chipone_writeb(icn, BIST_POL, pol); 3362dff97f2SMarek Vasut 337f30cf0ecSMarek Vasut /* Configure PLL settings */ 338f30cf0ecSMarek Vasut chipone_configure_pll(icn, mode); 339f30cf0ecSMarek Vasut 34033f1036bSMarek Vasut chipone_writeb(icn, SYS_CTRL(0), 0x40); 34133f1036bSMarek Vasut chipone_writeb(icn, SYS_CTRL(1), 0x88); 342ce517f18SJagan Teki 343ce517f18SJagan Teki /* icn6211 specific sequence */ 34433f1036bSMarek Vasut chipone_writeb(icn, MIPI_FORCE_0, 0x20); 34533f1036bSMarek Vasut chipone_writeb(icn, PLL_CTRL(1), 0x20); 34633f1036bSMarek Vasut chipone_writeb(icn, CONFIG_FINISH, 0x10); 347ce517f18SJagan Teki 348ce517f18SJagan Teki usleep_range(10000, 11000); 349ce517f18SJagan Teki } 350ce517f18SJagan Teki 3513b26a291SJagan Teki static void chipone_atomic_pre_enable(struct drm_bridge *bridge, 3523b26a291SJagan Teki struct drm_bridge_state *old_bridge_state) 353ce517f18SJagan Teki { 354ce517f18SJagan Teki struct chipone *icn = bridge_to_chipone(bridge); 355ce517f18SJagan Teki int ret; 356ce517f18SJagan Teki 357ce517f18SJagan Teki if (icn->vdd1) { 358ce517f18SJagan Teki ret = regulator_enable(icn->vdd1); 359ce517f18SJagan Teki if (ret) 360ce517f18SJagan Teki DRM_DEV_ERROR(icn->dev, 361ce517f18SJagan Teki "failed to enable VDD1 regulator: %d\n", ret); 362ce517f18SJagan Teki } 363ce517f18SJagan Teki 364ce517f18SJagan Teki if (icn->vdd2) { 365ce517f18SJagan Teki ret = regulator_enable(icn->vdd2); 366ce517f18SJagan Teki if (ret) 367ce517f18SJagan Teki DRM_DEV_ERROR(icn->dev, 368ce517f18SJagan Teki "failed to enable VDD2 regulator: %d\n", ret); 369ce517f18SJagan Teki } 370ce517f18SJagan Teki 371ce517f18SJagan Teki if (icn->vdd3) { 372ce517f18SJagan Teki ret = regulator_enable(icn->vdd3); 373ce517f18SJagan Teki if (ret) 374ce517f18SJagan Teki DRM_DEV_ERROR(icn->dev, 375ce517f18SJagan Teki "failed to enable VDD3 regulator: %d\n", ret); 376ce517f18SJagan Teki } 377ce517f18SJagan Teki 378ce517f18SJagan Teki gpiod_set_value(icn->enable_gpio, 1); 379ce517f18SJagan Teki 380ce517f18SJagan Teki usleep_range(10000, 11000); 381ce517f18SJagan Teki } 382ce517f18SJagan Teki 3833b26a291SJagan Teki static void chipone_atomic_post_disable(struct drm_bridge *bridge, 3843b26a291SJagan Teki struct drm_bridge_state *old_bridge_state) 385ce517f18SJagan Teki { 386ce517f18SJagan Teki struct chipone *icn = bridge_to_chipone(bridge); 387ce517f18SJagan Teki 388ce517f18SJagan Teki if (icn->vdd1) 389ce517f18SJagan Teki regulator_disable(icn->vdd1); 390ce517f18SJagan Teki 391ce517f18SJagan Teki if (icn->vdd2) 392ce517f18SJagan Teki regulator_disable(icn->vdd2); 393ce517f18SJagan Teki 394ce517f18SJagan Teki if (icn->vdd3) 395ce517f18SJagan Teki regulator_disable(icn->vdd3); 396ce517f18SJagan Teki 397ce517f18SJagan Teki gpiod_set_value(icn->enable_gpio, 0); 398ce517f18SJagan Teki } 399ce517f18SJagan Teki 40050d76e3dSJagan Teki static void chipone_mode_set(struct drm_bridge *bridge, 40150d76e3dSJagan Teki const struct drm_display_mode *mode, 40250d76e3dSJagan Teki const struct drm_display_mode *adjusted_mode) 40350d76e3dSJagan Teki { 40450d76e3dSJagan Teki struct chipone *icn = bridge_to_chipone(bridge); 40550d76e3dSJagan Teki 40650d76e3dSJagan Teki drm_mode_copy(&icn->mode, adjusted_mode); 4078dde6f74SMarek Vasut }; 4088dde6f74SMarek Vasut 4098dde6f74SMarek Vasut static int chipone_dsi_attach(struct chipone *icn) 4108dde6f74SMarek Vasut { 4118dde6f74SMarek Vasut struct mipi_dsi_device *dsi = icn->dsi; 4128dde6f74SMarek Vasut int ret; 4138dde6f74SMarek Vasut 4148dde6f74SMarek Vasut dsi->lanes = 4; 4158dde6f74SMarek Vasut dsi->format = MIPI_DSI_FMT_RGB888; 4168dde6f74SMarek Vasut dsi->mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST | 4178dde6f74SMarek Vasut MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET; 4188dde6f74SMarek Vasut 4198dde6f74SMarek Vasut ret = mipi_dsi_attach(dsi); 4208dde6f74SMarek Vasut if (ret < 0) 4218dde6f74SMarek Vasut dev_err(icn->dev, "failed to attach dsi\n"); 4228dde6f74SMarek Vasut 4238dde6f74SMarek Vasut return ret; 4248dde6f74SMarek Vasut } 4258dde6f74SMarek Vasut 4268dde6f74SMarek Vasut static int chipone_dsi_host_attach(struct chipone *icn) 4278dde6f74SMarek Vasut { 4288dde6f74SMarek Vasut struct device *dev = icn->dev; 4298dde6f74SMarek Vasut struct device_node *host_node; 4308dde6f74SMarek Vasut struct device_node *endpoint; 4318dde6f74SMarek Vasut struct mipi_dsi_device *dsi; 4328dde6f74SMarek Vasut struct mipi_dsi_host *host; 4338dde6f74SMarek Vasut int ret = 0; 4348dde6f74SMarek Vasut 4358dde6f74SMarek Vasut const struct mipi_dsi_device_info info = { 4368dde6f74SMarek Vasut .type = "chipone", 4378dde6f74SMarek Vasut .channel = 0, 4388dde6f74SMarek Vasut .node = NULL, 4398dde6f74SMarek Vasut }; 4408dde6f74SMarek Vasut 4418dde6f74SMarek Vasut endpoint = of_graph_get_endpoint_by_regs(dev->of_node, 0, 0); 4428dde6f74SMarek Vasut host_node = of_graph_get_remote_port_parent(endpoint); 4438dde6f74SMarek Vasut of_node_put(endpoint); 4448dde6f74SMarek Vasut 4458dde6f74SMarek Vasut if (!host_node) 4468dde6f74SMarek Vasut return -EINVAL; 4478dde6f74SMarek Vasut 4488dde6f74SMarek Vasut host = of_find_mipi_dsi_host_by_node(host_node); 4498dde6f74SMarek Vasut of_node_put(host_node); 4508dde6f74SMarek Vasut if (!host) { 4518dde6f74SMarek Vasut dev_err(dev, "failed to find dsi host\n"); 4528dde6f74SMarek Vasut return -EPROBE_DEFER; 4538dde6f74SMarek Vasut } 4548dde6f74SMarek Vasut 4558dde6f74SMarek Vasut dsi = mipi_dsi_device_register_full(host, &info); 4568dde6f74SMarek Vasut if (IS_ERR(dsi)) { 4578dde6f74SMarek Vasut return dev_err_probe(dev, PTR_ERR(dsi), 4588dde6f74SMarek Vasut "failed to create dsi device\n"); 4598dde6f74SMarek Vasut } 4608dde6f74SMarek Vasut 4618dde6f74SMarek Vasut icn->dsi = dsi; 4628dde6f74SMarek Vasut 4638dde6f74SMarek Vasut ret = chipone_dsi_attach(icn); 4648dde6f74SMarek Vasut if (ret < 0) 4658dde6f74SMarek Vasut mipi_dsi_device_unregister(dsi); 4668dde6f74SMarek Vasut 4678dde6f74SMarek Vasut return ret; 46850d76e3dSJagan Teki } 46950d76e3dSJagan Teki 470ce517f18SJagan Teki static int chipone_attach(struct drm_bridge *bridge, enum drm_bridge_attach_flags flags) 471ce517f18SJagan Teki { 472ce517f18SJagan Teki struct chipone *icn = bridge_to_chipone(bridge); 473ce517f18SJagan Teki 474ce517f18SJagan Teki return drm_bridge_attach(bridge->encoder, icn->panel_bridge, bridge, flags); 475ce517f18SJagan Teki } 476ce517f18SJagan Teki 477cda3822aSMarek Vasut #define MAX_INPUT_SEL_FORMATS 1 478cda3822aSMarek Vasut 479cda3822aSMarek Vasut static u32 * 480cda3822aSMarek Vasut chipone_atomic_get_input_bus_fmts(struct drm_bridge *bridge, 481cda3822aSMarek Vasut struct drm_bridge_state *bridge_state, 482cda3822aSMarek Vasut struct drm_crtc_state *crtc_state, 483cda3822aSMarek Vasut struct drm_connector_state *conn_state, 484cda3822aSMarek Vasut u32 output_fmt, 485cda3822aSMarek Vasut unsigned int *num_input_fmts) 486cda3822aSMarek Vasut { 487cda3822aSMarek Vasut u32 *input_fmts; 488cda3822aSMarek Vasut 489cda3822aSMarek Vasut *num_input_fmts = 0; 490cda3822aSMarek Vasut 491cda3822aSMarek Vasut input_fmts = kcalloc(MAX_INPUT_SEL_FORMATS, sizeof(*input_fmts), 492cda3822aSMarek Vasut GFP_KERNEL); 493cda3822aSMarek Vasut if (!input_fmts) 494cda3822aSMarek Vasut return NULL; 495cda3822aSMarek Vasut 496cda3822aSMarek Vasut /* This is the DSI-end bus format */ 497cda3822aSMarek Vasut input_fmts[0] = MEDIA_BUS_FMT_RGB888_1X24; 498cda3822aSMarek Vasut *num_input_fmts = 1; 499cda3822aSMarek Vasut 500cda3822aSMarek Vasut return input_fmts; 501cda3822aSMarek Vasut } 502cda3822aSMarek Vasut 503ce517f18SJagan Teki static const struct drm_bridge_funcs chipone_bridge_funcs = { 5043b26a291SJagan Teki .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 5053b26a291SJagan Teki .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 5063b26a291SJagan Teki .atomic_reset = drm_atomic_helper_bridge_reset, 5073b26a291SJagan Teki .atomic_pre_enable = chipone_atomic_pre_enable, 5083b26a291SJagan Teki .atomic_enable = chipone_atomic_enable, 5093b26a291SJagan Teki .atomic_post_disable = chipone_atomic_post_disable, 51050d76e3dSJagan Teki .mode_set = chipone_mode_set, 511ce517f18SJagan Teki .attach = chipone_attach, 512cda3822aSMarek Vasut .atomic_get_input_bus_fmts = chipone_atomic_get_input_bus_fmts, 513ce517f18SJagan Teki }; 514ce517f18SJagan Teki 515ce517f18SJagan Teki static int chipone_parse_dt(struct chipone *icn) 516ce517f18SJagan Teki { 517ce517f18SJagan Teki struct device *dev = icn->dev; 518ce517f18SJagan Teki int ret; 519ce517f18SJagan Teki 520ce517f18SJagan Teki icn->vdd1 = devm_regulator_get_optional(dev, "vdd1"); 521ce517f18SJagan Teki if (IS_ERR(icn->vdd1)) { 522ce517f18SJagan Teki ret = PTR_ERR(icn->vdd1); 523ce517f18SJagan Teki if (ret == -EPROBE_DEFER) 524ce517f18SJagan Teki return -EPROBE_DEFER; 525ce517f18SJagan Teki icn->vdd1 = NULL; 526ce517f18SJagan Teki DRM_DEV_DEBUG(dev, "failed to get VDD1 regulator: %d\n", ret); 527ce517f18SJagan Teki } 528ce517f18SJagan Teki 529ce517f18SJagan Teki icn->vdd2 = devm_regulator_get_optional(dev, "vdd2"); 530ce517f18SJagan Teki if (IS_ERR(icn->vdd2)) { 531ce517f18SJagan Teki ret = PTR_ERR(icn->vdd2); 532ce517f18SJagan Teki if (ret == -EPROBE_DEFER) 533ce517f18SJagan Teki return -EPROBE_DEFER; 534ce517f18SJagan Teki icn->vdd2 = NULL; 535ce517f18SJagan Teki DRM_DEV_DEBUG(dev, "failed to get VDD2 regulator: %d\n", ret); 536ce517f18SJagan Teki } 537ce517f18SJagan Teki 538ce517f18SJagan Teki icn->vdd3 = devm_regulator_get_optional(dev, "vdd3"); 539ce517f18SJagan Teki if (IS_ERR(icn->vdd3)) { 540ce517f18SJagan Teki ret = PTR_ERR(icn->vdd3); 541ce517f18SJagan Teki if (ret == -EPROBE_DEFER) 542ce517f18SJagan Teki return -EPROBE_DEFER; 543ce517f18SJagan Teki icn->vdd3 = NULL; 544ce517f18SJagan Teki DRM_DEV_DEBUG(dev, "failed to get VDD3 regulator: %d\n", ret); 545ce517f18SJagan Teki } 546ce517f18SJagan Teki 547ce517f18SJagan Teki icn->enable_gpio = devm_gpiod_get(dev, "enable", GPIOD_OUT_LOW); 548ce517f18SJagan Teki if (IS_ERR(icn->enable_gpio)) { 549ce517f18SJagan Teki DRM_DEV_ERROR(dev, "failed to get enable GPIO\n"); 550ce517f18SJagan Teki return PTR_ERR(icn->enable_gpio); 551ce517f18SJagan Teki } 552ce517f18SJagan Teki 553c803ae6dSJosé Expósito icn->panel_bridge = devm_drm_of_get_bridge(dev, dev->of_node, 1, 0); 554ce517f18SJagan Teki if (IS_ERR(icn->panel_bridge)) 555ce517f18SJagan Teki return PTR_ERR(icn->panel_bridge); 556ce517f18SJagan Teki 557ce517f18SJagan Teki return 0; 558ce517f18SJagan Teki } 559ce517f18SJagan Teki 5608dde6f74SMarek Vasut static int chipone_common_probe(struct device *dev, struct chipone **icnr) 561ce517f18SJagan Teki { 562ce517f18SJagan Teki struct chipone *icn; 563ce517f18SJagan Teki int ret; 564ce517f18SJagan Teki 565ce517f18SJagan Teki icn = devm_kzalloc(dev, sizeof(struct chipone), GFP_KERNEL); 566ce517f18SJagan Teki if (!icn) 567ce517f18SJagan Teki return -ENOMEM; 568ce517f18SJagan Teki 569ce517f18SJagan Teki icn->dev = dev; 570ce517f18SJagan Teki 571ce517f18SJagan Teki ret = chipone_parse_dt(icn); 572ce517f18SJagan Teki if (ret) 573ce517f18SJagan Teki return ret; 574ce517f18SJagan Teki 575ce517f18SJagan Teki icn->bridge.funcs = &chipone_bridge_funcs; 576ce517f18SJagan Teki icn->bridge.type = DRM_MODE_CONNECTOR_DPI; 577ce517f18SJagan Teki icn->bridge.of_node = dev->of_node; 578ce517f18SJagan Teki 5798dde6f74SMarek Vasut *icnr = icn; 580ce517f18SJagan Teki 581ce517f18SJagan Teki return ret; 582ce517f18SJagan Teki } 583ce517f18SJagan Teki 5848dde6f74SMarek Vasut static int chipone_dsi_probe(struct mipi_dsi_device *dsi) 5858dde6f74SMarek Vasut { 5868dde6f74SMarek Vasut struct device *dev = &dsi->dev; 5878dde6f74SMarek Vasut struct chipone *icn; 5888dde6f74SMarek Vasut int ret; 5898dde6f74SMarek Vasut 5908dde6f74SMarek Vasut ret = chipone_common_probe(dev, &icn); 5918dde6f74SMarek Vasut if (ret) 5928dde6f74SMarek Vasut return ret; 5938dde6f74SMarek Vasut 5948dde6f74SMarek Vasut icn->interface_i2c = false; 5958dde6f74SMarek Vasut icn->dsi = dsi; 5968dde6f74SMarek Vasut 5978dde6f74SMarek Vasut mipi_dsi_set_drvdata(dsi, icn); 5988dde6f74SMarek Vasut 5998dde6f74SMarek Vasut drm_bridge_add(&icn->bridge); 6008dde6f74SMarek Vasut 6018dde6f74SMarek Vasut ret = chipone_dsi_attach(icn); 6028dde6f74SMarek Vasut if (ret) 6038dde6f74SMarek Vasut drm_bridge_remove(&icn->bridge); 6048dde6f74SMarek Vasut 6058dde6f74SMarek Vasut return ret; 6068dde6f74SMarek Vasut } 6078dde6f74SMarek Vasut 6088dde6f74SMarek Vasut static int chipone_i2c_probe(struct i2c_client *client, 6098dde6f74SMarek Vasut const struct i2c_device_id *id) 6108dde6f74SMarek Vasut { 6118dde6f74SMarek Vasut struct device *dev = &client->dev; 6128dde6f74SMarek Vasut struct chipone *icn; 6138dde6f74SMarek Vasut int ret; 6148dde6f74SMarek Vasut 6158dde6f74SMarek Vasut ret = chipone_common_probe(dev, &icn); 6168dde6f74SMarek Vasut if (ret) 6178dde6f74SMarek Vasut return ret; 6188dde6f74SMarek Vasut 6198dde6f74SMarek Vasut icn->interface_i2c = true; 6208dde6f74SMarek Vasut icn->client = client; 6218dde6f74SMarek Vasut dev_set_drvdata(dev, icn); 6228dde6f74SMarek Vasut i2c_set_clientdata(client, icn); 6238dde6f74SMarek Vasut 6248dde6f74SMarek Vasut drm_bridge_add(&icn->bridge); 6258dde6f74SMarek Vasut 6268dde6f74SMarek Vasut return chipone_dsi_host_attach(icn); 6278dde6f74SMarek Vasut } 6288dde6f74SMarek Vasut 6298dde6f74SMarek Vasut static int chipone_dsi_remove(struct mipi_dsi_device *dsi) 630ce517f18SJagan Teki { 631ce517f18SJagan Teki struct chipone *icn = mipi_dsi_get_drvdata(dsi); 632ce517f18SJagan Teki 633ce517f18SJagan Teki mipi_dsi_detach(dsi); 634ce517f18SJagan Teki drm_bridge_remove(&icn->bridge); 635ce517f18SJagan Teki 636ce517f18SJagan Teki return 0; 637ce517f18SJagan Teki } 638ce517f18SJagan Teki 639ce517f18SJagan Teki static const struct of_device_id chipone_of_match[] = { 640ce517f18SJagan Teki { .compatible = "chipone,icn6211", }, 641ce517f18SJagan Teki { /* sentinel */ } 642ce517f18SJagan Teki }; 643ce517f18SJagan Teki MODULE_DEVICE_TABLE(of, chipone_of_match); 644ce517f18SJagan Teki 6458dde6f74SMarek Vasut static struct mipi_dsi_driver chipone_dsi_driver = { 6468dde6f74SMarek Vasut .probe = chipone_dsi_probe, 6478dde6f74SMarek Vasut .remove = chipone_dsi_remove, 648ce517f18SJagan Teki .driver = { 649ce517f18SJagan Teki .name = "chipone-icn6211", 650ce517f18SJagan Teki .owner = THIS_MODULE, 651ce517f18SJagan Teki .of_match_table = chipone_of_match, 652ce517f18SJagan Teki }, 653ce517f18SJagan Teki }; 6548dde6f74SMarek Vasut 6558dde6f74SMarek Vasut static struct i2c_device_id chipone_i2c_id[] = { 6568dde6f74SMarek Vasut { "chipone,icn6211" }, 6578dde6f74SMarek Vasut {}, 6588dde6f74SMarek Vasut }; 6598dde6f74SMarek Vasut MODULE_DEVICE_TABLE(i2c, chipone_i2c_id); 6608dde6f74SMarek Vasut 6618dde6f74SMarek Vasut static struct i2c_driver chipone_i2c_driver = { 6628dde6f74SMarek Vasut .probe = chipone_i2c_probe, 6638dde6f74SMarek Vasut .id_table = chipone_i2c_id, 6648dde6f74SMarek Vasut .driver = { 6658dde6f74SMarek Vasut .name = "chipone-icn6211-i2c", 6668dde6f74SMarek Vasut .owner = THIS_MODULE, 6678dde6f74SMarek Vasut .of_match_table = chipone_of_match, 6688dde6f74SMarek Vasut }, 6698dde6f74SMarek Vasut }; 6708dde6f74SMarek Vasut 6718dde6f74SMarek Vasut static int __init chipone_init(void) 6728dde6f74SMarek Vasut { 6738dde6f74SMarek Vasut if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 6748dde6f74SMarek Vasut mipi_dsi_driver_register(&chipone_dsi_driver); 6758dde6f74SMarek Vasut 6768dde6f74SMarek Vasut return i2c_add_driver(&chipone_i2c_driver); 6778dde6f74SMarek Vasut } 6788dde6f74SMarek Vasut module_init(chipone_init); 6798dde6f74SMarek Vasut 680*7a828f1fSMarek Vasut static void __exit chipone_exit(void) 6818dde6f74SMarek Vasut { 6828dde6f74SMarek Vasut i2c_del_driver(&chipone_i2c_driver); 6838dde6f74SMarek Vasut 6848dde6f74SMarek Vasut if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) 6858dde6f74SMarek Vasut mipi_dsi_driver_unregister(&chipone_dsi_driver); 6868dde6f74SMarek Vasut } 6878dde6f74SMarek Vasut module_exit(chipone_exit); 688ce517f18SJagan Teki 689ce517f18SJagan Teki MODULE_AUTHOR("Jagan Teki <jagan@amarulasolutions.com>"); 690ce517f18SJagan Teki MODULE_DESCRIPTION("Chipone ICN6211 MIPI-DSI to RGB Converter Bridge"); 691ce517f18SJagan Teki MODULE_LICENSE("GPL"); 692