1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 7 #ifndef __ANX7625_H__ 8 #define __ANX7625_H__ 9 10 #define ANX7625_DRV_VERSION "0.1.04" 11 12 /* Loading OCM re-trying times */ 13 #define OCM_LOADING_TIME 10 14 15 /********* ANX7625 Register **********/ 16 #define TX_P0_ADDR 0x70 17 #define TX_P1_ADDR 0x7A 18 #define TX_P2_ADDR 0x72 19 20 #define RX_P0_ADDR 0x7e 21 #define RX_P1_ADDR 0x84 22 #define RX_P2_ADDR 0x54 23 24 #define RSVD_00_ADDR 0x00 25 #define RSVD_D1_ADDR 0xD1 26 #define RSVD_60_ADDR 0x60 27 #define RSVD_39_ADDR 0x39 28 #define RSVD_7F_ADDR 0x7F 29 30 #define TCPC_INTERFACE_ADDR 0x58 31 32 /* Clock frequency in Hz */ 33 #define XTAL_FRQ (27 * 1000000) 34 35 #define POST_DIVIDER_MIN 1 36 #define POST_DIVIDER_MAX 16 37 #define PLL_OUT_FREQ_MIN 520000000UL 38 #define PLL_OUT_FREQ_MAX 730000000UL 39 #define PLL_OUT_FREQ_ABS_MIN 300000000UL 40 #define PLL_OUT_FREQ_ABS_MAX 800000000UL 41 #define MAX_UNSIGNED_24BIT 16777215UL 42 43 /***************************************************************/ 44 /* Register definition of device address 0x58 */ 45 46 #define PRODUCT_ID_L 0x02 47 #define PRODUCT_ID_H 0x03 48 49 #define INTR_ALERT_1 0xCC 50 #define INTR_SOFTWARE_INT BIT(3) 51 #define INTR_RECEIVED_MSG BIT(5) 52 53 #define SYSTEM_STSTUS 0x45 54 #define INTERFACE_CHANGE_INT 0x44 55 #define HPD_STATUS_CHANGE 0x80 56 #define HPD_STATUS 0x80 57 58 /******** END of I2C Address 0x58 ********/ 59 60 /***************************************************************/ 61 /* Register definition of device address 0x70 */ 62 #define I2C_ADDR_70_DPTX 0x70 63 64 #define SP_TX_LINK_BW_SET_REG 0xA0 65 #define SP_TX_LANE_COUNT_SET_REG 0xA1 66 67 #define M_VID_0 0xC0 68 #define M_VID_1 0xC1 69 #define M_VID_2 0xC2 70 #define N_VID_0 0xC3 71 #define N_VID_1 0xC4 72 #define N_VID_2 0xC5 73 74 /***************************************************************/ 75 /* Register definition of device address 0x72 */ 76 #define AUX_RST 0x04 77 #define RST_CTRL2 0x07 78 79 #define SP_TX_TOTAL_LINE_STA_L 0x24 80 #define SP_TX_TOTAL_LINE_STA_H 0x25 81 #define SP_TX_ACT_LINE_STA_L 0x26 82 #define SP_TX_ACT_LINE_STA_H 0x27 83 #define SP_TX_V_F_PORCH_STA 0x28 84 #define SP_TX_V_SYNC_STA 0x29 85 #define SP_TX_V_B_PORCH_STA 0x2A 86 #define SP_TX_TOTAL_PIXEL_STA_L 0x2B 87 #define SP_TX_TOTAL_PIXEL_STA_H 0x2C 88 #define SP_TX_ACT_PIXEL_STA_L 0x2D 89 #define SP_TX_ACT_PIXEL_STA_H 0x2E 90 #define SP_TX_H_F_PORCH_STA_L 0x2F 91 #define SP_TX_H_F_PORCH_STA_H 0x30 92 #define SP_TX_H_SYNC_STA_L 0x31 93 #define SP_TX_H_SYNC_STA_H 0x32 94 #define SP_TX_H_B_PORCH_STA_L 0x33 95 #define SP_TX_H_B_PORCH_STA_H 0x34 96 97 #define SP_TX_VID_CTRL 0x84 98 #define SP_TX_BPC_MASK 0xE0 99 #define SP_TX_BPC_6 0x00 100 #define SP_TX_BPC_8 0x20 101 #define SP_TX_BPC_10 0x40 102 #define SP_TX_BPC_12 0x60 103 104 #define VIDEO_BIT_MATRIX_12 0x4c 105 106 #define AUDIO_CHANNEL_STATUS_1 0xd0 107 #define AUDIO_CHANNEL_STATUS_2 0xd1 108 #define AUDIO_CHANNEL_STATUS_3 0xd2 109 #define AUDIO_CHANNEL_STATUS_4 0xd3 110 #define AUDIO_CHANNEL_STATUS_5 0xd4 111 #define AUDIO_CHANNEL_STATUS_6 0xd5 112 #define TDM_SLAVE_MODE 0x10 113 #define I2S_SLAVE_MODE 0x08 114 #define AUDIO_LAYOUT 0x01 115 116 #define AUDIO_CONTROL_REGISTER 0xe6 117 #define TDM_TIMING_MODE 0x08 118 119 #define I2C_ADDR_72_DPTX 0x72 120 121 #define HP_MIN 8 122 #define HBLANKING_MIN 80 123 #define SYNC_LEN_DEF 32 124 #define HFP_HBP_DEF ((HBLANKING_MIN - SYNC_LEN_DEF) / 2) 125 #define VIDEO_CONTROL_0 0x08 126 127 #define ACTIVE_LINES_L 0x14 128 #define ACTIVE_LINES_H 0x15 /* Bit[7:6] are reserved */ 129 #define VERTICAL_FRONT_PORCH 0x16 130 #define VERTICAL_SYNC_WIDTH 0x17 131 #define VERTICAL_BACK_PORCH 0x18 132 133 #define HORIZONTAL_TOTAL_PIXELS_L 0x19 134 #define HORIZONTAL_TOTAL_PIXELS_H 0x1A /* Bit[7:6] are reserved */ 135 #define HORIZONTAL_ACTIVE_PIXELS_L 0x1B 136 #define HORIZONTAL_ACTIVE_PIXELS_H 0x1C /* Bit[7:6] are reserved */ 137 #define HORIZONTAL_FRONT_PORCH_L 0x1D 138 #define HORIZONTAL_FRONT_PORCH_H 0x1E /* Bit[7:4] are reserved */ 139 #define HORIZONTAL_SYNC_WIDTH_L 0x1F 140 #define HORIZONTAL_SYNC_WIDTH_H 0x20 /* Bit[7:4] are reserved */ 141 #define HORIZONTAL_BACK_PORCH_L 0x21 142 #define HORIZONTAL_BACK_PORCH_H 0x22 /* Bit[7:4] are reserved */ 143 144 /******** END of I2C Address 0x72 *********/ 145 146 /***************************************************************/ 147 /* Register definition of device address 0x7a */ 148 #define DP_TX_SWING_REG_CNT 0x14 149 #define DP_TX_LANE0_SWING_REG0 0x00 150 #define DP_TX_LANE1_SWING_REG0 0x14 151 /******** END of I2C Address 0x7a *********/ 152 153 /***************************************************************/ 154 /* Register definition of device address 0x7e */ 155 156 #define I2C_ADDR_7E_FLASH_CONTROLLER 0x7E 157 158 #define FLASH_LOAD_STA 0x05 159 #define FLASH_LOAD_STA_CHK BIT(7) 160 161 #define XTAL_FRQ_SEL 0x3F 162 /* bit field positions */ 163 #define XTAL_FRQ_SEL_POS 5 164 /* bit field values */ 165 #define XTAL_FRQ_19M2 (0 << XTAL_FRQ_SEL_POS) 166 #define XTAL_FRQ_27M (4 << XTAL_FRQ_SEL_POS) 167 168 #define R_DSC_CTRL_0 0x40 169 #define READ_STATUS_EN 7 170 #define CLK_1MEG_RB 6 /* 1MHz clock reset; 0=reset, 0=reset release */ 171 #define DSC_BIST_DONE 1 /* Bit[5:1]: 1=DSC MBIST pass */ 172 #define DSC_EN 0x01 /* 1=DSC enabled, 0=DSC disabled */ 173 174 #define OCM_FW_VERSION 0x31 175 #define OCM_FW_REVERSION 0x32 176 177 #define AP_AUX_ADDR_7_0 0x11 178 #define AP_AUX_ADDR_15_8 0x12 179 #define AP_AUX_ADDR_19_16 0x13 180 181 /* Bit[0:3] AUX status, bit 4 op_en, bit 5 address only */ 182 #define AP_AUX_CTRL_STATUS 0x14 183 #define AP_AUX_CTRL_OP_EN 0x10 184 #define AP_AUX_CTRL_ADDRONLY 0x20 185 186 #define AP_AUX_BUFF_START 0x15 187 #define PIXEL_CLOCK_L 0x25 188 #define PIXEL_CLOCK_H 0x26 189 190 #define AP_AUX_COMMAND 0x27 /* com+len */ 191 /* Bit 0&1: 3D video structure */ 192 /* 0x01: frame packing, 0x02:Line alternative, 0x03:Side-by-side(full) */ 193 #define AP_AV_STATUS 0x28 194 #define AP_VIDEO_CHG BIT(2) 195 #define AP_AUDIO_CHG BIT(3) 196 #define AP_MIPI_MUTE BIT(4) /* 1:MIPI input mute, 0: ummute */ 197 #define AP_MIPI_RX_EN BIT(5) /* 1: MIPI RX input in 0: no RX in */ 198 #define AP_DISABLE_PD BIT(6) 199 #define AP_DISABLE_DISPLAY BIT(7) 200 /***************************************************************/ 201 /* Register definition of device address 0x84 */ 202 #define MIPI_PHY_CONTROL_3 0x03 203 #define MIPI_HS_PWD_CLK 7 204 #define MIPI_HS_RT_CLK 6 205 #define MIPI_PD_CLK 5 206 #define MIPI_CLK_RT_MANUAL_PD_EN 4 207 #define MIPI_CLK_HS_MANUAL_PD_EN 3 208 #define MIPI_CLK_DET_DET_BYPASS 2 209 #define MIPI_CLK_MISS_CTRL 1 210 #define MIPI_PD_LPTX_CH_MANUAL_PD_EN 0 211 212 #define MIPI_LANE_CTRL_0 0x05 213 #define MIPI_TIME_HS_PRPR 0x08 214 215 /* 216 * After MIPI RX protocol layer received video frames, 217 * Protocol layer starts to reconstruct video stream from PHY 218 */ 219 #define MIPI_VIDEO_STABLE_CNT 0x0A 220 221 #define MIPI_LANE_CTRL_10 0x0F 222 #define MIPI_DIGITAL_ADJ_1 0x1B 223 #define IVO_MID0 0x26 224 #define IVO_MID1 0xCF 225 226 #define MIPI_PLL_M_NUM_23_16 0x1E 227 #define MIPI_PLL_M_NUM_15_8 0x1F 228 #define MIPI_PLL_M_NUM_7_0 0x20 229 #define MIPI_PLL_N_NUM_23_16 0x21 230 #define MIPI_PLL_N_NUM_15_8 0x22 231 #define MIPI_PLL_N_NUM_7_0 0x23 232 233 #define MIPI_DIGITAL_PLL_6 0x2A 234 /* Bit[7:6]: VCO band control, only effective */ 235 #define MIPI_M_NUM_READY 0x10 236 #define MIPI_N_NUM_READY 0x08 237 #define STABLE_INTEGER_CNT_EN 0x04 238 #define MIPI_PLL_TEST_BIT 0 239 /* Bit[1:0]: test point output select - */ 240 /* 00: VCO power, 01: dvdd_pdt, 10: dvdd, 11: vcox */ 241 242 #define MIPI_DIGITAL_PLL_7 0x2B 243 #define MIPI_PLL_FORCE_N_EN 7 244 #define MIPI_PLL_FORCE_BAND_EN 6 245 246 #define MIPI_PLL_VCO_TUNE_REG 4 247 /* Bit[5:4]: VCO metal capacitance - */ 248 /* 00: +20% fast, 01: +10% fast (default), 10: typical, 11: -10% slow */ 249 #define MIPI_PLL_VCO_TUNE_REG_VAL 0x30 250 251 #define MIPI_PLL_PLL_LDO_BIT 2 252 /* Bit[3:2]: vco_v2i power - */ 253 /* 00: 1.40V, 01: 1.45V (default), 10: 1.50V, 11: 1.55V */ 254 #define MIPI_PLL_RESET_N 0x02 255 #define MIPI_FRQ_FORCE_NDET 0 256 257 #define MIPI_ALERT_CLR_0 0x2D 258 #define HS_link_error_clear 7 259 /* This bit itself is S/C, and it clears 0x84:0x31[7] */ 260 261 #define MIPI_ALERT_OUT_0 0x31 262 #define check_sum_err_hs_sync 7 263 /* This bit is cleared by 0x84:0x2D[7] */ 264 265 #define MIPI_DIGITAL_PLL_8 0x33 266 #define MIPI_POST_DIV_VAL 4 267 /* N means divided by (n+1), n = 0~15 */ 268 #define MIPI_EN_LOCK_FRZ 3 269 #define MIPI_FRQ_COUNTER_RST 2 270 #define MIPI_FRQ_SET_REG_8 1 271 /* Bit 0 is reserved */ 272 273 #define MIPI_DIGITAL_PLL_9 0x34 274 275 #define MIPI_DIGITAL_PLL_16 0x3B 276 #define MIPI_FRQ_FREEZE_NDET 7 277 #define MIPI_FRQ_REG_SET_ENABLE 6 278 #define MIPI_REG_FORCE_SEL_EN 5 279 #define MIPI_REG_SEL_DIV_REG 4 280 #define MIPI_REG_FORCE_PRE_DIV_EN 3 281 /* Bit 2 is reserved */ 282 #define MIPI_FREF_D_IND 1 283 #define REF_CLK_27000KHZ 1 284 #define REF_CLK_19200KHZ 0 285 #define MIPI_REG_PLL_PLL_TEST_ENABLE 0 286 287 #define MIPI_DIGITAL_PLL_18 0x3D 288 #define FRQ_COUNT_RB_SEL 7 289 #define REG_FORCE_POST_DIV_EN 6 290 #define MIPI_DPI_SELECT 5 291 #define SELECT_DSI 1 292 #define SELECT_DPI 0 293 #define REG_BAUD_DIV_RATIO 0 294 295 #define H_BLANK_L 0x3E 296 /* For DSC only */ 297 #define H_BLANK_H 0x3F 298 /* For DSC only; note: bit[7:6] are reserved */ 299 #define MIPI_SWAP 0x4A 300 #define MIPI_SWAP_CH0 7 301 #define MIPI_SWAP_CH1 6 302 #define MIPI_SWAP_CH2 5 303 #define MIPI_SWAP_CH3 4 304 #define MIPI_SWAP_CLK 3 305 /* Bit[2:0] are reserved */ 306 307 /******** END of I2C Address 0x84 *********/ 308 309 /* DPCD regs */ 310 #define DPCD_DPCD_REV 0x00 311 #define DPCD_MAX_LINK_RATE 0x01 312 #define DPCD_MAX_LANE_COUNT 0x02 313 314 /********* ANX7625 Register End **********/ 315 316 /***************** Display *****************/ 317 enum audio_fs { 318 AUDIO_FS_441K = 0x00, 319 AUDIO_FS_48K = 0x02, 320 AUDIO_FS_32K = 0x03, 321 AUDIO_FS_882K = 0x08, 322 AUDIO_FS_96K = 0x0a, 323 AUDIO_FS_1764K = 0x0c, 324 AUDIO_FS_192K = 0x0e 325 }; 326 327 enum audio_wd_len { 328 AUDIO_W_LEN_16_20MAX = 0x02, 329 AUDIO_W_LEN_18_20MAX = 0x04, 330 AUDIO_W_LEN_17_20MAX = 0x0c, 331 AUDIO_W_LEN_19_20MAX = 0x08, 332 AUDIO_W_LEN_20_20MAX = 0x0a, 333 AUDIO_W_LEN_20_24MAX = 0x03, 334 AUDIO_W_LEN_22_24MAX = 0x05, 335 AUDIO_W_LEN_21_24MAX = 0x0d, 336 AUDIO_W_LEN_23_24MAX = 0x09, 337 AUDIO_W_LEN_24_24MAX = 0x0b 338 }; 339 340 #define I2S_CH_2 0x01 341 #define TDM_CH_4 0x03 342 #define TDM_CH_6 0x05 343 #define TDM_CH_8 0x07 344 345 #define MAX_DPCD_BUFFER_SIZE 16 346 347 #define ONE_BLOCK_SIZE 128 348 #define FOUR_BLOCK_SIZE (128 * 4) 349 350 #define MAX_EDID_BLOCK 3 351 #define EDID_TRY_CNT 3 352 #define SUPPORT_PIXEL_CLOCK 300000 353 354 struct s_edid_data { 355 int edid_block_num; 356 u8 edid_raw_data[FOUR_BLOCK_SIZE]; 357 }; 358 359 /***************** Display End *****************/ 360 361 #define MAX_LANES_SUPPORT 4 362 363 struct anx7625_platform_data { 364 struct gpio_desc *gpio_p_on; 365 struct gpio_desc *gpio_reset; 366 struct regulator_bulk_data supplies[3]; 367 struct drm_bridge *panel_bridge; 368 int intp_irq; 369 int is_dpi; 370 int mipi_lanes; 371 int audio_en; 372 int dp_lane0_swing_reg_cnt; 373 int lane0_reg_data[DP_TX_SWING_REG_CNT]; 374 int dp_lane1_swing_reg_cnt; 375 int lane1_reg_data[DP_TX_SWING_REG_CNT]; 376 u32 low_power_mode; 377 struct device_node *mipi_host_node; 378 }; 379 380 struct anx7625_i2c_client { 381 struct i2c_client *tx_p0_client; 382 struct i2c_client *tx_p1_client; 383 struct i2c_client *tx_p2_client; 384 struct i2c_client *rx_p0_client; 385 struct i2c_client *rx_p1_client; 386 struct i2c_client *rx_p2_client; 387 struct i2c_client *tcpc_client; 388 }; 389 390 struct anx7625_data { 391 struct anx7625_platform_data pdata; 392 struct platform_device *audio_pdev; 393 int hpd_status; 394 int hpd_high_cnt; 395 /* Lock for work queue */ 396 struct mutex lock; 397 struct i2c_client *client; 398 struct anx7625_i2c_client i2c; 399 struct i2c_client *last_client; 400 struct s_edid_data slimport_edid_p; 401 struct device *codec_dev; 402 hdmi_codec_plugged_cb plugged_cb; 403 struct work_struct work; 404 struct workqueue_struct *workqueue; 405 char edid_block; 406 struct display_timing dt; 407 u8 display_timing_valid; 408 struct drm_bridge bridge; 409 u8 bridge_attached; 410 struct mipi_dsi_device *dsi; 411 }; 412 413 #endif /* __ANX7625_H__ */ 414