1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright(c) 2020, Analogix Semiconductor. All rights reserved. 4 * 5 */ 6 #include <linux/cleanup.h> 7 #include <linux/gcd.h> 8 #include <linux/gpio/consumer.h> 9 #include <linux/i2c.h> 10 #include <linux/interrupt.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/mutex.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regulator/consumer.h> 17 #include <linux/slab.h> 18 #include <linux/types.h> 19 #include <linux/usb.h> 20 #include <linux/usb/pd.h> 21 #include <linux/usb/role.h> 22 #include <linux/workqueue.h> 23 24 #include <linux/of_graph.h> 25 #include <linux/of_platform.h> 26 27 #include <drm/display/drm_dp_aux_bus.h> 28 #include <drm/display/drm_dp_helper.h> 29 #include <drm/display/drm_hdcp_helper.h> 30 #include <drm/drm_atomic_helper.h> 31 #include <drm/drm_bridge.h> 32 #include <drm/drm_edid.h> 33 #include <drm/drm_mipi_dsi.h> 34 #include <drm/drm_of.h> 35 #include <drm/drm_panel.h> 36 #include <drm/drm_print.h> 37 #include <drm/drm_probe_helper.h> 38 39 #include <media/v4l2-fwnode.h> 40 #include <sound/hdmi-codec.h> 41 #include <video/display_timing.h> 42 43 #include "anx7625.h" 44 45 /* 46 * There is a sync issue while access I2C register between AP(CPU) and 47 * internal firmware(OCM), to avoid the race condition, AP should access 48 * the reserved slave address before slave address occurs changes. 49 */ 50 static int i2c_access_workaround(struct anx7625_data *ctx, 51 struct i2c_client *client) 52 { 53 u8 offset; 54 struct device *dev = &client->dev; 55 int ret; 56 57 if (client == ctx->last_client) 58 return 0; 59 60 ctx->last_client = client; 61 62 if (client == ctx->i2c.tcpc_client) 63 offset = RSVD_00_ADDR; 64 else if (client == ctx->i2c.tx_p0_client) 65 offset = RSVD_D1_ADDR; 66 else if (client == ctx->i2c.tx_p1_client) 67 offset = RSVD_60_ADDR; 68 else if (client == ctx->i2c.rx_p0_client) 69 offset = RSVD_39_ADDR; 70 else if (client == ctx->i2c.rx_p1_client) 71 offset = RSVD_7F_ADDR; 72 else 73 offset = RSVD_00_ADDR; 74 75 ret = i2c_smbus_write_byte_data(client, offset, 0x00); 76 if (ret < 0) 77 DRM_DEV_ERROR(dev, 78 "fail to access i2c id=%x\n:%x", 79 client->addr, offset); 80 81 return ret; 82 } 83 84 static int anx7625_reg_read(struct anx7625_data *ctx, 85 struct i2c_client *client, u8 reg_addr) 86 { 87 int ret; 88 struct device *dev = &client->dev; 89 90 i2c_access_workaround(ctx, client); 91 92 ret = i2c_smbus_read_byte_data(client, reg_addr); 93 if (ret < 0) 94 DRM_DEV_ERROR(dev, "read i2c fail id=%x:%x\n", 95 client->addr, reg_addr); 96 97 return ret; 98 } 99 100 static int anx7625_reg_block_read(struct anx7625_data *ctx, 101 struct i2c_client *client, 102 u8 reg_addr, u8 len, u8 *buf) 103 { 104 int ret; 105 struct device *dev = &client->dev; 106 107 i2c_access_workaround(ctx, client); 108 109 ret = i2c_smbus_read_i2c_block_data(client, reg_addr, len, buf); 110 if (ret < 0) 111 DRM_DEV_ERROR(dev, "read i2c block fail id=%x:%x\n", 112 client->addr, reg_addr); 113 114 return ret; 115 } 116 117 static int anx7625_reg_write(struct anx7625_data *ctx, 118 struct i2c_client *client, 119 u8 reg_addr, u8 reg_val) 120 { 121 int ret; 122 struct device *dev = &client->dev; 123 124 i2c_access_workaround(ctx, client); 125 126 ret = i2c_smbus_write_byte_data(client, reg_addr, reg_val); 127 128 if (ret < 0) 129 DRM_DEV_ERROR(dev, "fail to write i2c id=%x\n:%x", 130 client->addr, reg_addr); 131 132 return ret; 133 } 134 135 static int anx7625_reg_block_write(struct anx7625_data *ctx, 136 struct i2c_client *client, 137 u8 reg_addr, u8 len, u8 *buf) 138 { 139 int ret; 140 struct device *dev = &client->dev; 141 142 i2c_access_workaround(ctx, client); 143 144 ret = i2c_smbus_write_i2c_block_data(client, reg_addr, len, buf); 145 if (ret < 0) 146 dev_err(dev, "write i2c block failed id=%x\n:%x", 147 client->addr, reg_addr); 148 149 return ret; 150 } 151 152 static int anx7625_write_or(struct anx7625_data *ctx, 153 struct i2c_client *client, 154 u8 offset, u8 mask) 155 { 156 int val; 157 158 val = anx7625_reg_read(ctx, client, offset); 159 if (val < 0) 160 return val; 161 162 return anx7625_reg_write(ctx, client, offset, (val | (mask))); 163 } 164 165 static int anx7625_write_and(struct anx7625_data *ctx, 166 struct i2c_client *client, 167 u8 offset, u8 mask) 168 { 169 int val; 170 171 val = anx7625_reg_read(ctx, client, offset); 172 if (val < 0) 173 return val; 174 175 return anx7625_reg_write(ctx, client, offset, (val & (mask))); 176 } 177 178 static int anx7625_write_and_or(struct anx7625_data *ctx, 179 struct i2c_client *client, 180 u8 offset, u8 and_mask, u8 or_mask) 181 { 182 int val; 183 184 val = anx7625_reg_read(ctx, client, offset); 185 if (val < 0) 186 return val; 187 188 return anx7625_reg_write(ctx, client, 189 offset, (val & and_mask) | (or_mask)); 190 } 191 192 static int anx7625_config_bit_matrix(struct anx7625_data *ctx) 193 { 194 int i, ret; 195 196 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 197 AUDIO_CONTROL_REGISTER, 0x80); 198 for (i = 0; i < 13; i++) 199 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 200 VIDEO_BIT_MATRIX_12 + i, 201 0x18 + i); 202 203 return ret; 204 } 205 206 static int anx7625_read_ctrl_status_p0(struct anx7625_data *ctx) 207 { 208 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_CTRL_STATUS); 209 } 210 211 static int wait_aux_op_finish(struct anx7625_data *ctx) 212 { 213 struct device *dev = ctx->dev; 214 int val; 215 int ret; 216 217 ret = readx_poll_timeout(anx7625_read_ctrl_status_p0, 218 ctx, val, 219 (!(val & AP_AUX_CTRL_OP_EN) || (val < 0)), 220 2000, 221 2000 * 150); 222 if (ret) { 223 DRM_DEV_ERROR(dev, "aux operation fail!\n"); 224 return -EIO; 225 } 226 227 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 228 AP_AUX_CTRL_STATUS); 229 if (val < 0 || (val & 0x0F)) { 230 DRM_DEV_ERROR(dev, "aux status %02x\n", val); 231 return -EIO; 232 } 233 234 return 0; 235 } 236 237 static int anx7625_aux_trans(struct anx7625_data *ctx, u8 op, u32 address, 238 u8 len, u8 *buf) 239 { 240 struct device *dev = ctx->dev; 241 int ret; 242 u8 addrh, addrm, addrl; 243 u8 cmd; 244 bool is_write = !(op & DP_AUX_I2C_READ); 245 246 if (len > DP_AUX_MAX_PAYLOAD_BYTES) { 247 dev_err(dev, "exceed aux buffer len.\n"); 248 return -EINVAL; 249 } 250 251 if (!len) 252 return len; 253 254 addrl = address & 0xFF; 255 addrm = (address >> 8) & 0xFF; 256 addrh = (address >> 16) & 0xFF; 257 258 if (!is_write) 259 op &= ~DP_AUX_I2C_MOT; 260 cmd = DPCD_CMD(len, op); 261 262 /* Set command and length */ 263 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 264 AP_AUX_COMMAND, cmd); 265 266 /* Set aux access address */ 267 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 268 AP_AUX_ADDR_7_0, addrl); 269 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 270 AP_AUX_ADDR_15_8, addrm); 271 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 272 AP_AUX_ADDR_19_16, addrh); 273 274 if (is_write) 275 ret |= anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client, 276 AP_AUX_BUFF_START, len, buf); 277 /* Enable aux access */ 278 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 279 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 280 281 if (ret < 0) { 282 dev_err(dev, "cannot access aux related register.\n"); 283 return -EIO; 284 } 285 286 ret = wait_aux_op_finish(ctx); 287 if (ret < 0) { 288 dev_err(dev, "aux IO error: wait aux op finish.\n"); 289 return ret; 290 } 291 292 /* Write done */ 293 if (is_write) 294 return len; 295 296 /* Read done, read out dpcd data */ 297 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 298 AP_AUX_BUFF_START, len, buf); 299 if (ret < 0) { 300 dev_err(dev, "read dpcd register failed\n"); 301 return -EIO; 302 } 303 304 return len; 305 } 306 307 static int anx7625_video_mute_control(struct anx7625_data *ctx, 308 u8 status) 309 { 310 int ret; 311 312 if (status) { 313 /* Set mute on flag */ 314 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 315 AP_AV_STATUS, AP_MIPI_MUTE); 316 /* Clear mipi RX en */ 317 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 318 AP_AV_STATUS, (u8)~AP_MIPI_RX_EN); 319 } else { 320 /* Mute off flag */ 321 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 322 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 323 /* Set MIPI RX EN */ 324 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 325 AP_AV_STATUS, AP_MIPI_RX_EN); 326 } 327 328 return ret; 329 } 330 331 /* Reduction of fraction a/b */ 332 static void anx7625_reduction_of_a_fraction(unsigned long *a, unsigned long *b) 333 { 334 unsigned long gcd_num; 335 unsigned long tmp_a, tmp_b; 336 u32 i = 1; 337 338 gcd_num = gcd(*a, *b); 339 *a /= gcd_num; 340 *b /= gcd_num; 341 342 tmp_a = *a; 343 tmp_b = *b; 344 345 while ((*a > MAX_UNSIGNED_24BIT) || (*b > MAX_UNSIGNED_24BIT)) { 346 i++; 347 *a = tmp_a / i; 348 *b = tmp_b / i; 349 } 350 351 /* 352 * In the end, make a, b larger to have higher ODFC PLL 353 * output frequency accuracy 354 */ 355 while ((*a < MAX_UNSIGNED_24BIT) && (*b < MAX_UNSIGNED_24BIT)) { 356 *a <<= 1; 357 *b <<= 1; 358 } 359 360 *a >>= 1; 361 *b >>= 1; 362 } 363 364 static int anx7625_calculate_m_n(u32 pixelclock, 365 unsigned long *m, 366 unsigned long *n, 367 u8 *post_divider) 368 { 369 if (pixelclock > PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN) { 370 /* Pixel clock frequency is too high */ 371 DRM_ERROR("pixelclock too high, act(%d), maximum(%lu)\n", 372 pixelclock, 373 PLL_OUT_FREQ_ABS_MAX / POST_DIVIDER_MIN); 374 return -EINVAL; 375 } 376 377 if (pixelclock < PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX) { 378 /* Pixel clock frequency is too low */ 379 DRM_ERROR("pixelclock too low, act(%d), maximum(%lu)\n", 380 pixelclock, 381 PLL_OUT_FREQ_ABS_MIN / POST_DIVIDER_MAX); 382 return -EINVAL; 383 } 384 385 for (*post_divider = 1; 386 pixelclock < (PLL_OUT_FREQ_MIN / (*post_divider));) 387 *post_divider += 1; 388 389 if (*post_divider > POST_DIVIDER_MAX) { 390 for (*post_divider = 1; 391 (pixelclock < 392 (PLL_OUT_FREQ_ABS_MIN / (*post_divider)));) 393 *post_divider += 1; 394 395 if (*post_divider > POST_DIVIDER_MAX) { 396 DRM_ERROR("cannot find property post_divider(%d)\n", 397 *post_divider); 398 return -EDOM; 399 } 400 } 401 402 /* Patch to improve the accuracy */ 403 if (*post_divider == 7) { 404 /* 27,000,000 is not divisible by 7 */ 405 *post_divider = 8; 406 } else if (*post_divider == 11) { 407 /* 27,000,000 is not divisible by 11 */ 408 *post_divider = 12; 409 } else if ((*post_divider == 13) || (*post_divider == 14)) { 410 /* 27,000,000 is not divisible by 13 or 14 */ 411 *post_divider = 15; 412 } 413 414 if (pixelclock * (*post_divider) > PLL_OUT_FREQ_ABS_MAX) { 415 DRM_ERROR("act clock(%u) large than maximum(%lu)\n", 416 pixelclock * (*post_divider), 417 PLL_OUT_FREQ_ABS_MAX); 418 return -EDOM; 419 } 420 421 *m = pixelclock; 422 *n = XTAL_FRQ / (*post_divider); 423 424 anx7625_reduction_of_a_fraction(m, n); 425 426 return 0; 427 } 428 429 static int anx7625_odfc_config(struct anx7625_data *ctx, 430 u8 post_divider) 431 { 432 int ret; 433 struct device *dev = ctx->dev; 434 435 /* Config input reference clock frequency 27MHz/19.2MHz */ 436 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 437 ~(REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 438 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_16, 439 (REF_CLK_27000KHZ << MIPI_FREF_D_IND)); 440 /* Post divider */ 441 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 442 MIPI_DIGITAL_PLL_8, 0x0f); 443 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_8, 444 post_divider << 4); 445 446 /* Add patch for MIS2-125 (5pcs ANX7625 fail ATE MBIST test) */ 447 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 448 ~MIPI_PLL_VCO_TUNE_REG_VAL); 449 450 /* Reset ODFC PLL */ 451 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 452 ~MIPI_PLL_RESET_N); 453 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_7, 454 MIPI_PLL_RESET_N); 455 456 if (ret < 0) 457 DRM_DEV_ERROR(dev, "IO error.\n"); 458 459 return ret; 460 } 461 462 /* 463 * The MIPI source video data exist large variation (e.g. 59Hz ~ 61Hz), 464 * anx7625 defined K ratio for matching MIPI input video clock and 465 * DP output video clock. Increase K value can match bigger video data 466 * variation. IVO panel has small variation than DP CTS spec, need 467 * decrease the K value. 468 */ 469 static int anx7625_set_k_value(struct anx7625_data *ctx) 470 { 471 struct drm_edid_product_id id; 472 473 drm_edid_get_product_id(ctx->cached_drm_edid, &id); 474 475 if (be16_to_cpu(id.manufacturer_name) == IVO_MID) 476 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 477 MIPI_DIGITAL_ADJ_1, 0x3B); 478 479 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 480 MIPI_DIGITAL_ADJ_1, 0x3D); 481 } 482 483 static int anx7625_dsi_video_timing_config(struct anx7625_data *ctx) 484 { 485 struct device *dev = ctx->dev; 486 unsigned long m, n; 487 u16 htotal; 488 int ret; 489 u8 post_divider = 0; 490 491 ret = anx7625_calculate_m_n(ctx->dt.pixelclock.min * 1000, 492 &m, &n, &post_divider); 493 494 if (ret) { 495 DRM_DEV_ERROR(dev, "cannot get property m n value.\n"); 496 return ret; 497 } 498 499 DRM_DEV_DEBUG_DRIVER(dev, "compute M(%lu), N(%lu), divider(%d).\n", 500 m, n, post_divider); 501 502 /* Configure pixel clock */ 503 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_L, 504 (ctx->dt.pixelclock.min / 1000) & 0xFF); 505 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, PIXEL_CLOCK_H, 506 (ctx->dt.pixelclock.min / 1000) >> 8); 507 /* Lane count */ 508 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 509 MIPI_LANE_CTRL_0, 0xfc); 510 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 511 MIPI_LANE_CTRL_0, ctx->pdata.mipi_lanes - 1); 512 513 /* Htotal */ 514 htotal = ctx->dt.hactive.min + ctx->dt.hfront_porch.min + 515 ctx->dt.hback_porch.min + ctx->dt.hsync_len.min; 516 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 517 HORIZONTAL_TOTAL_PIXELS_L, htotal & 0xFF); 518 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 519 HORIZONTAL_TOTAL_PIXELS_H, htotal >> 8); 520 /* Hactive */ 521 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 522 HORIZONTAL_ACTIVE_PIXELS_L, ctx->dt.hactive.min & 0xFF); 523 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 524 HORIZONTAL_ACTIVE_PIXELS_H, ctx->dt.hactive.min >> 8); 525 /* HFP */ 526 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 527 HORIZONTAL_FRONT_PORCH_L, ctx->dt.hfront_porch.min); 528 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 529 HORIZONTAL_FRONT_PORCH_H, 530 ctx->dt.hfront_porch.min >> 8); 531 /* HWS */ 532 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 533 HORIZONTAL_SYNC_WIDTH_L, ctx->dt.hsync_len.min); 534 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 535 HORIZONTAL_SYNC_WIDTH_H, ctx->dt.hsync_len.min >> 8); 536 /* HBP */ 537 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 538 HORIZONTAL_BACK_PORCH_L, ctx->dt.hback_porch.min); 539 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 540 HORIZONTAL_BACK_PORCH_H, ctx->dt.hback_porch.min >> 8); 541 /* Vactive */ 542 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_L, 543 ctx->dt.vactive.min); 544 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, ACTIVE_LINES_H, 545 ctx->dt.vactive.min >> 8); 546 /* VFP */ 547 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 548 VERTICAL_FRONT_PORCH, ctx->dt.vfront_porch.min); 549 /* VWS */ 550 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 551 VERTICAL_SYNC_WIDTH, ctx->dt.vsync_len.min); 552 /* VBP */ 553 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p2_client, 554 VERTICAL_BACK_PORCH, ctx->dt.vback_porch.min); 555 /* M value */ 556 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 557 MIPI_PLL_M_NUM_23_16, (m >> 16) & 0xff); 558 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 559 MIPI_PLL_M_NUM_15_8, (m >> 8) & 0xff); 560 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 561 MIPI_PLL_M_NUM_7_0, (m & 0xff)); 562 /* N value */ 563 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 564 MIPI_PLL_N_NUM_23_16, (n >> 16) & 0xff); 565 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 566 MIPI_PLL_N_NUM_15_8, (n >> 8) & 0xff); 567 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_PLL_N_NUM_7_0, 568 (n & 0xff)); 569 570 anx7625_set_k_value(ctx); 571 572 ret |= anx7625_odfc_config(ctx, post_divider - 1); 573 574 if (ret < 0) 575 DRM_DEV_ERROR(dev, "mipi dsi setup IO error.\n"); 576 577 return ret; 578 } 579 580 static int anx7625_swap_dsi_lane3(struct anx7625_data *ctx) 581 { 582 int val; 583 struct device *dev = ctx->dev; 584 585 /* Swap MIPI-DSI data lane 3 P and N */ 586 val = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP); 587 if (val < 0) { 588 DRM_DEV_ERROR(dev, "IO error : access MIPI_SWAP.\n"); 589 return -EIO; 590 } 591 592 val |= (1 << MIPI_SWAP_CH3); 593 return anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, MIPI_SWAP, val); 594 } 595 596 static int anx7625_api_dsi_config(struct anx7625_data *ctx) 597 598 { 599 int val, ret; 600 struct device *dev = ctx->dev; 601 602 /* Swap MIPI-DSI data lane 3 P and N */ 603 ret = anx7625_swap_dsi_lane3(ctx); 604 if (ret < 0) { 605 DRM_DEV_ERROR(dev, "IO error : swap dsi lane 3 fail.\n"); 606 return ret; 607 } 608 609 /* DSI clock settings */ 610 val = (0 << MIPI_HS_PWD_CLK) | 611 (0 << MIPI_HS_RT_CLK) | 612 (0 << MIPI_PD_CLK) | 613 (1 << MIPI_CLK_RT_MANUAL_PD_EN) | 614 (1 << MIPI_CLK_HS_MANUAL_PD_EN) | 615 (0 << MIPI_CLK_DET_DET_BYPASS) | 616 (0 << MIPI_CLK_MISS_CTRL) | 617 (0 << MIPI_PD_LPTX_CH_MANUAL_PD_EN); 618 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 619 MIPI_PHY_CONTROL_3, val); 620 621 /* 622 * Decreased HS prepare timing delay from 160ns to 80ns work with 623 * a) Dragon board 810 series (Qualcomm AP) 624 * b) Moving Pixel DSI source (PG3A pattern generator + 625 * P332 D-PHY Probe) default D-PHY timing 626 * 5ns/step 627 */ 628 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 629 MIPI_TIME_HS_PRPR, 0x10); 630 631 /* Enable DSI mode*/ 632 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_18, 633 SELECT_DSI << MIPI_DPI_SELECT); 634 635 ret |= anx7625_dsi_video_timing_config(ctx); 636 if (ret < 0) { 637 DRM_DEV_ERROR(dev, "dsi video timing config fail\n"); 638 return ret; 639 } 640 641 /* Toggle m, n ready */ 642 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 643 ~(MIPI_M_NUM_READY | MIPI_N_NUM_READY)); 644 usleep_range(1000, 1100); 645 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, MIPI_DIGITAL_PLL_6, 646 MIPI_M_NUM_READY | MIPI_N_NUM_READY); 647 648 /* Configure integer stable register */ 649 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 650 MIPI_VIDEO_STABLE_CNT, 0x02); 651 /* Power on MIPI RX */ 652 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 653 MIPI_LANE_CTRL_10, 0x00); 654 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 655 MIPI_LANE_CTRL_10, 0x80); 656 657 if (ret < 0) 658 DRM_DEV_ERROR(dev, "IO error : mipi dsi enable init fail.\n"); 659 660 return ret; 661 } 662 663 static int anx7625_dsi_config(struct anx7625_data *ctx) 664 { 665 struct device *dev = ctx->dev; 666 int ret; 667 668 DRM_DEV_DEBUG_DRIVER(dev, "config dsi.\n"); 669 670 /* DSC disable */ 671 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 672 R_DSC_CTRL_0, ~DSC_EN); 673 674 ret |= anx7625_api_dsi_config(ctx); 675 676 if (ret < 0) { 677 DRM_DEV_ERROR(dev, "IO error : api dsi config error.\n"); 678 return ret; 679 } 680 681 /* Set MIPI RX EN */ 682 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 683 AP_AV_STATUS, AP_MIPI_RX_EN); 684 /* Clear mute flag */ 685 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 686 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 687 if (ret < 0) 688 DRM_DEV_ERROR(dev, "IO error : enable mipi rx fail.\n"); 689 else 690 DRM_DEV_DEBUG_DRIVER(dev, "success to config DSI\n"); 691 692 return ret; 693 } 694 695 static int anx7625_api_dpi_config(struct anx7625_data *ctx) 696 { 697 struct device *dev = ctx->dev; 698 u16 freq = ctx->dt.pixelclock.min / 1000; 699 int ret; 700 701 /* configure pixel clock */ 702 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 703 PIXEL_CLOCK_L, freq & 0xFF); 704 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 705 PIXEL_CLOCK_H, (freq >> 8)); 706 707 /* set DPI mode */ 708 /* set to DPI PLL module sel */ 709 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 710 MIPI_DIGITAL_PLL_9, 0x20); 711 /* power down MIPI */ 712 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 713 MIPI_LANE_CTRL_10, 0x08); 714 /* enable DPI mode */ 715 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p1_client, 716 MIPI_DIGITAL_PLL_18, 0x1C); 717 /* set first edge */ 718 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 719 VIDEO_CONTROL_0, 0x06); 720 if (ret < 0) 721 DRM_DEV_ERROR(dev, "IO error : dpi phy set failed.\n"); 722 723 return ret; 724 } 725 726 static int anx7625_dpi_config(struct anx7625_data *ctx) 727 { 728 struct device *dev = ctx->dev; 729 int ret; 730 731 DRM_DEV_DEBUG_DRIVER(dev, "config dpi\n"); 732 733 /* DSC disable */ 734 ret = anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 735 R_DSC_CTRL_0, ~DSC_EN); 736 if (ret < 0) { 737 DRM_DEV_ERROR(dev, "IO error : disable dsc failed.\n"); 738 return ret; 739 } 740 741 ret = anx7625_config_bit_matrix(ctx); 742 if (ret < 0) { 743 DRM_DEV_ERROR(dev, "config bit matrix failed.\n"); 744 return ret; 745 } 746 747 ret = anx7625_api_dpi_config(ctx); 748 if (ret < 0) { 749 DRM_DEV_ERROR(dev, "mipi phy(dpi) setup failed.\n"); 750 return ret; 751 } 752 753 /* set MIPI RX EN */ 754 ret = anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 755 AP_AV_STATUS, AP_MIPI_RX_EN); 756 /* clear mute flag */ 757 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 758 AP_AV_STATUS, (u8)~AP_MIPI_MUTE); 759 if (ret < 0) 760 DRM_DEV_ERROR(dev, "IO error : enable mipi rx failed.\n"); 761 762 return ret; 763 } 764 765 static int anx7625_read_flash_status(struct anx7625_data *ctx) 766 { 767 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, R_RAM_CTRL); 768 } 769 770 static int anx7625_hdcp_key_probe(struct anx7625_data *ctx) 771 { 772 int ret, val; 773 struct device *dev = ctx->dev; 774 u8 ident[FLASH_BUF_LEN]; 775 776 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 777 FLASH_ADDR_HIGH, 0x91); 778 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 779 FLASH_ADDR_LOW, 0xA0); 780 if (ret < 0) { 781 dev_err(dev, "IO error : set key flash address.\n"); 782 return ret; 783 } 784 785 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 786 FLASH_LEN_HIGH, (FLASH_BUF_LEN - 1) >> 8); 787 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 788 FLASH_LEN_LOW, (FLASH_BUF_LEN - 1) & 0xFF); 789 if (ret < 0) { 790 dev_err(dev, "IO error : set key flash len.\n"); 791 return ret; 792 } 793 794 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 795 R_FLASH_RW_CTRL, FLASH_READ); 796 ret |= readx_poll_timeout(anx7625_read_flash_status, 797 ctx, val, 798 ((val & FLASH_DONE) || (val < 0)), 799 2000, 800 2000 * 150); 801 if (ret) { 802 dev_err(dev, "flash read access fail!\n"); 803 return -EIO; 804 } 805 806 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 807 FLASH_BUF_BASE_ADDR, 808 FLASH_BUF_LEN, ident); 809 if (ret < 0) { 810 dev_err(dev, "read flash data fail!\n"); 811 return -EIO; 812 } 813 814 if (ident[29] == 0xFF && ident[30] == 0xFF && ident[31] == 0xFF) 815 return -EINVAL; 816 817 return 0; 818 } 819 820 static int anx7625_hdcp_key_load(struct anx7625_data *ctx) 821 { 822 int ret; 823 struct device *dev = ctx->dev; 824 825 /* Select HDCP 1.4 KEY */ 826 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 827 R_BOOT_RETRY, 0x12); 828 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 829 FLASH_ADDR_HIGH, HDCP14KEY_START_ADDR >> 8); 830 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 831 FLASH_ADDR_LOW, HDCP14KEY_START_ADDR & 0xFF); 832 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 833 R_RAM_LEN_H, HDCP14KEY_SIZE >> 12); 834 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 835 R_RAM_LEN_L, HDCP14KEY_SIZE >> 4); 836 837 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 838 R_RAM_ADDR_H, 0); 839 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 840 R_RAM_ADDR_L, 0); 841 /* Enable HDCP 1.4 KEY load */ 842 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 843 R_RAM_CTRL, DECRYPT_EN | LOAD_START); 844 dev_dbg(dev, "load HDCP 1.4 key done\n"); 845 return ret; 846 } 847 848 static int anx7625_hdcp_disable(struct anx7625_data *ctx) 849 { 850 int ret; 851 struct device *dev = ctx->dev; 852 853 dev_dbg(dev, "disable HDCP 1.4\n"); 854 855 /* Disable HDCP */ 856 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 857 /* Try auth flag */ 858 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 859 /* Interrupt for DRM */ 860 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 861 if (ret < 0) 862 dev_err(dev, "fail to disable HDCP\n"); 863 864 return anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 865 TX_HDCP_CTRL0, ~HARD_AUTH_EN & 0xFF); 866 } 867 868 static int anx7625_hdcp_enable(struct anx7625_data *ctx) 869 { 870 u8 bcap; 871 int ret; 872 struct device *dev = ctx->dev; 873 874 ret = anx7625_hdcp_key_probe(ctx); 875 if (ret) { 876 dev_dbg(dev, "no key found, not to do hdcp\n"); 877 return ret; 878 } 879 880 /* Read downstream capability */ 881 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_READ, DP_AUX_HDCP_BCAPS, 1, &bcap); 882 if (ret < 0) 883 return ret; 884 885 if (!(bcap & DP_BCAPS_HDCP_CAPABLE)) { 886 pr_warn("downstream not support HDCP 1.4, cap(%x).\n", bcap); 887 return 0; 888 } 889 890 dev_dbg(dev, "enable HDCP 1.4\n"); 891 892 /* First clear HDCP state */ 893 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 894 TX_HDCP_CTRL0, 895 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 896 usleep_range(1000, 1100); 897 /* Second clear HDCP state */ 898 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 899 TX_HDCP_CTRL0, 900 KSVLIST_VLD | BKSV_SRM_PASS | RE_AUTHEN); 901 902 /* Set time for waiting KSVR */ 903 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 904 SP_TX_WAIT_KSVR_TIME, 0xc8); 905 /* Set time for waiting R0 */ 906 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p0_client, 907 SP_TX_WAIT_R0_TIME, 0xb0); 908 ret |= anx7625_hdcp_key_load(ctx); 909 if (ret) { 910 pr_warn("prepare HDCP key failed.\n"); 911 return ret; 912 } 913 914 ret = anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xee, 0x20); 915 916 /* Try auth flag */ 917 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 918 /* Interrupt for DRM */ 919 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 920 if (ret < 0) 921 dev_err(dev, "fail to enable HDCP\n"); 922 923 return anx7625_write_or(ctx, ctx->i2c.tx_p0_client, 924 TX_HDCP_CTRL0, HARD_AUTH_EN); 925 } 926 927 static void anx7625_dp_start(struct anx7625_data *ctx) 928 { 929 int ret; 930 struct device *dev = ctx->dev; 931 u8 data; 932 933 if (!ctx->display_timing_valid) { 934 DRM_DEV_ERROR(dev, "mipi not set display timing yet.\n"); 935 return; 936 } 937 938 dev_dbg(dev, "set downstream sink into normal\n"); 939 /* Downstream sink enter into normal mode */ 940 data = DP_SET_POWER_D0; 941 ret = anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, DP_SET_POWER, 1, &data); 942 if (ret < 0) 943 dev_err(dev, "IO error : set sink into normal mode fail\n"); 944 945 /* Disable HDCP */ 946 anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 947 948 if (ctx->pdata.is_dpi) 949 ret = anx7625_dpi_config(ctx); 950 else 951 ret = anx7625_dsi_config(ctx); 952 953 if (ret < 0) 954 DRM_DEV_ERROR(dev, "MIPI phy setup error.\n"); 955 956 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 957 958 ctx->dp_en = 1; 959 } 960 961 static void anx7625_dp_stop(struct anx7625_data *ctx) 962 { 963 struct device *dev = ctx->dev; 964 int ret; 965 u8 data; 966 967 DRM_DEV_DEBUG_DRIVER(dev, "stop dp output\n"); 968 969 /* 970 * Video disable: 0x72:08 bit 7 = 0; 971 * Audio disable: 0x70:87 bit 0 = 0; 972 */ 973 ret = anx7625_write_and(ctx, ctx->i2c.tx_p0_client, 0x87, 0xfe); 974 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 0x08, 0x7f); 975 976 ret |= anx7625_video_mute_control(ctx, 1); 977 978 dev_dbg(dev, "notify downstream enter into standby\n"); 979 /* Downstream monitor enter into standby mode */ 980 data = DP_SET_POWER_D3; 981 ret |= anx7625_aux_trans(ctx, DP_AUX_NATIVE_WRITE, DP_SET_POWER, 1, &data); 982 if (ret < 0) 983 DRM_DEV_ERROR(dev, "IO error : mute video fail\n"); 984 985 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_UNDESIRED; 986 987 ctx->dp_en = 0; 988 } 989 990 static int sp_tx_rst_aux(struct anx7625_data *ctx) 991 { 992 int ret; 993 994 ret = anx7625_write_or(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 995 AUX_RST); 996 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, RST_CTRL2, 997 ~AUX_RST); 998 return ret; 999 } 1000 1001 static int sp_tx_aux_wr(struct anx7625_data *ctx, u8 offset) 1002 { 1003 int ret; 1004 1005 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1006 AP_AUX_BUFF_START, offset); 1007 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1008 AP_AUX_COMMAND, 0x04); 1009 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1010 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 1011 return (ret | wait_aux_op_finish(ctx)); 1012 } 1013 1014 static int sp_tx_aux_rd(struct anx7625_data *ctx, u8 len_cmd) 1015 { 1016 int ret; 1017 1018 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1019 AP_AUX_COMMAND, len_cmd); 1020 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 1021 AP_AUX_CTRL_STATUS, AP_AUX_CTRL_OP_EN); 1022 return (ret | wait_aux_op_finish(ctx)); 1023 } 1024 1025 static int sp_tx_get_edid_block(struct anx7625_data *ctx) 1026 { 1027 int c = 0; 1028 struct device *dev = ctx->dev; 1029 1030 sp_tx_aux_wr(ctx, 0x7e); 1031 sp_tx_aux_rd(ctx, 0x01); 1032 c = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, AP_AUX_BUFF_START); 1033 if (c < 0) { 1034 DRM_DEV_ERROR(dev, "IO error : access AUX BUFF.\n"); 1035 return -EIO; 1036 } 1037 1038 DRM_DEV_DEBUG_DRIVER(dev, " EDID Block = %d\n", c + 1); 1039 1040 if (c > MAX_EDID_BLOCK) 1041 c = 1; 1042 1043 return c; 1044 } 1045 1046 static int edid_read(struct anx7625_data *ctx, 1047 u8 offset, u8 *pblock_buf) 1048 { 1049 int ret, cnt; 1050 struct device *dev = ctx->dev; 1051 1052 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1053 sp_tx_aux_wr(ctx, offset); 1054 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1055 ret = sp_tx_aux_rd(ctx, 0xf1); 1056 1057 if (ret) { 1058 ret = sp_tx_rst_aux(ctx); 1059 DRM_DEV_DEBUG_DRIVER(dev, "edid read fail, reset!\n"); 1060 } else { 1061 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1062 AP_AUX_BUFF_START, 1063 MAX_DPCD_BUFFER_SIZE, 1064 pblock_buf); 1065 if (ret > 0) 1066 break; 1067 } 1068 } 1069 1070 if (cnt > EDID_TRY_CNT) 1071 return -EIO; 1072 1073 return ret; 1074 } 1075 1076 static int segments_edid_read(struct anx7625_data *ctx, 1077 u8 segment, u8 *buf, u8 offset) 1078 { 1079 u8 cnt; 1080 int ret; 1081 struct device *dev = ctx->dev; 1082 1083 /* Write address only */ 1084 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1085 AP_AUX_ADDR_7_0, 0x30); 1086 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1087 AP_AUX_COMMAND, 0x04); 1088 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1089 AP_AUX_CTRL_STATUS, 1090 AP_AUX_CTRL_ADDRONLY | AP_AUX_CTRL_OP_EN); 1091 1092 ret |= wait_aux_op_finish(ctx); 1093 /* Write segment address */ 1094 ret |= sp_tx_aux_wr(ctx, segment); 1095 /* Data read */ 1096 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1097 AP_AUX_ADDR_7_0, 0x50); 1098 if (ret) { 1099 DRM_DEV_ERROR(dev, "IO error : aux initial fail.\n"); 1100 return ret; 1101 } 1102 1103 for (cnt = 0; cnt <= EDID_TRY_CNT; cnt++) { 1104 sp_tx_aux_wr(ctx, offset); 1105 /* Set I2C read com 0x01 mot = 0 and read 16 bytes */ 1106 ret = sp_tx_aux_rd(ctx, 0xf1); 1107 1108 if (ret) { 1109 ret = sp_tx_rst_aux(ctx); 1110 DRM_DEV_ERROR(dev, "segment read fail, reset!\n"); 1111 } else { 1112 ret = anx7625_reg_block_read(ctx, ctx->i2c.rx_p0_client, 1113 AP_AUX_BUFF_START, 1114 MAX_DPCD_BUFFER_SIZE, buf); 1115 if (ret > 0) 1116 break; 1117 } 1118 } 1119 1120 if (cnt > EDID_TRY_CNT) 1121 return -EIO; 1122 1123 return ret; 1124 } 1125 1126 static int sp_tx_edid_read(struct anx7625_data *ctx, 1127 u8 *pedid_blocks_buf) 1128 { 1129 u8 offset; 1130 int edid_pos; 1131 int count, blocks_num; 1132 u8 pblock_buf[MAX_DPCD_BUFFER_SIZE]; 1133 u8 i, j; 1134 int g_edid_break = 0; 1135 int ret; 1136 struct device *dev = ctx->dev; 1137 1138 /* Address initial */ 1139 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1140 AP_AUX_ADDR_7_0, 0x50); 1141 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1142 AP_AUX_ADDR_15_8, 0); 1143 ret |= anx7625_write_and(ctx, ctx->i2c.rx_p0_client, 1144 AP_AUX_ADDR_19_16, 0xf0); 1145 if (ret < 0) { 1146 DRM_DEV_ERROR(dev, "access aux channel IO error.\n"); 1147 return -EIO; 1148 } 1149 1150 blocks_num = sp_tx_get_edid_block(ctx); 1151 if (blocks_num < 0) 1152 return blocks_num; 1153 1154 count = 0; 1155 1156 do { 1157 switch (count) { 1158 case 0: 1159 case 1: 1160 for (i = 0; i < 8; i++) { 1161 offset = (i + count * 8) * MAX_DPCD_BUFFER_SIZE; 1162 g_edid_break = edid_read(ctx, offset, 1163 pblock_buf); 1164 1165 if (g_edid_break < 0) 1166 break; 1167 1168 memcpy(&pedid_blocks_buf[offset], 1169 pblock_buf, 1170 MAX_DPCD_BUFFER_SIZE); 1171 } 1172 1173 break; 1174 case 2: 1175 offset = 0x00; 1176 1177 for (j = 0; j < 8; j++) { 1178 edid_pos = (j + count * 8) * 1179 MAX_DPCD_BUFFER_SIZE; 1180 1181 if (g_edid_break == 1) 1182 break; 1183 1184 ret = segments_edid_read(ctx, count / 2, 1185 pblock_buf, offset); 1186 if (ret < 0) 1187 return ret; 1188 1189 memcpy(&pedid_blocks_buf[edid_pos], 1190 pblock_buf, 1191 MAX_DPCD_BUFFER_SIZE); 1192 offset = offset + 0x10; 1193 } 1194 1195 break; 1196 case 3: 1197 offset = 0x80; 1198 1199 for (j = 0; j < 8; j++) { 1200 edid_pos = (j + count * 8) * 1201 MAX_DPCD_BUFFER_SIZE; 1202 if (g_edid_break == 1) 1203 break; 1204 1205 ret = segments_edid_read(ctx, count / 2, 1206 pblock_buf, offset); 1207 if (ret < 0) 1208 return ret; 1209 1210 memcpy(&pedid_blocks_buf[edid_pos], 1211 pblock_buf, 1212 MAX_DPCD_BUFFER_SIZE); 1213 offset = offset + 0x10; 1214 } 1215 1216 break; 1217 default: 1218 break; 1219 } 1220 1221 count++; 1222 1223 } while (blocks_num >= count); 1224 1225 /* Check edid data */ 1226 if (!drm_edid_is_valid((struct edid *)pedid_blocks_buf)) { 1227 DRM_DEV_ERROR(dev, "WARNING! edid check fail!\n"); 1228 return -EINVAL; 1229 } 1230 1231 /* Reset aux channel */ 1232 ret = sp_tx_rst_aux(ctx); 1233 if (ret < 0) { 1234 DRM_DEV_ERROR(dev, "Failed to reset aux channel!\n"); 1235 return ret; 1236 } 1237 1238 return (blocks_num + 1); 1239 } 1240 1241 static void anx7625_power_on(struct anx7625_data *ctx) 1242 { 1243 struct device *dev = ctx->dev; 1244 int ret, i; 1245 1246 if (!ctx->pdata.low_power_mode) { 1247 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1248 return; 1249 } 1250 1251 for (i = 0; i < ARRAY_SIZE(ctx->pdata.supplies); i++) { 1252 ret = regulator_enable(ctx->pdata.supplies[i].consumer); 1253 if (ret < 0) { 1254 DRM_DEV_DEBUG_DRIVER(dev, "cannot enable supply %d: %d\n", 1255 i, ret); 1256 goto reg_err; 1257 } 1258 usleep_range(2000, 2100); 1259 } 1260 1261 usleep_range(11000, 12000); 1262 1263 /* Power on pin enable */ 1264 gpiod_set_value_cansleep(ctx->pdata.gpio_p_on, 1); 1265 usleep_range(10000, 11000); 1266 /* Power reset pin enable */ 1267 gpiod_set_value_cansleep(ctx->pdata.gpio_reset, 1); 1268 usleep_range(10000, 11000); 1269 1270 DRM_DEV_DEBUG_DRIVER(dev, "power on !\n"); 1271 return; 1272 reg_err: 1273 for (--i; i >= 0; i--) 1274 regulator_disable(ctx->pdata.supplies[i].consumer); 1275 } 1276 1277 static void anx7625_power_standby(struct anx7625_data *ctx) 1278 { 1279 struct device *dev = ctx->dev; 1280 int ret; 1281 1282 if (!ctx->pdata.low_power_mode) { 1283 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode!\n"); 1284 return; 1285 } 1286 1287 gpiod_set_value_cansleep(ctx->pdata.gpio_reset, 0); 1288 usleep_range(1000, 1100); 1289 gpiod_set_value_cansleep(ctx->pdata.gpio_p_on, 0); 1290 usleep_range(1000, 1100); 1291 1292 ret = regulator_bulk_disable(ARRAY_SIZE(ctx->pdata.supplies), 1293 ctx->pdata.supplies); 1294 if (ret < 0) 1295 DRM_DEV_DEBUG_DRIVER(dev, "cannot disable supplies %d\n", ret); 1296 1297 DRM_DEV_DEBUG_DRIVER(dev, "power down\n"); 1298 } 1299 1300 /* Basic configurations of ANX7625 */ 1301 static void anx7625_config(struct anx7625_data *ctx) 1302 { 1303 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1304 XTAL_FRQ_SEL, XTAL_FRQ_27M); 1305 } 1306 1307 static int anx7625_hpd_timer_config(struct anx7625_data *ctx) 1308 { 1309 int ret; 1310 1311 /* Set irq detect window to 2ms */ 1312 ret = anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 1313 HPD_DET_TIMER_BIT0_7, HPD_TIME & 0xFF); 1314 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 1315 HPD_DET_TIMER_BIT8_15, 1316 (HPD_TIME >> 8) & 0xFF); 1317 ret |= anx7625_reg_write(ctx, ctx->i2c.tx_p2_client, 1318 HPD_DET_TIMER_BIT16_23, 1319 (HPD_TIME >> 16) & 0xFF); 1320 1321 return ret; 1322 } 1323 1324 static int anx7625_read_hpd_gpio_config_status(struct anx7625_data *ctx) 1325 { 1326 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, GPIO_CTRL_2); 1327 } 1328 1329 static void anx7625_disable_pd_protocol(struct anx7625_data *ctx) 1330 { 1331 struct device *dev = ctx->dev; 1332 int ret; 1333 1334 /* Reset main ocm */ 1335 ret = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x40); 1336 /* Disable PD */ 1337 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1338 AP_AV_STATUS, AP_DISABLE_PD); 1339 /* Release main ocm */ 1340 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 0x88, 0x00); 1341 1342 if (ret < 0) 1343 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature fail.\n"); 1344 else 1345 DRM_DEV_DEBUG_DRIVER(dev, "disable PD feature succeeded.\n"); 1346 } 1347 1348 static void anx7625_configure_hpd(struct anx7625_data *ctx) 1349 { 1350 int val; 1351 1352 /* 1353 * Make sure the HPD GPIO already be configured after OCM release before 1354 * setting HPD detect window register. Here we poll the status register 1355 * at maximum 40ms, then config HPD irq detect window register 1356 */ 1357 readx_poll_timeout(anx7625_read_hpd_gpio_config_status, 1358 ctx, val, 1359 ((val & HPD_SOURCE) || (val < 0)), 1360 2000, 2000 * 20); 1361 1362 /* Set HPD irq detect window to 2ms */ 1363 anx7625_hpd_timer_config(ctx); 1364 } 1365 1366 static bool anx7625_need_pd(struct anx7625_data *ctx) 1367 { 1368 struct fwnode_handle *fwnode; 1369 1370 fwnode = device_get_named_child_node(ctx->dev, "connector"); 1371 if (!fwnode) 1372 return false; 1373 1374 fwnode_handle_put(fwnode); 1375 return true; 1376 } 1377 1378 static int anx7625_ocm_loading_check(struct anx7625_data *ctx) 1379 { 1380 int ret; 1381 struct device *dev = ctx->dev; 1382 1383 /* Check interface workable */ 1384 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1385 FLASH_LOAD_STA); 1386 if (ret < 0) { 1387 DRM_DEV_ERROR(dev, "IO error : access flash load.\n"); 1388 return ret; 1389 } 1390 if ((ret & FLASH_LOAD_STA_CHK) != FLASH_LOAD_STA_CHK) 1391 return -ENODEV; 1392 1393 if (!anx7625_need_pd(ctx)) 1394 anx7625_disable_pd_protocol(ctx); 1395 anx7625_configure_hpd(ctx); 1396 1397 DRM_DEV_DEBUG_DRIVER(dev, "Firmware ver %02x%02x,", 1398 anx7625_reg_read(ctx, 1399 ctx->i2c.rx_p0_client, 1400 OCM_FW_VERSION), 1401 anx7625_reg_read(ctx, 1402 ctx->i2c.rx_p0_client, 1403 OCM_FW_REVERSION)); 1404 DRM_DEV_DEBUG_DRIVER(dev, "Driver version %s\n", 1405 ANX7625_DRV_VERSION); 1406 1407 return 0; 1408 } 1409 1410 static void anx7625_power_on_init(struct anx7625_data *ctx) 1411 { 1412 int retry_count, i; 1413 1414 for (retry_count = 0; retry_count < 3; retry_count++) { 1415 anx7625_power_on(ctx); 1416 anx7625_config(ctx); 1417 1418 for (i = 0; i < OCM_LOADING_TIME; i++) { 1419 if (!anx7625_ocm_loading_check(ctx)) 1420 return; 1421 usleep_range(1000, 1100); 1422 } 1423 anx7625_power_standby(ctx); 1424 } 1425 } 1426 1427 static void anx7625_init_gpio(struct anx7625_data *platform) 1428 { 1429 struct device *dev = platform->dev; 1430 1431 DRM_DEV_DEBUG_DRIVER(dev, "init gpio\n"); 1432 1433 /* Gpio for chip power enable */ 1434 platform->pdata.gpio_p_on = 1435 devm_gpiod_get_optional(dev, "enable", GPIOD_OUT_LOW); 1436 if (IS_ERR_OR_NULL(platform->pdata.gpio_p_on)) { 1437 DRM_DEV_DEBUG_DRIVER(dev, "no enable gpio found\n"); 1438 platform->pdata.gpio_p_on = NULL; 1439 } 1440 1441 /* Gpio for chip reset */ 1442 platform->pdata.gpio_reset = 1443 devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 1444 if (IS_ERR_OR_NULL(platform->pdata.gpio_reset)) { 1445 DRM_DEV_DEBUG_DRIVER(dev, "no reset gpio found\n"); 1446 platform->pdata.gpio_reset = NULL; 1447 } 1448 1449 if (platform->pdata.gpio_p_on && platform->pdata.gpio_reset) { 1450 platform->pdata.low_power_mode = 1; 1451 DRM_DEV_DEBUG_DRIVER(dev, "low power mode, pon %d, reset %d.\n", 1452 desc_to_gpio(platform->pdata.gpio_p_on), 1453 desc_to_gpio(platform->pdata.gpio_reset)); 1454 } else { 1455 platform->pdata.low_power_mode = 0; 1456 DRM_DEV_DEBUG_DRIVER(dev, "not low power mode.\n"); 1457 } 1458 } 1459 1460 static void anx7625_stop_dp_work(struct anx7625_data *ctx) 1461 { 1462 ctx->hpd_status = 0; 1463 ctx->hpd_high_cnt = 0; 1464 } 1465 1466 static void anx7625_start_dp_work(struct anx7625_data *ctx) 1467 { 1468 int ret; 1469 struct device *dev = ctx->dev; 1470 1471 if (ctx->hpd_high_cnt >= 2) { 1472 DRM_DEV_DEBUG_DRIVER(dev, "filter useless HPD\n"); 1473 return; 1474 } 1475 1476 ctx->hpd_status = 1; 1477 ctx->hpd_high_cnt++; 1478 1479 /* Not support HDCP */ 1480 ret = anx7625_write_and(ctx, ctx->i2c.rx_p1_client, 0xee, 0x9f); 1481 1482 /* Try auth flag */ 1483 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xec, 0x10); 1484 /* Interrupt for DRM */ 1485 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p1_client, 0xff, 0x01); 1486 if (ret < 0) { 1487 DRM_DEV_ERROR(dev, "fail to setting HDCP/auth\n"); 1488 return; 1489 } 1490 1491 ret = anx7625_reg_read(ctx, ctx->i2c.rx_p1_client, 0x86); 1492 if (ret < 0) 1493 return; 1494 1495 DRM_DEV_DEBUG_DRIVER(dev, "Secure OCM version=%02x\n", ret); 1496 } 1497 1498 static u8 anx7625_checksum(u8 *buf, u8 len) 1499 { 1500 u8 ret = 0; 1501 u8 i; 1502 1503 for (i = 0; i < len; i++) 1504 ret += buf[i]; 1505 1506 return ret; 1507 } 1508 1509 static int anx7625_read_msg_ctrl_status(struct anx7625_data *ctx) 1510 { 1511 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, CMD_SEND_BUF); 1512 } 1513 1514 static int anx7625_wait_msg_empty(struct anx7625_data *ctx) 1515 { 1516 int val; 1517 1518 return readx_poll_timeout(anx7625_read_msg_ctrl_status, ctx, 1519 val, (val < 0) || (val == 0), 1520 2000, 2000 * 150); 1521 } 1522 1523 static int anx7625_send_msg(struct anx7625_data *ctx, u8 type, u8 *buf, u8 size) 1524 { 1525 struct fw_msg *msg = &ctx->send_msg; 1526 u8 crc; 1527 int ret; 1528 1529 size = min_t(u8, size, (u8)MAX_BUF_LEN); 1530 memcpy(msg->buf, buf, size); 1531 msg->msg_type = type; 1532 1533 /* msg len equals buffer length + msg_type */ 1534 msg->msg_len = size + 1; 1535 1536 crc = anx7625_checksum((u8 *)msg, size + HEADER_LEN); 1537 msg->buf[size] = 0 - crc; 1538 1539 ret = anx7625_wait_msg_empty(ctx); 1540 if (ret) 1541 return ret; 1542 1543 ret = anx7625_reg_block_write(ctx, ctx->i2c.rx_p0_client, 1544 CMD_SEND_BUF + 1, size + HEADER_LEN, 1545 &msg->msg_type); 1546 ret |= anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, CMD_SEND_BUF, 1547 msg->msg_len); 1548 return ret; 1549 } 1550 1551 static int anx7625_typec_dr_set(struct typec_port *port, enum typec_data_role role) 1552 { 1553 struct anx7625_data *ctx = typec_get_drvdata(port); 1554 1555 if (role == ctx->typec_data_role) 1556 return 0; 1557 1558 return anx7625_send_msg(ctx, 0x11, NULL, 0); 1559 } 1560 1561 static const struct typec_operations anx7625_typec_ops = { 1562 .dr_set = anx7625_typec_dr_set, 1563 }; 1564 1565 static void anx7625_typec_set_orientation(struct anx7625_data *ctx) 1566 { 1567 u32 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1568 1569 if (val & (CC1_RP | CC1_RD)) 1570 typec_set_orientation(ctx->typec_port, TYPEC_ORIENTATION_NORMAL); 1571 else if (val & (CC2_RP | CC2_RD)) 1572 typec_set_orientation(ctx->typec_port, TYPEC_ORIENTATION_REVERSE); 1573 else 1574 typec_set_orientation(ctx->typec_port, TYPEC_ORIENTATION_NONE); 1575 } 1576 1577 static void anx7625_typec_set_status(struct anx7625_data *ctx, 1578 unsigned int intr_status, 1579 unsigned int intr_vector) 1580 { 1581 if (!ctx->typec_port) 1582 return; 1583 1584 if (intr_vector & CC_STATUS) 1585 anx7625_typec_set_orientation(ctx); 1586 if (intr_vector & DATA_ROLE_STATUS) { 1587 enum typec_data_role data_role = (intr_status & DATA_ROLE_STATUS) ? 1588 TYPEC_HOST : TYPEC_DEVICE; 1589 usb_role_switch_set_role(ctx->role_sw, 1590 (intr_status & DATA_ROLE_STATUS) ? 1591 USB_ROLE_HOST : USB_ROLE_DEVICE); 1592 typec_set_data_role(ctx->typec_port, data_role); 1593 ctx->typec_data_role = data_role; 1594 } 1595 if (intr_vector & VBUS_STATUS) 1596 typec_set_pwr_role(ctx->typec_port, 1597 (intr_status & VBUS_STATUS) ? 1598 TYPEC_SOURCE : TYPEC_SINK); 1599 if (intr_vector & VCONN_STATUS) 1600 typec_set_vconn_role(ctx->typec_port, 1601 (intr_status & VCONN_STATUS) ? 1602 TYPEC_SOURCE : TYPEC_SINK); 1603 } 1604 1605 static int anx7625_typec_register(struct anx7625_data *ctx) 1606 { 1607 struct typec_capability typec_cap = { }; 1608 struct fwnode_handle *fwnode __free(fwnode_handle) = 1609 device_get_named_child_node(ctx->dev, "connector"); 1610 u32 val; 1611 int ret; 1612 1613 if (!fwnode) 1614 return 0; 1615 1616 ret = typec_get_fw_cap(&typec_cap, fwnode); 1617 if (ret < 0) 1618 return ret; 1619 1620 typec_cap.revision = 0x0120; 1621 typec_cap.pd_revision = 0x0300; 1622 typec_cap.usb_capability = USB_CAPABILITY_USB2 | USB_CAPABILITY_USB3; 1623 typec_cap.orientation_aware = true; 1624 1625 typec_cap.driver_data = ctx; 1626 typec_cap.ops = &anx7625_typec_ops; 1627 1628 ctx->typec_port = typec_register_port(ctx->dev, &typec_cap); 1629 if (IS_ERR(ctx->typec_port)) 1630 return PTR_ERR(ctx->typec_port); 1631 1632 ctx->role_sw = fwnode_usb_role_switch_get(fwnode); 1633 if (IS_ERR(ctx->role_sw)) { 1634 typec_unregister_port(ctx->typec_port); 1635 return PTR_ERR(ctx->role_sw); 1636 } 1637 1638 val = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1639 1640 anx7625_typec_set_status(ctx, val, 1641 CC_STATUS | DATA_ROLE_STATUS | 1642 VBUS_STATUS | VCONN_STATUS); 1643 1644 return 0; 1645 } 1646 1647 static void anx7625_typec_unregister(struct anx7625_data *ctx) 1648 { 1649 usb_role_switch_put(ctx->role_sw); 1650 typec_unregister_port(ctx->typec_port); 1651 } 1652 1653 static int anx7625_read_hpd_status_p0(struct anx7625_data *ctx) 1654 { 1655 return anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, SYSTEM_STSTUS); 1656 } 1657 1658 static int _anx7625_hpd_polling(struct anx7625_data *ctx, 1659 unsigned long wait_us) 1660 { 1661 int ret, val; 1662 struct device *dev = ctx->dev; 1663 1664 /* Interrupt mode, no need poll HPD status, just return */ 1665 if (ctx->pdata.intp_irq) 1666 return 0; 1667 1668 ret = readx_poll_timeout(anx7625_read_hpd_status_p0, 1669 ctx, val, 1670 ((val & HPD_STATUS) || (val < 0)), 1671 wait_us / 100, 1672 wait_us); 1673 if (ret) { 1674 DRM_DEV_ERROR(dev, "no hpd.\n"); 1675 return ret; 1676 } 1677 1678 DRM_DEV_DEBUG_DRIVER(dev, "system status: 0x%x. HPD raise up.\n", val); 1679 anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1680 INTR_ALERT_1, 0xFF); 1681 anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1682 INTERFACE_CHANGE_INT, 0); 1683 1684 anx7625_start_dp_work(ctx); 1685 1686 if (!ctx->pdata.panel_bridge && ctx->bridge_attached) 1687 drm_helper_hpd_irq_event(ctx->bridge.dev); 1688 1689 return 0; 1690 } 1691 1692 static int anx7625_wait_hpd_asserted(struct drm_dp_aux *aux, 1693 unsigned long wait_us) 1694 { 1695 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux); 1696 struct device *dev = ctx->dev; 1697 int ret; 1698 1699 pm_runtime_get_sync(dev); 1700 ret = _anx7625_hpd_polling(ctx, wait_us); 1701 pm_runtime_mark_last_busy(dev); 1702 pm_runtime_put_autosuspend(dev); 1703 1704 return ret; 1705 } 1706 1707 static void anx7625_remove_edid(struct anx7625_data *ctx) 1708 { 1709 drm_edid_free(ctx->cached_drm_edid); 1710 ctx->cached_drm_edid = NULL; 1711 } 1712 1713 static void anx7625_dp_adjust_swing(struct anx7625_data *ctx) 1714 { 1715 int i; 1716 1717 for (i = 0; i < ctx->pdata.dp_lane0_swing_reg_cnt; i++) 1718 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1719 DP_TX_LANE0_SWING_REG0 + i, 1720 ctx->pdata.lane0_reg_data[i]); 1721 1722 for (i = 0; i < ctx->pdata.dp_lane1_swing_reg_cnt; i++) 1723 anx7625_reg_write(ctx, ctx->i2c.tx_p1_client, 1724 DP_TX_LANE1_SWING_REG0 + i, 1725 ctx->pdata.lane1_reg_data[i]); 1726 } 1727 1728 static void dp_hpd_change_handler(struct anx7625_data *ctx, bool on) 1729 { 1730 struct device *dev = ctx->dev; 1731 1732 /* HPD changed */ 1733 DRM_DEV_DEBUG_DRIVER(dev, "dp_hpd_change_default_func: %d\n", 1734 (u32)on); 1735 1736 if (on == 0) { 1737 DRM_DEV_DEBUG_DRIVER(dev, " HPD low\n"); 1738 anx7625_remove_edid(ctx); 1739 anx7625_stop_dp_work(ctx); 1740 } else { 1741 DRM_DEV_DEBUG_DRIVER(dev, " HPD high\n"); 1742 anx7625_start_dp_work(ctx); 1743 anx7625_dp_adjust_swing(ctx); 1744 } 1745 } 1746 1747 static int anx7625_intr_status(struct anx7625_data *ctx) 1748 { 1749 int intr_vector, status; 1750 struct device *dev = ctx->dev; 1751 1752 status = anx7625_reg_write(ctx, ctx->i2c.tcpc_client, 1753 INTR_ALERT_1, 0xFF); 1754 if (status < 0) { 1755 DRM_DEV_ERROR(dev, "cannot clear alert reg.\n"); 1756 return status; 1757 } 1758 1759 intr_vector = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1760 INTERFACE_CHANGE_INT); 1761 if (intr_vector < 0) { 1762 DRM_DEV_ERROR(dev, "cannot access interrupt change reg.\n"); 1763 return intr_vector; 1764 } 1765 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x44=%x\n", intr_vector); 1766 status = anx7625_reg_write(ctx, ctx->i2c.rx_p0_client, 1767 INTERFACE_CHANGE_INT, 1768 intr_vector & (~intr_vector)); 1769 if (status < 0) { 1770 DRM_DEV_ERROR(dev, "cannot clear interrupt change reg.\n"); 1771 return status; 1772 } 1773 1774 status = anx7625_reg_read(ctx, ctx->i2c.rx_p0_client, 1775 SYSTEM_STSTUS); 1776 if (status < 0) { 1777 DRM_DEV_ERROR(dev, "cannot clear interrupt status.\n"); 1778 return status; 1779 } 1780 1781 DRM_DEV_DEBUG_DRIVER(dev, "0x7e:0x45=%x\n", status); 1782 1783 anx7625_typec_set_status(ctx, status, intr_vector); 1784 1785 if (!(intr_vector & HPD_STATUS)) 1786 return -ENOENT; 1787 1788 dp_hpd_change_handler(ctx, status & HPD_STATUS); 1789 1790 return 0; 1791 } 1792 1793 static void anx7625_work_func(struct work_struct *work) 1794 { 1795 int event; 1796 struct anx7625_data *ctx = container_of(work, 1797 struct anx7625_data, work); 1798 1799 mutex_lock(&ctx->lock); 1800 1801 if (pm_runtime_suspended(ctx->dev)) { 1802 mutex_unlock(&ctx->lock); 1803 return; 1804 } 1805 1806 event = anx7625_intr_status(ctx); 1807 1808 mutex_unlock(&ctx->lock); 1809 1810 if (event < 0) 1811 return; 1812 1813 if (ctx->bridge_attached) 1814 drm_helper_hpd_irq_event(ctx->bridge.dev); 1815 } 1816 1817 static irqreturn_t anx7625_intr_hpd_isr(int irq, void *data) 1818 { 1819 struct anx7625_data *ctx = (struct anx7625_data *)data; 1820 1821 queue_work(ctx->workqueue, &ctx->work); 1822 1823 return IRQ_HANDLED; 1824 } 1825 1826 static int anx7625_get_swing_setting(struct device *dev, 1827 struct anx7625_platform_data *pdata) 1828 { 1829 int num_regs; 1830 1831 num_regs = of_property_read_variable_u8_array(dev->of_node, "analogix,lane0-swing", 1832 pdata->lane0_reg_data, 1, DP_TX_SWING_REG_CNT); 1833 if (num_regs > 0) 1834 pdata->dp_lane0_swing_reg_cnt = num_regs; 1835 1836 num_regs = of_property_read_variable_u8_array(dev->of_node, "analogix,lane1-swing", 1837 pdata->lane1_reg_data, 1, DP_TX_SWING_REG_CNT); 1838 if (num_regs > 0) 1839 pdata->dp_lane1_swing_reg_cnt = num_regs; 1840 1841 return 0; 1842 } 1843 1844 static int anx7625_parse_dt(struct device *dev, 1845 struct anx7625_platform_data *pdata) 1846 { 1847 struct device_node *np = dev->of_node, *ep0; 1848 int bus_type, mipi_lanes; 1849 1850 anx7625_get_swing_setting(dev, pdata); 1851 1852 pdata->is_dpi = 0; /* default dsi mode */ 1853 of_node_put(pdata->mipi_host_node); 1854 pdata->mipi_host_node = of_graph_get_remote_node(np, 0, 0); 1855 if (!pdata->mipi_host_node) { 1856 DRM_DEV_ERROR(dev, "fail to get internal panel.\n"); 1857 return -ENODEV; 1858 } 1859 1860 bus_type = 0; 1861 mipi_lanes = MAX_LANES_SUPPORT; 1862 ep0 = of_graph_get_endpoint_by_regs(np, 0, 0); 1863 if (ep0) { 1864 if (of_property_read_u32(ep0, "bus-type", &bus_type)) 1865 bus_type = 0; 1866 1867 mipi_lanes = drm_of_get_data_lanes_count(ep0, 1, MAX_LANES_SUPPORT); 1868 of_node_put(ep0); 1869 } 1870 1871 if (bus_type == V4L2_FWNODE_BUS_TYPE_DPI) /* bus type is DPI */ 1872 pdata->is_dpi = 1; 1873 1874 pdata->mipi_lanes = MAX_LANES_SUPPORT; 1875 if (mipi_lanes > 0) 1876 pdata->mipi_lanes = mipi_lanes; 1877 1878 if (pdata->is_dpi) 1879 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DPI host node.\n"); 1880 else 1881 DRM_DEV_DEBUG_DRIVER(dev, "found MIPI DSI host node.\n"); 1882 1883 if (of_property_read_bool(np, "analogix,audio-enable")) 1884 pdata->audio_en = 1; 1885 1886 return 0; 1887 } 1888 1889 static int anx7625_parse_dt_panel(struct device *dev, 1890 struct anx7625_platform_data *pdata) 1891 { 1892 struct device_node *np = dev->of_node; 1893 1894 pdata->panel_bridge = devm_drm_of_get_bridge(dev, np, 1, 0); 1895 if (IS_ERR(pdata->panel_bridge)) { 1896 if (PTR_ERR(pdata->panel_bridge) == -ENODEV) { 1897 pdata->panel_bridge = NULL; 1898 return 0; 1899 } 1900 1901 return PTR_ERR(pdata->panel_bridge); 1902 } 1903 1904 DRM_DEV_DEBUG_DRIVER(dev, "get panel node.\n"); 1905 1906 return 0; 1907 } 1908 1909 static bool anx7625_of_panel_on_aux_bus(struct device *dev) 1910 { 1911 struct device_node *bus, *panel; 1912 1913 bus = of_get_child_by_name(dev->of_node, "aux-bus"); 1914 if (!bus) 1915 return false; 1916 1917 panel = of_get_child_by_name(bus, "panel"); 1918 of_node_put(bus); 1919 if (!panel) 1920 return false; 1921 of_node_put(panel); 1922 1923 return true; 1924 } 1925 1926 static inline struct anx7625_data *bridge_to_anx7625(struct drm_bridge *bridge) 1927 { 1928 return container_of(bridge, struct anx7625_data, bridge); 1929 } 1930 1931 static ssize_t anx7625_aux_transfer(struct drm_dp_aux *aux, 1932 struct drm_dp_aux_msg *msg) 1933 { 1934 struct anx7625_data *ctx = container_of(aux, struct anx7625_data, aux); 1935 struct device *dev = ctx->dev; 1936 u8 request = msg->request & ~DP_AUX_I2C_MOT; 1937 int ret = 0; 1938 1939 mutex_lock(&ctx->aux_lock); 1940 pm_runtime_get_sync(dev); 1941 msg->reply = 0; 1942 switch (request) { 1943 case DP_AUX_NATIVE_WRITE: 1944 case DP_AUX_I2C_WRITE: 1945 case DP_AUX_NATIVE_READ: 1946 case DP_AUX_I2C_READ: 1947 break; 1948 default: 1949 ret = -EINVAL; 1950 } 1951 if (!ret) 1952 ret = anx7625_aux_trans(ctx, msg->request, msg->address, 1953 msg->size, msg->buffer); 1954 pm_runtime_mark_last_busy(dev); 1955 pm_runtime_put_autosuspend(dev); 1956 mutex_unlock(&ctx->aux_lock); 1957 1958 return ret; 1959 } 1960 1961 static const struct drm_edid *anx7625_edid_read(struct anx7625_data *ctx) 1962 { 1963 struct device *dev = ctx->dev; 1964 u8 *edid_buf; 1965 int edid_num; 1966 1967 if (ctx->cached_drm_edid) 1968 goto out; 1969 1970 edid_buf = kmalloc(FOUR_BLOCK_SIZE, GFP_KERNEL); 1971 if (!edid_buf) 1972 return NULL; 1973 1974 pm_runtime_get_sync(dev); 1975 _anx7625_hpd_polling(ctx, 5000 * 100); 1976 edid_num = sp_tx_edid_read(ctx, edid_buf); 1977 pm_runtime_put_sync(dev); 1978 1979 if (edid_num < 1) { 1980 DRM_DEV_ERROR(dev, "Fail to read EDID: %d\n", edid_num); 1981 kfree(edid_buf); 1982 return NULL; 1983 } 1984 1985 ctx->cached_drm_edid = drm_edid_alloc(edid_buf, edid_num * ONE_BLOCK_SIZE); 1986 kfree(edid_buf); 1987 1988 out: 1989 return drm_edid_dup(ctx->cached_drm_edid); 1990 } 1991 1992 static enum drm_connector_status anx7625_sink_detect(struct anx7625_data *ctx) 1993 { 1994 struct device *dev = ctx->dev; 1995 1996 DRM_DEV_DEBUG_DRIVER(dev, "sink detect\n"); 1997 1998 return ctx->hpd_status ? connector_status_connected : 1999 connector_status_disconnected; 2000 } 2001 2002 static int anx7625_audio_hw_params(struct device *dev, void *data, 2003 struct hdmi_codec_daifmt *fmt, 2004 struct hdmi_codec_params *params) 2005 { 2006 struct anx7625_data *ctx = dev_get_drvdata(dev); 2007 int wl, ch, rate; 2008 int ret = 0; 2009 2010 if (anx7625_sink_detect(ctx) == connector_status_disconnected) { 2011 DRM_DEV_DEBUG_DRIVER(dev, "DP not connected\n"); 2012 return 0; 2013 } 2014 2015 if (fmt->fmt != HDMI_DSP_A && fmt->fmt != HDMI_I2S) { 2016 DRM_DEV_ERROR(dev, "only supports DSP_A & I2S\n"); 2017 return -EINVAL; 2018 } 2019 2020 DRM_DEV_DEBUG_DRIVER(dev, "setting %d Hz, %d bit, %d channels\n", 2021 params->sample_rate, params->sample_width, 2022 params->cea.channels); 2023 2024 if (fmt->fmt == HDMI_DSP_A) 2025 ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 2026 AUDIO_CHANNEL_STATUS_6, 2027 ~I2S_SLAVE_MODE, 2028 TDM_SLAVE_MODE); 2029 else 2030 ret = anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 2031 AUDIO_CHANNEL_STATUS_6, 2032 ~TDM_SLAVE_MODE, 2033 I2S_SLAVE_MODE); 2034 2035 /* Word length */ 2036 switch (params->sample_width) { 2037 case 16: 2038 wl = AUDIO_W_LEN_16_20MAX; 2039 break; 2040 case 18: 2041 wl = AUDIO_W_LEN_18_20MAX; 2042 break; 2043 case 20: 2044 wl = AUDIO_W_LEN_20_20MAX; 2045 break; 2046 case 24: 2047 wl = AUDIO_W_LEN_24_24MAX; 2048 break; 2049 default: 2050 DRM_DEV_DEBUG_DRIVER(dev, "wordlength: %d bit not support", 2051 params->sample_width); 2052 return -EINVAL; 2053 } 2054 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 2055 AUDIO_CHANNEL_STATUS_5, 2056 0xf0, wl); 2057 2058 /* Channel num */ 2059 switch (params->cea.channels) { 2060 case 2: 2061 ch = I2S_CH_2; 2062 break; 2063 case 4: 2064 ch = TDM_CH_4; 2065 break; 2066 case 6: 2067 ch = TDM_CH_6; 2068 break; 2069 case 8: 2070 ch = TDM_CH_8; 2071 break; 2072 default: 2073 DRM_DEV_DEBUG_DRIVER(dev, "channel number: %d not support", 2074 params->cea.channels); 2075 return -EINVAL; 2076 } 2077 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 2078 AUDIO_CHANNEL_STATUS_6, 0x1f, ch << 5); 2079 if (ch > I2S_CH_2) 2080 ret |= anx7625_write_or(ctx, ctx->i2c.tx_p2_client, 2081 AUDIO_CHANNEL_STATUS_6, AUDIO_LAYOUT); 2082 else 2083 ret |= anx7625_write_and(ctx, ctx->i2c.tx_p2_client, 2084 AUDIO_CHANNEL_STATUS_6, ~AUDIO_LAYOUT); 2085 2086 /* FS */ 2087 switch (params->sample_rate) { 2088 case 32000: 2089 rate = AUDIO_FS_32K; 2090 break; 2091 case 44100: 2092 rate = AUDIO_FS_441K; 2093 break; 2094 case 48000: 2095 rate = AUDIO_FS_48K; 2096 break; 2097 case 88200: 2098 rate = AUDIO_FS_882K; 2099 break; 2100 case 96000: 2101 rate = AUDIO_FS_96K; 2102 break; 2103 case 176400: 2104 rate = AUDIO_FS_1764K; 2105 break; 2106 case 192000: 2107 rate = AUDIO_FS_192K; 2108 break; 2109 default: 2110 DRM_DEV_DEBUG_DRIVER(dev, "sample rate: %d not support", 2111 params->sample_rate); 2112 return -EINVAL; 2113 } 2114 ret |= anx7625_write_and_or(ctx, ctx->i2c.tx_p2_client, 2115 AUDIO_CHANNEL_STATUS_4, 2116 0xf0, rate); 2117 ret |= anx7625_write_or(ctx, ctx->i2c.rx_p0_client, 2118 AP_AV_STATUS, AP_AUDIO_CHG); 2119 if (ret < 0) { 2120 DRM_DEV_ERROR(dev, "IO error : config audio.\n"); 2121 return -EIO; 2122 } 2123 2124 return 0; 2125 } 2126 2127 static void anx7625_audio_shutdown(struct device *dev, void *data) 2128 { 2129 DRM_DEV_DEBUG_DRIVER(dev, "stop audio\n"); 2130 } 2131 2132 static int anx7625_hdmi_i2s_get_dai_id(struct snd_soc_component *component, 2133 struct device_node *endpoint, 2134 void *data) 2135 { 2136 struct of_endpoint of_ep; 2137 int ret; 2138 2139 ret = of_graph_parse_endpoint(endpoint, &of_ep); 2140 if (ret < 0) 2141 return ret; 2142 2143 /* 2144 * HDMI sound should be located at external DPI port 2145 * Didn't have good way to check where is internal(DSI) 2146 * or external(DPI) bridge 2147 */ 2148 return 0; 2149 } 2150 2151 static void 2152 anx7625_audio_update_connector_status(struct anx7625_data *ctx, 2153 enum drm_connector_status status) 2154 { 2155 if (ctx->plugged_cb && ctx->codec_dev) { 2156 ctx->plugged_cb(ctx->codec_dev, 2157 status == connector_status_connected); 2158 } 2159 } 2160 2161 static int anx7625_audio_hook_plugged_cb(struct device *dev, void *data, 2162 hdmi_codec_plugged_cb fn, 2163 struct device *codec_dev) 2164 { 2165 struct anx7625_data *ctx = data; 2166 2167 ctx->plugged_cb = fn; 2168 ctx->codec_dev = codec_dev; 2169 anx7625_audio_update_connector_status(ctx, anx7625_sink_detect(ctx)); 2170 2171 return 0; 2172 } 2173 2174 static int anx7625_audio_get_eld(struct device *dev, void *data, 2175 u8 *buf, size_t len) 2176 { 2177 struct anx7625_data *ctx = dev_get_drvdata(dev); 2178 2179 if (!ctx->connector) { 2180 /* Pass en empty ELD if connector not available */ 2181 memset(buf, 0, len); 2182 } else { 2183 dev_dbg(dev, "audio copy eld\n"); 2184 mutex_lock(&ctx->connector->eld_mutex); 2185 memcpy(buf, ctx->connector->eld, 2186 min(sizeof(ctx->connector->eld), len)); 2187 mutex_unlock(&ctx->connector->eld_mutex); 2188 } 2189 2190 return 0; 2191 } 2192 2193 static const struct hdmi_codec_ops anx7625_codec_ops = { 2194 .hw_params = anx7625_audio_hw_params, 2195 .audio_shutdown = anx7625_audio_shutdown, 2196 .get_eld = anx7625_audio_get_eld, 2197 .get_dai_id = anx7625_hdmi_i2s_get_dai_id, 2198 .hook_plugged_cb = anx7625_audio_hook_plugged_cb, 2199 }; 2200 2201 static void anx7625_unregister_audio(struct anx7625_data *ctx) 2202 { 2203 struct device *dev = ctx->dev; 2204 2205 if (ctx->audio_pdev) { 2206 platform_device_unregister(ctx->audio_pdev); 2207 ctx->audio_pdev = NULL; 2208 } 2209 2210 DRM_DEV_DEBUG_DRIVER(dev, "unbound to %s", HDMI_CODEC_DRV_NAME); 2211 } 2212 2213 static int anx7625_register_audio(struct device *dev, struct anx7625_data *ctx) 2214 { 2215 struct hdmi_codec_pdata codec_data = { 2216 .ops = &anx7625_codec_ops, 2217 .max_i2s_channels = 8, 2218 .i2s = 1, 2219 .data = ctx, 2220 }; 2221 2222 ctx->audio_pdev = platform_device_register_data(dev, 2223 HDMI_CODEC_DRV_NAME, 2224 PLATFORM_DEVID_AUTO, 2225 &codec_data, 2226 sizeof(codec_data)); 2227 2228 if (IS_ERR(ctx->audio_pdev)) 2229 return PTR_ERR(ctx->audio_pdev); 2230 2231 DRM_DEV_DEBUG_DRIVER(dev, "bound to %s", HDMI_CODEC_DRV_NAME); 2232 2233 return 0; 2234 } 2235 2236 static int anx7625_setup_dsi_device(struct anx7625_data *ctx) 2237 { 2238 struct mipi_dsi_device *dsi; 2239 struct device *dev = ctx->dev; 2240 struct mipi_dsi_host *host; 2241 const struct mipi_dsi_device_info info = { 2242 .type = "anx7625", 2243 .channel = 0, 2244 .node = NULL, 2245 }; 2246 2247 host = of_find_mipi_dsi_host_by_node(ctx->pdata.mipi_host_node); 2248 if (!host) 2249 return dev_err_probe(dev, -EPROBE_DEFER, "fail to find dsi host.\n"); 2250 2251 dsi = devm_mipi_dsi_device_register_full(dev, host, &info); 2252 if (IS_ERR(dsi)) { 2253 DRM_DEV_ERROR(dev, "fail to create dsi device.\n"); 2254 return -EINVAL; 2255 } 2256 2257 dsi->lanes = ctx->pdata.mipi_lanes; 2258 dsi->format = MIPI_DSI_FMT_RGB888; 2259 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | 2260 MIPI_DSI_MODE_VIDEO_SYNC_PULSE | 2261 MIPI_DSI_MODE_VIDEO_HSE | 2262 MIPI_DSI_HS_PKT_END_ALIGNED; 2263 2264 ctx->dsi = dsi; 2265 2266 return 0; 2267 } 2268 2269 static int anx7625_attach_dsi(struct anx7625_data *ctx) 2270 { 2271 struct device *dev = ctx->dev; 2272 int ret; 2273 2274 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi\n"); 2275 2276 ret = devm_mipi_dsi_attach(dev, ctx->dsi); 2277 if (ret) { 2278 DRM_DEV_ERROR(dev, "fail to attach dsi to host.\n"); 2279 return ret; 2280 } 2281 2282 DRM_DEV_DEBUG_DRIVER(dev, "attach dsi succeeded.\n"); 2283 2284 return 0; 2285 } 2286 2287 static void hdcp_check_work_func(struct work_struct *work) 2288 { 2289 u8 status; 2290 struct delayed_work *dwork; 2291 struct anx7625_data *ctx; 2292 struct device *dev; 2293 struct drm_device *drm_dev; 2294 2295 dwork = to_delayed_work(work); 2296 ctx = container_of(dwork, struct anx7625_data, hdcp_work); 2297 dev = ctx->dev; 2298 2299 if (!ctx->connector) { 2300 dev_err(dev, "HDCP connector is null!"); 2301 return; 2302 } 2303 2304 drm_dev = ctx->connector->dev; 2305 drm_modeset_lock(&drm_dev->mode_config.connection_mutex, NULL); 2306 mutex_lock(&ctx->hdcp_wq_lock); 2307 2308 status = anx7625_reg_read(ctx, ctx->i2c.tx_p0_client, 0); 2309 dev_dbg(dev, "sink HDCP status check: %.02x\n", status); 2310 if (status & BIT(1)) { 2311 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_ENABLED; 2312 drm_hdcp_update_content_protection(ctx->connector, 2313 ctx->hdcp_cp); 2314 dev_dbg(dev, "update CP to ENABLE\n"); 2315 } 2316 2317 mutex_unlock(&ctx->hdcp_wq_lock); 2318 drm_modeset_unlock(&drm_dev->mode_config.connection_mutex); 2319 } 2320 2321 static int anx7625_bridge_attach(struct drm_bridge *bridge, 2322 struct drm_encoder *encoder, 2323 enum drm_bridge_attach_flags flags) 2324 { 2325 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2326 int err; 2327 struct device *dev = ctx->dev; 2328 2329 DRM_DEV_DEBUG_DRIVER(dev, "drm attach\n"); 2330 if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) 2331 return -EINVAL; 2332 2333 ctx->aux.drm_dev = bridge->dev; 2334 err = drm_dp_aux_register(&ctx->aux); 2335 if (err) { 2336 dev_err(dev, "failed to register aux channel: %d\n", err); 2337 return err; 2338 } 2339 2340 if (ctx->pdata.panel_bridge) { 2341 err = drm_bridge_attach(encoder, 2342 ctx->pdata.panel_bridge, 2343 &ctx->bridge, flags); 2344 if (err) 2345 return err; 2346 } 2347 2348 ctx->bridge_attached = 1; 2349 2350 return 0; 2351 } 2352 2353 static void anx7625_bridge_detach(struct drm_bridge *bridge) 2354 { 2355 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2356 2357 drm_dp_aux_unregister(&ctx->aux); 2358 } 2359 2360 static enum drm_mode_status 2361 anx7625_bridge_mode_valid(struct drm_bridge *bridge, 2362 const struct drm_display_info *info, 2363 const struct drm_display_mode *mode) 2364 { 2365 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2366 struct device *dev = ctx->dev; 2367 2368 DRM_DEV_DEBUG_DRIVER(dev, "drm mode checking\n"); 2369 2370 /* Max 1200p at 5.4 Ghz, one lane, pixel clock 300M */ 2371 if (mode->clock > SUPPORT_PIXEL_CLOCK) { 2372 DRM_DEV_DEBUG_DRIVER(dev, 2373 "drm mode invalid, pixelclock too high.\n"); 2374 return MODE_CLOCK_HIGH; 2375 } 2376 2377 DRM_DEV_DEBUG_DRIVER(dev, "drm mode valid.\n"); 2378 2379 return MODE_OK; 2380 } 2381 2382 static void anx7625_bridge_mode_set(struct drm_bridge *bridge, 2383 const struct drm_display_mode *old_mode, 2384 const struct drm_display_mode *mode) 2385 { 2386 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2387 struct device *dev = ctx->dev; 2388 2389 DRM_DEV_DEBUG_DRIVER(dev, "drm mode set\n"); 2390 2391 ctx->dt.pixelclock.min = mode->clock; 2392 ctx->dt.hactive.min = mode->hdisplay; 2393 ctx->dt.hsync_len.min = mode->hsync_end - mode->hsync_start; 2394 ctx->dt.hfront_porch.min = mode->hsync_start - mode->hdisplay; 2395 ctx->dt.hback_porch.min = mode->htotal - mode->hsync_end; 2396 ctx->dt.vactive.min = mode->vdisplay; 2397 ctx->dt.vsync_len.min = mode->vsync_end - mode->vsync_start; 2398 ctx->dt.vfront_porch.min = mode->vsync_start - mode->vdisplay; 2399 ctx->dt.vback_porch.min = mode->vtotal - mode->vsync_end; 2400 2401 ctx->display_timing_valid = 1; 2402 2403 DRM_DEV_DEBUG_DRIVER(dev, "pixelclock(%d).\n", ctx->dt.pixelclock.min); 2404 DRM_DEV_DEBUG_DRIVER(dev, "hactive(%d), hsync(%d), hfp(%d), hbp(%d)\n", 2405 ctx->dt.hactive.min, 2406 ctx->dt.hsync_len.min, 2407 ctx->dt.hfront_porch.min, 2408 ctx->dt.hback_porch.min); 2409 DRM_DEV_DEBUG_DRIVER(dev, "vactive(%d), vsync(%d), vfp(%d), vbp(%d)\n", 2410 ctx->dt.vactive.min, 2411 ctx->dt.vsync_len.min, 2412 ctx->dt.vfront_porch.min, 2413 ctx->dt.vback_porch.min); 2414 DRM_DEV_DEBUG_DRIVER(dev, "hdisplay(%d),hsync_start(%d).\n", 2415 mode->hdisplay, 2416 mode->hsync_start); 2417 DRM_DEV_DEBUG_DRIVER(dev, "hsync_end(%d),htotal(%d).\n", 2418 mode->hsync_end, 2419 mode->htotal); 2420 DRM_DEV_DEBUG_DRIVER(dev, "vdisplay(%d),vsync_start(%d).\n", 2421 mode->vdisplay, 2422 mode->vsync_start); 2423 DRM_DEV_DEBUG_DRIVER(dev, "vsync_end(%d),vtotal(%d).\n", 2424 mode->vsync_end, 2425 mode->vtotal); 2426 } 2427 2428 static bool anx7625_bridge_mode_fixup(struct drm_bridge *bridge, 2429 const struct drm_display_mode *mode, 2430 struct drm_display_mode *adj) 2431 { 2432 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2433 struct device *dev = ctx->dev; 2434 u32 hsync, hfp, hbp, hblanking; 2435 u32 adj_hsync, adj_hfp, adj_hbp, adj_hblanking, delta_adj; 2436 u32 vref, adj_clock; 2437 2438 DRM_DEV_DEBUG_DRIVER(dev, "drm mode fixup set\n"); 2439 2440 /* No need fixup for external monitor */ 2441 if (!ctx->pdata.panel_bridge) 2442 return true; 2443 2444 hsync = mode->hsync_end - mode->hsync_start; 2445 hfp = mode->hsync_start - mode->hdisplay; 2446 hbp = mode->htotal - mode->hsync_end; 2447 hblanking = mode->htotal - mode->hdisplay; 2448 2449 DRM_DEV_DEBUG_DRIVER(dev, "before mode fixup\n"); 2450 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2451 hsync, hfp, hbp, adj->clock); 2452 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2453 adj->hsync_start, adj->hsync_end, adj->htotal); 2454 2455 adj_hfp = hfp; 2456 adj_hsync = hsync; 2457 adj_hbp = hbp; 2458 adj_hblanking = hblanking; 2459 2460 /* HFP needs to be even */ 2461 if (hfp & 0x1) { 2462 adj_hfp += 1; 2463 adj_hblanking += 1; 2464 } 2465 2466 /* HBP needs to be even */ 2467 if (hbp & 0x1) { 2468 adj_hbp -= 1; 2469 adj_hblanking -= 1; 2470 } 2471 2472 /* HSYNC needs to be even */ 2473 if (hsync & 0x1) { 2474 if (adj_hblanking < hblanking) 2475 adj_hsync += 1; 2476 else 2477 adj_hsync -= 1; 2478 } 2479 2480 /* 2481 * Once illegal timing detected, use default HFP, HSYNC, HBP 2482 * This adjusting made for built-in eDP panel, for the externel 2483 * DP monitor, may need return false. 2484 */ 2485 if (hblanking < HBLANKING_MIN || (hfp < HP_MIN && hbp < HP_MIN)) { 2486 adj_hsync = SYNC_LEN_DEF; 2487 adj_hfp = HFP_HBP_DEF; 2488 adj_hbp = HFP_HBP_DEF; 2489 vref = adj->clock * 1000 / (adj->htotal * adj->vtotal); 2490 if (hblanking < HBLANKING_MIN) { 2491 delta_adj = HBLANKING_MIN - hblanking; 2492 adj_clock = vref * delta_adj * adj->vtotal; 2493 adj->clock += DIV_ROUND_UP(adj_clock, 1000); 2494 } else { 2495 delta_adj = hblanking - HBLANKING_MIN; 2496 adj_clock = vref * delta_adj * adj->vtotal; 2497 adj->clock -= DIV_ROUND_UP(adj_clock, 1000); 2498 } 2499 2500 DRM_WARN("illegal hblanking timing, use default.\n"); 2501 DRM_WARN("hfp(%d), hbp(%d), hsync(%d).\n", hfp, hbp, hsync); 2502 } else if (adj_hfp < HP_MIN) { 2503 /* Adjust hfp if hfp less than HP_MIN */ 2504 delta_adj = HP_MIN - adj_hfp; 2505 adj_hfp = HP_MIN; 2506 2507 /* 2508 * Balance total HBlanking pixel, if HBP does not have enough 2509 * space, adjust HSYNC length, otherwise adjust HBP 2510 */ 2511 if ((adj_hbp - delta_adj) < HP_MIN) 2512 /* HBP not enough space */ 2513 adj_hsync -= delta_adj; 2514 else 2515 adj_hbp -= delta_adj; 2516 } else if (adj_hbp < HP_MIN) { 2517 delta_adj = HP_MIN - adj_hbp; 2518 adj_hbp = HP_MIN; 2519 2520 /* 2521 * Balance total HBlanking pixel, if HBP hasn't enough space, 2522 * adjust HSYNC length, otherwize adjust HBP 2523 */ 2524 if ((adj_hfp - delta_adj) < HP_MIN) 2525 /* HFP not enough space */ 2526 adj_hsync -= delta_adj; 2527 else 2528 adj_hfp -= delta_adj; 2529 } 2530 2531 DRM_DEV_DEBUG_DRIVER(dev, "after mode fixup\n"); 2532 DRM_DEV_DEBUG_DRIVER(dev, "hsync(%d), hfp(%d), hbp(%d), clock(%d)\n", 2533 adj_hsync, adj_hfp, adj_hbp, adj->clock); 2534 2535 /* Reconstruct timing */ 2536 adj->hsync_start = adj->hdisplay + adj_hfp; 2537 adj->hsync_end = adj->hsync_start + adj_hsync; 2538 adj->htotal = adj->hsync_end + adj_hbp; 2539 DRM_DEV_DEBUG_DRIVER(dev, "hsync_start(%d), hsync_end(%d), htot(%d)\n", 2540 adj->hsync_start, adj->hsync_end, adj->htotal); 2541 2542 return true; 2543 } 2544 2545 static int anx7625_bridge_atomic_check(struct drm_bridge *bridge, 2546 struct drm_bridge_state *bridge_state, 2547 struct drm_crtc_state *crtc_state, 2548 struct drm_connector_state *conn_state) 2549 { 2550 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2551 struct device *dev = ctx->dev; 2552 2553 dev_dbg(dev, "drm bridge atomic check\n"); 2554 2555 anx7625_bridge_mode_fixup(bridge, &crtc_state->mode, 2556 &crtc_state->adjusted_mode); 2557 2558 return 0; 2559 } 2560 2561 static void anx7625_bridge_atomic_enable(struct drm_bridge *bridge, 2562 struct drm_atomic_state *state) 2563 { 2564 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2565 struct device *dev = ctx->dev; 2566 struct drm_connector *connector; 2567 struct drm_connector_state *conn_state; 2568 2569 dev_dbg(dev, "drm atomic enable\n"); 2570 2571 connector = drm_atomic_get_new_connector_for_encoder(state, 2572 bridge->encoder); 2573 if (!connector) 2574 return; 2575 2576 ctx->connector = connector; 2577 2578 pm_runtime_get_sync(dev); 2579 _anx7625_hpd_polling(ctx, 5000 * 100); 2580 2581 anx7625_dp_start(ctx); 2582 2583 conn_state = drm_atomic_get_new_connector_state(state, connector); 2584 2585 if (WARN_ON(!conn_state)) 2586 return; 2587 2588 if (conn_state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) { 2589 if (ctx->dp_en) { 2590 dev_dbg(dev, "enable HDCP\n"); 2591 anx7625_hdcp_enable(ctx); 2592 2593 queue_delayed_work(ctx->hdcp_workqueue, 2594 &ctx->hdcp_work, 2595 msecs_to_jiffies(2000)); 2596 } 2597 } 2598 } 2599 2600 static void anx7625_bridge_atomic_disable(struct drm_bridge *bridge, 2601 struct drm_atomic_state *state) 2602 { 2603 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2604 struct device *dev = ctx->dev; 2605 2606 dev_dbg(dev, "drm atomic disable\n"); 2607 2608 flush_workqueue(ctx->hdcp_workqueue); 2609 2610 if (ctx->connector && 2611 ctx->hdcp_cp == DRM_MODE_CONTENT_PROTECTION_ENABLED) { 2612 anx7625_hdcp_disable(ctx); 2613 ctx->hdcp_cp = DRM_MODE_CONTENT_PROTECTION_DESIRED; 2614 drm_hdcp_update_content_protection(ctx->connector, 2615 ctx->hdcp_cp); 2616 dev_dbg(dev, "update CP to DESIRE\n"); 2617 } 2618 2619 ctx->connector = NULL; 2620 anx7625_dp_stop(ctx); 2621 2622 mutex_lock(&ctx->aux_lock); 2623 pm_runtime_put_sync_suspend(dev); 2624 mutex_unlock(&ctx->aux_lock); 2625 } 2626 2627 static void 2628 anx7625_audio_update_connector_status(struct anx7625_data *ctx, 2629 enum drm_connector_status status); 2630 2631 static enum drm_connector_status 2632 anx7625_bridge_detect(struct drm_bridge *bridge, struct drm_connector *connector) 2633 { 2634 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2635 struct device *dev = ctx->dev; 2636 enum drm_connector_status status; 2637 2638 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge detect\n"); 2639 2640 status = anx7625_sink_detect(ctx); 2641 anx7625_audio_update_connector_status(ctx, status); 2642 return status; 2643 } 2644 2645 static const struct drm_edid *anx7625_bridge_edid_read(struct drm_bridge *bridge, 2646 struct drm_connector *connector) 2647 { 2648 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2649 struct device *dev = ctx->dev; 2650 2651 DRM_DEV_DEBUG_DRIVER(dev, "drm bridge get edid\n"); 2652 2653 return anx7625_edid_read(ctx); 2654 } 2655 2656 static void anx7625_bridge_hpd_enable(struct drm_bridge *bridge) 2657 { 2658 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2659 struct device *dev = ctx->dev; 2660 2661 pm_runtime_get_sync(dev); 2662 } 2663 2664 static void anx7625_bridge_hpd_disable(struct drm_bridge *bridge) 2665 { 2666 struct anx7625_data *ctx = bridge_to_anx7625(bridge); 2667 struct device *dev = ctx->dev; 2668 2669 pm_runtime_put_sync(dev); 2670 } 2671 2672 static const struct drm_bridge_funcs anx7625_bridge_funcs = { 2673 .attach = anx7625_bridge_attach, 2674 .detach = anx7625_bridge_detach, 2675 .mode_valid = anx7625_bridge_mode_valid, 2676 .mode_set = anx7625_bridge_mode_set, 2677 .atomic_check = anx7625_bridge_atomic_check, 2678 .atomic_enable = anx7625_bridge_atomic_enable, 2679 .atomic_disable = anx7625_bridge_atomic_disable, 2680 .atomic_duplicate_state = drm_atomic_helper_bridge_duplicate_state, 2681 .atomic_destroy_state = drm_atomic_helper_bridge_destroy_state, 2682 .atomic_reset = drm_atomic_helper_bridge_reset, 2683 .detect = anx7625_bridge_detect, 2684 .edid_read = anx7625_bridge_edid_read, 2685 .hpd_enable = anx7625_bridge_hpd_enable, 2686 .hpd_disable = anx7625_bridge_hpd_disable, 2687 }; 2688 2689 static int anx7625_register_i2c_dummy_clients(struct anx7625_data *ctx, 2690 struct i2c_client *client) 2691 { 2692 struct device *dev = ctx->dev; 2693 2694 ctx->i2c.tx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter, 2695 TX_P0_ADDR >> 1); 2696 if (IS_ERR(ctx->i2c.tx_p0_client)) 2697 return PTR_ERR(ctx->i2c.tx_p0_client); 2698 2699 ctx->i2c.tx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter, 2700 TX_P1_ADDR >> 1); 2701 if (IS_ERR(ctx->i2c.tx_p1_client)) 2702 return PTR_ERR(ctx->i2c.tx_p1_client); 2703 2704 ctx->i2c.tx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter, 2705 TX_P2_ADDR >> 1); 2706 if (IS_ERR(ctx->i2c.tx_p2_client)) 2707 return PTR_ERR(ctx->i2c.tx_p2_client); 2708 2709 ctx->i2c.rx_p0_client = devm_i2c_new_dummy_device(dev, client->adapter, 2710 RX_P0_ADDR >> 1); 2711 if (IS_ERR(ctx->i2c.rx_p0_client)) 2712 return PTR_ERR(ctx->i2c.rx_p0_client); 2713 2714 ctx->i2c.rx_p1_client = devm_i2c_new_dummy_device(dev, client->adapter, 2715 RX_P1_ADDR >> 1); 2716 if (IS_ERR(ctx->i2c.rx_p1_client)) 2717 return PTR_ERR(ctx->i2c.rx_p1_client); 2718 2719 ctx->i2c.rx_p2_client = devm_i2c_new_dummy_device(dev, client->adapter, 2720 RX_P2_ADDR >> 1); 2721 if (IS_ERR(ctx->i2c.rx_p2_client)) 2722 return PTR_ERR(ctx->i2c.rx_p2_client); 2723 2724 ctx->i2c.tcpc_client = devm_i2c_new_dummy_device(dev, client->adapter, 2725 TCPC_INTERFACE_ADDR >> 1); 2726 if (IS_ERR(ctx->i2c.tcpc_client)) 2727 return PTR_ERR(ctx->i2c.tcpc_client); 2728 2729 return 0; 2730 } 2731 2732 static int __maybe_unused anx7625_runtime_pm_suspend(struct device *dev) 2733 { 2734 struct anx7625_data *ctx = dev_get_drvdata(dev); 2735 2736 mutex_lock(&ctx->lock); 2737 2738 anx7625_stop_dp_work(ctx); 2739 if (!ctx->pdata.panel_bridge) 2740 anx7625_remove_edid(ctx); 2741 anx7625_power_standby(ctx); 2742 2743 mutex_unlock(&ctx->lock); 2744 2745 return 0; 2746 } 2747 2748 static int __maybe_unused anx7625_runtime_pm_resume(struct device *dev) 2749 { 2750 struct anx7625_data *ctx = dev_get_drvdata(dev); 2751 2752 mutex_lock(&ctx->lock); 2753 2754 anx7625_power_on_init(ctx); 2755 2756 mutex_unlock(&ctx->lock); 2757 2758 return 0; 2759 } 2760 2761 static const struct dev_pm_ops anx7625_pm_ops = { 2762 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 2763 pm_runtime_force_resume) 2764 SET_RUNTIME_PM_OPS(anx7625_runtime_pm_suspend, 2765 anx7625_runtime_pm_resume, NULL) 2766 }; 2767 2768 static int anx7625_link_bridge(struct drm_dp_aux *aux) 2769 { 2770 struct anx7625_data *platform = container_of(aux, struct anx7625_data, aux); 2771 struct device *dev = aux->dev; 2772 int ret; 2773 2774 ret = anx7625_parse_dt_panel(dev, &platform->pdata); 2775 if (ret) { 2776 DRM_DEV_ERROR(dev, "fail to parse DT for panel : %d\n", ret); 2777 return ret; 2778 } 2779 2780 platform->bridge.of_node = dev->of_node; 2781 if (!anx7625_of_panel_on_aux_bus(dev)) 2782 platform->bridge.ops |= DRM_BRIDGE_OP_EDID; 2783 if (!platform->pdata.panel_bridge || !anx7625_of_panel_on_aux_bus(dev)) 2784 platform->bridge.ops |= DRM_BRIDGE_OP_HPD | DRM_BRIDGE_OP_DETECT; 2785 platform->bridge.type = platform->pdata.panel_bridge ? 2786 DRM_MODE_CONNECTOR_eDP : 2787 DRM_MODE_CONNECTOR_DisplayPort; 2788 platform->bridge.support_hdcp = true; 2789 2790 drm_bridge_add(&platform->bridge); 2791 2792 if (!platform->pdata.is_dpi) { 2793 ret = anx7625_attach_dsi(platform); 2794 if (ret) 2795 drm_bridge_remove(&platform->bridge); 2796 } 2797 2798 return ret; 2799 } 2800 2801 static int anx7625_i2c_probe(struct i2c_client *client) 2802 { 2803 struct anx7625_data *platform; 2804 struct anx7625_platform_data *pdata; 2805 int ret = 0; 2806 struct device *dev = &client->dev; 2807 2808 if (!i2c_check_functionality(client->adapter, 2809 I2C_FUNC_SMBUS_I2C_BLOCK)) { 2810 DRM_DEV_ERROR(dev, "anx7625's i2c bus doesn't support\n"); 2811 return -ENODEV; 2812 } 2813 2814 platform = devm_drm_bridge_alloc(dev, struct anx7625_data, bridge, &anx7625_bridge_funcs); 2815 if (IS_ERR(platform)) { 2816 DRM_DEV_ERROR(dev, "fail to allocate driver data\n"); 2817 return PTR_ERR(platform); 2818 } 2819 2820 pdata = &platform->pdata; 2821 2822 platform->dev = &client->dev; 2823 i2c_set_clientdata(client, platform); 2824 2825 pdata->supplies[0].supply = "vdd10"; 2826 pdata->supplies[1].supply = "vdd18"; 2827 pdata->supplies[2].supply = "vdd33"; 2828 ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(pdata->supplies), 2829 pdata->supplies); 2830 if (ret) { 2831 DRM_DEV_ERROR(dev, "fail to get power supplies: %d\n", ret); 2832 return ret; 2833 } 2834 anx7625_init_gpio(platform); 2835 2836 mutex_init(&platform->lock); 2837 mutex_init(&platform->hdcp_wq_lock); 2838 mutex_init(&platform->aux_lock); 2839 2840 INIT_DELAYED_WORK(&platform->hdcp_work, hdcp_check_work_func); 2841 platform->hdcp_workqueue = create_workqueue("hdcp workqueue"); 2842 if (!platform->hdcp_workqueue) { 2843 dev_err(dev, "fail to create work queue\n"); 2844 ret = -ENOMEM; 2845 return ret; 2846 } 2847 2848 platform->pdata.intp_irq = client->irq; 2849 if (platform->pdata.intp_irq) { 2850 INIT_WORK(&platform->work, anx7625_work_func); 2851 platform->workqueue = alloc_workqueue("anx7625_work", 2852 WQ_FREEZABLE | WQ_MEM_RECLAIM, 1); 2853 if (!platform->workqueue) { 2854 DRM_DEV_ERROR(dev, "fail to create work queue\n"); 2855 ret = -ENOMEM; 2856 goto free_hdcp_wq; 2857 } 2858 2859 ret = devm_request_threaded_irq(dev, platform->pdata.intp_irq, 2860 NULL, anx7625_intr_hpd_isr, 2861 IRQF_TRIGGER_FALLING | 2862 IRQF_ONESHOT | IRQF_NO_AUTOEN, 2863 "anx7625-intp", platform); 2864 if (ret) { 2865 DRM_DEV_ERROR(dev, "fail to request irq\n"); 2866 goto free_wq; 2867 } 2868 } 2869 2870 platform->aux.name = "anx7625-aux"; 2871 platform->aux.dev = dev; 2872 platform->aux.transfer = anx7625_aux_transfer; 2873 platform->aux.wait_hpd_asserted = anx7625_wait_hpd_asserted; 2874 drm_dp_aux_init(&platform->aux); 2875 2876 ret = anx7625_parse_dt(dev, pdata); 2877 if (ret) { 2878 if (ret != -EPROBE_DEFER) 2879 DRM_DEV_ERROR(dev, "fail to parse DT : %d\n", ret); 2880 goto free_wq; 2881 } 2882 2883 if (!platform->pdata.is_dpi) { 2884 ret = anx7625_setup_dsi_device(platform); 2885 if (ret < 0) 2886 goto free_wq; 2887 } 2888 2889 /* 2890 * Registering the i2c devices will retrigger deferred probe, so it 2891 * needs to be done after calls that might return EPROBE_DEFER, 2892 * otherwise we can get an infinite loop. 2893 */ 2894 if (anx7625_register_i2c_dummy_clients(platform, client) != 0) { 2895 ret = -ENOMEM; 2896 DRM_DEV_ERROR(dev, "fail to reserve I2C bus.\n"); 2897 goto free_wq; 2898 } 2899 2900 pm_runtime_set_autosuspend_delay(dev, 1000); 2901 pm_runtime_use_autosuspend(dev); 2902 pm_suspend_ignore_children(dev, true); 2903 ret = devm_pm_runtime_enable(dev); 2904 if (ret) 2905 goto free_wq; 2906 2907 /* 2908 * Populating the aux bus will retrigger deferred probe, so it needs to 2909 * be done after calls that might return EPROBE_DEFER, otherwise we can 2910 * get an infinite loop. 2911 */ 2912 ret = devm_of_dp_aux_populate_bus(&platform->aux, anx7625_link_bridge); 2913 if (ret) { 2914 if (ret != -ENODEV) { 2915 DRM_DEV_ERROR(dev, "failed to populate aux bus : %d\n", ret); 2916 goto free_wq; 2917 } 2918 2919 ret = anx7625_link_bridge(&platform->aux); 2920 if (ret) 2921 goto free_wq; 2922 } 2923 2924 if (!platform->pdata.low_power_mode) { 2925 if (!anx7625_need_pd(platform)) 2926 anx7625_disable_pd_protocol(platform); 2927 2928 anx7625_configure_hpd(platform); 2929 2930 pm_runtime_get_sync(dev); 2931 _anx7625_hpd_polling(platform, 5000 * 100); 2932 } 2933 2934 if (platform->pdata.intp_irq) 2935 anx7625_reg_write(platform, platform->i2c.rx_p0_client, 2936 INTERFACE_CHANGE_INT_MASK, 0); 2937 2938 /* After getting runtime handle */ 2939 ret = anx7625_typec_register(platform); 2940 if (ret) 2941 goto pm_suspend; 2942 2943 /* Add work function */ 2944 if (platform->pdata.intp_irq) { 2945 enable_irq(platform->pdata.intp_irq); 2946 queue_work(platform->workqueue, &platform->work); 2947 } 2948 2949 if (platform->pdata.audio_en) 2950 anx7625_register_audio(dev, platform); 2951 2952 DRM_DEV_DEBUG_DRIVER(dev, "probe done\n"); 2953 2954 return 0; 2955 2956 pm_suspend: 2957 if (!platform->pdata.low_power_mode) 2958 pm_runtime_put_sync_suspend(&client->dev); 2959 2960 free_wq: 2961 if (platform->workqueue) 2962 destroy_workqueue(platform->workqueue); 2963 2964 free_hdcp_wq: 2965 if (platform->hdcp_workqueue) 2966 destroy_workqueue(platform->hdcp_workqueue); 2967 2968 return ret; 2969 } 2970 2971 static void anx7625_i2c_remove(struct i2c_client *client) 2972 { 2973 struct anx7625_data *platform = i2c_get_clientdata(client); 2974 2975 anx7625_typec_unregister(platform); 2976 2977 drm_bridge_remove(&platform->bridge); 2978 2979 if (platform->pdata.intp_irq) 2980 destroy_workqueue(platform->workqueue); 2981 2982 if (platform->hdcp_workqueue) { 2983 cancel_delayed_work(&platform->hdcp_work); 2984 destroy_workqueue(platform->hdcp_workqueue); 2985 } 2986 2987 if (!platform->pdata.low_power_mode) 2988 pm_runtime_put_sync_suspend(&client->dev); 2989 2990 if (platform->pdata.audio_en) 2991 anx7625_unregister_audio(platform); 2992 } 2993 2994 static const struct i2c_device_id anx7625_id[] = { 2995 { "anx7625" }, 2996 {} 2997 }; 2998 2999 MODULE_DEVICE_TABLE(i2c, anx7625_id); 3000 3001 static const struct of_device_id anx_match_table[] = { 3002 {.compatible = "analogix,anx7625",}, 3003 {}, 3004 }; 3005 MODULE_DEVICE_TABLE(of, anx_match_table); 3006 3007 static struct i2c_driver anx7625_driver = { 3008 .driver = { 3009 .name = "anx7625", 3010 .of_match_table = anx_match_table, 3011 .pm = &anx7625_pm_ops, 3012 }, 3013 .probe = anx7625_i2c_probe, 3014 .remove = anx7625_i2c_remove, 3015 3016 .id_table = anx7625_id, 3017 }; 3018 3019 module_i2c_driver(anx7625_driver); 3020 3021 MODULE_DESCRIPTION("MIPI2DP anx7625 driver"); 3022 MODULE_AUTHOR("Xin Ji <xji@analogixsemi.com>"); 3023 MODULE_LICENSE("GPL v2"); 3024 MODULE_VERSION(ANX7625_DRV_VERSION); 3025