1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Analogix DP (Display port) core register interface driver. 4 * 5 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 6 * Author: Jingoo Han <jg1.han@samsung.com> 7 */ 8 9 #include <linux/delay.h> 10 #include <linux/device.h> 11 #include <linux/gpio/consumer.h> 12 #include <linux/io.h> 13 #include <linux/iopoll.h> 14 15 #include <drm/bridge/analogix_dp.h> 16 17 #include "analogix_dp_core.h" 18 #include "analogix_dp_reg.h" 19 20 #define COMMON_INT_MASK_1 0 21 #define COMMON_INT_MASK_2 0 22 #define COMMON_INT_MASK_3 0 23 #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) 24 #define INT_STA_MASK INT_HPD 25 26 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable) 27 { 28 u32 reg; 29 30 if (enable) { 31 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 32 reg |= HDCP_VIDEO_MUTE; 33 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 34 } else { 35 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 36 reg &= ~HDCP_VIDEO_MUTE; 37 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 38 } 39 } 40 41 void analogix_dp_stop_video(struct analogix_dp_device *dp) 42 { 43 u32 reg; 44 45 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 46 reg &= ~VIDEO_EN; 47 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 48 } 49 50 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable) 51 { 52 u32 reg; 53 54 if (enable) 55 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | 56 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3; 57 else 58 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | 59 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; 60 61 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); 62 } 63 64 void analogix_dp_init_analog_param(struct analogix_dp_device *dp) 65 { 66 u32 reg; 67 68 reg = TX_TERMINAL_CTRL_50_OHM; 69 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); 70 71 reg = SEL_24M | TX_DVDD_BIT_1_0625V; 72 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); 73 74 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) { 75 reg = REF_CLK_24M; 76 if (dp->plat_data->dev_type == RK3288_DP) 77 reg ^= REF_CLK_MASK; 78 79 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_REG_1); 80 writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2); 81 writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3); 82 writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4); 83 writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5); 84 } 85 86 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; 87 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3); 88 89 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | 90 TX_CUR1_2X | TX_CUR_16_MA; 91 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1); 92 93 reg = CH3_AMP_400_MV | CH2_AMP_400_MV | 94 CH1_AMP_400_MV | CH0_AMP_400_MV; 95 writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL); 96 } 97 98 void analogix_dp_init_interrupt(struct analogix_dp_device *dp) 99 { 100 /* Set interrupt pin assertion polarity as high */ 101 writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL); 102 103 /* Clear pending regisers */ 104 writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); 105 writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2); 106 writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3); 107 writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); 108 writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA); 109 110 /* 0:mask,1: unmask */ 111 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); 112 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); 113 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); 114 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 115 writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 116 } 117 118 void analogix_dp_reset(struct analogix_dp_device *dp) 119 { 120 u32 reg; 121 122 analogix_dp_stop_video(dp); 123 analogix_dp_enable_video_mute(dp, 0); 124 125 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) 126 reg = RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N | 127 SW_FUNC_EN_N; 128 else 129 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | 130 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | 131 HDCP_FUNC_EN_N | SW_FUNC_EN_N; 132 133 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 134 135 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | 136 SERDES_FIFO_FUNC_EN_N | 137 LS_CLK_DOMAIN_FUNC_EN_N; 138 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 139 140 usleep_range(20, 30); 141 142 analogix_dp_lane_swap(dp, 0); 143 144 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 145 writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 146 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 147 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 148 149 writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 150 writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL); 151 152 writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L); 153 writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H); 154 155 writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL); 156 157 writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST); 158 159 writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD); 160 writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN); 161 162 writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH); 163 writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH); 164 165 writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 166 } 167 168 void analogix_dp_swreset(struct analogix_dp_device *dp) 169 { 170 writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET); 171 } 172 173 void analogix_dp_config_interrupt(struct analogix_dp_device *dp) 174 { 175 u32 reg; 176 177 /* 0: mask, 1: unmask */ 178 reg = COMMON_INT_MASK_1; 179 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); 180 181 reg = COMMON_INT_MASK_2; 182 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); 183 184 reg = COMMON_INT_MASK_3; 185 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); 186 187 reg = COMMON_INT_MASK_4; 188 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 189 190 reg = INT_STA_MASK; 191 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 192 } 193 194 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp) 195 { 196 u32 reg; 197 198 /* 0: mask, 1: unmask */ 199 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 200 reg &= ~COMMON_INT_MASK_4; 201 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 202 203 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 204 reg &= ~INT_STA_MASK; 205 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 206 } 207 208 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp) 209 { 210 u32 reg; 211 212 /* 0: mask, 1: unmask */ 213 reg = COMMON_INT_MASK_4; 214 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 215 216 reg = INT_STA_MASK; 217 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 218 } 219 220 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp) 221 { 222 u32 reg; 223 224 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); 225 if (reg & PLL_LOCK) 226 return PLL_LOCKED; 227 else 228 return PLL_UNLOCKED; 229 } 230 231 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable) 232 { 233 u32 reg; 234 u32 mask = DP_PLL_PD; 235 u32 pd_addr = ANALOGIX_DP_PLL_CTL; 236 237 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) { 238 pd_addr = ANALOGIX_DP_PD; 239 mask = RK_PLL_PD; 240 } 241 242 reg = readl(dp->reg_base + pd_addr); 243 if (enable) 244 reg |= mask; 245 else 246 reg &= ~mask; 247 writel(reg, dp->reg_base + pd_addr); 248 } 249 250 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 251 enum analog_power_block block, 252 bool enable) 253 { 254 u32 reg; 255 u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; 256 u32 mask; 257 258 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) 259 phy_pd_addr = ANALOGIX_DP_PD; 260 261 switch (block) { 262 case AUX_BLOCK: 263 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) 264 mask = RK_AUX_PD; 265 else 266 mask = AUX_PD; 267 268 reg = readl(dp->reg_base + phy_pd_addr); 269 if (enable) 270 reg |= mask; 271 else 272 reg &= ~mask; 273 writel(reg, dp->reg_base + phy_pd_addr); 274 break; 275 case CH0_BLOCK: 276 mask = CH0_PD; 277 reg = readl(dp->reg_base + phy_pd_addr); 278 279 if (enable) 280 reg |= mask; 281 else 282 reg &= ~mask; 283 writel(reg, dp->reg_base + phy_pd_addr); 284 break; 285 case CH1_BLOCK: 286 mask = CH1_PD; 287 reg = readl(dp->reg_base + phy_pd_addr); 288 289 if (enable) 290 reg |= mask; 291 else 292 reg &= ~mask; 293 writel(reg, dp->reg_base + phy_pd_addr); 294 break; 295 case CH2_BLOCK: 296 mask = CH2_PD; 297 reg = readl(dp->reg_base + phy_pd_addr); 298 299 if (enable) 300 reg |= mask; 301 else 302 reg &= ~mask; 303 writel(reg, dp->reg_base + phy_pd_addr); 304 break; 305 case CH3_BLOCK: 306 mask = CH3_PD; 307 reg = readl(dp->reg_base + phy_pd_addr); 308 309 if (enable) 310 reg |= mask; 311 else 312 reg &= ~mask; 313 writel(reg, dp->reg_base + phy_pd_addr); 314 break; 315 case ANALOG_TOTAL: 316 /* 317 * There is no bit named DP_PHY_PD, so We used DP_INC_BG 318 * to power off everything instead of DP_PHY_PD in 319 * Rockchip 320 */ 321 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) 322 mask = DP_INC_BG; 323 else 324 mask = DP_PHY_PD; 325 326 reg = readl(dp->reg_base + phy_pd_addr); 327 if (enable) 328 reg |= mask; 329 else 330 reg &= ~mask; 331 332 writel(reg, dp->reg_base + phy_pd_addr); 333 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) 334 usleep_range(10, 15); 335 break; 336 case POWER_ALL: 337 if (enable) { 338 reg = DP_ALL_PD; 339 writel(reg, dp->reg_base + phy_pd_addr); 340 } else { 341 reg = DP_ALL_PD; 342 writel(reg, dp->reg_base + phy_pd_addr); 343 usleep_range(10, 15); 344 reg &= ~DP_INC_BG; 345 writel(reg, dp->reg_base + phy_pd_addr); 346 usleep_range(10, 15); 347 348 writel(0x00, dp->reg_base + phy_pd_addr); 349 } 350 break; 351 default: 352 break; 353 } 354 } 355 356 int analogix_dp_init_analog_func(struct analogix_dp_device *dp) 357 { 358 u32 reg; 359 int timeout_loop = 0; 360 361 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 362 363 reg = PLL_LOCK_CHG; 364 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); 365 366 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); 367 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); 368 writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL); 369 370 /* Power up PLL */ 371 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 372 analogix_dp_set_pll_power_down(dp, 0); 373 374 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 375 timeout_loop++; 376 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { 377 dev_err(dp->dev, "failed to get pll lock status\n"); 378 return -ETIMEDOUT; 379 } 380 usleep_range(10, 20); 381 } 382 } 383 384 /* Enable Serdes FIFO function and Link symbol clock domain module */ 385 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 386 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N 387 | AUX_FUNC_EN_N); 388 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 389 return 0; 390 } 391 392 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp) 393 { 394 u32 reg; 395 396 if (dp->hpd_gpiod) 397 return; 398 399 reg = HOTPLUG_CHG | HPD_LOST | PLUG; 400 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); 401 402 reg = INT_HPD; 403 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); 404 } 405 406 void analogix_dp_init_hpd(struct analogix_dp_device *dp) 407 { 408 u32 reg; 409 410 if (dp->hpd_gpiod) 411 return; 412 413 analogix_dp_clear_hotplug_interrupts(dp); 414 415 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 416 reg &= ~(F_HPD | HPD_CTRL); 417 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 418 } 419 420 void analogix_dp_force_hpd(struct analogix_dp_device *dp) 421 { 422 u32 reg; 423 424 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 425 reg = (F_HPD | HPD_CTRL); 426 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 427 } 428 429 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp) 430 { 431 u32 reg; 432 433 if (dp->hpd_gpiod) { 434 reg = gpiod_get_value(dp->hpd_gpiod); 435 if (reg) 436 return DP_IRQ_TYPE_HP_CABLE_IN; 437 else 438 return DP_IRQ_TYPE_HP_CABLE_OUT; 439 } else { 440 /* Parse hotplug interrupt status register */ 441 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); 442 443 if (reg & PLUG) 444 return DP_IRQ_TYPE_HP_CABLE_IN; 445 446 if (reg & HPD_LOST) 447 return DP_IRQ_TYPE_HP_CABLE_OUT; 448 449 if (reg & HOTPLUG_CHG) 450 return DP_IRQ_TYPE_HP_CHANGE; 451 452 return DP_IRQ_TYPE_UNKNOWN; 453 } 454 } 455 456 void analogix_dp_reset_aux(struct analogix_dp_device *dp) 457 { 458 u32 reg; 459 460 /* Disable AUX channel module */ 461 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 462 reg |= AUX_FUNC_EN_N; 463 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 464 } 465 466 void analogix_dp_init_aux(struct analogix_dp_device *dp) 467 { 468 u32 reg; 469 470 /* Clear inerrupts related to AUX channel */ 471 reg = RPLY_RECEIV | AUX_ERR; 472 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); 473 474 analogix_dp_set_analog_power_down(dp, AUX_BLOCK, true); 475 usleep_range(10, 11); 476 analogix_dp_set_analog_power_down(dp, AUX_BLOCK, false); 477 478 analogix_dp_reset_aux(dp); 479 480 /* AUX_BIT_PERIOD_EXPECTED_DELAY doesn't apply to Rockchip IP */ 481 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) 482 reg = 0; 483 else 484 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3); 485 486 /* Disable AUX transaction H/W retry */ 487 reg |= AUX_HW_RETRY_COUNT_SEL(0) | 488 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 489 490 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL); 491 492 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ 493 reg = DEFER_CTRL_EN | DEFER_COUNT(1); 494 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL); 495 496 /* Enable AUX channel module */ 497 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 498 reg &= ~AUX_FUNC_EN_N; 499 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 500 } 501 502 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp) 503 { 504 u32 reg; 505 506 if (dp->hpd_gpiod) { 507 if (gpiod_get_value(dp->hpd_gpiod)) 508 return 0; 509 } else { 510 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 511 if (reg & HPD_STATUS) 512 return 0; 513 } 514 515 return -EINVAL; 516 } 517 518 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp) 519 { 520 u32 reg; 521 522 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 523 reg &= ~SW_FUNC_EN_N; 524 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 525 } 526 527 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) 528 { 529 u32 reg; 530 531 reg = bwtype; 532 if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62)) 533 writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET); 534 } 535 536 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) 537 { 538 u32 reg; 539 540 reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET); 541 *bwtype = reg; 542 } 543 544 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count) 545 { 546 u32 reg; 547 548 reg = count; 549 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); 550 } 551 552 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) 553 { 554 u32 reg; 555 556 reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); 557 *count = reg; 558 } 559 560 void analogix_dp_set_lane_link_training(struct analogix_dp_device *dp) 561 { 562 u8 lane; 563 564 for (lane = 0; lane < dp->link_train.lane_count; lane++) 565 writel(dp->link_train.training_lane[lane], 566 dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane); 567 } 568 569 u32 analogix_dp_get_lane_link_training(struct analogix_dp_device *dp, u8 lane) 570 { 571 return readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL + 4 * lane); 572 } 573 574 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 575 bool enable) 576 { 577 u32 reg; 578 579 if (enable) { 580 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 581 reg |= ENHANCED; 582 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 583 } else { 584 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 585 reg &= ~ENHANCED; 586 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 587 } 588 } 589 590 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 591 enum pattern_set pattern) 592 { 593 u32 reg; 594 595 switch (pattern) { 596 case PRBS7: 597 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; 598 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 599 break; 600 case D10_2: 601 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; 602 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 603 break; 604 case TRAINING_PTN1: 605 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; 606 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 607 break; 608 case TRAINING_PTN2: 609 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; 610 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 611 break; 612 case DP_NONE: 613 reg = SCRAMBLING_ENABLE | 614 LINK_QUAL_PATTERN_SET_DISABLE | 615 SW_TRAINING_PATTERN_SET_NORMAL; 616 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 617 break; 618 default: 619 break; 620 } 621 } 622 623 void analogix_dp_reset_macro(struct analogix_dp_device *dp) 624 { 625 u32 reg; 626 627 reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST); 628 reg |= MACRO_RST; 629 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); 630 631 /* 10 us is the minimum reset time. */ 632 usleep_range(10, 20); 633 634 reg &= ~MACRO_RST; 635 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); 636 } 637 638 void analogix_dp_init_video(struct analogix_dp_device *dp) 639 { 640 u32 reg; 641 642 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; 643 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); 644 645 reg = 0x0; 646 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 647 648 reg = CHA_CRI(4) | CHA_CTRL; 649 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 650 651 reg = 0x0; 652 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 653 654 reg = VID_HRES_TH(2) | VID_VRES_TH(0); 655 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8); 656 } 657 658 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp) 659 { 660 u32 reg; 661 662 /* Configure the input color depth, color space, dynamic range */ 663 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) | 664 (dp->video_info.color_depth << IN_BPC_SHIFT) | 665 (dp->video_info.color_space << IN_COLOR_F_SHIFT); 666 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2); 667 668 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ 669 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); 670 reg &= ~IN_YC_COEFFI_MASK; 671 if (dp->video_info.ycbcr_coeff) 672 reg |= IN_YC_COEFFI_ITU709; 673 else 674 reg |= IN_YC_COEFFI_ITU601; 675 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); 676 } 677 678 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp) 679 { 680 u32 reg; 681 682 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 683 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 684 685 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 686 687 if (!(reg & DET_STA)) { 688 dev_dbg(dp->dev, "Input stream clock not detected.\n"); 689 return -EINVAL; 690 } 691 692 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 693 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 694 695 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 696 dev_dbg(dp->dev, "wait SYS_CTL_2.\n"); 697 698 if (reg & CHA_STA) { 699 dev_dbg(dp->dev, "Input stream clk is changing\n"); 700 return -EINVAL; 701 } 702 703 return 0; 704 } 705 706 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 707 enum clock_recovery_m_value_type type, 708 u32 m_value, u32 n_value) 709 { 710 u32 reg; 711 712 if (type == REGISTER_M) { 713 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 714 reg |= FIX_M_VID; 715 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 716 reg = m_value & 0xff; 717 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0); 718 reg = (m_value >> 8) & 0xff; 719 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1); 720 reg = (m_value >> 16) & 0xff; 721 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2); 722 723 reg = n_value & 0xff; 724 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0); 725 reg = (n_value >> 8) & 0xff; 726 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1); 727 reg = (n_value >> 16) & 0xff; 728 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2); 729 } else { 730 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 731 reg &= ~FIX_M_VID; 732 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 733 734 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0); 735 writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1); 736 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2); 737 } 738 } 739 740 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type) 741 { 742 u32 reg; 743 744 if (type == VIDEO_TIMING_FROM_CAPTURE) { 745 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 746 reg &= ~FORMAT_SEL; 747 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 748 } else { 749 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 750 reg |= FORMAT_SEL; 751 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 752 } 753 } 754 755 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable) 756 { 757 u32 reg; 758 759 if (enable) { 760 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 761 reg &= ~VIDEO_MODE_MASK; 762 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; 763 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 764 } else { 765 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 766 reg &= ~VIDEO_MODE_MASK; 767 reg |= VIDEO_MODE_SLAVE_MODE; 768 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 769 } 770 } 771 772 void analogix_dp_start_video(struct analogix_dp_device *dp) 773 { 774 u32 reg; 775 776 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 777 reg |= VIDEO_EN; 778 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 779 } 780 781 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp) 782 { 783 u32 reg; 784 785 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 786 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 787 788 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 789 if (!(reg & STRM_VALID)) { 790 dev_dbg(dp->dev, "Input video stream is not detected.\n"); 791 return -EINVAL; 792 } 793 794 return 0; 795 } 796 797 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp) 798 { 799 u32 reg; 800 801 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 802 if (dp->plat_data && is_rockchip(dp->plat_data->dev_type)) { 803 reg &= ~(RK_VID_CAP_FUNC_EN_N | RK_VID_FIFO_FUNC_EN_N); 804 } else { 805 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); 806 reg |= MASTER_VID_FUNC_EN_N; 807 } 808 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 809 810 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 811 reg &= ~INTERACE_SCAN_CFG; 812 reg |= (dp->video_info.interlaced << 2); 813 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 814 815 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 816 reg &= ~VSYNC_POLARITY_CFG; 817 reg |= (dp->video_info.v_sync_polarity << 1); 818 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 819 820 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 821 reg &= ~HSYNC_POLARITY_CFG; 822 reg |= (dp->video_info.h_sync_polarity << 0); 823 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 824 825 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; 826 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 827 } 828 829 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp) 830 { 831 u32 reg; 832 833 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 834 reg &= ~SCRAMBLING_DISABLE; 835 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 836 } 837 838 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp) 839 { 840 u32 reg; 841 842 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 843 reg |= SCRAMBLING_DISABLE; 844 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 845 } 846 847 void analogix_dp_enable_psr_crc(struct analogix_dp_device *dp) 848 { 849 writel(PSR_VID_CRC_ENABLE, dp->reg_base + ANALOGIX_DP_CRC_CON); 850 } 851 852 static ssize_t analogix_dp_get_psr_status(struct analogix_dp_device *dp) 853 { 854 ssize_t val; 855 u8 status; 856 857 val = drm_dp_dpcd_readb(&dp->aux, DP_PSR_STATUS, &status); 858 if (val < 0) { 859 dev_err(dp->dev, "PSR_STATUS read failed ret=%zd", val); 860 return val; 861 } 862 return status; 863 } 864 865 int analogix_dp_send_psr_spd(struct analogix_dp_device *dp, 866 struct dp_sdp *vsc, bool blocking) 867 { 868 unsigned int val; 869 int ret; 870 ssize_t psr_status; 871 872 /* don't send info frame */ 873 val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 874 val &= ~IF_EN; 875 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 876 877 /* configure single frame update mode */ 878 writel(PSR_FRAME_UP_TYPE_BURST | PSR_CRC_SEL_HARDWARE, 879 dp->reg_base + ANALOGIX_DP_PSR_FRAME_UPDATE_CTRL); 880 881 /* configure VSC HB0~HB3 */ 882 writel(vsc->sdp_header.HB0, dp->reg_base + ANALOGIX_DP_SPD_HB0); 883 writel(vsc->sdp_header.HB1, dp->reg_base + ANALOGIX_DP_SPD_HB1); 884 writel(vsc->sdp_header.HB2, dp->reg_base + ANALOGIX_DP_SPD_HB2); 885 writel(vsc->sdp_header.HB3, dp->reg_base + ANALOGIX_DP_SPD_HB3); 886 887 /* configure reused VSC PB0~PB3, magic number from vendor */ 888 writel(0x00, dp->reg_base + ANALOGIX_DP_SPD_PB0); 889 writel(0x16, dp->reg_base + ANALOGIX_DP_SPD_PB1); 890 writel(0xCE, dp->reg_base + ANALOGIX_DP_SPD_PB2); 891 writel(0x5D, dp->reg_base + ANALOGIX_DP_SPD_PB3); 892 893 /* configure DB0 / DB1 values */ 894 writel(vsc->db[0], dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB0); 895 writel(vsc->db[1], dp->reg_base + ANALOGIX_DP_VSC_SHADOW_DB1); 896 897 /* set reuse spd inforframe */ 898 val = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); 899 val |= REUSE_SPD_EN; 900 writel(val, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); 901 902 /* mark info frame update */ 903 val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 904 val = (val | IF_UP) & ~IF_EN; 905 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 906 907 /* send info frame */ 908 val = readl(dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 909 val |= IF_EN; 910 writel(val, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 911 912 if (!blocking) 913 return 0; 914 915 /* 916 * db[1]!=0: entering PSR, wait for fully active remote frame buffer. 917 * db[1]==0: exiting PSR, wait for either 918 * (a) ACTIVE_RESYNC - the sink "must display the 919 * incoming active frames from the Source device with no visible 920 * glitches and/or artifacts", even though timings may still be 921 * re-synchronizing; or 922 * (b) INACTIVE - the transition is fully complete. 923 */ 924 ret = readx_poll_timeout(analogix_dp_get_psr_status, dp, psr_status, 925 psr_status >= 0 && 926 ((vsc->db[1] && psr_status == DP_PSR_SINK_ACTIVE_RFB) || 927 (!vsc->db[1] && (psr_status == DP_PSR_SINK_ACTIVE_RESYNC || 928 psr_status == DP_PSR_SINK_INACTIVE))), 929 1500, DP_TIMEOUT_PSR_LOOP_MS * 1000); 930 if (ret) { 931 dev_warn(dp->dev, "Failed to apply PSR %d\n", ret); 932 return ret; 933 } 934 return 0; 935 } 936 937 ssize_t analogix_dp_transfer(struct analogix_dp_device *dp, 938 struct drm_dp_aux_msg *msg) 939 { 940 u32 reg; 941 u32 status_reg; 942 u8 *buffer = msg->buffer; 943 unsigned int i; 944 int ret; 945 946 /* Buffer size of AUX CH is 16 bytes */ 947 if (WARN_ON(msg->size > 16)) 948 return -E2BIG; 949 950 /* Clear AUX CH data buffer */ 951 reg = BUF_CLR; 952 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); 953 954 switch (msg->request & ~DP_AUX_I2C_MOT) { 955 case DP_AUX_I2C_WRITE: 956 reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_I2C_TRANSACTION; 957 if (msg->request & DP_AUX_I2C_MOT) 958 reg |= AUX_TX_COMM_MOT; 959 break; 960 961 case DP_AUX_I2C_READ: 962 reg = AUX_TX_COMM_READ | AUX_TX_COMM_I2C_TRANSACTION; 963 if (msg->request & DP_AUX_I2C_MOT) 964 reg |= AUX_TX_COMM_MOT; 965 break; 966 967 case DP_AUX_NATIVE_WRITE: 968 reg = AUX_TX_COMM_WRITE | AUX_TX_COMM_DP_TRANSACTION; 969 break; 970 971 case DP_AUX_NATIVE_READ: 972 reg = AUX_TX_COMM_READ | AUX_TX_COMM_DP_TRANSACTION; 973 break; 974 975 default: 976 return -EINVAL; 977 } 978 979 reg |= AUX_LENGTH(msg->size); 980 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); 981 982 /* Select DPCD device address */ 983 reg = AUX_ADDR_7_0(msg->address); 984 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); 985 reg = AUX_ADDR_15_8(msg->address); 986 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); 987 reg = AUX_ADDR_19_16(msg->address); 988 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); 989 990 if (!(msg->request & DP_AUX_I2C_READ)) { 991 for (i = 0; i < msg->size; i++) { 992 reg = buffer[i]; 993 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + 994 4 * i); 995 } 996 } 997 998 /* Enable AUX CH operation */ 999 reg = AUX_EN; 1000 1001 /* Zero-sized messages specify address-only transactions. */ 1002 if (msg->size < 1) 1003 reg |= ADDR_ONLY; 1004 1005 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); 1006 1007 ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2, 1008 reg, !(reg & AUX_EN), 25, 500 * 1000); 1009 if (ret) { 1010 dev_err(dp->dev, "AUX CH enable timeout!\n"); 1011 goto aux_error; 1012 } 1013 1014 /* TODO: Wait for an interrupt instead of looping? */ 1015 /* Is AUX CH command reply received? */ 1016 ret = readx_poll_timeout(readl, dp->reg_base + ANALOGIX_DP_INT_STA, 1017 reg, reg & RPLY_RECEIV, 10, 20 * 1000); 1018 if (ret) { 1019 dev_err(dp->dev, "AUX CH cmd reply timeout!\n"); 1020 goto aux_error; 1021 } 1022 1023 /* Clear interrupt source for AUX CH command reply */ 1024 writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA); 1025 1026 /* Clear interrupt source for AUX CH access error */ 1027 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); 1028 status_reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA); 1029 if ((reg & AUX_ERR) || (status_reg & AUX_STATUS_MASK)) { 1030 writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA); 1031 1032 dev_warn(dp->dev, "AUX CH error happened: %#x (%d)\n", 1033 status_reg & AUX_STATUS_MASK, !!(reg & AUX_ERR)); 1034 goto aux_error; 1035 } 1036 1037 if (msg->request & DP_AUX_I2C_READ) { 1038 for (i = 0; i < msg->size; i++) { 1039 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 + 1040 4 * i); 1041 buffer[i] = (unsigned char)reg; 1042 } 1043 } 1044 1045 /* Check if Rx sends defer */ 1046 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM); 1047 if (reg == AUX_RX_COMM_AUX_DEFER) 1048 msg->reply = DP_AUX_NATIVE_REPLY_DEFER; 1049 else if (reg == AUX_RX_COMM_I2C_DEFER) 1050 msg->reply = DP_AUX_I2C_REPLY_DEFER; 1051 else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_WRITE || 1052 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_I2C_READ) 1053 msg->reply = DP_AUX_I2C_REPLY_ACK; 1054 else if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE || 1055 (msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_READ) 1056 msg->reply = DP_AUX_NATIVE_REPLY_ACK; 1057 1058 return msg->size; 1059 1060 aux_error: 1061 /* if aux err happen, reset aux */ 1062 analogix_dp_init_aux(dp); 1063 1064 return -EREMOTEIO; 1065 } 1066