1 /* 2 * Analogix DP (Display port) core register interface driver. 3 * 4 * Copyright (C) 2012 Samsung Electronics Co., Ltd. 5 * Author: Jingoo Han <jg1.han@samsung.com> 6 * 7 * This program is free software; you can redistribute it and/or modify it 8 * under the terms of the GNU General Public License as published by the 9 * Free Software Foundation; either version 2 of the License, or (at your 10 * option) any later version. 11 */ 12 13 #include <linux/device.h> 14 #include <linux/io.h> 15 #include <linux/delay.h> 16 #include <linux/gpio.h> 17 18 #include <drm/bridge/analogix_dp.h> 19 20 #include "analogix_dp_core.h" 21 #include "analogix_dp_reg.h" 22 23 #define COMMON_INT_MASK_1 0 24 #define COMMON_INT_MASK_2 0 25 #define COMMON_INT_MASK_3 0 26 #define COMMON_INT_MASK_4 (HOTPLUG_CHG | HPD_LOST | PLUG) 27 #define INT_STA_MASK INT_HPD 28 29 void analogix_dp_enable_video_mute(struct analogix_dp_device *dp, bool enable) 30 { 31 u32 reg; 32 33 if (enable) { 34 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 35 reg |= HDCP_VIDEO_MUTE; 36 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 37 } else { 38 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 39 reg &= ~HDCP_VIDEO_MUTE; 40 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 41 } 42 } 43 44 void analogix_dp_stop_video(struct analogix_dp_device *dp) 45 { 46 u32 reg; 47 48 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 49 reg &= ~VIDEO_EN; 50 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 51 } 52 53 void analogix_dp_lane_swap(struct analogix_dp_device *dp, bool enable) 54 { 55 u32 reg; 56 57 if (enable) 58 reg = LANE3_MAP_LOGIC_LANE_0 | LANE2_MAP_LOGIC_LANE_1 | 59 LANE1_MAP_LOGIC_LANE_2 | LANE0_MAP_LOGIC_LANE_3; 60 else 61 reg = LANE3_MAP_LOGIC_LANE_3 | LANE2_MAP_LOGIC_LANE_2 | 62 LANE1_MAP_LOGIC_LANE_1 | LANE0_MAP_LOGIC_LANE_0; 63 64 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_MAP); 65 } 66 67 void analogix_dp_init_analog_param(struct analogix_dp_device *dp) 68 { 69 u32 reg; 70 71 reg = TX_TERMINAL_CTRL_50_OHM; 72 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_1); 73 74 reg = SEL_24M | TX_DVDD_BIT_1_0625V; 75 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_2); 76 77 if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) { 78 writel(REF_CLK_24M, dp->reg_base + ANALOGIX_DP_PLL_REG_1); 79 writel(0x95, dp->reg_base + ANALOGIX_DP_PLL_REG_2); 80 writel(0x40, dp->reg_base + ANALOGIX_DP_PLL_REG_3); 81 writel(0x58, dp->reg_base + ANALOGIX_DP_PLL_REG_4); 82 writel(0x22, dp->reg_base + ANALOGIX_DP_PLL_REG_5); 83 } 84 85 reg = DRIVE_DVDD_BIT_1_0625V | VCO_BIT_600_MICRO; 86 writel(reg, dp->reg_base + ANALOGIX_DP_ANALOG_CTL_3); 87 88 reg = PD_RING_OSC | AUX_TERMINAL_CTRL_50_OHM | 89 TX_CUR1_2X | TX_CUR_16_MA; 90 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_FILTER_CTL_1); 91 92 reg = CH3_AMP_400_MV | CH2_AMP_400_MV | 93 CH1_AMP_400_MV | CH0_AMP_400_MV; 94 writel(reg, dp->reg_base + ANALOGIX_DP_TX_AMP_TUNING_CTL); 95 } 96 97 void analogix_dp_init_interrupt(struct analogix_dp_device *dp) 98 { 99 /* Set interrupt pin assertion polarity as high */ 100 writel(INT_POL1 | INT_POL0, dp->reg_base + ANALOGIX_DP_INT_CTL); 101 102 /* Clear pending regisers */ 103 writel(0xff, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); 104 writel(0x4f, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_2); 105 writel(0xe0, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_3); 106 writel(0xe7, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); 107 writel(0x63, dp->reg_base + ANALOGIX_DP_INT_STA); 108 109 /* 0:mask,1: unmask */ 110 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); 111 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); 112 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); 113 writel(0x00, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 114 writel(0x00, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 115 } 116 117 void analogix_dp_reset(struct analogix_dp_device *dp) 118 { 119 u32 reg; 120 121 analogix_dp_stop_video(dp); 122 analogix_dp_enable_video_mute(dp, 0); 123 124 reg = MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N | 125 AUD_FIFO_FUNC_EN_N | AUD_FUNC_EN_N | 126 HDCP_FUNC_EN_N | SW_FUNC_EN_N; 127 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 128 129 reg = SSC_FUNC_EN_N | AUX_FUNC_EN_N | 130 SERDES_FIFO_FUNC_EN_N | 131 LS_CLK_DOMAIN_FUNC_EN_N; 132 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 133 134 usleep_range(20, 30); 135 136 analogix_dp_lane_swap(dp, 0); 137 138 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 139 writel(0x40, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 140 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 141 writel(0x0, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 142 143 writel(0x0, dp->reg_base + ANALOGIX_DP_PKT_SEND_CTL); 144 writel(0x0, dp->reg_base + ANALOGIX_DP_HDCP_CTL); 145 146 writel(0x5e, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_L); 147 writel(0x1a, dp->reg_base + ANALOGIX_DP_HPD_DEGLITCH_H); 148 149 writel(0x10, dp->reg_base + ANALOGIX_DP_LINK_DEBUG_CTL); 150 151 writel(0x0, dp->reg_base + ANALOGIX_DP_PHY_TEST); 152 153 writel(0x0, dp->reg_base + ANALOGIX_DP_VIDEO_FIFO_THRD); 154 writel(0x20, dp->reg_base + ANALOGIX_DP_AUDIO_MARGIN); 155 156 writel(0x4, dp->reg_base + ANALOGIX_DP_M_VID_GEN_FILTER_TH); 157 writel(0x2, dp->reg_base + ANALOGIX_DP_M_AUD_GEN_FILTER_TH); 158 159 writel(0x00000101, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 160 } 161 162 void analogix_dp_swreset(struct analogix_dp_device *dp) 163 { 164 writel(RESET_DP_TX, dp->reg_base + ANALOGIX_DP_TX_SW_RESET); 165 } 166 167 void analogix_dp_config_interrupt(struct analogix_dp_device *dp) 168 { 169 u32 reg; 170 171 /* 0: mask, 1: unmask */ 172 reg = COMMON_INT_MASK_1; 173 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_1); 174 175 reg = COMMON_INT_MASK_2; 176 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_2); 177 178 reg = COMMON_INT_MASK_3; 179 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_3); 180 181 reg = COMMON_INT_MASK_4; 182 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 183 184 reg = INT_STA_MASK; 185 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 186 } 187 188 void analogix_dp_mute_hpd_interrupt(struct analogix_dp_device *dp) 189 { 190 u32 reg; 191 192 /* 0: mask, 1: unmask */ 193 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 194 reg &= ~COMMON_INT_MASK_4; 195 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 196 197 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 198 reg &= ~INT_STA_MASK; 199 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 200 } 201 202 void analogix_dp_unmute_hpd_interrupt(struct analogix_dp_device *dp) 203 { 204 u32 reg; 205 206 /* 0: mask, 1: unmask */ 207 reg = COMMON_INT_MASK_4; 208 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_MASK_4); 209 210 reg = INT_STA_MASK; 211 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA_MASK); 212 } 213 214 enum pll_status analogix_dp_get_pll_lock_status(struct analogix_dp_device *dp) 215 { 216 u32 reg; 217 218 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); 219 if (reg & PLL_LOCK) 220 return PLL_LOCKED; 221 else 222 return PLL_UNLOCKED; 223 } 224 225 void analogix_dp_set_pll_power_down(struct analogix_dp_device *dp, bool enable) 226 { 227 u32 reg; 228 229 if (enable) { 230 reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); 231 reg |= DP_PLL_PD; 232 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); 233 } else { 234 reg = readl(dp->reg_base + ANALOGIX_DP_PLL_CTL); 235 reg &= ~DP_PLL_PD; 236 writel(reg, dp->reg_base + ANALOGIX_DP_PLL_CTL); 237 } 238 } 239 240 void analogix_dp_set_analog_power_down(struct analogix_dp_device *dp, 241 enum analog_power_block block, 242 bool enable) 243 { 244 u32 reg; 245 u32 phy_pd_addr = ANALOGIX_DP_PHY_PD; 246 247 if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) 248 phy_pd_addr = ANALOGIX_DP_PD; 249 250 switch (block) { 251 case AUX_BLOCK: 252 if (enable) { 253 reg = readl(dp->reg_base + phy_pd_addr); 254 reg |= AUX_PD; 255 writel(reg, dp->reg_base + phy_pd_addr); 256 } else { 257 reg = readl(dp->reg_base + phy_pd_addr); 258 reg &= ~AUX_PD; 259 writel(reg, dp->reg_base + phy_pd_addr); 260 } 261 break; 262 case CH0_BLOCK: 263 if (enable) { 264 reg = readl(dp->reg_base + phy_pd_addr); 265 reg |= CH0_PD; 266 writel(reg, dp->reg_base + phy_pd_addr); 267 } else { 268 reg = readl(dp->reg_base + phy_pd_addr); 269 reg &= ~CH0_PD; 270 writel(reg, dp->reg_base + phy_pd_addr); 271 } 272 break; 273 case CH1_BLOCK: 274 if (enable) { 275 reg = readl(dp->reg_base + phy_pd_addr); 276 reg |= CH1_PD; 277 writel(reg, dp->reg_base + phy_pd_addr); 278 } else { 279 reg = readl(dp->reg_base + phy_pd_addr); 280 reg &= ~CH1_PD; 281 writel(reg, dp->reg_base + phy_pd_addr); 282 } 283 break; 284 case CH2_BLOCK: 285 if (enable) { 286 reg = readl(dp->reg_base + phy_pd_addr); 287 reg |= CH2_PD; 288 writel(reg, dp->reg_base + phy_pd_addr); 289 } else { 290 reg = readl(dp->reg_base + phy_pd_addr); 291 reg &= ~CH2_PD; 292 writel(reg, dp->reg_base + phy_pd_addr); 293 } 294 break; 295 case CH3_BLOCK: 296 if (enable) { 297 reg = readl(dp->reg_base + phy_pd_addr); 298 reg |= CH3_PD; 299 writel(reg, dp->reg_base + phy_pd_addr); 300 } else { 301 reg = readl(dp->reg_base + phy_pd_addr); 302 reg &= ~CH3_PD; 303 writel(reg, dp->reg_base + phy_pd_addr); 304 } 305 break; 306 case ANALOG_TOTAL: 307 if (enable) { 308 reg = readl(dp->reg_base + phy_pd_addr); 309 reg |= DP_PHY_PD; 310 writel(reg, dp->reg_base + phy_pd_addr); 311 } else { 312 reg = readl(dp->reg_base + phy_pd_addr); 313 reg &= ~DP_PHY_PD; 314 writel(reg, dp->reg_base + phy_pd_addr); 315 } 316 break; 317 case POWER_ALL: 318 if (enable) { 319 reg = DP_PHY_PD | AUX_PD | CH3_PD | CH2_PD | 320 CH1_PD | CH0_PD; 321 writel(reg, dp->reg_base + phy_pd_addr); 322 } else { 323 writel(0x00, dp->reg_base + phy_pd_addr); 324 } 325 break; 326 default: 327 break; 328 } 329 } 330 331 void analogix_dp_init_analog_func(struct analogix_dp_device *dp) 332 { 333 u32 reg; 334 int timeout_loop = 0; 335 336 analogix_dp_set_analog_power_down(dp, POWER_ALL, 0); 337 338 reg = PLL_LOCK_CHG; 339 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); 340 341 reg = readl(dp->reg_base + ANALOGIX_DP_DEBUG_CTL); 342 reg &= ~(F_PLL_LOCK | PLL_LOCK_CTRL); 343 writel(reg, dp->reg_base + ANALOGIX_DP_DEBUG_CTL); 344 345 /* Power up PLL */ 346 if (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 347 analogix_dp_set_pll_power_down(dp, 0); 348 349 while (analogix_dp_get_pll_lock_status(dp) == PLL_UNLOCKED) { 350 timeout_loop++; 351 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { 352 dev_err(dp->dev, "failed to get pll lock status\n"); 353 return; 354 } 355 usleep_range(10, 20); 356 } 357 } 358 359 /* Enable Serdes FIFO function and Link symbol clock domain module */ 360 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 361 reg &= ~(SERDES_FIFO_FUNC_EN_N | LS_CLK_DOMAIN_FUNC_EN_N 362 | AUX_FUNC_EN_N); 363 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 364 } 365 366 void analogix_dp_clear_hotplug_interrupts(struct analogix_dp_device *dp) 367 { 368 u32 reg; 369 370 if (gpio_is_valid(dp->hpd_gpio)) 371 return; 372 373 reg = HOTPLUG_CHG | HPD_LOST | PLUG; 374 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); 375 376 reg = INT_HPD; 377 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); 378 } 379 380 void analogix_dp_init_hpd(struct analogix_dp_device *dp) 381 { 382 u32 reg; 383 384 if (gpio_is_valid(dp->hpd_gpio)) 385 return; 386 387 analogix_dp_clear_hotplug_interrupts(dp); 388 389 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 390 reg &= ~(F_HPD | HPD_CTRL); 391 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 392 } 393 394 void analogix_dp_force_hpd(struct analogix_dp_device *dp) 395 { 396 u32 reg; 397 398 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 399 reg = (F_HPD | HPD_CTRL); 400 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 401 } 402 403 enum dp_irq_type analogix_dp_get_irq_type(struct analogix_dp_device *dp) 404 { 405 u32 reg; 406 407 if (gpio_is_valid(dp->hpd_gpio)) { 408 reg = gpio_get_value(dp->hpd_gpio); 409 if (reg) 410 return DP_IRQ_TYPE_HP_CABLE_IN; 411 else 412 return DP_IRQ_TYPE_HP_CABLE_OUT; 413 } else { 414 /* Parse hotplug interrupt status register */ 415 reg = readl(dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_4); 416 417 if (reg & PLUG) 418 return DP_IRQ_TYPE_HP_CABLE_IN; 419 420 if (reg & HPD_LOST) 421 return DP_IRQ_TYPE_HP_CABLE_OUT; 422 423 if (reg & HOTPLUG_CHG) 424 return DP_IRQ_TYPE_HP_CHANGE; 425 426 return DP_IRQ_TYPE_UNKNOWN; 427 } 428 } 429 430 void analogix_dp_reset_aux(struct analogix_dp_device *dp) 431 { 432 u32 reg; 433 434 /* Disable AUX channel module */ 435 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 436 reg |= AUX_FUNC_EN_N; 437 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 438 } 439 440 void analogix_dp_init_aux(struct analogix_dp_device *dp) 441 { 442 u32 reg; 443 444 /* Clear inerrupts related to AUX channel */ 445 reg = RPLY_RECEIV | AUX_ERR; 446 writel(reg, dp->reg_base + ANALOGIX_DP_INT_STA); 447 448 analogix_dp_reset_aux(dp); 449 450 /* Disable AUX transaction H/W retry */ 451 if (dp->plat_data && (dp->plat_data->dev_type == RK3288_DP)) 452 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(0) | 453 AUX_HW_RETRY_COUNT_SEL(3) | 454 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 455 else 456 reg = AUX_BIT_PERIOD_EXPECTED_DELAY(3) | 457 AUX_HW_RETRY_COUNT_SEL(0) | 458 AUX_HW_RETRY_INTERVAL_600_MICROSECONDS; 459 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_HW_RETRY_CTL); 460 461 /* Receive AUX Channel DEFER commands equal to DEFFER_COUNT*64 */ 462 reg = DEFER_CTRL_EN | DEFER_COUNT(1); 463 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_DEFER_CTL); 464 465 /* Enable AUX channel module */ 466 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 467 reg &= ~AUX_FUNC_EN_N; 468 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_2); 469 } 470 471 int analogix_dp_get_plug_in_status(struct analogix_dp_device *dp) 472 { 473 u32 reg; 474 475 if (gpio_is_valid(dp->hpd_gpio)) { 476 if (gpio_get_value(dp->hpd_gpio)) 477 return 0; 478 } else { 479 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 480 if (reg & HPD_STATUS) 481 return 0; 482 } 483 484 return -EINVAL; 485 } 486 487 void analogix_dp_enable_sw_function(struct analogix_dp_device *dp) 488 { 489 u32 reg; 490 491 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 492 reg &= ~SW_FUNC_EN_N; 493 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 494 } 495 496 int analogix_dp_start_aux_transaction(struct analogix_dp_device *dp) 497 { 498 int reg; 499 int retval = 0; 500 int timeout_loop = 0; 501 502 /* Enable AUX CH operation */ 503 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); 504 reg |= AUX_EN; 505 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); 506 507 /* Is AUX CH command reply received? */ 508 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); 509 while (!(reg & RPLY_RECEIV)) { 510 timeout_loop++; 511 if (DP_TIMEOUT_LOOP_COUNT < timeout_loop) { 512 dev_err(dp->dev, "AUX CH command reply failed!\n"); 513 return -ETIMEDOUT; 514 } 515 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); 516 usleep_range(10, 11); 517 } 518 519 /* Clear interrupt source for AUX CH command reply */ 520 writel(RPLY_RECEIV, dp->reg_base + ANALOGIX_DP_INT_STA); 521 522 /* Clear interrupt source for AUX CH access error */ 523 reg = readl(dp->reg_base + ANALOGIX_DP_INT_STA); 524 if (reg & AUX_ERR) { 525 writel(AUX_ERR, dp->reg_base + ANALOGIX_DP_INT_STA); 526 return -EREMOTEIO; 527 } 528 529 /* Check AUX CH error access status */ 530 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_STA); 531 if ((reg & AUX_STATUS_MASK) != 0) { 532 dev_err(dp->dev, "AUX CH error happens: %d\n\n", 533 reg & AUX_STATUS_MASK); 534 return -EREMOTEIO; 535 } 536 537 return retval; 538 } 539 540 int analogix_dp_write_byte_to_dpcd(struct analogix_dp_device *dp, 541 unsigned int reg_addr, 542 unsigned char data) 543 { 544 u32 reg; 545 int i; 546 int retval; 547 548 for (i = 0; i < 3; i++) { 549 /* Clear AUX CH data buffer */ 550 reg = BUF_CLR; 551 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); 552 553 /* Select DPCD device address */ 554 reg = AUX_ADDR_7_0(reg_addr); 555 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); 556 reg = AUX_ADDR_15_8(reg_addr); 557 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); 558 reg = AUX_ADDR_19_16(reg_addr); 559 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); 560 561 /* Write data buffer */ 562 reg = (unsigned int)data; 563 writel(reg, dp->reg_base + ANALOGIX_DP_BUF_DATA_0); 564 565 /* 566 * Set DisplayPort transaction and write 1 byte 567 * If bit 3 is 1, DisplayPort transaction. 568 * If Bit 3 is 0, I2C transaction. 569 */ 570 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 571 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); 572 573 /* Start AUX transaction */ 574 retval = analogix_dp_start_aux_transaction(dp); 575 if (retval == 0) 576 break; 577 578 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__); 579 } 580 581 return retval; 582 } 583 584 int analogix_dp_read_byte_from_dpcd(struct analogix_dp_device *dp, 585 unsigned int reg_addr, 586 unsigned char *data) 587 { 588 u32 reg; 589 int i; 590 int retval; 591 592 for (i = 0; i < 3; i++) { 593 /* Clear AUX CH data buffer */ 594 reg = BUF_CLR; 595 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); 596 597 /* Select DPCD device address */ 598 reg = AUX_ADDR_7_0(reg_addr); 599 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); 600 reg = AUX_ADDR_15_8(reg_addr); 601 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); 602 reg = AUX_ADDR_19_16(reg_addr); 603 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); 604 605 /* 606 * Set DisplayPort transaction and read 1 byte 607 * If bit 3 is 1, DisplayPort transaction. 608 * If Bit 3 is 0, I2C transaction. 609 */ 610 reg = AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 611 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); 612 613 /* Start AUX transaction */ 614 retval = analogix_dp_start_aux_transaction(dp); 615 if (retval == 0) 616 break; 617 618 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__); 619 } 620 621 /* Read data buffer */ 622 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0); 623 *data = (unsigned char)(reg & 0xff); 624 625 return retval; 626 } 627 628 int analogix_dp_write_bytes_to_dpcd(struct analogix_dp_device *dp, 629 unsigned int reg_addr, 630 unsigned int count, 631 unsigned char data[]) 632 { 633 u32 reg; 634 unsigned int start_offset; 635 unsigned int cur_data_count; 636 unsigned int cur_data_idx; 637 int i; 638 int retval = 0; 639 640 /* Clear AUX CH data buffer */ 641 reg = BUF_CLR; 642 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); 643 644 start_offset = 0; 645 while (start_offset < count) { 646 /* Buffer size of AUX CH is 16 * 4bytes */ 647 if ((count - start_offset) > 16) 648 cur_data_count = 16; 649 else 650 cur_data_count = count - start_offset; 651 652 for (i = 0; i < 3; i++) { 653 /* Select DPCD device address */ 654 reg = AUX_ADDR_7_0(reg_addr + start_offset); 655 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); 656 reg = AUX_ADDR_15_8(reg_addr + start_offset); 657 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); 658 reg = AUX_ADDR_19_16(reg_addr + start_offset); 659 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); 660 661 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 662 cur_data_idx++) { 663 reg = data[start_offset + cur_data_idx]; 664 writel(reg, dp->reg_base + 665 ANALOGIX_DP_BUF_DATA_0 + 666 4 * cur_data_idx); 667 } 668 669 /* 670 * Set DisplayPort transaction and write 671 * If bit 3 is 1, DisplayPort transaction. 672 * If Bit 3 is 0, I2C transaction. 673 */ 674 reg = AUX_LENGTH(cur_data_count) | 675 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_WRITE; 676 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); 677 678 /* Start AUX transaction */ 679 retval = analogix_dp_start_aux_transaction(dp); 680 if (retval == 0) 681 break; 682 683 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", 684 __func__); 685 } 686 687 start_offset += cur_data_count; 688 } 689 690 return retval; 691 } 692 693 int analogix_dp_read_bytes_from_dpcd(struct analogix_dp_device *dp, 694 unsigned int reg_addr, 695 unsigned int count, 696 unsigned char data[]) 697 { 698 u32 reg; 699 unsigned int start_offset; 700 unsigned int cur_data_count; 701 unsigned int cur_data_idx; 702 int i; 703 int retval = 0; 704 705 /* Clear AUX CH data buffer */ 706 reg = BUF_CLR; 707 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); 708 709 start_offset = 0; 710 while (start_offset < count) { 711 /* Buffer size of AUX CH is 16 * 4bytes */ 712 if ((count - start_offset) > 16) 713 cur_data_count = 16; 714 else 715 cur_data_count = count - start_offset; 716 717 /* AUX CH Request Transaction process */ 718 for (i = 0; i < 3; i++) { 719 /* Select DPCD device address */ 720 reg = AUX_ADDR_7_0(reg_addr + start_offset); 721 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); 722 reg = AUX_ADDR_15_8(reg_addr + start_offset); 723 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); 724 reg = AUX_ADDR_19_16(reg_addr + start_offset); 725 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); 726 727 /* 728 * Set DisplayPort transaction and read 729 * If bit 3 is 1, DisplayPort transaction. 730 * If Bit 3 is 0, I2C transaction. 731 */ 732 reg = AUX_LENGTH(cur_data_count) | 733 AUX_TX_COMM_DP_TRANSACTION | AUX_TX_COMM_READ; 734 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); 735 736 /* Start AUX transaction */ 737 retval = analogix_dp_start_aux_transaction(dp); 738 if (retval == 0) 739 break; 740 741 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", 742 __func__); 743 } 744 745 for (cur_data_idx = 0; cur_data_idx < cur_data_count; 746 cur_data_idx++) { 747 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 748 + 4 * cur_data_idx); 749 data[start_offset + cur_data_idx] = 750 (unsigned char)reg; 751 } 752 753 start_offset += cur_data_count; 754 } 755 756 return retval; 757 } 758 759 int analogix_dp_select_i2c_device(struct analogix_dp_device *dp, 760 unsigned int device_addr, 761 unsigned int reg_addr) 762 { 763 u32 reg; 764 int retval; 765 766 /* Set EDID device address */ 767 reg = device_addr; 768 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_ADDR_7_0); 769 writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_15_8); 770 writel(0x0, dp->reg_base + ANALOGIX_DP_AUX_ADDR_19_16); 771 772 /* Set offset from base address of EDID device */ 773 writel(reg_addr, dp->reg_base + ANALOGIX_DP_BUF_DATA_0); 774 775 /* 776 * Set I2C transaction and write address 777 * If bit 3 is 1, DisplayPort transaction. 778 * If Bit 3 is 0, I2C transaction. 779 */ 780 reg = AUX_TX_COMM_I2C_TRANSACTION | AUX_TX_COMM_MOT | 781 AUX_TX_COMM_WRITE; 782 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); 783 784 /* Start AUX transaction */ 785 retval = analogix_dp_start_aux_transaction(dp); 786 if (retval != 0) 787 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__); 788 789 return retval; 790 } 791 792 int analogix_dp_read_byte_from_i2c(struct analogix_dp_device *dp, 793 unsigned int device_addr, 794 unsigned int reg_addr, 795 unsigned int *data) 796 { 797 u32 reg; 798 int i; 799 int retval; 800 801 for (i = 0; i < 3; i++) { 802 /* Clear AUX CH data buffer */ 803 reg = BUF_CLR; 804 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); 805 806 /* Select EDID device */ 807 retval = analogix_dp_select_i2c_device(dp, device_addr, 808 reg_addr); 809 if (retval != 0) 810 continue; 811 812 /* 813 * Set I2C transaction and read data 814 * If bit 3 is 1, DisplayPort transaction. 815 * If Bit 3 is 0, I2C transaction. 816 */ 817 reg = AUX_TX_COMM_I2C_TRANSACTION | 818 AUX_TX_COMM_READ; 819 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_1); 820 821 /* Start AUX transaction */ 822 retval = analogix_dp_start_aux_transaction(dp); 823 if (retval == 0) 824 break; 825 826 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", __func__); 827 } 828 829 /* Read data */ 830 if (retval == 0) 831 *data = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0); 832 833 return retval; 834 } 835 836 int analogix_dp_read_bytes_from_i2c(struct analogix_dp_device *dp, 837 unsigned int device_addr, 838 unsigned int reg_addr, 839 unsigned int count, 840 unsigned char edid[]) 841 { 842 u32 reg; 843 unsigned int i, j; 844 unsigned int cur_data_idx; 845 unsigned int defer = 0; 846 int retval = 0; 847 848 for (i = 0; i < count; i += 16) { 849 for (j = 0; j < 3; j++) { 850 /* Clear AUX CH data buffer */ 851 reg = BUF_CLR; 852 writel(reg, dp->reg_base + ANALOGIX_DP_BUFFER_DATA_CTL); 853 854 /* Set normal AUX CH command */ 855 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); 856 reg &= ~ADDR_ONLY; 857 writel(reg, dp->reg_base + ANALOGIX_DP_AUX_CH_CTL_2); 858 859 /* 860 * If Rx sends defer, Tx sends only reads 861 * request without sending address 862 */ 863 if (!defer) 864 retval = analogix_dp_select_i2c_device(dp, 865 device_addr, reg_addr + i); 866 else 867 defer = 0; 868 869 if (retval == 0) { 870 /* 871 * Set I2C transaction and write data 872 * If bit 3 is 1, DisplayPort transaction. 873 * If Bit 3 is 0, I2C transaction. 874 */ 875 reg = AUX_LENGTH(16) | 876 AUX_TX_COMM_I2C_TRANSACTION | 877 AUX_TX_COMM_READ; 878 writel(reg, dp->reg_base + 879 ANALOGIX_DP_AUX_CH_CTL_1); 880 881 /* Start AUX transaction */ 882 retval = analogix_dp_start_aux_transaction(dp); 883 if (retval == 0) 884 break; 885 886 dev_dbg(dp->dev, "%s: Aux Transaction fail!\n", 887 __func__); 888 } 889 /* Check if Rx sends defer */ 890 reg = readl(dp->reg_base + ANALOGIX_DP_AUX_RX_COMM); 891 if (reg == AUX_RX_COMM_AUX_DEFER || 892 reg == AUX_RX_COMM_I2C_DEFER) { 893 dev_err(dp->dev, "Defer: %d\n\n", reg); 894 defer = 1; 895 } 896 } 897 898 for (cur_data_idx = 0; cur_data_idx < 16; cur_data_idx++) { 899 reg = readl(dp->reg_base + ANALOGIX_DP_BUF_DATA_0 900 + 4 * cur_data_idx); 901 edid[i + cur_data_idx] = (unsigned char)reg; 902 } 903 } 904 905 return retval; 906 } 907 908 void analogix_dp_set_link_bandwidth(struct analogix_dp_device *dp, u32 bwtype) 909 { 910 u32 reg; 911 912 reg = bwtype; 913 if ((bwtype == DP_LINK_BW_2_7) || (bwtype == DP_LINK_BW_1_62)) 914 writel(reg, dp->reg_base + ANALOGIX_DP_LINK_BW_SET); 915 } 916 917 void analogix_dp_get_link_bandwidth(struct analogix_dp_device *dp, u32 *bwtype) 918 { 919 u32 reg; 920 921 reg = readl(dp->reg_base + ANALOGIX_DP_LINK_BW_SET); 922 *bwtype = reg; 923 } 924 925 void analogix_dp_set_lane_count(struct analogix_dp_device *dp, u32 count) 926 { 927 u32 reg; 928 929 reg = count; 930 writel(reg, dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); 931 } 932 933 void analogix_dp_get_lane_count(struct analogix_dp_device *dp, u32 *count) 934 { 935 u32 reg; 936 937 reg = readl(dp->reg_base + ANALOGIX_DP_LANE_COUNT_SET); 938 *count = reg; 939 } 940 941 void analogix_dp_enable_enhanced_mode(struct analogix_dp_device *dp, 942 bool enable) 943 { 944 u32 reg; 945 946 if (enable) { 947 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 948 reg |= ENHANCED; 949 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 950 } else { 951 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 952 reg &= ~ENHANCED; 953 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 954 } 955 } 956 957 void analogix_dp_set_training_pattern(struct analogix_dp_device *dp, 958 enum pattern_set pattern) 959 { 960 u32 reg; 961 962 switch (pattern) { 963 case PRBS7: 964 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_PRBS7; 965 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 966 break; 967 case D10_2: 968 reg = SCRAMBLING_ENABLE | LINK_QUAL_PATTERN_SET_D10_2; 969 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 970 break; 971 case TRAINING_PTN1: 972 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN1; 973 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 974 break; 975 case TRAINING_PTN2: 976 reg = SCRAMBLING_DISABLE | SW_TRAINING_PATTERN_SET_PTN2; 977 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 978 break; 979 case DP_NONE: 980 reg = SCRAMBLING_ENABLE | 981 LINK_QUAL_PATTERN_SET_DISABLE | 982 SW_TRAINING_PATTERN_SET_NORMAL; 983 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 984 break; 985 default: 986 break; 987 } 988 } 989 990 void analogix_dp_set_lane0_pre_emphasis(struct analogix_dp_device *dp, 991 u32 level) 992 { 993 u32 reg; 994 995 reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 996 reg &= ~PRE_EMPHASIS_SET_MASK; 997 reg |= level << PRE_EMPHASIS_SET_SHIFT; 998 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 999 } 1000 1001 void analogix_dp_set_lane1_pre_emphasis(struct analogix_dp_device *dp, 1002 u32 level) 1003 { 1004 u32 reg; 1005 1006 reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 1007 reg &= ~PRE_EMPHASIS_SET_MASK; 1008 reg |= level << PRE_EMPHASIS_SET_SHIFT; 1009 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 1010 } 1011 1012 void analogix_dp_set_lane2_pre_emphasis(struct analogix_dp_device *dp, 1013 u32 level) 1014 { 1015 u32 reg; 1016 1017 reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 1018 reg &= ~PRE_EMPHASIS_SET_MASK; 1019 reg |= level << PRE_EMPHASIS_SET_SHIFT; 1020 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 1021 } 1022 1023 void analogix_dp_set_lane3_pre_emphasis(struct analogix_dp_device *dp, 1024 u32 level) 1025 { 1026 u32 reg; 1027 1028 reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 1029 reg &= ~PRE_EMPHASIS_SET_MASK; 1030 reg |= level << PRE_EMPHASIS_SET_SHIFT; 1031 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 1032 } 1033 1034 void analogix_dp_set_lane0_link_training(struct analogix_dp_device *dp, 1035 u32 training_lane) 1036 { 1037 u32 reg; 1038 1039 reg = training_lane; 1040 writel(reg, dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 1041 } 1042 1043 void analogix_dp_set_lane1_link_training(struct analogix_dp_device *dp, 1044 u32 training_lane) 1045 { 1046 u32 reg; 1047 1048 reg = training_lane; 1049 writel(reg, dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 1050 } 1051 1052 void analogix_dp_set_lane2_link_training(struct analogix_dp_device *dp, 1053 u32 training_lane) 1054 { 1055 u32 reg; 1056 1057 reg = training_lane; 1058 writel(reg, dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 1059 } 1060 1061 void analogix_dp_set_lane3_link_training(struct analogix_dp_device *dp, 1062 u32 training_lane) 1063 { 1064 u32 reg; 1065 1066 reg = training_lane; 1067 writel(reg, dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 1068 } 1069 1070 u32 analogix_dp_get_lane0_link_training(struct analogix_dp_device *dp) 1071 { 1072 u32 reg; 1073 1074 reg = readl(dp->reg_base + ANALOGIX_DP_LN0_LINK_TRAINING_CTL); 1075 return reg; 1076 } 1077 1078 u32 analogix_dp_get_lane1_link_training(struct analogix_dp_device *dp) 1079 { 1080 u32 reg; 1081 1082 reg = readl(dp->reg_base + ANALOGIX_DP_LN1_LINK_TRAINING_CTL); 1083 return reg; 1084 } 1085 1086 u32 analogix_dp_get_lane2_link_training(struct analogix_dp_device *dp) 1087 { 1088 u32 reg; 1089 1090 reg = readl(dp->reg_base + ANALOGIX_DP_LN2_LINK_TRAINING_CTL); 1091 return reg; 1092 } 1093 1094 u32 analogix_dp_get_lane3_link_training(struct analogix_dp_device *dp) 1095 { 1096 u32 reg; 1097 1098 reg = readl(dp->reg_base + ANALOGIX_DP_LN3_LINK_TRAINING_CTL); 1099 return reg; 1100 } 1101 1102 void analogix_dp_reset_macro(struct analogix_dp_device *dp) 1103 { 1104 u32 reg; 1105 1106 reg = readl(dp->reg_base + ANALOGIX_DP_PHY_TEST); 1107 reg |= MACRO_RST; 1108 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); 1109 1110 /* 10 us is the minimum reset time. */ 1111 usleep_range(10, 20); 1112 1113 reg &= ~MACRO_RST; 1114 writel(reg, dp->reg_base + ANALOGIX_DP_PHY_TEST); 1115 } 1116 1117 void analogix_dp_init_video(struct analogix_dp_device *dp) 1118 { 1119 u32 reg; 1120 1121 reg = VSYNC_DET | VID_FORMAT_CHG | VID_CLK_CHG; 1122 writel(reg, dp->reg_base + ANALOGIX_DP_COMMON_INT_STA_1); 1123 1124 reg = 0x0; 1125 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 1126 1127 reg = CHA_CRI(4) | CHA_CTRL; 1128 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 1129 1130 reg = 0x0; 1131 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 1132 1133 reg = VID_HRES_TH(2) | VID_VRES_TH(0); 1134 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_8); 1135 } 1136 1137 void analogix_dp_set_video_color_format(struct analogix_dp_device *dp) 1138 { 1139 u32 reg; 1140 1141 /* Configure the input color depth, color space, dynamic range */ 1142 reg = (dp->video_info.dynamic_range << IN_D_RANGE_SHIFT) | 1143 (dp->video_info.color_depth << IN_BPC_SHIFT) | 1144 (dp->video_info.color_space << IN_COLOR_F_SHIFT); 1145 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_2); 1146 1147 /* Set Input Color YCbCr Coefficients to ITU601 or ITU709 */ 1148 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); 1149 reg &= ~IN_YC_COEFFI_MASK; 1150 if (dp->video_info.ycbcr_coeff) 1151 reg |= IN_YC_COEFFI_ITU709; 1152 else 1153 reg |= IN_YC_COEFFI_ITU601; 1154 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_3); 1155 } 1156 1157 int analogix_dp_is_slave_video_stream_clock_on(struct analogix_dp_device *dp) 1158 { 1159 u32 reg; 1160 1161 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 1162 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 1163 1164 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_1); 1165 1166 if (!(reg & DET_STA)) { 1167 dev_dbg(dp->dev, "Input stream clock not detected.\n"); 1168 return -EINVAL; 1169 } 1170 1171 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 1172 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 1173 1174 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_2); 1175 dev_dbg(dp->dev, "wait SYS_CTL_2.\n"); 1176 1177 if (reg & CHA_STA) { 1178 dev_dbg(dp->dev, "Input stream clk is changing\n"); 1179 return -EINVAL; 1180 } 1181 1182 return 0; 1183 } 1184 1185 void analogix_dp_set_video_cr_mn(struct analogix_dp_device *dp, 1186 enum clock_recovery_m_value_type type, 1187 u32 m_value, u32 n_value) 1188 { 1189 u32 reg; 1190 1191 if (type == REGISTER_M) { 1192 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 1193 reg |= FIX_M_VID; 1194 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 1195 reg = m_value & 0xff; 1196 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_0); 1197 reg = (m_value >> 8) & 0xff; 1198 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_1); 1199 reg = (m_value >> 16) & 0xff; 1200 writel(reg, dp->reg_base + ANALOGIX_DP_M_VID_2); 1201 1202 reg = n_value & 0xff; 1203 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_0); 1204 reg = (n_value >> 8) & 0xff; 1205 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_1); 1206 reg = (n_value >> 16) & 0xff; 1207 writel(reg, dp->reg_base + ANALOGIX_DP_N_VID_2); 1208 } else { 1209 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 1210 reg &= ~FIX_M_VID; 1211 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_4); 1212 1213 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_0); 1214 writel(0x80, dp->reg_base + ANALOGIX_DP_N_VID_1); 1215 writel(0x00, dp->reg_base + ANALOGIX_DP_N_VID_2); 1216 } 1217 } 1218 1219 void analogix_dp_set_video_timing_mode(struct analogix_dp_device *dp, u32 type) 1220 { 1221 u32 reg; 1222 1223 if (type == VIDEO_TIMING_FROM_CAPTURE) { 1224 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1225 reg &= ~FORMAT_SEL; 1226 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1227 } else { 1228 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1229 reg |= FORMAT_SEL; 1230 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1231 } 1232 } 1233 1234 void analogix_dp_enable_video_master(struct analogix_dp_device *dp, bool enable) 1235 { 1236 u32 reg; 1237 1238 if (enable) { 1239 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 1240 reg &= ~VIDEO_MODE_MASK; 1241 reg |= VIDEO_MASTER_MODE_EN | VIDEO_MODE_MASTER_MODE; 1242 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 1243 } else { 1244 reg = readl(dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 1245 reg &= ~VIDEO_MODE_MASK; 1246 reg |= VIDEO_MODE_SLAVE_MODE; 1247 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 1248 } 1249 } 1250 1251 void analogix_dp_start_video(struct analogix_dp_device *dp) 1252 { 1253 u32 reg; 1254 1255 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 1256 reg |= VIDEO_EN; 1257 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_1); 1258 } 1259 1260 int analogix_dp_is_video_stream_on(struct analogix_dp_device *dp) 1261 { 1262 u32 reg; 1263 1264 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 1265 writel(reg, dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 1266 1267 reg = readl(dp->reg_base + ANALOGIX_DP_SYS_CTL_3); 1268 if (!(reg & STRM_VALID)) { 1269 dev_dbg(dp->dev, "Input video stream is not detected.\n"); 1270 return -EINVAL; 1271 } 1272 1273 return 0; 1274 } 1275 1276 void analogix_dp_config_video_slave_mode(struct analogix_dp_device *dp) 1277 { 1278 u32 reg; 1279 1280 reg = readl(dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 1281 reg &= ~(MASTER_VID_FUNC_EN_N | SLAVE_VID_FUNC_EN_N); 1282 reg |= MASTER_VID_FUNC_EN_N; 1283 writel(reg, dp->reg_base + ANALOGIX_DP_FUNC_EN_1); 1284 1285 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1286 reg &= ~INTERACE_SCAN_CFG; 1287 reg |= (dp->video_info.interlaced << 2); 1288 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1289 1290 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1291 reg &= ~VSYNC_POLARITY_CFG; 1292 reg |= (dp->video_info.v_sync_polarity << 1); 1293 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1294 1295 reg = readl(dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1296 reg &= ~HSYNC_POLARITY_CFG; 1297 reg |= (dp->video_info.h_sync_polarity << 0); 1298 writel(reg, dp->reg_base + ANALOGIX_DP_VIDEO_CTL_10); 1299 1300 reg = AUDIO_MODE_SPDIF_MODE | VIDEO_MODE_SLAVE_MODE; 1301 writel(reg, dp->reg_base + ANALOGIX_DP_SOC_GENERAL_CTL); 1302 } 1303 1304 void analogix_dp_enable_scrambling(struct analogix_dp_device *dp) 1305 { 1306 u32 reg; 1307 1308 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 1309 reg &= ~SCRAMBLING_DISABLE; 1310 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 1311 } 1312 1313 void analogix_dp_disable_scrambling(struct analogix_dp_device *dp) 1314 { 1315 u32 reg; 1316 1317 reg = readl(dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 1318 reg |= SCRAMBLING_DISABLE; 1319 writel(reg, dp->reg_base + ANALOGIX_DP_TRAINING_PTN_SET); 1320 } 1321