1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright(c) 2016, Analogix Semiconductor. 4 * 5 * Based on anx7808 driver obtained from chromeos with copyright: 6 * Copyright(c) 2013, Google Inc. 7 */ 8 #ifndef _ANALOGIX_I2C_DPTX_H_ 9 #define _ANALOGIX_I2C_DPTX_H_ 10 11 /***************************************************************/ 12 /* Register definitions for TX_P0 */ 13 /***************************************************************/ 14 15 /* HDCP Status Register */ 16 #define SP_TX_HDCP_STATUS_REG 0x00 17 #define SP_AUTH_FAIL BIT(5) 18 #define SP_AUTHEN_PASS BIT(1) 19 20 /* HDCP Control Register 0 */ 21 #define SP_HDCP_CTRL0_REG 0x01 22 #define SP_RX_REPEATER BIT(6) 23 #define SP_RE_AUTH BIT(5) 24 #define SP_SW_AUTH_OK BIT(4) 25 #define SP_HARD_AUTH_EN BIT(3) 26 #define SP_HDCP_ENC_EN BIT(2) 27 #define SP_BKSV_SRM_PASS BIT(1) 28 #define SP_KSVLIST_VLD BIT(0) 29 /* HDCP Function Enabled */ 30 #define SP_HDCP_FUNCTION_ENABLED (BIT(0) | BIT(1) | BIT(2) | BIT(3)) 31 32 /* HDCP Receiver BSTATUS Register 0 */ 33 #define SP_HDCP_RX_BSTATUS0_REG 0x1b 34 /* HDCP Receiver BSTATUS Register 1 */ 35 #define SP_HDCP_RX_BSTATUS1_REG 0x1c 36 37 /* HDCP Embedded "Blue Screen" Content Registers */ 38 #define SP_HDCP_VID0_BLUE_SCREEN_REG 0x2c 39 #define SP_HDCP_VID1_BLUE_SCREEN_REG 0x2d 40 #define SP_HDCP_VID2_BLUE_SCREEN_REG 0x2e 41 42 /* HDCP Wait R0 Timing Register */ 43 #define SP_HDCP_WAIT_R0_TIME_REG 0x40 44 45 /* HDCP Link Integrity Check Timer Register */ 46 #define SP_HDCP_LINK_CHECK_TIMER_REG 0x41 47 48 /* HDCP Repeater Ready Wait Timer Register */ 49 #define SP_HDCP_RPTR_RDY_WAIT_TIME_REG 0x42 50 51 /* HDCP Auto Timer Register */ 52 #define SP_HDCP_AUTO_TIMER_REG 0x51 53 54 /* HDCP Key Status Register */ 55 #define SP_HDCP_KEY_STATUS_REG 0x5e 56 57 /* HDCP Key Command Register */ 58 #define SP_HDCP_KEY_COMMAND_REG 0x5f 59 #define SP_DISABLE_SYNC_HDCP BIT(2) 60 61 /* OTP Memory Key Protection Registers */ 62 #define SP_OTP_KEY_PROTECT1_REG 0x60 63 #define SP_OTP_KEY_PROTECT2_REG 0x61 64 #define SP_OTP_KEY_PROTECT3_REG 0x62 65 #define SP_OTP_PSW1 0xa2 66 #define SP_OTP_PSW2 0x7e 67 #define SP_OTP_PSW3 0xc6 68 69 /* DP System Control Registers */ 70 #define SP_DP_SYSTEM_CTRL_BASE (0x80 - 1) 71 /* Bits for DP System Control Register 2 */ 72 #define SP_CHA_STA BIT(2) 73 /* Bits for DP System Control Register 3 */ 74 #define SP_HPD_STATUS BIT(6) 75 #define SP_HPD_FORCE BIT(5) 76 #define SP_HPD_CTRL BIT(4) 77 #define SP_STRM_VALID BIT(2) 78 #define SP_STRM_FORCE BIT(1) 79 #define SP_STRM_CTRL BIT(0) 80 /* Bits for DP System Control Register 4 */ 81 #define SP_ENHANCED_MODE BIT(3) 82 83 /* DP Video Control Register */ 84 #define SP_DP_VIDEO_CTRL_REG 0x84 85 #define SP_COLOR_F_MASK 0x06 86 #define SP_COLOR_F_SHIFT 1 87 #define SP_BPC_MASK 0xe0 88 #define SP_BPC_SHIFT 5 89 # define SP_BPC_6BITS 0x00 90 # define SP_BPC_8BITS 0x01 91 # define SP_BPC_10BITS 0x02 92 # define SP_BPC_12BITS 0x03 93 94 /* DP Audio Control Register */ 95 #define SP_DP_AUDIO_CTRL_REG 0x87 96 #define SP_AUD_EN BIT(0) 97 98 /* 10us Pulse Generate Timer Registers */ 99 #define SP_I2C_GEN_10US_TIMER0_REG 0x88 100 #define SP_I2C_GEN_10US_TIMER1_REG 0x89 101 102 /* Packet Send Control Register */ 103 #define SP_PACKET_SEND_CTRL_REG 0x90 104 #define SP_AUD_IF_UP BIT(7) 105 #define SP_AVI_IF_UD BIT(6) 106 #define SP_MPEG_IF_UD BIT(5) 107 #define SP_SPD_IF_UD BIT(4) 108 #define SP_AUD_IF_EN BIT(3) 109 #define SP_AVI_IF_EN BIT(2) 110 #define SP_MPEG_IF_EN BIT(1) 111 #define SP_SPD_IF_EN BIT(0) 112 113 /* DP HDCP Control Register */ 114 #define SP_DP_HDCP_CTRL_REG 0x92 115 #define SP_AUTO_EN BIT(7) 116 #define SP_AUTO_START BIT(5) 117 #define SP_LINK_POLLING BIT(1) 118 119 /* DP Main Link Bandwidth Setting Register */ 120 #define SP_DP_MAIN_LINK_BW_SET_REG 0xa0 121 #define SP_LINK_BW_SET_MASK 0x1f 122 #define SP_INITIAL_SLIM_M_AUD_SEL BIT(5) 123 124 /* DP Lane Count Setting Register */ 125 #define SP_DP_LANE_COUNT_SET_REG 0xa1 126 127 /* DP Training Pattern Set Register */ 128 #define SP_DP_TRAINING_PATTERN_SET_REG 0xa2 129 130 /* DP Lane 0 Link Training Control Register */ 131 #define SP_DP_LANE0_LT_CTRL_REG 0xa3 132 #define SP_TX_SW_SET_MASK 0x1b 133 #define SP_MAX_PRE_REACH BIT(5) 134 #define SP_MAX_DRIVE_REACH BIT(4) 135 #define SP_PRE_EMP_LEVEL1 BIT(3) 136 #define SP_DRVIE_CURRENT_LEVEL1 BIT(0) 137 138 /* DP Link Training Control Register */ 139 #define SP_DP_LT_CTRL_REG 0xa8 140 #define SP_DP_LT_INPROGRESS 0x80 141 #define SP_LT_ERROR_TYPE_MASK 0x70 142 # define SP_LT_NO_ERROR 0x00 143 # define SP_LT_AUX_WRITE_ERROR 0x01 144 # define SP_LT_MAX_DRIVE_REACHED 0x02 145 # define SP_LT_WRONG_LANE_COUNT_SET 0x03 146 # define SP_LT_LOOP_SAME_5_TIME 0x04 147 # define SP_LT_CR_FAIL_IN_EQ 0x05 148 # define SP_LT_EQ_LOOP_5_TIME 0x06 149 #define SP_LT_EN BIT(0) 150 151 /* DP CEP Training Control Registers */ 152 #define SP_DP_CEP_TRAINING_CTRL0_REG 0xa9 153 #define SP_DP_CEP_TRAINING_CTRL1_REG 0xaa 154 155 /* DP Debug Register 1 */ 156 #define SP_DP_DEBUG1_REG 0xb0 157 #define SP_DEBUG_PLL_LOCK BIT(4) 158 #define SP_POLLING_EN BIT(1) 159 160 /* DP Polling Control Register */ 161 #define SP_DP_POLLING_CTRL_REG 0xb4 162 #define SP_AUTO_POLLING_DISABLE BIT(0) 163 164 /* DP Link Debug Control Register */ 165 #define SP_DP_LINK_DEBUG_CTRL_REG 0xb8 166 #define SP_M_VID_DEBUG BIT(5) 167 #define SP_NEW_PRBS7 BIT(4) 168 #define SP_INSERT_ER BIT(1) 169 #define SP_PRBS31_EN BIT(0) 170 171 /* AUX Misc control Register */ 172 #define SP_AUX_MISC_CTRL_REG 0xbf 173 174 /* DP PLL control Register */ 175 #define SP_DP_PLL_CTRL_REG 0xc7 176 #define SP_PLL_RST BIT(6) 177 178 /* DP Analog Power Down Register */ 179 #define SP_DP_ANALOG_POWER_DOWN_REG 0xc8 180 #define SP_CH0_PD BIT(0) 181 182 /* DP Misc Control Register */ 183 #define SP_DP_MISC_CTRL_REG 0xcd 184 #define SP_EQ_TRAINING_LOOP BIT(6) 185 186 /* DP Extra I2C Device Address Register */ 187 #define SP_DP_EXTRA_I2C_DEV_ADDR_REG 0xce 188 #define SP_I2C_STRETCH_DISABLE BIT(7) 189 190 #define SP_I2C_EXTRA_ADDR 0x50 191 192 /* DP Downspread Control Register 1 */ 193 #define SP_DP_DOWNSPREAD_CTRL1_REG 0xd0 194 195 /* DP M Value Calculation Control Register */ 196 #define SP_DP_M_CALCULATION_CTRL_REG 0xd9 197 #define SP_M_GEN_CLK_SEL BIT(0) 198 199 /* AUX Channel Access Status Register */ 200 #define SP_AUX_CH_STATUS_REG 0xe0 201 #define SP_AUX_STATUS 0x0f 202 203 /* AUX Channel DEFER Control Register */ 204 #define SP_AUX_DEFER_CTRL_REG 0xe2 205 #define SP_DEFER_CTRL_EN BIT(7) 206 207 /* DP Buffer Data Count Register */ 208 #define SP_BUF_DATA_COUNT_REG 0xe4 209 #define SP_BUF_DATA_COUNT_MASK 0x1f 210 #define SP_BUF_CLR BIT(7) 211 212 /* DP AUX Channel Control Register 1 */ 213 #define SP_DP_AUX_CH_CTRL1_REG 0xe5 214 #define SP_AUX_TX_COMM_MASK 0x0f 215 #define SP_AUX_LENGTH_MASK 0xf0 216 #define SP_AUX_LENGTH_SHIFT 4 217 218 /* DP AUX CH Address Register 0 */ 219 #define SP_AUX_ADDR_7_0_REG 0xe6 220 221 /* DP AUX CH Address Register 1 */ 222 #define SP_AUX_ADDR_15_8_REG 0xe7 223 224 /* DP AUX CH Address Register 2 */ 225 #define SP_AUX_ADDR_19_16_REG 0xe8 226 #define SP_AUX_ADDR_19_16_MASK 0x0f 227 228 /* DP AUX Channel Control Register 2 */ 229 #define SP_DP_AUX_CH_CTRL2_REG 0xe9 230 #define SP_AUX_SEL_RXCM BIT(6) 231 #define SP_AUX_CHSEL BIT(3) 232 #define SP_AUX_PN_INV BIT(2) 233 #define SP_ADDR_ONLY BIT(1) 234 #define SP_AUX_EN BIT(0) 235 236 /* DP Video Stream Control InfoFrame Register */ 237 #define SP_DP_3D_VSC_CTRL_REG 0xea 238 #define SP_INFO_FRAME_VSC_EN BIT(0) 239 240 /* DP Video Stream Data Byte 1 Register */ 241 #define SP_DP_VSC_DB1_REG 0xeb 242 243 /* DP AUX Channel Control Register 3 */ 244 #define SP_DP_AUX_CH_CTRL3_REG 0xec 245 #define SP_WAIT_COUNTER_7_0_MASK 0xff 246 247 /* DP AUX Channel Control Register 4 */ 248 #define SP_DP_AUX_CH_CTRL4_REG 0xed 249 250 /* DP AUX Buffer Data Registers */ 251 #define SP_DP_BUF_DATA0_REG 0xf0 252 253 ssize_t anx_dp_aux_transfer(struct regmap *map_dptx, 254 struct drm_dp_aux_msg *msg); 255 256 #endif 257