1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2014 Traphandler 4 * Copyright (C) 2014 Free Electrons 5 * Copyright (C) 2014 Atmel 6 * 7 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com> 8 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> 9 */ 10 11 #ifndef DRM_ATMEL_HLCDC_H 12 #define DRM_ATMEL_HLCDC_H 13 14 #include <linux/regmap.h> 15 16 #include <drm/drm_plane.h> 17 18 /* LCD controller common registers */ 19 #define ATMEL_HLCDC_LAYER_CHER 0x0 20 #define ATMEL_HLCDC_LAYER_CHDR 0x4 21 #define ATMEL_HLCDC_LAYER_CHSR 0x8 22 #define ATMEL_HLCDC_LAYER_EN BIT(0) 23 #define ATMEL_HLCDC_LAYER_UPDATE BIT(1) 24 #define ATMEL_HLCDC_LAYER_A2Q BIT(2) 25 #define ATMEL_HLCDC_LAYER_RST BIT(8) 26 27 #define ATMEL_HLCDC_LAYER_IER 0xc 28 #define ATMEL_HLCDC_LAYER_IDR 0x10 29 #define ATMEL_HLCDC_LAYER_IMR 0x14 30 #define ATMEL_HLCDC_LAYER_ISR 0x18 31 #define ATMEL_HLCDC_LAYER_DFETCH BIT(0) 32 #define ATMEL_HLCDC_LAYER_LFETCH BIT(1) 33 #define ATMEL_HLCDC_LAYER_DMA_IRQ(p) BIT(2 + (8 * (p))) 34 #define ATMEL_HLCDC_LAYER_DSCR_IRQ(p) BIT(3 + (8 * (p))) 35 #define ATMEL_HLCDC_LAYER_ADD_IRQ(p) BIT(4 + (8 * (p))) 36 #define ATMEL_HLCDC_LAYER_DONE_IRQ(p) BIT(5 + (8 * (p))) 37 #define ATMEL_HLCDC_LAYER_OVR_IRQ(p) BIT(6 + (8 * (p))) 38 39 #define ATMEL_HLCDC_LAYER_PLANE_HEAD(p) (((p) * 0x10) + 0x1c) 40 #define ATMEL_HLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x10) + 0x20) 41 #define ATMEL_HLCDC_LAYER_PLANE_CTRL(p) (((p) * 0x10) + 0x24) 42 #define ATMEL_HLCDC_LAYER_PLANE_NEXT(p) (((p) * 0x10) + 0x28) 43 44 #define ATMEL_HLCDC_LAYER_DMA_CFG 0 45 #define ATMEL_HLCDC_LAYER_DMA_SIF BIT(0) 46 #define ATMEL_HLCDC_LAYER_DMA_BLEN_MASK GENMASK(5, 4) 47 #define ATMEL_HLCDC_LAYER_DMA_BLEN_SINGLE (0 << 4) 48 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR4 (1 << 4) 49 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR8 (2 << 4) 50 #define ATMEL_HLCDC_LAYER_DMA_BLEN_INCR16 (3 << 4) 51 #define ATMEL_HLCDC_LAYER_DMA_DLBO BIT(8) 52 #define ATMEL_HLCDC_LAYER_DMA_ROTDIS BIT(12) 53 #define ATMEL_HLCDC_LAYER_DMA_LOCKDIS BIT(13) 54 55 #define ATMEL_HLCDC_LAYER_FORMAT_CFG 1 56 #define ATMEL_HLCDC_LAYER_RGB (0 << 0) 57 #define ATMEL_HLCDC_LAYER_CLUT (1 << 0) 58 #define ATMEL_HLCDC_LAYER_YUV (2 << 0) 59 #define ATMEL_HLCDC_RGB_MODE(m) \ 60 (ATMEL_HLCDC_LAYER_RGB | (((m) & 0xf) << 4)) 61 #define ATMEL_HLCDC_CLUT_MODE(m) \ 62 (ATMEL_HLCDC_LAYER_CLUT | (((m) & 0x3) << 8)) 63 #define ATMEL_HLCDC_YUV_MODE(m) \ 64 (ATMEL_HLCDC_LAYER_YUV | (((m) & 0xf) << 12)) 65 #define ATMEL_HLCDC_YUV422ROT BIT(16) 66 #define ATMEL_HLCDC_YUV422SWP BIT(17) 67 #define ATMEL_HLCDC_DSCALEOPT BIT(20) 68 69 #define ATMEL_HLCDC_C1_MODE ATMEL_HLCDC_CLUT_MODE(0) 70 #define ATMEL_HLCDC_C2_MODE ATMEL_HLCDC_CLUT_MODE(1) 71 #define ATMEL_HLCDC_C4_MODE ATMEL_HLCDC_CLUT_MODE(2) 72 #define ATMEL_HLCDC_C8_MODE ATMEL_HLCDC_CLUT_MODE(3) 73 74 #define ATMEL_HLCDC_XRGB4444_MODE ATMEL_HLCDC_RGB_MODE(0) 75 #define ATMEL_HLCDC_ARGB4444_MODE ATMEL_HLCDC_RGB_MODE(1) 76 #define ATMEL_HLCDC_RGBA4444_MODE ATMEL_HLCDC_RGB_MODE(2) 77 #define ATMEL_HLCDC_RGB565_MODE ATMEL_HLCDC_RGB_MODE(3) 78 #define ATMEL_HLCDC_ARGB1555_MODE ATMEL_HLCDC_RGB_MODE(4) 79 #define ATMEL_HLCDC_XRGB8888_MODE ATMEL_HLCDC_RGB_MODE(9) 80 #define ATMEL_HLCDC_RGB888_MODE ATMEL_HLCDC_RGB_MODE(10) 81 #define ATMEL_HLCDC_ARGB8888_MODE ATMEL_HLCDC_RGB_MODE(12) 82 #define ATMEL_HLCDC_RGBA8888_MODE ATMEL_HLCDC_RGB_MODE(13) 83 84 #define ATMEL_HLCDC_AYUV_MODE ATMEL_HLCDC_YUV_MODE(0) 85 #define ATMEL_HLCDC_YUYV_MODE ATMEL_HLCDC_YUV_MODE(1) 86 #define ATMEL_HLCDC_UYVY_MODE ATMEL_HLCDC_YUV_MODE(2) 87 #define ATMEL_HLCDC_YVYU_MODE ATMEL_HLCDC_YUV_MODE(3) 88 #define ATMEL_HLCDC_VYUY_MODE ATMEL_HLCDC_YUV_MODE(4) 89 #define ATMEL_HLCDC_NV61_MODE ATMEL_HLCDC_YUV_MODE(5) 90 #define ATMEL_HLCDC_YUV422_MODE ATMEL_HLCDC_YUV_MODE(6) 91 #define ATMEL_HLCDC_NV21_MODE ATMEL_HLCDC_YUV_MODE(7) 92 #define ATMEL_HLCDC_YUV420_MODE ATMEL_HLCDC_YUV_MODE(8) 93 94 #define ATMEL_HLCDC_LAYER_POS(x, y) ((x) | ((y) << 16)) 95 #define ATMEL_HLCDC_LAYER_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16)) 96 97 #define ATMEL_HLCDC_LAYER_CRKEY BIT(0) 98 #define ATMEL_HLCDC_LAYER_INV BIT(1) 99 #define ATMEL_HLCDC_LAYER_ITER2BL BIT(2) 100 #define ATMEL_HLCDC_LAYER_ITER BIT(3) 101 #define ATMEL_HLCDC_LAYER_REVALPHA BIT(4) 102 #define ATMEL_HLCDC_LAYER_GAEN BIT(5) 103 #define ATMEL_HLCDC_LAYER_LAEN BIT(6) 104 #define ATMEL_HLCDC_LAYER_OVR BIT(7) 105 #define ATMEL_HLCDC_LAYER_DMA BIT(8) 106 #define ATMEL_HLCDC_LAYER_REP BIT(9) 107 #define ATMEL_HLCDC_LAYER_DSTKEY BIT(10) 108 #define ATMEL_HLCDC_LAYER_DISCEN BIT(11) 109 #define ATMEL_HLCDC_LAYER_GA_SHIFT 16 110 #define ATMEL_HLCDC_LAYER_GA_MASK \ 111 GENMASK(23, ATMEL_HLCDC_LAYER_GA_SHIFT) 112 #define ATMEL_HLCDC_LAYER_GA(x) \ 113 ((x) << ATMEL_HLCDC_LAYER_GA_SHIFT) 114 115 #define ATMEL_HLCDC_LAYER_DISC_POS(x, y) ((x) | ((y) << 16)) 116 #define ATMEL_HLCDC_LAYER_DISC_SIZE(w, h) (((w) - 1) | (((h) - 1) << 16)) 117 118 #define ATMEL_HLCDC_LAYER_SCALER_FACTORS(x, y) ((x) | ((y) << 16)) 119 #define ATMEL_HLCDC_LAYER_SCALER_ENABLE BIT(31) 120 121 #define ATMEL_HLCDC_LAYER_MAX_PLANES 3 122 123 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_RESERVED BIT(0) 124 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_LOADED BIT(1) 125 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_DONE BIT(2) 126 #define ATMEL_HLCDC_DMA_CHANNEL_DSCR_OVERRUN BIT(3) 127 128 #define ATMEL_HLCDC_CLUT_SIZE 256 129 130 #define ATMEL_HLCDC_MAX_LAYERS 6 131 132 /* XLCDC controller specific registers */ 133 #define ATMEL_XLCDC_LAYER_ENR 0x10 134 #define ATMEL_XLCDC_LAYER_EN BIT(0) 135 136 #define ATMEL_XLCDC_LAYER_IER 0x0 137 #define ATMEL_XLCDC_LAYER_IDR 0x4 138 #define ATMEL_XLCDC_LAYER_ISR 0xc 139 #define ATMEL_XLCDC_LAYER_OVR_IRQ(p) BIT(2 + (8 * (p))) 140 141 #define ATMEL_XLCDC_LAYER_PLANE_ADDR(p) (((p) * 0x4) + 0x18) 142 143 #define ATMEL_XLCDC_LAYER_DMA_CFG 0 144 145 #define ATMEL_XLCDC_LAYER_DMA BIT(0) 146 #define ATMEL_XLCDC_LAYER_REP BIT(1) 147 #define ATMEL_XLCDC_LAYER_DISCEN BIT(4) 148 149 #define ATMEL_XLCDC_LAYER_SFACTC_A0_MULT_AS (4 << 6) 150 #define ATMEL_XLCDC_LAYER_SFACTA_ONE BIT(9) 151 #define ATMEL_XLCDC_LAYER_DFACTC_M_A0_MULT_AS (6 << 11) 152 #define ATMEL_XLCDC_LAYER_DFACTA_ONE BIT(14) 153 154 #define ATMEL_XLCDC_LAYER_A0_SHIFT 16 155 #define ATMEL_XLCDC_LAYER_A0(x) \ 156 ((x) << ATMEL_XLCDC_LAYER_A0_SHIFT) 157 158 #define ATMEL_XLCDC_LAYER_VSCALER_LUMA_ENABLE BIT(0) 159 #define ATMEL_XLCDC_LAYER_VSCALER_CHROMA_ENABLE BIT(1) 160 #define ATMEL_XLCDC_LAYER_HSCALER_LUMA_ENABLE BIT(4) 161 #define ATMEL_XLCDC_LAYER_HSCALER_CHROMA_ENABLE BIT(5) 162 163 #define ATMEL_XLCDC_LAYER_VXSYCFG_ONE BIT(0) 164 #define ATMEL_XLCDC_LAYER_VXSYTAP2_ENABLE BIT(4) 165 #define ATMEL_XLCDC_LAYER_VXSCCFG_ONE BIT(16) 166 #define ATMEL_XLCDC_LAYER_VXSCTAP2_ENABLE BIT(20) 167 168 #define ATMEL_XLCDC_LAYER_HXSYCFG_ONE BIT(0) 169 #define ATMEL_XLCDC_LAYER_HXSYTAP2_ENABLE BIT(4) 170 #define ATMEL_XLCDC_LAYER_HXSCCFG_ONE BIT(16) 171 #define ATMEL_XLCDC_LAYER_HXSCTAP2_ENABLE BIT(20) 172 173 /** 174 * Atmel HLCDC Layer registers layout structure 175 * 176 * Each HLCDC layer has its own register organization and a given register 177 * can be placed differently on 2 different layers depending on its 178 * capabilities. 179 * This structure stores common registers layout for a given layer and is 180 * used by HLCDC layer code to choose the appropriate register to write to 181 * or to read from. 182 * 183 * For all fields, a value of zero means "unsupported". 184 * 185 * See Atmel's datasheet for a detailled description of these registers. 186 * 187 * @xstride: xstride registers 188 * @pstride: pstride registers 189 * @pos: position register 190 * @size: displayed size register 191 * @memsize: memory size register 192 * @default_color: default color register 193 * @chroma_key: chroma key register 194 * @chroma_key_mask: chroma key mask register 195 * @general_config: general layer config register 196 * @sacler_config: scaler factors register 197 * @phicoeffs: X/Y PHI coefficient registers 198 * @disc_pos: discard area position register 199 * @disc_size: discard area size register 200 * @csc: color space conversion register 201 * @vxs_config: vertical scalar filter taps control register 202 * @hxs_config: horizontal scalar filter taps control register 203 */ 204 struct atmel_hlcdc_layer_cfg_layout { 205 int xstride[ATMEL_HLCDC_LAYER_MAX_PLANES]; 206 int pstride[ATMEL_HLCDC_LAYER_MAX_PLANES]; 207 int pos; 208 int size; 209 int memsize; 210 int default_color; 211 int chroma_key; 212 int chroma_key_mask; 213 int general_config; 214 int scaler_config; 215 struct { 216 int x; 217 int y; 218 } phicoeffs; 219 int disc_pos; 220 int disc_size; 221 int csc; 222 int vxs_config; 223 int hxs_config; 224 }; 225 226 /** 227 * Atmel HLCDC DMA descriptor structure 228 * 229 * This structure is used by the HLCDC DMA engine to schedule a DMA transfer. 230 * 231 * The structure fields must remain in this specific order, because they're 232 * used by the HLCDC DMA engine, which expect them in this order. 233 * HLCDC DMA descriptors must be aligned on 64 bits. 234 * 235 * @addr: buffer DMA address 236 * @ctrl: DMA transfer options 237 * @next: next DMA descriptor to fetch 238 * @self: descriptor DMA address 239 */ 240 struct atmel_hlcdc_dma_channel_dscr { 241 dma_addr_t addr; 242 u32 ctrl; 243 dma_addr_t next; 244 dma_addr_t self; 245 } __aligned(sizeof(u64)); 246 247 /** 248 * Atmel HLCDC layer types 249 */ 250 enum atmel_hlcdc_layer_type { 251 ATMEL_HLCDC_NO_LAYER, 252 ATMEL_HLCDC_BASE_LAYER, 253 ATMEL_HLCDC_OVERLAY_LAYER, 254 ATMEL_HLCDC_CURSOR_LAYER, 255 ATMEL_HLCDC_PP_LAYER, 256 }; 257 258 /** 259 * Atmel HLCDC Supported formats structure 260 * 261 * This structure list all the formats supported by a given layer. 262 * 263 * @nformats: number of supported formats 264 * @formats: supported formats 265 */ 266 struct atmel_hlcdc_formats { 267 int nformats; 268 u32 *formats; 269 }; 270 271 /** 272 * Atmel HLCDC Layer description structure 273 * 274 * This structure describes the capabilities provided by a given layer. 275 * 276 * @name: layer name 277 * @type: layer type 278 * @id: layer id 279 * @regs_offset: offset of the layer registers from the HLCDC registers base 280 * @cfgs_offset: CFGX registers offset from the layer registers base 281 * @formats: supported formats 282 * @layout: config registers layout 283 * @max_width: maximum width supported by this layer (0 means unlimited) 284 * @max_height: maximum height supported by this layer (0 means unlimited) 285 */ 286 struct atmel_hlcdc_layer_desc { 287 const char *name; 288 enum atmel_hlcdc_layer_type type; 289 int id; 290 int regs_offset; 291 int cfgs_offset; 292 int clut_offset; 293 struct atmel_hlcdc_formats *formats; 294 struct atmel_hlcdc_layer_cfg_layout layout; 295 int max_width; 296 int max_height; 297 }; 298 299 /** 300 * Atmel HLCDC Layer. 301 * 302 * A layer can be a DRM plane of a post processing layer used to render 303 * HLCDC composition into memory. 304 * 305 * @desc: layer description 306 * @regmap: pointer to the HLCDC regmap 307 */ 308 struct atmel_hlcdc_layer { 309 const struct atmel_hlcdc_layer_desc *desc; 310 struct regmap *regmap; 311 }; 312 313 /** 314 * Atmel HLCDC Plane. 315 * 316 * @base: base DRM plane structure 317 * @layer: HLCDC layer structure 318 * @properties: pointer to the property definitions structure 319 */ 320 struct atmel_hlcdc_plane { 321 struct drm_plane base; 322 struct atmel_hlcdc_layer layer; 323 }; 324 325 static inline struct atmel_hlcdc_plane * 326 drm_plane_to_atmel_hlcdc_plane(struct drm_plane *p) 327 { 328 return container_of(p, struct atmel_hlcdc_plane, base); 329 } 330 331 static inline struct atmel_hlcdc_plane * 332 atmel_hlcdc_layer_to_plane(struct atmel_hlcdc_layer *layer) 333 { 334 return container_of(layer, struct atmel_hlcdc_plane, layer); 335 } 336 337 /** 338 * struct atmel_hlcdc_dc - Atmel HLCDC Display Controller. 339 * @desc: HLCDC Display Controller description 340 * @dscrpool: DMA coherent pool used to allocate DMA descriptors 341 * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device 342 * @crtc: CRTC provided by the display controller 343 * @layers: active HLCDC layers 344 * @suspend: used to store the HLCDC state when entering suspend 345 * @suspend.imr: used to read/write LCDC Interrupt Mask Register 346 * @suspend.state: Atomic commit structure 347 */ 348 struct atmel_hlcdc_dc { 349 const struct atmel_hlcdc_dc_desc *desc; 350 struct dma_pool *dscrpool; 351 struct atmel_hlcdc *hlcdc; 352 struct drm_crtc *crtc; 353 struct atmel_hlcdc_layer *layers[ATMEL_HLCDC_MAX_LAYERS]; 354 struct { 355 u32 imr; 356 struct drm_atomic_state *state; 357 } suspend; 358 }; 359 360 struct atmel_hlcdc_plane_state; 361 362 /** 363 * struct atmel_lcdc_dc_ops - describes atmel_lcdc ops group 364 * to differentiate HLCDC and XLCDC IP code support 365 * @plane_setup_scaler: update the vertical and horizontal scaling factors 366 * @update_lcdc_buffers: update the each LCDC layers DMA registers 367 * @lcdc_atomic_disable: disable LCDC interrupts and layers 368 * @lcdc_update_general_settings: update each LCDC layers general 369 * configuration register 370 * @lcdc_atomic_update: enable the LCDC layers and interrupts 371 * @lcdc_csc_init: update the color space conversion co-efficient of 372 * High-end overlay register 373 * @lcdc_irq_dbg: to raise alert incase of interrupt overrun in any LCDC layer 374 */ 375 struct atmel_lcdc_dc_ops { 376 void (*plane_setup_scaler)(struct atmel_hlcdc_plane *plane, 377 struct atmel_hlcdc_plane_state *state); 378 void (*lcdc_update_buffers)(struct atmel_hlcdc_plane *plane, 379 struct atmel_hlcdc_plane_state *state, 380 u32 sr, int i); 381 void (*lcdc_atomic_disable)(struct atmel_hlcdc_plane *plane); 382 void (*lcdc_update_general_settings)(struct atmel_hlcdc_plane *plane, 383 struct atmel_hlcdc_plane_state *state); 384 void (*lcdc_atomic_update)(struct atmel_hlcdc_plane *plane, 385 struct atmel_hlcdc_dc *dc); 386 void (*lcdc_csc_init)(struct atmel_hlcdc_plane *plane, 387 const struct atmel_hlcdc_layer_desc *desc); 388 void (*lcdc_irq_dbg)(struct atmel_hlcdc_plane *plane, 389 const struct atmel_hlcdc_layer_desc *desc); 390 }; 391 392 extern const struct atmel_lcdc_dc_ops atmel_hlcdc_ops; 393 extern const struct atmel_lcdc_dc_ops atmel_xlcdc_ops; 394 395 /** 396 * Atmel HLCDC Display Controller description structure. 397 * 398 * This structure describes the HLCDC IP capabilities and depends on the 399 * HLCDC IP version (or Atmel SoC family). 400 * 401 * @min_width: minimum width supported by the Display Controller 402 * @min_height: minimum height supported by the Display Controller 403 * @max_width: maximum width supported by the Display Controller 404 * @max_height: maximum height supported by the Display Controller 405 * @max_spw: maximum vertical/horizontal pulse width 406 * @max_vpw: maximum vertical back/front porch width 407 * @max_hpw: maximum horizontal back/front porch width 408 * @conflicting_output_formats: true if RGBXXX output formats conflict with 409 * each other. 410 * @fixed_clksrc: true if clock source is fixed 411 * @is_xlcdc: true if XLCDC IP is supported 412 * @layers: a layer description table describing available layers 413 * @nlayers: layer description table size 414 * @ops: atmel lcdc dc ops 415 */ 416 struct atmel_hlcdc_dc_desc { 417 int min_width; 418 int min_height; 419 int max_width; 420 int max_height; 421 int max_spw; 422 int max_vpw; 423 int max_hpw; 424 bool conflicting_output_formats; 425 bool fixed_clksrc; 426 bool is_xlcdc; 427 const struct atmel_hlcdc_layer_desc *layers; 428 int nlayers; 429 const struct atmel_lcdc_dc_ops *ops; 430 }; 431 432 extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_formats; 433 extern struct atmel_hlcdc_formats atmel_hlcdc_plane_rgb_and_yuv_formats; 434 435 static inline void atmel_hlcdc_layer_write_reg(struct atmel_hlcdc_layer *layer, 436 unsigned int reg, u32 val) 437 { 438 regmap_write(layer->regmap, layer->desc->regs_offset + reg, val); 439 } 440 441 static inline u32 atmel_hlcdc_layer_read_reg(struct atmel_hlcdc_layer *layer, 442 unsigned int reg) 443 { 444 u32 val; 445 446 regmap_read(layer->regmap, layer->desc->regs_offset + reg, &val); 447 448 return val; 449 } 450 451 static inline void atmel_hlcdc_layer_write_cfg(struct atmel_hlcdc_layer *layer, 452 unsigned int cfgid, u32 val) 453 { 454 atmel_hlcdc_layer_write_reg(layer, 455 layer->desc->cfgs_offset + 456 (cfgid * sizeof(u32)), val); 457 } 458 459 static inline u32 atmel_hlcdc_layer_read_cfg(struct atmel_hlcdc_layer *layer, 460 unsigned int cfgid) 461 { 462 return atmel_hlcdc_layer_read_reg(layer, 463 layer->desc->cfgs_offset + 464 (cfgid * sizeof(u32))); 465 } 466 467 static inline void atmel_hlcdc_layer_write_clut(struct atmel_hlcdc_layer *layer, 468 unsigned int c, u32 val) 469 { 470 regmap_write(layer->regmap, 471 layer->desc->clut_offset + c * sizeof(u32), 472 val); 473 } 474 475 static inline void atmel_hlcdc_layer_init(struct atmel_hlcdc_layer *layer, 476 const struct atmel_hlcdc_layer_desc *desc, 477 struct regmap *regmap) 478 { 479 layer->desc = desc; 480 layer->regmap = regmap; 481 } 482 483 enum drm_mode_status 484 atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc, 485 const struct drm_display_mode *mode); 486 487 int atmel_hlcdc_create_planes(struct drm_device *dev); 488 void atmel_hlcdc_plane_irq(struct atmel_hlcdc_plane *plane); 489 490 int atmel_hlcdc_plane_prepare_disc_area(struct drm_crtc_state *c_state); 491 int atmel_hlcdc_plane_prepare_ahb_routing(struct drm_crtc_state *c_state); 492 493 void atmel_hlcdc_crtc_irq(struct drm_crtc *c); 494 495 int atmel_hlcdc_crtc_create(struct drm_device *dev); 496 497 int atmel_hlcdc_create_outputs(struct drm_device *dev); 498 int atmel_hlcdc_encoder_get_bus_fmt(struct drm_encoder *encoder); 499 500 #endif /* DRM_ATMEL_HLCDC_H */ 501