1 /* 2 * Copyright (C) 2014 Traphandler 3 * Copyright (C) 2014 Free Electrons 4 * 5 * Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com> 6 * Author: Boris BREZILLON <boris.brezillon@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or modify it 9 * under the terms of the GNU General Public License version 2 as published by 10 * the Free Software Foundation. 11 * 12 * This program is distributed in the hope that it will be useful, but WITHOUT 13 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 14 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 15 * more details. 16 * 17 * You should have received a copy of the GNU General Public License along with 18 * this program. If not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include <linux/clk.h> 22 #include <linux/pm.h> 23 #include <linux/pm_runtime.h> 24 #include <linux/pinctrl/consumer.h> 25 26 #include <drm/drm_crtc.h> 27 #include <drm/drm_crtc_helper.h> 28 #include <drm/drmP.h> 29 30 #include <video/videomode.h> 31 32 #include "atmel_hlcdc_dc.h" 33 34 /** 35 * Atmel HLCDC CRTC structure 36 * 37 * @base: base DRM CRTC structure 38 * @hlcdc: pointer to the atmel_hlcdc structure provided by the MFD device 39 * @event: pointer to the current page flip event 40 * @id: CRTC id (returned by drm_crtc_index) 41 * @enabled: CRTC state 42 */ 43 struct atmel_hlcdc_crtc { 44 struct drm_crtc base; 45 struct atmel_hlcdc_dc *dc; 46 struct drm_pending_vblank_event *event; 47 int id; 48 bool enabled; 49 }; 50 51 static inline struct atmel_hlcdc_crtc * 52 drm_crtc_to_atmel_hlcdc_crtc(struct drm_crtc *crtc) 53 { 54 return container_of(crtc, struct atmel_hlcdc_crtc, base); 55 } 56 57 static void atmel_hlcdc_crtc_mode_set_nofb(struct drm_crtc *c) 58 { 59 struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); 60 struct regmap *regmap = crtc->dc->hlcdc->regmap; 61 struct drm_display_mode *adj = &c->state->adjusted_mode; 62 unsigned long mode_rate; 63 struct videomode vm; 64 unsigned long prate; 65 unsigned int cfg; 66 int div; 67 68 vm.vfront_porch = adj->crtc_vsync_start - adj->crtc_vdisplay; 69 vm.vback_porch = adj->crtc_vtotal - adj->crtc_vsync_end; 70 vm.vsync_len = adj->crtc_vsync_end - adj->crtc_vsync_start; 71 vm.hfront_porch = adj->crtc_hsync_start - adj->crtc_hdisplay; 72 vm.hback_porch = adj->crtc_htotal - adj->crtc_hsync_end; 73 vm.hsync_len = adj->crtc_hsync_end - adj->crtc_hsync_start; 74 75 regmap_write(regmap, ATMEL_HLCDC_CFG(1), 76 (vm.hsync_len - 1) | ((vm.vsync_len - 1) << 16)); 77 78 regmap_write(regmap, ATMEL_HLCDC_CFG(2), 79 (vm.vfront_porch - 1) | (vm.vback_porch << 16)); 80 81 regmap_write(regmap, ATMEL_HLCDC_CFG(3), 82 (vm.hfront_porch - 1) | ((vm.hback_porch - 1) << 16)); 83 84 regmap_write(regmap, ATMEL_HLCDC_CFG(4), 85 (adj->crtc_hdisplay - 1) | 86 ((adj->crtc_vdisplay - 1) << 16)); 87 88 cfg = 0; 89 90 prate = clk_get_rate(crtc->dc->hlcdc->sys_clk); 91 mode_rate = adj->crtc_clock * 1000; 92 if ((prate / 2) < mode_rate) { 93 prate *= 2; 94 cfg |= ATMEL_HLCDC_CLKSEL; 95 } 96 97 div = DIV_ROUND_UP(prate, mode_rate); 98 if (div < 2) 99 div = 2; 100 101 cfg |= ATMEL_HLCDC_CLKDIV(div); 102 103 regmap_update_bits(regmap, ATMEL_HLCDC_CFG(0), 104 ATMEL_HLCDC_CLKSEL | ATMEL_HLCDC_CLKDIV_MASK | 105 ATMEL_HLCDC_CLKPOL, cfg); 106 107 cfg = 0; 108 109 if (adj->flags & DRM_MODE_FLAG_NVSYNC) 110 cfg |= ATMEL_HLCDC_VSPOL; 111 112 if (adj->flags & DRM_MODE_FLAG_NHSYNC) 113 cfg |= ATMEL_HLCDC_HSPOL; 114 115 regmap_update_bits(regmap, ATMEL_HLCDC_CFG(5), 116 ATMEL_HLCDC_HSPOL | ATMEL_HLCDC_VSPOL | 117 ATMEL_HLCDC_VSPDLYS | ATMEL_HLCDC_VSPDLYE | 118 ATMEL_HLCDC_DISPPOL | ATMEL_HLCDC_DISPDLY | 119 ATMEL_HLCDC_VSPSU | ATMEL_HLCDC_VSPHO | 120 ATMEL_HLCDC_GUARDTIME_MASK, 121 cfg); 122 } 123 124 static void atmel_hlcdc_crtc_disable(struct drm_crtc *c) 125 { 126 struct drm_device *dev = c->dev; 127 struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); 128 struct regmap *regmap = crtc->dc->hlcdc->regmap; 129 unsigned int status; 130 131 if (!crtc->enabled) 132 return; 133 134 drm_crtc_vblank_off(c); 135 136 pm_runtime_get_sync(dev->dev); 137 138 regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_DISP); 139 while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && 140 (status & ATMEL_HLCDC_DISP)) 141 cpu_relax(); 142 143 regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_SYNC); 144 while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && 145 (status & ATMEL_HLCDC_SYNC)) 146 cpu_relax(); 147 148 regmap_write(regmap, ATMEL_HLCDC_DIS, ATMEL_HLCDC_PIXEL_CLK); 149 while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && 150 (status & ATMEL_HLCDC_PIXEL_CLK)) 151 cpu_relax(); 152 153 clk_disable_unprepare(crtc->dc->hlcdc->sys_clk); 154 pinctrl_pm_select_sleep_state(dev->dev); 155 156 pm_runtime_allow(dev->dev); 157 158 pm_runtime_put_sync(dev->dev); 159 160 crtc->enabled = false; 161 } 162 163 static void atmel_hlcdc_crtc_enable(struct drm_crtc *c) 164 { 165 struct drm_device *dev = c->dev; 166 struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); 167 struct regmap *regmap = crtc->dc->hlcdc->regmap; 168 unsigned int status; 169 170 if (crtc->enabled) 171 return; 172 173 pm_runtime_get_sync(dev->dev); 174 175 pm_runtime_forbid(dev->dev); 176 177 pinctrl_pm_select_default_state(dev->dev); 178 clk_prepare_enable(crtc->dc->hlcdc->sys_clk); 179 180 regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_PIXEL_CLK); 181 while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && 182 !(status & ATMEL_HLCDC_PIXEL_CLK)) 183 cpu_relax(); 184 185 186 regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_SYNC); 187 while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && 188 !(status & ATMEL_HLCDC_SYNC)) 189 cpu_relax(); 190 191 regmap_write(regmap, ATMEL_HLCDC_EN, ATMEL_HLCDC_DISP); 192 while (!regmap_read(regmap, ATMEL_HLCDC_SR, &status) && 193 !(status & ATMEL_HLCDC_DISP)) 194 cpu_relax(); 195 196 pm_runtime_put_sync(dev->dev); 197 198 drm_crtc_vblank_on(c); 199 200 crtc->enabled = true; 201 } 202 203 void atmel_hlcdc_crtc_suspend(struct drm_crtc *c) 204 { 205 struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); 206 207 if (crtc->enabled) { 208 atmel_hlcdc_crtc_disable(c); 209 /* save enable state for resume */ 210 crtc->enabled = true; 211 } 212 } 213 214 void atmel_hlcdc_crtc_resume(struct drm_crtc *c) 215 { 216 struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); 217 218 if (crtc->enabled) { 219 crtc->enabled = false; 220 atmel_hlcdc_crtc_enable(c); 221 } 222 } 223 224 static int atmel_hlcdc_crtc_atomic_check(struct drm_crtc *c, 225 struct drm_crtc_state *s) 226 { 227 struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); 228 229 if (atmel_hlcdc_dc_mode_valid(crtc->dc, &s->adjusted_mode) != MODE_OK) 230 return -EINVAL; 231 232 return atmel_hlcdc_plane_prepare_disc_area(s); 233 } 234 235 static void atmel_hlcdc_crtc_atomic_begin(struct drm_crtc *c, 236 struct drm_crtc_state *old_s) 237 { 238 struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); 239 240 if (c->state->event) { 241 c->state->event->pipe = drm_crtc_index(c); 242 243 WARN_ON(drm_crtc_vblank_get(c) != 0); 244 245 crtc->event = c->state->event; 246 c->state->event = NULL; 247 } 248 } 249 250 static void atmel_hlcdc_crtc_atomic_flush(struct drm_crtc *crtc, 251 struct drm_crtc_state *old_s) 252 { 253 /* TODO: write common plane control register if available */ 254 } 255 256 static const struct drm_crtc_helper_funcs lcdc_crtc_helper_funcs = { 257 .mode_set = drm_helper_crtc_mode_set, 258 .mode_set_nofb = atmel_hlcdc_crtc_mode_set_nofb, 259 .mode_set_base = drm_helper_crtc_mode_set_base, 260 .disable = atmel_hlcdc_crtc_disable, 261 .enable = atmel_hlcdc_crtc_enable, 262 .atomic_check = atmel_hlcdc_crtc_atomic_check, 263 .atomic_begin = atmel_hlcdc_crtc_atomic_begin, 264 .atomic_flush = atmel_hlcdc_crtc_atomic_flush, 265 }; 266 267 static void atmel_hlcdc_crtc_destroy(struct drm_crtc *c) 268 { 269 struct atmel_hlcdc_crtc *crtc = drm_crtc_to_atmel_hlcdc_crtc(c); 270 271 drm_crtc_cleanup(c); 272 kfree(crtc); 273 } 274 275 static void atmel_hlcdc_crtc_finish_page_flip(struct atmel_hlcdc_crtc *crtc) 276 { 277 struct drm_device *dev = crtc->base.dev; 278 unsigned long flags; 279 280 spin_lock_irqsave(&dev->event_lock, flags); 281 if (crtc->event) { 282 drm_send_vblank_event(dev, crtc->id, crtc->event); 283 drm_vblank_put(dev, crtc->id); 284 crtc->event = NULL; 285 } 286 spin_unlock_irqrestore(&dev->event_lock, flags); 287 } 288 289 void atmel_hlcdc_crtc_irq(struct drm_crtc *c) 290 { 291 drm_handle_vblank(c->dev, 0); 292 atmel_hlcdc_crtc_finish_page_flip(drm_crtc_to_atmel_hlcdc_crtc(c)); 293 } 294 295 static const struct drm_crtc_funcs atmel_hlcdc_crtc_funcs = { 296 .page_flip = drm_atomic_helper_page_flip, 297 .set_config = drm_atomic_helper_set_config, 298 .destroy = atmel_hlcdc_crtc_destroy, 299 .reset = drm_atomic_helper_crtc_reset, 300 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 301 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 302 }; 303 304 int atmel_hlcdc_crtc_create(struct drm_device *dev) 305 { 306 struct atmel_hlcdc_dc *dc = dev->dev_private; 307 struct atmel_hlcdc_planes *planes = dc->planes; 308 struct atmel_hlcdc_crtc *crtc; 309 int ret; 310 int i; 311 312 crtc = kzalloc(sizeof(*crtc), GFP_KERNEL); 313 if (!crtc) 314 return -ENOMEM; 315 316 crtc->dc = dc; 317 318 ret = drm_crtc_init_with_planes(dev, &crtc->base, 319 &planes->primary->base, 320 planes->cursor ? &planes->cursor->base : NULL, 321 &atmel_hlcdc_crtc_funcs, NULL); 322 if (ret < 0) 323 goto fail; 324 325 crtc->id = drm_crtc_index(&crtc->base); 326 327 if (planes->cursor) 328 planes->cursor->base.possible_crtcs = 1 << crtc->id; 329 330 for (i = 0; i < planes->noverlays; i++) 331 planes->overlays[i]->base.possible_crtcs = 1 << crtc->id; 332 333 drm_crtc_helper_add(&crtc->base, &lcdc_crtc_helper_funcs); 334 drm_crtc_vblank_reset(&crtc->base); 335 336 dc->crtc = &crtc->base; 337 338 return 0; 339 340 fail: 341 atmel_hlcdc_crtc_destroy(&crtc->base); 342 return ret; 343 } 344